[deliverable/binutils-gdb.git] / sim / testsuite / sky / t-dma.c

#include <stdio.h>
#include <string.h>

#define error(x) { printf(x); exit( 999); }

void wrtest( unsigned *reg, unsigned w, unsigned e)
{
    unsigned r;

    *reg = w;
    r = *reg;
    if( r != e)
    {
	printf( "wrtest: at 0x%08lx wrote=0x%08x read=0x%08x expected=0x%08x\n",
		reg, w, r, e);
	exit( 999);
    }
}

/*
DMA tag in target format (LE).
BE=0x00000000_00000000_aaaaaaa0_ip00cccc
*/
typedef struct { unsigned tagL __attribute__ ((aligned (16))), tagH, pke1, pke0; } quad;

			quad data0 = {  3,  2,  1,  0};

/* DMArefe 1, data0 */	quad dma_refe =	{ 0x0c000001, 000, 0, 0};
/* DMAcnt 2 */		quad dma_cnt =	{ 0x10000002, 0, 0, 0};
			quad data1 =	{  7,  6,  5,  4};
			quad data2 =	{ 11, 10,  9,  8};
/* DMAnext 3,dma_ref */	quad dma_next =	{ 0x20000003, 000, 0, 0};
			quad data3 =	{ 15, 14, 13, 12};
			quad data4 =	{ 19, 18, 17, 16};
			quad data5 =	{ 23, 22, 21, 20};

			quad data6 =	{ 27, 26, 25, 24};
			quad data7 =	{ 31, 30, 29, 28};
			quad data8 =	{ 35, 34, 33, 32};
/* DMAref 1,data6 */	quad dma_ref =	{ 0x30000001, 000, 0, 0};
/* DMArefs 2,data7 */	quad dma_refs =	{ 0x40000002, 000, 0, 0};
/* DMAcall 3,dma_cal2 */quad dma_call =	{ 0x50000003, 000, 0, 0};
			quad data9 =	{ 39, 38, 37, 36};
			quad dataA =	{ 43, 42, 41, 40};
			quad dataB =	{ 47, 46, 45, 44};
/* DMAend 1 */  	quad dma_end =	{ 0x78000001, 0, 0, 0};
			quad dataE =	{ 59, 58, 57, 56};

/* DMAcall 1,dma_rt2 */	quad dma_cal2 =	{ 0x50000001, 000, 0, 0 };
			quad dataC =	{ 51, 50, 49, 48};
/* DMAret 0 */		quad dma_ret =	{ 0x60000000, 0, 0, 0}; 

/* DMAret 1 */		quad dma_rt2 =	{ 0x60000001, 0, 0, 0};
			quad dataD =	{ 55, 54, 53, 52};

int main()
{

#define DMA_D0_START	0x10008000
#define DMA_D0_CHCR	(unsigned*) 0x10008000
#define DMA_Dn_CHCR__STR	0x00000100
#define DMA_Dn_CHCR__TIE	0x00000080
#define DMA_Dn_CHCR__TTE	0x00000040
#define DMA_Dn_CHCR__MOD	0x0000000c
#define DMA_Dn_CHCR__MOD_NORM	0x00000000
#define DMA_Dn_CHCR__MOD_CHAIN	0x00000004
#define DMA_Dn_CHCR__DIR	0x00000001
#define DMA_D0_MADR	(unsigned*) 0x10008010
#define DMA_D0_QWC	(unsigned*) 0x10008020
#define DMA_D0_TADR	(unsigned*) 0x10008030
#define DMA_D0_ASR0	(unsigned*) 0x10008040
#define DMA_D0_ASR1	(unsigned*) 0x10008050
#define DMA_D0_PKTFLAG	(unsigned*) 0x10008060	/* virtual reg to indicate presence of tag in data */
#define DMA_D0_END	0x10008070

#define DMA_D1_START	0x10009000
#define DMA_D1_CHCR	(unsigned*) 0x10009000
#define DMA_D1_MADR	(unsigned*) 0x10009010
#define DMA_D1_QWC	(unsigned*) 0x10009020
#define DMA_D1_TADR	(unsigned*) 0x10009030
#define DMA_D1_ASR0	(unsigned*) 0x10009040
#define DMA_D1_ASR1	(unsigned*) 0x10009050
#define DMA_D1_PKTFLAG	(unsigned*) 0x10009060	/* virtual reg to indicate presence of tag in data */ 
#define DMA_D1_END	0x10009070

#define DMA_D2_START	0x1000a000
#define DMA_D2_CHCR	(unsigned*) 0x1000a000
#define DMA_D2_MADR	(unsigned*) 0x1000a010
#define DMA_D2_QWC	(unsigned*) 0x1000a020
#define DMA_D2_TADR	(unsigned*) 0x1000a030
#define DMA_D2_ASR0	(unsigned*) 0x1000a040
#define DMA_D2_ASR1	(unsigned*) 0x1000a050
#define DMA_D2_PKTFLAG	(unsigned*) 0x1000a060	/* virtual reg to indicate presence of tag in data */ 
#define DMA_D2_END	0x1000a070

#define DMA_D_CTRL	(unsigned*) 0x1000e000
#define DMA_D_CTRL__DMAE	0x00000001
#define DMA_D_STAT	(unsigned*) 0x1000e010
#define DMA_D_STAT__TOGGLE	0x63ff0000
#define DMA_D_STAT__CLEAR	0x0000e3ff
#define DMA_D_PCR	(unsigned*) 0x1000e020
#define DMA_D_PCR__PCE		0x80000000
#define DMA_D_PCR__CDE		0x03ff0000
#define DMA_D_PCR__CDE0		0x00010000
#define DMA_D_PCR__CDE1		0x00020000
#define DMA_D_PCR__CDE2		0x00040000
#define DMA_D_SQWC	(unsigned*) 0x1000e030
#define DMA_D_RBSR	(unsigned*) 0x1000e040
#define DMA_D_RBOR	(unsigned*) 0x1000e050
#define DMA_D_STADR	(unsigned*) 0x1000e060

#define DMA_TAG_IRQ	0x80000000;


    unsigned *reg, temp;

    printf( "Testing DMA_D_CTRL...\n");
    reg = DMA_D_CTRL;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x00000555, 0x00000555);
    wrtest( reg, 0x000002aa, 0x000002aa);
    *reg = 0;

    printf( "Testing DMA_D_STAT...\n");
    reg = DMA_D_STAT;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0xffffffff, 0x63ff0000);
    wrtest( reg, 0x63ff0000, 0x00000000);

    printf( "Testing DMA_D_PCR...\n");
    reg = DMA_D_PCR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x80000000, 0x83ff0000);
    wrtest( reg, 0x8fff0000, 0x83ff0000);
    wrtest( reg, 0x05550000, 0x01550000);
    wrtest( reg, 0x0155aaaa, 0x015502aa);
    wrtest( reg, 0x00005555, 0x00000155);
    *reg = 0;

    printf( "Testing DMA_D_SQWC...\n");
    reg = DMA_D_SQWC;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x005500aa);
    wrtest( reg, 0xaaaa5555, 0x00aa0055);
    *reg = 0;

    printf( "Testing DMA_D_RBOR...\n");
    reg = DMA_D_RBOR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0xaaaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D_RBSR...\n");
    reg = DMA_D_RBSR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0xaaaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D_STADR...\n");
    reg = DMA_D_STADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0xaaaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D0_CHCR...\n");
    reg = DMA_D0_CHCR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x000000aa);
    wrtest( reg, 0xaaaa5555, 0x00000155);
    *reg = 0;

    printf( "Testing DMA_D0_MADR...\n");
    reg = DMA_D0_MADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D0_TADR...\n");
    reg = DMA_D0_TADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D0_ASR0...\n");
    reg = DMA_D0_ASR0;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D0_ASR1...\n");
    reg = DMA_D0_ASR1;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D0_QWC...\n");
    reg = DMA_D0_QWC;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x0000aaaa);
    wrtest( reg, 0xaaaa5555, 0x00005555);
    *reg = 0;

    printf( "Testing DMA_D0_PKTFLAG...\n");
    reg = DMA_D0_PKTFLAG;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaaa);
    wrtest( reg, 0xaaaa5555, 0xaaaa5555);
    *reg = 0;

    printf( "Testing DMA_D1_CHCR...\n");
    reg = DMA_D1_CHCR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x000000aa);
    wrtest( reg, 0xaaaa5555, 0x00000155);
    *reg = 0;

    printf( "Testing DMA_D1_MADR...\n");
    reg = DMA_D1_MADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D1_TADR...\n");
    reg = DMA_D1_TADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D1_ASR0...\n");
    reg = DMA_D1_ASR0;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D1_ASR1...\n");
    reg = DMA_D1_ASR1;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D1_QWC...\n");
    reg = DMA_D1_QWC;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x0000aaaa);
    wrtest( reg, 0xaaaa5555, 0x00005555);
    *reg = 0;

    printf( "Testing DMA_D1_PKTFLAG...\n");
    reg = DMA_D1_PKTFLAG;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaaa);
    wrtest( reg, 0xaaaa5555, 0xaaaa5555);
    *reg = 0;

    printf( "Testing DMA_D2_CHCR...\n");
    reg = DMA_D2_CHCR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x000000aa);
    wrtest( reg, 0xaaaa5555, 0x00000155);
    *reg = 0;

    printf( "Testing DMA_D2_MADR...\n");
    reg = DMA_D2_MADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D2_TADR...\n");
    reg = DMA_D2_TADR;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D2_ASR0...\n");
    reg = DMA_D2_ASR0;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D2_ASR1...\n");
    reg = DMA_D2_ASR1;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaa0);
    wrtest( reg, 0x2aaa5555, 0x2aaa5550);
    *reg = 0;

    printf( "Testing DMA_D2_QWC...\n");
    reg = DMA_D2_QWC;
    if( *reg)
    {
	printf ("Not initialized to zero (0x%08x).\n", *reg);
	exit (999);
    }
    wrtest( reg, 0x5555aaaa, 0x0000aaaa);
    wrtest( reg, 0xaaaa5555, 0x00005555);
    *reg = 0;

    printf( "Testing DMA_D2_PKTFLAG...\n");
    reg = DMA_D2_PKTFLAG;
    if( *reg) error( "Not initialized to zero.\n");
    wrtest( reg, 0x5555aaaa, 0x5555aaaa);
    wrtest( reg, 0xaaaa5555, 0xaaaa5555);
    *reg = 0;

    /* Initiate a non-chained 0-length transfer. */
    printf ("\nPreparing for a DMA1 NORM transfer...\n");
    reg = DMA_D_CTRL;			/* enable DMA */
    *reg = DMA_D_CTRL__DMAE;
    reg = DMA_D1_QWC;			/* set # of quad words to xfr */
    *reg = 0;
    reg = DMA_D1_MADR;			/* set data address */
    *reg = 0x00012340;
    reg = DMA_D1_CHCR;
    printf ("Ready...\n");
    *reg = DMA_Dn_CHCR__STR | DMA_Dn_CHCR__MOD_NORM;

    reg = DMA_D1_QWC;
    if (*reg)
    {
	printf ("D1_QWC is not zero after transfer.\n");
	exit (999);
    }
    reg = DMA_D1_MADR;
    if (*reg != 0x00012340)
    {
	printf ("D1_MADR value is wrong after transfer.\n");
	exit (999);
    }
    reg = DMA_D1_CHCR;
    if ((*reg & DMA_Dn_CHCR__STR) != 0)
    {
	printf ("D1_CHCR.STR is not reset after transfer.\n");
	exit (999);
    }
    printf ("Completed OK...\n");

    /* Initiate a chained transfer. */

    /* Some of the "tag" fields couldn't be initialised statically. */
    /* The first address is unaligned to force a warning. */
    dma_refe.tagH = (unsigned)&data0 + 1;
    dma_next.tagH = (unsigned)&dma_ref;
    dma_ref.tagH = (unsigned)&data6;
    dma_refs.tagH = (unsigned)&data7;
    dma_call.tagH = (unsigned)&dma_cal2;
    dma_cal2.tagH = (unsigned)&dma_rt2;

    printf ("\nPreparing for a DMA0 TAG transfer...\n");
    reg = DMA_D_PCR;			/* disable DMA0 */
    *reg &= ~DMA_D_PCR__CDE0;
    *reg |= DMA_D_PCR__PCE;
    reg = DMA_D_CTRL;			/* enable DMA */
    *reg = DMA_D_CTRL__DMAE;
    reg = DMA_D0_TADR;			/* set tag address */
    *reg = (unsigned) & dma_refe;
    reg = DMA_D0_QWC;			/* set fictitious count */
    *reg = 51;
    printf ("Ready...\n");
    reg = DMA_D0_CHCR;
    *reg = DMA_Dn_CHCR__STR | DMA_Dn_CHCR__TTE | DMA_Dn_CHCR__MOD_CHAIN;

    reg = DMA_D0_QWC;
    if (*reg != 51)
    {
	printf ("DMA0 transfer not inhibited by DMA_D_PCR__CDE0 (%d).\n", *reg);
	exit (999);
    }
    reg = DMA_D_PCR;			/* enable DMA0 */
    *reg &= ~DMA_D_PCR__PCE;

    reg = DMA_D0_QWC;
    if (*reg)
    {
	printf ("D0_QWC is not zero after transfer.\n");
	exit (999);
    }
    reg = DMA_D0_MADR;
    if (*reg != (unsigned)&dma_cal2)
    {
	printf ("D0_MADR value is wrong after transfer.\n");
	exit (999);
    }
    reg = DMA_D0_CHCR;
    if ((*reg & DMA_Dn_CHCR__STR) != 0)
    {
	printf ("D0_CHCR.STR is not reset after transfer.\n");
	exit (999);
    }
    printf ("Completed OK...\n");

    /* Initiate a chained transfer that will be suspended
    and restarted. */

    /* Request suspension part way through. */
    dma_ref.tagL |= DMA_TAG_IRQ;

    printf ("\nPreparing for a DMA2 TAG transfer with suspension...\n");
    reg = DMA_D_CTRL;			/* enable DMA */
    *reg = DMA_D_CTRL__DMAE;
    reg = DMA_D2_TADR;			/* set tag address */
    *reg = (unsigned) & dma_refe;
    printf ("Ready...\n");
    reg = DMA_D2_CHCR;
    *reg = DMA_Dn_CHCR__STR | DMA_Dn_CHCR__MOD_CHAIN;
    printf ("returns...\n");

    reg = DMA_D2_QWC;
    if (*reg)
    {
	printf ("D2_QWC (0x%08x) is not zero after suspension.\n", *reg);
	exit (999);
    }
    reg = DMA_D2_MADR;
    if (*reg != (unsigned)&data7)
    {
	printf ("D2_MADR value (0x%08x) is wrong after suspension.\n", *reg);
	exit (999);
    }
    reg = DMA_D2_TADR;
    if (*reg != (unsigned)&dma_refs)
    {
	printf ("D2_TADR value (0x%08x) is wrong after suspension.\n", *reg);
	exit (999);
    }
    reg = DMA_D2_CHCR;
    if ((*reg & DMA_Dn_CHCR__STR) != 0)
    {
	printf ("D2_CHCR.STR (0x%08x) is not reset after suspension.\n", *reg);
	exit (999);
    }
    reg = DMA_D_PCR;
    if ((*reg & DMA_D_PCR__PCE) == 0)
    {
	printf ("DMA_D_PCR__PCE not set by transfer.\n");
	exit (999);
    }
    printf ("Suspended OK...\n");

    /* Reset the suspension request and continue. */
    dma_ref.tagL &= ~DMA_TAG_IRQ;
    reg = DMA_D2_CHCR;
    *reg |= DMA_Dn_CHCR__STR;

    reg = DMA_D2_QWC;
    if (*reg)
    {
	printf ("D2_QWC (0x%08x) is not zero after transfer.\n", *reg);
	exit (999);
    }
    reg = DMA_D2_MADR;
    if (*reg != (unsigned)&dma_cal2)
    {
	printf ("D2_MADR value (0x%08x) is wrong after transfer.\n", *reg);
	exit (999);
    }
    reg = DMA_D2_CHCR;
    if ((*reg & DMA_Dn_CHCR__STR) != 0)
    {
	printf ("D2_CHCR.STR (0x%08x) is not reset after transfer.\n", *reg);
	exit (999);
    }
    reg = DMA_D_PCR;
    if (*reg & DMA_D_PCR__PCE)
    {
	printf ("DMA_D_PCR__PCE not reset by transfer.\n");
	exit (999);
    }
    printf ("Completed OK...\n");

    exit (0);
}
Commit	Line	Data
fc609c6c JL	1	#include <stdio.h>
	2	#include <string.h>
	3
	4	#define error(x) { printf(x); exit( 999); }
	5
	6	void wrtest( unsigned *reg, unsigned w, unsigned e)
	7	{
	8	unsigned r;
	9
	10	*reg = w;
	11	r = *reg;
	12	if( r != e)
	13	{
	14	printf( "wrtest: at 0x%08lx wrote=0x%08x read=0x%08x expected=0x%08x\n",
	15	reg, w, r, e);
	16	exit( 999);
	17	}
	18	}
	19
	20	/*
	21	DMA tag in target format (LE).
	22	BE=0x00000000_00000000_aaaaaaa0_ip00cccc
	23	*/
	24	typedef struct { unsigned tagL __attribute__ ((aligned (16))), tagH, pke1, pke0; } quad;
	25
	26	quad data0 = { 3, 2, 1, 0};
	27
	28	/* DMArefe 1, data0 */ quad dma_refe = { 0x0c000001, 000, 0, 0};
	29	/* DMAcnt 2 */ quad dma_cnt = { 0x10000002, 0, 0, 0};
	30	quad data1 = { 7, 6, 5, 4};
	31	quad data2 = { 11, 10, 9, 8};
	32	/* DMAnext 3,dma_ref */ quad dma_next = { 0x20000003, 000, 0, 0};
	33	quad data3 = { 15, 14, 13, 12};
	34	quad data4 = { 19, 18, 17, 16};
	35	quad data5 = { 23, 22, 21, 20};
	36
	37	quad data6 = { 27, 26, 25, 24};
	38	quad data7 = { 31, 30, 29, 28};
	39	quad data8 = { 35, 34, 33, 32};
	40	/* DMAref 1,data6 */ quad dma_ref = { 0x30000001, 000, 0, 0};
	41	/* DMArefs 2,data7 */ quad dma_refs = { 0x40000002, 000, 0, 0};
	42	/* DMAcall 3,dma_cal2 */quad dma_call = { 0x50000003, 000, 0, 0};
	43	quad data9 = { 39, 38, 37, 36};
	44	quad dataA = { 43, 42, 41, 40};
	45	quad dataB = { 47, 46, 45, 44};
	46	/* DMAend 1 */ quad dma_end = { 0x78000001, 0, 0, 0};
	47	quad dataE = { 59, 58, 57, 56};
	48
	49	/* DMAcall 1,dma_rt2 */ quad dma_cal2 = { 0x50000001, 000, 0, 0 };
	50	quad dataC = { 51, 50, 49, 48};
	51	/* DMAret 0 */ quad dma_ret = { 0x60000000, 0, 0, 0};
	52
	53	/* DMAret 1 */ quad dma_rt2 = { 0x60000001, 0, 0, 0};
	54	quad dataD = { 55, 54, 53, 52};
	55
	56	int main()
	57	{
	58
	59	#define DMA_D0_START 0x10008000
	60	#define DMA_D0_CHCR (unsigned*) 0x10008000
	61	#define DMA_Dn_CHCR__STR 0x00000100
	62	#define DMA_Dn_CHCR__TIE 0x00000080
	63	#define DMA_Dn_CHCR__TTE 0x00000040
	64	#define DMA_Dn_CHCR__MOD 0x0000000c
65	#define DMA_Dn_CHCR__MOD_NORM 0x00000000
66	#define DMA_Dn_CHCR__MOD_CHAIN 0x00000004
67	#define DMA_Dn_CHCR__DIR 0x00000001
68	#define DMA_D0_MADR (unsigned*) 0x10008010
69	#define DMA_D0_QWC (unsigned*) 0x10008020
70	#define DMA_D0_TADR (unsigned*) 0x10008030
71	#define DMA_D0_ASR0 (unsigned*) 0x10008040
72	#define DMA_D0_ASR1 (unsigned*) 0x10008050
73	#define DMA_D0_PKTFLAG (unsigned) 0x10008060 / virtual reg to indicate presence of tag in data */
74	#define DMA_D0_END 0x10008070
75
76	#define DMA_D1_START 0x10009000
77	#define DMA_D1_CHCR (unsigned*) 0x10009000
78	#define DMA_D1_MADR (unsigned*) 0x10009010
79	#define DMA_D1_QWC (unsigned*) 0x10009020
80	#define DMA_D1_TADR (unsigned*) 0x10009030
81	#define DMA_D1_ASR0 (unsigned*) 0x10009040
82	#define DMA_D1_ASR1 (unsigned*) 0x10009050
83	#define DMA_D1_PKTFLAG (unsigned) 0x10009060 / virtual reg to indicate presence of tag in data */
84	#define DMA_D1_END 0x10009070
85
86	#define DMA_D2_START 0x1000a000
87	#define DMA_D2_CHCR (unsigned*) 0x1000a000
88	#define DMA_D2_MADR (unsigned*) 0x1000a010
89	#define DMA_D2_QWC (unsigned*) 0x1000a020
90	#define DMA_D2_TADR (unsigned*) 0x1000a030
91	#define DMA_D2_ASR0 (unsigned*) 0x1000a040
92	#define DMA_D2_ASR1 (unsigned*) 0x1000a050
93	#define DMA_D2_PKTFLAG (unsigned) 0x1000a060 / virtual reg to indicate presence of tag in data */
94	#define DMA_D2_END 0x1000a070
95
96	#define DMA_D_CTRL (unsigned*) 0x1000e000
97	#define DMA_D_CTRL__DMAE 0x00000001
98	#define DMA_D_STAT (unsigned*) 0x1000e010
99	#define DMA_D_STAT__TOGGLE 0x63ff0000
100	#define DMA_D_STAT__CLEAR 0x0000e3ff
101	#define DMA_D_PCR (unsigned*) 0x1000e020
102	#define DMA_D_PCR__PCE 0x80000000
103	#define DMA_D_PCR__CDE 0x03ff0000
104	#define DMA_D_PCR__CDE0 0x00010000
105	#define DMA_D_PCR__CDE1 0x00020000
106	#define DMA_D_PCR__CDE2 0x00040000
107	#define DMA_D_SQWC (unsigned*) 0x1000e030
108	#define DMA_D_RBSR (unsigned*) 0x1000e040
109	#define DMA_D_RBOR (unsigned*) 0x1000e050
110	#define DMA_D_STADR (unsigned*) 0x1000e060
111
112	#define DMA_TAG_IRQ 0x80000000;
113
114
115	unsigned *reg, temp;
116
117	printf( "Testing DMA_D_CTRL...\n");
118	reg = DMA_D_CTRL;
119	if( *reg) error( "Not initialized to zero.\n");
120	wrtest( reg, 0x00000555, 0x00000555);
121	wrtest( reg, 0x000002aa, 0x000002aa);
122	*reg = 0;
123
124	printf( "Testing DMA_D_STAT...\n");
125	reg = DMA_D_STAT;
126	if( *reg) error( "Not initialized to zero.\n");
127	wrtest( reg, 0xffffffff, 0x63ff0000);
128	wrtest( reg, 0x63ff0000, 0x00000000);
129
130	printf( "Testing DMA_D_PCR...\n");
131	reg = DMA_D_PCR;
132	if( *reg) error( "Not initialized to zero.\n");
133	wrtest( reg, 0x80000000, 0x83ff0000);
134	wrtest( reg, 0x8fff0000, 0x83ff0000);
135	wrtest( reg, 0x05550000, 0x01550000);
136	wrtest( reg, 0x0155aaaa, 0x015502aa);
137	wrtest( reg, 0x00005555, 0x00000155);
138	*reg = 0;
139
140	printf( "Testing DMA_D_SQWC...\n");
141	reg = DMA_D_SQWC;
142	if( *reg) error( "Not initialized to zero.\n");
143	wrtest( reg, 0x5555aaaa, 0x005500aa);
144	wrtest( reg, 0xaaaa5555, 0x00aa0055);
145	*reg = 0;
146
147	printf( "Testing DMA_D_RBOR...\n");
148	reg = DMA_D_RBOR;
149	if( *reg) error( "Not initialized to zero.\n");
150	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
151	wrtest( reg, 0xaaaa5555, 0x2aaa5550);
152	*reg = 0;
153
154	printf( "Testing DMA_D_RBSR...\n");
155	reg = DMA_D_RBSR;
156	if( *reg) error( "Not initialized to zero.\n");
157	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
158	wrtest( reg, 0xaaaa5555, 0x2aaa5550);
159	*reg = 0;
160
161	printf( "Testing DMA_D_STADR...\n");
162	reg = DMA_D_STADR;
163	if( *reg) error( "Not initialized to zero.\n");
164	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
165	wrtest( reg, 0xaaaa5555, 0x2aaa5550);
166	*reg = 0;
167
168	printf( "Testing DMA_D0_CHCR...\n");
169	reg = DMA_D0_CHCR;
170	if( *reg) error( "Not initialized to zero.\n");
171	wrtest( reg, 0x5555aaaa, 0x000000aa);
172	wrtest( reg, 0xaaaa5555, 0x00000155);
173	*reg = 0;
174
175	printf( "Testing DMA_D0_MADR...\n");
176	reg = DMA_D0_MADR;
177	if( *reg) error( "Not initialized to zero.\n");
178	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
179	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
180	*reg = 0;
181
182	printf( "Testing DMA_D0_TADR...\n");
183	reg = DMA_D0_TADR;
184	if( *reg) error( "Not initialized to zero.\n");
185	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
186	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
187	*reg = 0;
188
189	printf( "Testing DMA_D0_ASR0...\n");
190	reg = DMA_D0_ASR0;
191	if( *reg) error( "Not initialized to zero.\n");
192	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
193	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
194	*reg = 0;
195
196	printf( "Testing DMA_D0_ASR1...\n");
197	reg = DMA_D0_ASR1;
198	if( *reg) error( "Not initialized to zero.\n");
199	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
200	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
201	*reg = 0;
202
203	printf( "Testing DMA_D0_QWC...\n");
204	reg = DMA_D0_QWC;
205	if( *reg) error( "Not initialized to zero.\n");
206	wrtest( reg, 0x5555aaaa, 0x0000aaaa);
207	wrtest( reg, 0xaaaa5555, 0x00005555);
208	*reg = 0;
209
210	printf( "Testing DMA_D0_PKTFLAG...\n");
211	reg = DMA_D0_PKTFLAG;
212	if( *reg) error( "Not initialized to zero.\n");
213	wrtest( reg, 0x5555aaaa, 0x5555aaaa);
214	wrtest( reg, 0xaaaa5555, 0xaaaa5555);
215	*reg = 0;
216
217	printf( "Testing DMA_D1_CHCR...\n");
218	reg = DMA_D1_CHCR;
219	if( *reg) error( "Not initialized to zero.\n");
220	wrtest( reg, 0x5555aaaa, 0x000000aa);
221	wrtest( reg, 0xaaaa5555, 0x00000155);
222	*reg = 0;
223
224	printf( "Testing DMA_D1_MADR...\n");
225	reg = DMA_D1_MADR;
226	if( *reg) error( "Not initialized to zero.\n");
227	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
228	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
229	*reg = 0;
230
231	printf( "Testing DMA_D1_TADR...\n");
232	reg = DMA_D1_TADR;
233	if( *reg) error( "Not initialized to zero.\n");
234	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
235	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
236	*reg = 0;
237
238	printf( "Testing DMA_D1_ASR0...\n");
239	reg = DMA_D1_ASR0;
240	if( *reg) error( "Not initialized to zero.\n");
241	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
242	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
243	*reg = 0;
244
245	printf( "Testing DMA_D1_ASR1...\n");
246	reg = DMA_D1_ASR1;
247	if( *reg) error( "Not initialized to zero.\n");
248	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
249	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
250	*reg = 0;
251
252	printf( "Testing DMA_D1_QWC...\n");
253	reg = DMA_D1_QWC;
254	if( *reg) error( "Not initialized to zero.\n");
255	wrtest( reg, 0x5555aaaa, 0x0000aaaa);
256	wrtest( reg, 0xaaaa5555, 0x00005555);
257	*reg = 0;
258
259	printf( "Testing DMA_D1_PKTFLAG...\n");
260	reg = DMA_D1_PKTFLAG;
261	if( *reg) error( "Not initialized to zero.\n");
262	wrtest( reg, 0x5555aaaa, 0x5555aaaa);
263	wrtest( reg, 0xaaaa5555, 0xaaaa5555);
264	*reg = 0;
265
266	printf( "Testing DMA_D2_CHCR...\n");
267	reg = DMA_D2_CHCR;
268	if( *reg) error( "Not initialized to zero.\n");
269	wrtest( reg, 0x5555aaaa, 0x000000aa);
270	wrtest( reg, 0xaaaa5555, 0x00000155);
271	*reg = 0;
272
273	printf( "Testing DMA_D2_MADR...\n");
274	reg = DMA_D2_MADR;
275	if( *reg) error( "Not initialized to zero.\n");
276	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
277	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
278	*reg = 0;
279
280	printf( "Testing DMA_D2_TADR...\n");
281	reg = DMA_D2_TADR;
282	if( *reg) error( "Not initialized to zero.\n");
283	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
284	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
285	*reg = 0;
286
287	printf( "Testing DMA_D2_ASR0...\n");
288	reg = DMA_D2_ASR0;
289	if( *reg) error( "Not initialized to zero.\n");
290	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
291	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
292	*reg = 0;
293
294	printf( "Testing DMA_D2_ASR1...\n");
295	reg = DMA_D2_ASR1;
296	if( *reg) error( "Not initialized to zero.\n");
297	wrtest( reg, 0x5555aaaa, 0x5555aaa0);
298	wrtest( reg, 0x2aaa5555, 0x2aaa5550);
299	*reg = 0;
300
301	printf( "Testing DMA_D2_QWC...\n");
302	reg = DMA_D2_QWC;
303	if( *reg)
304	{
305	printf ("Not initialized to zero (0x%08x).\n", *reg);
306	exit (999);
307	}
308	wrtest( reg, 0x5555aaaa, 0x0000aaaa);
309	wrtest( reg, 0xaaaa5555, 0x00005555);
310	*reg = 0;
311
312	printf( "Testing DMA_D2_PKTFLAG...\n");
313	reg = DMA_D2_PKTFLAG;
314	if( *reg) error( "Not initialized to zero.\n");
315	wrtest( reg, 0x5555aaaa, 0x5555aaaa);
316	wrtest( reg, 0xaaaa5555, 0xaaaa5555);
317	*reg = 0;
318
319	/* Initiate a non-chained 0-length transfer. */
320	printf ("\nPreparing for a DMA1 NORM transfer...\n");
321	reg = DMA_D_CTRL; /* enable DMA */
322	*reg = DMA_D_CTRL__DMAE;
323	reg = DMA_D1_QWC; /* set # of quad words to xfr */
324	*reg = 0;
325	reg = DMA_D1_MADR; /* set data address */
326	*reg = 0x00012340;
327	reg = DMA_D1_CHCR;
328	printf ("Ready...\n");
329	*reg = DMA_Dn_CHCR__STR \| DMA_Dn_CHCR__MOD_NORM;
330
331	reg = DMA_D1_QWC;
332	if (*reg)
333	{
334	printf ("D1_QWC is not zero after transfer.\n");
335	exit (999);
336	}
337	reg = DMA_D1_MADR;
338	if (*reg != 0x00012340)
339	{
340	printf ("D1_MADR value is wrong after transfer.\n");
341	exit (999);
342	}
343	reg = DMA_D1_CHCR;
344	if ((*reg & DMA_Dn_CHCR__STR) != 0)
345	{
346	printf ("D1_CHCR.STR is not reset after transfer.\n");
347	exit (999);
348	}
349	printf ("Completed OK...\n");
350
351	/* Initiate a chained transfer. */
352
353	/* Some of the "tag" fields couldn't be initialised statically. */
354	/* The first address is unaligned to force a warning. */
355	dma_refe.tagH = (unsigned)&data0 + 1;
356	dma_next.tagH = (unsigned)&dma_ref;
357	dma_ref.tagH = (unsigned)&data6;
358	dma_refs.tagH = (unsigned)&data7;
359	dma_call.tagH = (unsigned)&dma_cal2;
360	dma_cal2.tagH = (unsigned)&dma_rt2;
361
362	printf ("\nPreparing for a DMA0 TAG transfer...\n");
363	reg = DMA_D_PCR; /* disable DMA0 */
364	*reg &= ~DMA_D_PCR__CDE0;
365	*reg \|= DMA_D_PCR__PCE;
366	reg = DMA_D_CTRL; /* enable DMA */
367	*reg = DMA_D_CTRL__DMAE;
368	reg = DMA_D0_TADR; /* set tag address */
369	*reg = (unsigned) & dma_refe;
370	reg = DMA_D0_QWC; /* set fictitious count */
371	*reg = 51;
372	printf ("Ready...\n");
373	reg = DMA_D0_CHCR;
374	*reg = DMA_Dn_CHCR__STR \| DMA_Dn_CHCR__TTE \| DMA_Dn_CHCR__MOD_CHAIN;
375
376	reg = DMA_D0_QWC;
377	if (*reg != 51)
378	{
379	printf ("DMA0 transfer not inhibited by DMA_D_PCR__CDE0 (%d).\n", *reg);
380	exit (999);
381	}
382	reg = DMA_D_PCR; /* enable DMA0 */
383	*reg &= ~DMA_D_PCR__PCE;
384
385	reg = DMA_D0_QWC;
386	if (*reg)
387	{
388	printf ("D0_QWC is not zero after transfer.\n");
389	exit (999);
390	}
391	reg = DMA_D0_MADR;
392	if (*reg != (unsigned)&dma_cal2)
393	{
394	printf ("D0_MADR value is wrong after transfer.\n");
395	exit (999);
396	}
397	reg = DMA_D0_CHCR;
398	if ((*reg & DMA_Dn_CHCR__STR) != 0)
399	{
400	printf ("D0_CHCR.STR is not reset after transfer.\n");
401	exit (999);
402	}
403	printf ("Completed OK...\n");
404
405	/* Initiate a chained transfer that will be suspended
406	and restarted. */
407
408	/* Request suspension part way through. */
409	dma_ref.tagL \|= DMA_TAG_IRQ;
410
411	printf ("\nPreparing for a DMA2 TAG transfer with suspension...\n");
412	reg = DMA_D_CTRL; /* enable DMA */
413	*reg = DMA_D_CTRL__DMAE;
414	reg = DMA_D2_TADR; /* set tag address */
415	*reg = (unsigned) & dma_refe;
416	printf ("Ready...\n");
417	reg = DMA_D2_CHCR;
418	*reg = DMA_Dn_CHCR__STR \| DMA_Dn_CHCR__MOD_CHAIN;
419	printf ("returns...\n");
420
421	reg = DMA_D2_QWC;
422	if (*reg)
423	{
424	printf ("D2_QWC (0x%08x) is not zero after suspension.\n", *reg);
425	exit (999);
426	}
427	reg = DMA_D2_MADR;
428	if (*reg != (unsigned)&data7)
429	{
430	printf ("D2_MADR value (0x%08x) is wrong after suspension.\n", *reg);
431	exit (999);
432	}
433	reg = DMA_D2_TADR;
434	if (*reg != (unsigned)&dma_refs)
435	{
436	printf ("D2_TADR value (0x%08x) is wrong after suspension.\n", *reg);
437	exit (999);
438	}
439	reg = DMA_D2_CHCR;
440	if ((*reg & DMA_Dn_CHCR__STR) != 0)
441	{
442	printf ("D2_CHCR.STR (0x%08x) is not reset after suspension.\n", *reg);
443	exit (999);
444	}
445	reg = DMA_D_PCR;
446	if ((*reg & DMA_D_PCR__PCE) == 0)
447	{
448	printf ("DMA_D_PCR__PCE not set by transfer.\n");
449	exit (999);
450	}
451	printf ("Suspended OK...\n");
452
453	/* Reset the suspension request and continue. */
454	dma_ref.tagL &= ~DMA_TAG_IRQ;
455	reg = DMA_D2_CHCR;
456	*reg \|= DMA_Dn_CHCR__STR;
457
458	reg = DMA_D2_QWC;
459	if (*reg)
460	{
461	printf ("D2_QWC (0x%08x) is not zero after transfer.\n", *reg);
462	exit (999);
463	}
464	reg = DMA_D2_MADR;
465	if (*reg != (unsigned)&dma_cal2)
466	{
467	printf ("D2_MADR value (0x%08x) is wrong after transfer.\n", *reg);
468	exit (999);
469	}
470	reg = DMA_D2_CHCR;
471	if ((*reg & DMA_Dn_CHCR__STR) != 0)
472	{
473	printf ("D2_CHCR.STR (0x%08x) is not reset after transfer.\n", *reg);
474	exit (999);
475	}
476	reg = DMA_D_PCR;
477	if (*reg & DMA_D_PCR__PCE)
478	{
479	printf ("DMA_D_PCR__PCE not reset by transfer.\n");
480	exit (999);
481	}
482	printf ("Completed OK...\n");
483
484	exit (0);
485	}