projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Mon May 12 13:33:08 1997 H.J. Lu <hjl@gnu.ai.mit.edu>
[deliverable/binutils-gdb.git] / sim / tic80 / ChangeLog
CommitLineData
c445af5a
AC		 1Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
2
9af5dcea
AC		 3 * sim-calls.c (sim_stop_reason): Restore keep_running after a
4 CNTRL-C, don't re-clear it.
5
6 * interp.c (engine_error): stop rather than signal with SIGABRT
7 when an error.
8
c445af5a
AC		 9 * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
10 rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
11 (do_st): Converse for store.
12
13 * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
14
15Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
16
17 * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
18 was cleared.
19
20 * interp.c (engine_step): New function. Single step the simulator
21 taking care of cntrl-c during a step.
22
23 * sim-calls.c (sim_resume): Differentiate between stepping and
24 running so that a cntrl-c during a step is reported.
25
26Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
27
28 * sim-calls.c (sim_fetch_register): Use correct reg base.
29 (sim_store_register): Ditto.
30
450be234
MM		 31Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
32
33 * cpu.h (tic80_trace_shift): Add declaration.
34 (TRACE_SHIFT): New macro to trace shift instructions.
35
36 * misc.c (tic80_trace_alu2): Align spacing.
37 (tic80_trace_shift): New function to trace shifts.
38
39 * insns (lmo): Add missing 0b prefix to bits.
40 (do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT
41 instead of TRACE_ALU2.
42 (sl r): Use EndMask as is, instead of using Source+1 register.
43 (subu): Operands are unsigned, not signed.
8ad60788 44 (do_{ld,st}): Fix endian problems with ld.d/st.d.
450be234 45
20b2f9bc
MM		 46Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com>
47
48 * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
49 signed.
50
aaa7b252
MM		 51Fri May 9 15:47:36 1997 Mike Meissner <meissner@cygnus.com>
52
53 * insns (cmp_vals,do_cmp): Produce the correct bits as specified
54 by the architecture.
89d1a478 55 (xor): Fix xor immediate patterns to use the correct bits.
aaa7b252 56
9efd3f74
AC		 57Fri May 9 09:55:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
58
59 * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
60 the NIA when a 64bit insn.
61
e42224cc
MM		 62Thu May 8 11:57:47 1997 Michael Meissner <meissner@cygnus.com>
63
53dcd669
MM		 64 * insns (jsr,bsr): For non-allulled calls, set r31 so that the
65 return address does not reexecute the instruction in the delay
66 slot.
c3cad878
MM		 67 (bbo,bbz): Complement bit number to reverse the one's complement
68 that the assembler is required to do.
53dcd669 69
8c3b5af1
MM		 70 * misc.c (tic80_trace_*): Change format slightly to accomidate
71 real large decimal values.
e42224cc 72
43c53e07
AC		 73Thu May 8 14:07:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
74
75 * sim-calls.c (sim_do_command): Implement.
76 (sim_store_register): Fix typo T2H v H2T.
77
381f42ef
AC		 78Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
79
80 * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
81 * insn: Clean up fpu tracing.
82
83 * sim-calls.c (sim_create_inferior): Start out with interrupts
84 enabled.
85
86 * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
87 sink
88
89 * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
90
91 * insns (do_*): Remove MY_INDEX/indx argument from support functions,
92 igen now handles this.
93
94 * cpu.h (CR): New macro - access TIc80 control registers.
95
96 * misc.c: New file.
97 (tic80_cr2index): New function, map control register opcode index
98 into the internal CR enum.
99
100 * interp.c
101 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
102 here
103 * misc.c: to here.
104
105 * Makefile.in (SIM_OBJS): Add misc.o.
106
7b167b09
MM		 107Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com>
108
109 * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
110 big endian hosts.
111 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
112 new functions.
113 (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
114 trace various instruction types.
115
116 * insns: Modify all instructions to support semantic tracing.
117
118 * interp.c (toplevel): Include itable.h.
119 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
120 functions to provide semantic level tracing information.
121
7a418800
AC		 122Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
123
124 * alu.h: Update usage of core object to reflect recent changes in
125 ../common/sim-*core.
126 * sim-calls.c (sim_open): Ditto.
127
3971886a
AC		 128Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
129
130 * insn (cmnd): No-op cache flushes.
131
132 * insns (do_trap): Allow writes to STDERR.
133
134 * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
135 (SIM_EXTRA_LIBS): Link in the math library.
136
137 * alu.h: Add support for floating point unit using sim-alu.
138
139 * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
140
d9b75947
AC		 141Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
142
143 * sim-calls.c: Include sim-utils.h and sim-options.h.
144
145 * sim-main.h (sim_state): Drop sim_events and sim_core members,
146 moved to simulator base type.
147
148 * alu.h (IMEM, MEM, STORE): Update track changes in common
149 directory.
150
151 * insns: Drop cia argument from functions, igen now handles this.
152
153 * interp.c (engine_init): Include string.h/strings.h to define
154 memset et.al.
155
156 * sim-main.h (sim_cia): Delcare, tracking common dir changes.
157
158 * cpu.h (sim_cpu): Update instruction_address with sim_cia.
159
c1c77d40
AC		 160Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
161
162 * sim-main.h (signal.h): Include so that SIG* available to all
163 callers of sig_halt.
164
165 * insns (do_shift): New function, implement shift operations.
166 (do_trap): Add handler for trap 73 - SIGTRAP.
167
d5e2c74e
AC		 168Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
169
170 * alu.h (MEM, STORE): Force addresses to be correctly aligned.
171
172 * insns (do_jsr): Fix.
173 (do_st, do_ld): Handle 64bit transfers.
174 (do_trap): Match libgloss.
175 (rdcr): Implement nop - Dest == r0 - variant.
176
177 * sim-calls.c (sim_create_inferior): Initialize SP.
178
179 * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
180 (support.o): Depends on ENGINE_H.
181
182 * cpu.h: Four accumulators.
183
184 * Makefile.in (tmp-igen): Include line number information in
185 generated files.
186
187 * insns (dld, dst): Fill in.
188
189Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
190
191 * insns (vld): Fix instruction format wrong.
192
abe293a0
AC		 193Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
194
195 * dc: Add additional rules so that minor opcode files are
196 detected.
197 * insns: Enable more instructions.
198
199 * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
200 Implement.
201
dd442a44
DE		 202Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
203
204 * configure: Regenerated to track ../common/aclocal.m4 changes.
205 * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
206 * sim-calls.c (sim_open): Call sim_module_uninstall if argument
207 parsing fails. Call sim_post_argv_init.
208 (sim_close): Call sim_module_uninstall.
209
480e740c
AC		 210Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
211
212 * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
213 * ic: Add fields for enabled instructions.
214
GDB Binutils - Deliverables
This page took 0.032402 seconds and 4 git commands to generate.