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d5e2c74e AC |
1 | /* TIc80 Simulator. |
2 | Copyright (C) 1997 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Support. | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | ||
22 | ||
d9b75947 | 23 | struct _sim_cpu { |
abe293a0 | 24 | unsigned32 reg[32]; |
d5e2c74e | 25 | unsigned64 acc[4]; |
d9b75947 | 26 | sim_cia cia; |
abe293a0 | 27 | sim_cpu_base base; |
d9b75947 | 28 | }; |
15c16493 AC |
29 | |
30 | #define GPR(N) ((CPU)->reg[N]) | |
abe293a0 | 31 | #define ACC(N) ((CPU)->acc[N]) |
3971886a | 32 | |
7b167b09 MM |
33 | #if defined(WITH_TRACE) |
34 | extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32)); | |
35 | extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32)); | |
36 | extern char *tic80_trace_nop PARAMS ((int)); | |
37 | extern char *tic80_trace_sink1 PARAMS ((int, unsigned32)); | |
38 | extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32)); | |
39 | extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32)); | |
40 | extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32)); | |
41 | extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32)); | |
42 | ||
43 | #define TRACE_ALU3(indx, result, input1, input2) \ | |
44 | do { \ | |
45 | if (TRACE_ALU_P (CPU)) { \ | |
46 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
47 | itable[indx].line_nr, "alu", \ | |
48 | tic80_trace_alu3 (indx, result, input1, input2)); \ | |
49 | } \ | |
50 | } while (0) | |
51 | ||
52 | #define TRACE_ALU2(indx, result, input) \ | |
53 | do { \ | |
54 | if (TRACE_ALU_P (CPU)) { \ | |
55 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
56 | itable[indx].line_nr, "alu", \ | |
57 | tic80_trace_alu2 (indx, result, input)); \ | |
58 | } \ | |
59 | } while (0) | |
60 | ||
61 | #define TRACE_NOP(indx) \ | |
62 | do { \ | |
63 | if (TRACE_ALU_P (CPU)) { \ | |
64 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
65 | itable[indx].line_nr, "nop", \ | |
66 | tic80_trace_nop (indx)); \ | |
67 | } \ | |
68 | } while (0) | |
69 | ||
70 | #define TRACE_SINK1(indx, input) \ | |
71 | do { \ | |
72 | if (TRACE_ALU_P (CPU)) { \ | |
73 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
74 | itable[indx].line_nr, "nop", \ | |
75 | tic80_trace_sink1 (indx, input)); \ | |
76 | } \ | |
77 | } while (0) | |
78 | ||
79 | #define TRACE_SINK2(indx, input1, input2) \ | |
80 | do { \ | |
81 | if (TRACE_ALU_P (CPU)) { \ | |
82 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
83 | itable[indx].line_nr, "nop", \ | |
84 | tic80_trace_sink2 (indx, input1, input2)); \ | |
85 | } \ | |
86 | } while (0) | |
87 | ||
88 | #define TRACE_COND_BR(indx, jump_p, cond, target) \ | |
89 | do { \ | |
90 | if (TRACE_BRANCH_P (CPU)) { \ | |
91 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
92 | itable[indx].line_nr, "branch", \ | |
93 | tic80_trace_cond_br (indx, jump_p, cond, target)); \ | |
94 | } \ | |
95 | } while (0) | |
96 | ||
97 | #define TRACE_UCOND_BR(indx, target) \ | |
98 | do { \ | |
99 | if (TRACE_ALU_P (CPU)) { \ | |
100 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
101 | itable[indx].line_nr, "branch", \ | |
102 | tic80_trace_ucond_br (indx, target)); \ | |
103 | } \ | |
104 | } while (0) | |
105 | ||
106 | #define TRACE_LD(indx, result, m, s, addr1, addr2) \ | |
107 | do { \ | |
108 | if (TRACE_MEMORY_P (CPU)) { \ | |
109 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
110 | itable[indx].line_nr, "memory", \ | |
111 | tic80_trace_ldst (indx, 0, m, s, result, \ | |
112 | addr1, addr2)); \ | |
113 | } \ | |
114 | } while (0) | |
115 | ||
116 | #define TRACE_ST(indx, value, m, s, addr1, addr2) \ | |
117 | do { \ | |
118 | if (TRACE_MEMORY_P (CPU)) { \ | |
119 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
120 | itable[indx].line_nr, "memory", \ | |
121 | tic80_trace_ldst (indx, 1, m, s, value, \ | |
122 | addr1, addr2)); \ | |
123 | } \ | |
124 | } while (0) | |
125 | ||
126 | #else | |
127 | #define TRACE_ALU3(indx, result, input1, input2) | |
128 | #define TRACE_ALU2(indx, result, input) | |
129 | #define TRACE_NOP(indx) | |
130 | #define TRACE_SINK1(indx, input) | |
131 | #define TRACE_SINK2(indx, input1, input2) | |
132 | #define TRACE_COND_BR(indx, jump_p, cond, target) | |
133 | #define TRACE_UCOND_BR(indx, target) | |
134 | #define TRACE_LD(indx, m, s, result, addr1, addr2) | |
135 | #define TRACE_ST(indx, m, s, value, addr1, addr2) | |
136 | #endif |