projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| d81352b8 JL |
1 | Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com) |
| 2 | ||
| 3 | * interp.c: OP should be an array of 32bit operands! | |
| 4 | (v850_callback): Declare. | |
| 5 | (do_format_5): Fix extraction of OP[0]. | |
| 6 | (sim_size): Remove debugging printf. | |
| 7 | (sim_set_callbacks): Do something useful. | |
| 8 | (sim_stop_reason): Gross hacks to get c-torture running. | |
| 9 | * simops.c: Simplify code for computing targets of bCC | |
| 10 | insns. Invert 's' bit if 'ov' bit is set for some | |
| 11 | instructions. Fix 'cy' bit handling for numerous | |
| 12 | instructions. Make the simulator stop when a halt | |
| 13 | instruction is encountered. Very crude support for | |
| 14 | emulated syscalls (trap 0). | |
| 15 | * v850_sim.h: Include "callback.h" and declare | |
| 16 | v850_callback. Items in the operand array are 32bits. | |
| 17 | ||
| 18 | Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com) | |
| 19 | ||
| 20 | * interp.c (sim_resume): Fix code to check for a format 3 | |
| 21 | opcode. | |
| 22 | * simops.c: bCC insns only argument is a constant, not a | |
| 23 | register value (duh...) | |
| 24 | ||
| 83fc3bac JL |
25 | Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com) |
| 26 | ||
| 787d66bb JL |
27 | * simops.c: Fix "not1" and "set1". |
| 28 | ||
| 3046d879 JL |
29 | * simops.c: Don't forget to initialize temp for |
| 30 | "ld.h" and "ld.w" | |
| 31 | ||
| ba853302 JL |
32 | * interp.c: Remove various debugging printfs. |
| 33 | ||
| 0e4ccc58 JL |
34 | * simops.c: Fix satadd, satsub boundary case handling. |
| 35 | ||
| 83fc3bac JL |
36 | * interp.c (hash): Fix. |
| 37 | * interp.c (do_format_8): Get operands correctly and | |
| 38 | call the target function. | |
| 39 | * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1". | |
| 40 | ||
| 1fe983dc JL |
41 | Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com) |
| 42 | ||
| 3cb6bf78 JL |
43 | * interp.c (do_format_4): Get operands correctly and |
| 44 | call the target function. | |
| 45 | * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b", | |
| 46 | "sst.h", and "sst.w". | |
| 47 | ||
| 28647e4c JL |
48 | * v850_sim.h: The V850 doesn't have split I&D spaces. Change |
| 49 | accordingly. Remove many unused definitions. | |
| 50 | * interp.c: The V850 doesn't have split I&D spaces. Change | |
| 51 | accordingly. | |
| 52 | (get_longlong, get_longword, get_word): Deleted. | |
| 53 | (write_longlong, write_longword, write_word): Deleted. | |
| 54 | (get_operands): Deleted. | |
| 55 | (get_byte, get_half, get_word): New functions. | |
| 56 | (put_byte, put_half, put_word): New functions. | |
| 57 | * simops.c: Remove unused functions. Rough cut at | |
| 58 | "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns. | |
| 59 | ||
| 614f1c68 JL |
60 | * v850_sim.h (struct _state): Remove "psw" field. Add |
| 61 | "sregs" field. | |
| 62 | (PSW): Remove bogus definition. | |
| 63 | * simops.c: Change condition code handling to use the psw | |
| 64 | register within the sregs array. Handle "ldsr" and "stsr". | |
| 65 | ||
| dca41ba7 JL |
66 | * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr". |
| 67 | ||
| e9b6cbac JL |
68 | * interp.c (do_format_5): Get operands correctly and |
| 69 | call the target function. | |
| 70 | (sim_resume): Don't do a PC update for format 5 instructions. | |
| 71 | * simops.c: Handle "jarl" and "jmp" instructions. | |
| 72 | ||
| 3095b8df JL |
73 | * simops.c: Fix minor typos. Handle "cmp", "setf", "tst" |
| 74 | "di", and "ei" instructions correctly. | |
| 75 | ||
| 2108e864 JL |
76 | * interp.c (do_format_3): Get operands correctly and call |
| 77 | the target function. | |
| 78 | * simops.c: Handle bCC instructions. | |
| 79 | ||
| 35404c7d JL |
80 | * simops.c: Add condition code handling to shift insns. |
| 81 | Fix minor typos in condition code handling for other insns. | |
| 82 | ||
| aabce0f4 JL |
83 | * Makefile.in: Fix typo. |
| 84 | * simops.c: Add condition code handling to "sub" "subr" and | |
| 85 | "divh" instructions. | |
| 86 | ||
| 0ef0eba5 JL |
87 | * interp.c (hash): Update to be more accurate. |
| 88 | (lookup_hash): Call hash rather than computing the hash | |
| 89 | code here. | |
| 90 | (do_format_1_2): Handle format 1 and format 2 instructions. | |
| 91 | Get operands correctly and call the target function. | |
| 92 | (do_format_6): Get operands correctly and call the target | |
| 93 | function. | |
| 94 | (do_formats_9_10): Rough cut so shift ops will work. | |
| 95 | (sim_resume): Tweak to deal with format 1 and format 2 | |
| 96 | handling in a single funtion. Don't update the PC | |
| 97 | for format 3 insns. Fix typos. | |
| 98 | * simops.c: Slightly reorganize. Add condition code handling | |
| 99 | to "add", "addi", "and", "andi", "or", "ori", "xor", "xori" | |
| 100 | and "not" instructions. | |
| 101 | * v850_sim.h (reg_t): Registers are 32bits. | |
| 102 | (_state): The V850 has 32 general registers. Add a 32bit | |
| 103 | psw and pc register too. Add accessor macros | |
| 104 | ||
| 105 | * Makefile.in, interp.c, v850_sim.h: Bring over endianness | |
| 106 | changes from the d10v simulator. | |
| 107 | ||
| 77553374 JL |
108 | * simops.c: Add shift support. |
| 109 | ||
| e98e3b2c JL |
110 | * simops.c: Add multiply & divide support. Abort for system |
| 111 | instructions. | |
| 112 | ||
| 1fe983dc JL |
113 | * simops.c: Add logicals, mov, movhi, movea, add, addi, sub |
| 114 | and subr. No condition codes yet. | |
| 115 | ||
| 22c1c7dd JL |
116 | Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com) |
| 117 | ||
| 118 | * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h, | |
| 119 | gencode.c, interp.c, simops.c: Created. | |
| 120 |