Commit | Line | Data |
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c906108c SS |
1 | :option:::insn-bit-size:16 |
2 | :option:::hi-bit-nr:15 | |
3 | ||
4 | ||
5 | :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X | |
6 | :option:::format-names:XI,XII,XIII | |
7 | :option:::format-names:XIV,XV | |
8 | :option:::format-names:Z | |
2aaed979 | 9 | :option:::format-names:F_I |
c906108c SS |
10 | |
11 | ||
12 | :model:::v850:v850: | |
13 | ||
14 | :option:::multi-sim:true | |
15 | :model:::v850e:v850e: | |
c5ea1d53 NC |
16 | :option:::multi-sim:true |
17 | :model:::v850e1:v850e1: | |
2aaed979 KB |
18 | :option:::multi-sim:true |
19 | :model:::v850e2:v850e2: | |
20 | :option:::multi-sim:true | |
21 | :model:::v850e2v3:v850e2v3: | |
c906108c | 22 | |
c906108c SS |
23 | // Cache macros |
24 | ||
25 | :cache:::unsigned:reg1:RRRRR:(RRRRR) | |
26 | :cache:::unsigned:reg2:rrrrr:(rrrrr) | |
27 | :cache:::unsigned:reg3:wwwww:(wwwww) | |
d99ff40f | 28 | :cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1)) |
2aaed979 KB |
29 | |
30 | :cache:::unsigned:reg1e:RRRR:(RRRR << 1) | |
31 | :cache:::unsigned:reg2e:rrrr:(rrrr << 1) | |
32 | :cache:::unsigned:reg3e:wwww:(wwww << 1) | |
33 | :cache:::unsigned:reg4e:mmmm:(mmmm << 1) | |
c906108c SS |
34 | |
35 | :cache:::unsigned:disp4:dddd:(dddd) | |
36 | :cache:::unsigned:disp5:dddd:(dddd << 1) | |
37 | :cache:::unsigned:disp7:ddddddd:ddddddd | |
38 | :cache:::unsigned:disp8:ddddddd:(ddddddd << 1) | |
39 | :cache:::unsigned:disp8:dddddd:(dddddd << 2) | |
40 | :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) | |
41 | :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd) | |
42 | :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1) | |
2aaed979 | 43 | :cache:::unsigned:disp17:d,ddddddddddddddd:SEXT32 (((d <<16) + (ddddddddddddddd << 1)), 17 - 1) |
c906108c | 44 | :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1) |
2aaed979 KB |
45 | :cache:::unsigned:disp23:ddddddd,dddddddddddddddd: SEXT32 ((ddddddd) + (dddddddddddddddd << 7), 23 - 1) |
46 | :cache:::unsigned:disp23:dddddd,dddddddddddddddd: SEXT32 ((dddddd << 1) + (dddddddddddddddd << 7), 23 - 1) | |
c906108c SS |
47 | |
48 | :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4) | |
49 | :cache:::unsigned:imm6:iiiiii:iiiiii | |
50 | :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1) | |
51 | :cache:::unsigned:imm5:iiii:(32 - (iiii << 1)) | |
52 | :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii) | |
53 | :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii | |
54 | :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII) | |
55 | :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd) | |
56 | ||
57 | :cache:::unsigned:vector:iiiii:iiiii | |
58 | ||
59 | :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL) | |
60 | :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL) | |
61 | ||
62 | :cache:::unsigned:bit3:bbb:bbb | |
2aaed979 | 63 | :cache:::unsigned:bit4:bbbb:bbbb |
c906108c SS |
64 | |
65 | ||
66 | // What do we do with an illegal instruction? | |
67 | :internal::::illegal: | |
68 | { | |
69 | sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", | |
70 | (unsigned long) cia); | |
71 | sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); | |
72 | } | |
73 | ||
74 | ||
75 | ||
2aaed979 | 76 | // ADD |
c906108c SS |
77 | rrrrr,001110,RRRRR:I:::add |
78 | "add r<reg1>, r<reg2>" | |
79 | { | |
80 | COMPAT_1 (OP_1C0 ()); | |
81 | } | |
82 | ||
83 | rrrrr,010010,iiiii:II:::add | |
84 | "add <imm5>,r<reg2>" | |
85 | { | |
86 | COMPAT_1 (OP_240 ()); | |
87 | } | |
88 | ||
89 | ||
90 | ||
91 | // ADDI | |
92 | rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi | |
93 | "addi <simm16>, r<reg1>, r<reg2>" | |
94 | { | |
95 | COMPAT_2 (OP_600 ()); | |
96 | } | |
97 | ||
98 | ||
99 | ||
2aaed979 KB |
100 | // ADF |
101 | rrrrr,111111,RRRRR + wwwww,011101,cccc!13,0:XI:::adf | |
102 | *v850e2 | |
103 | *v850e2v3 | |
104 | "adf %s<cccc>, r<reg1>, r<reg2>, r<reg3>" | |
105 | { | |
106 | int cond = condition_met (cccc); | |
107 | TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); | |
108 | GR[reg3] = GR[reg1] + GR[reg2] + (cond ? 1 : 0); | |
109 | TRACE_ALU_RESULT1 (GR[reg3]); | |
110 | } | |
111 | ||
112 | ||
113 | ||
c906108c SS |
114 | // AND |
115 | rrrrr,001010,RRRRR:I:::and | |
116 | "and r<reg1>, r<reg2>" | |
117 | { | |
118 | COMPAT_1 (OP_140 ()); | |
119 | } | |
120 | ||
121 | ||
122 | ||
123 | // ANDI | |
124 | rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi | |
125 | "andi <uimm16>, r<reg1>, r<reg2>" | |
126 | { | |
127 | COMPAT_2 (OP_6C0 ()); | |
128 | } | |
129 | ||
130 | ||
131 | ||
132 | // Map condition code to a string | |
133 | :%s::::cccc:int cccc | |
134 | { | |
135 | switch (cccc) | |
136 | { | |
137 | case 0xf: return "gt"; | |
138 | case 0xe: return "ge"; | |
139 | case 0x6: return "lt"; | |
140 | ||
141 | case 0x7: return "le"; | |
142 | ||
143 | case 0xb: return "h"; | |
144 | case 0x9: return "nl"; | |
145 | case 0x1: return "l"; | |
146 | ||
147 | case 0x3: return "nh"; | |
148 | ||
149 | case 0x2: return "e"; | |
150 | ||
151 | case 0xa: return "ne"; | |
152 | ||
153 | case 0x0: return "v"; | |
154 | case 0x8: return "nv"; | |
155 | case 0x4: return "n"; | |
156 | case 0xc: return "p"; | |
157 | /* case 0x1: return "c"; */ | |
158 | /* case 0x9: return "nc"; */ | |
159 | /* case 0x2: return "z"; */ | |
160 | /* case 0xa: return "nz"; */ | |
161 | case 0x5: return "r"; /* always */ | |
162 | case 0xd: return "sa"; | |
163 | } | |
164 | return "(null)"; | |
165 | } | |
166 | ||
167 | ||
168 | // Bcond | |
169 | ddddd,1011,ddd,cccc:III:::Bcond | |
170 | "b%s<cccc> <disp9>" | |
171 | { | |
b9791fcd FCE |
172 | int cond; |
173 | if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) { | |
174 | // Special case - treat "br *" like illegal instruction | |
175 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
176 | } else { | |
177 | cond = condition_met (cccc); | |
178 | if (cond) | |
179 | nia = cia + disp9; | |
180 | TRACE_BRANCH1 (cond); | |
181 | } | |
c906108c SS |
182 | } |
183 | ||
2aaed979 KB |
184 | 00000111111,d,cccc + ddddddddddddddd,1:VII:::Bcond |
185 | "breakpoint":((disp17 == 0) && (cccc == 0x05)) | |
186 | "b%s<cccc> <disp17>" | |
187 | *v850e2v3 | |
188 | { | |
189 | int cond; | |
190 | cond = condition_met (cccc); | |
191 | if (cond) | |
192 | nia = cia + disp17; | |
193 | TRACE_BRANCH_INPUT1 (cond); | |
194 | TRACE_BRANCH_RESULT (nia); | |
195 | } | |
196 | ||
c906108c SS |
197 | |
198 | ||
199 | // BSH | |
200 | rrrrr,11111100000 + wwwww,01101000010:XII:::bsh | |
201 | *v850e | |
c5ea1d53 | 202 | *v850e1 |
2aaed979 KB |
203 | *v850e2 |
204 | *v850e2v3 | |
c906108c SS |
205 | "bsh r<reg2>, r<reg3>" |
206 | { | |
207 | unsigned32 value; | |
208 | TRACE_ALU_INPUT1 (GR[reg2]); | |
209 | ||
210 | value = (MOVED32 (GR[reg2], 23, 16, 31, 24) | |
211 | | MOVED32 (GR[reg2], 31, 24, 23, 16) | |
212 | | MOVED32 (GR[reg2], 7, 0, 15, 8) | |
213 | | MOVED32 (GR[reg2], 15, 8, 7, 0)); | |
214 | ||
215 | GR[reg3] = value; | |
216 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
c5fbc25b | 217 | if ((value & 0xffff) == 0) PSW |= PSW_Z; |
c906108c | 218 | if (value & 0x80000000) PSW |= PSW_S; |
c5fbc25b | 219 | if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY; |
c906108c SS |
220 | |
221 | TRACE_ALU_RESULT (GR[reg3]); | |
222 | } | |
223 | ||
2aaed979 KB |
224 | |
225 | ||
c906108c SS |
226 | // BSW |
227 | rrrrr,11111100000 + wwwww,01101000000:XII:::bsw | |
228 | *v850e | |
c5ea1d53 | 229 | *v850e1 |
2aaed979 KB |
230 | *v850e2 |
231 | *v850e2v3 | |
c906108c SS |
232 | "bsw r<reg2>, r<reg3>" |
233 | { | |
234 | #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) | |
235 | unsigned32 value; | |
236 | TRACE_ALU_INPUT1 (GR[reg2]); | |
237 | ||
238 | value = GR[reg2]; | |
239 | value >>= 24; | |
240 | value |= (GR[reg2] << 24); | |
241 | value |= ((GR[reg2] << 8) & 0x00ff0000); | |
242 | value |= ((GR[reg2] >> 8) & 0x0000ff00); | |
243 | GR[reg3] = value; | |
244 | ||
245 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
246 | ||
247 | if (value == 0) PSW |= PSW_Z; | |
248 | if (value & 0x80000000) PSW |= PSW_S; | |
249 | if (WORDHASNULLBYTE (value)) PSW |= PSW_CY; | |
250 | ||
251 | TRACE_ALU_RESULT (GR[reg3]); | |
252 | } | |
253 | ||
2aaed979 KB |
254 | |
255 | ||
c906108c SS |
256 | // CALLT |
257 | 0000001000,iiiiii:II:::callt | |
258 | *v850e | |
c5ea1d53 | 259 | *v850e1 |
2aaed979 KB |
260 | *v850e2 |
261 | *v850e2v3 | |
c906108c SS |
262 | "callt <imm6>" |
263 | { | |
264 | unsigned32 adr; | |
265 | unsigned32 off; | |
266 | CTPC = cia + 2; | |
267 | CTPSW = PSW; | |
268 | adr = (CTBP & ~1) + (imm6 << 1); | |
269 | off = load_mem (adr, 2) & ~1; /* Force alignment */ | |
270 | nia = (CTBP & ~1) + off; | |
271 | TRACE_BRANCH3 (adr, CTBP, off); | |
272 | } | |
273 | ||
274 | ||
2aaed979 KB |
275 | |
276 | // CAXI | |
277 | rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi | |
278 | *v850e2 | |
279 | *v850e2v3 | |
280 | "caxi [reg1], reg2, reg3" | |
281 | { | |
282 | unsigned int z,s,cy,ov; | |
283 | unsigned32 addr; | |
284 | unsigned32 token,result; | |
285 | ||
286 | addr = GR[reg1]; | |
287 | ||
288 | if (mpu_load_mem_test(sd, addr, 4, reg1) | |
289 | && mpu_store_mem_test(sd, addr, 4, reg1)) | |
290 | { | |
291 | token = load_data_mem (sd, addr, 4); | |
292 | ||
293 | TRACE_ALU_INPUT2 (token, GR[reg2]); | |
294 | ||
295 | result = GR[reg2] - token; | |
296 | ||
297 | z = (result == 0); | |
298 | s = (result & 0x80000000); | |
299 | cy = (GR[reg2] < token); | |
300 | ov = ((GR[reg2] & 0x80000000) != (token & 0x80000000) | |
301 | && (GR[reg2] & 0x80000000) != (result & 0x80000000)); | |
302 | ||
303 | if (result == 0) | |
304 | { | |
305 | store_data_mem (sd, addr, 4, GR[reg3]); | |
306 | GR[reg3] = token; | |
307 | } | |
308 | else | |
309 | { | |
310 | store_data_mem (sd, addr, 4, token); | |
311 | GR[reg3] = token; | |
312 | } | |
313 | ||
314 | /* Set condition codes. */ | |
315 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
316 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
317 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
318 | ||
319 | TRACE_ALU_RESULT1 (GR[reg3]); | |
320 | } | |
321 | } | |
322 | ||
323 | ||
c906108c SS |
324 | // CLR1 |
325 | 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1 | |
326 | "clr1 <bit3>, <disp16>[r<reg1>]" | |
327 | { | |
328 | COMPAT_2 (OP_87C0 ()); | |
329 | } | |
330 | ||
331 | rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 | |
332 | *v850e | |
c5ea1d53 | 333 | *v850e1 |
2aaed979 KB |
334 | *v850e2 |
335 | *v850e2v3 | |
c906108c SS |
336 | "clr1 r<reg2>, [r<reg1>]" |
337 | { | |
338 | COMPAT_2 (OP_E407E0 ()); | |
339 | } | |
340 | ||
341 | ||
2aaed979 | 342 | |
c906108c SS |
343 | // CTRET |
344 | 0000011111100000 + 0000000101000100:X:::ctret | |
345 | *v850e | |
c5ea1d53 | 346 | *v850e1 |
2aaed979 KB |
347 | *v850e2 |
348 | *v850e2v3 | |
c906108c SS |
349 | "ctret" |
350 | { | |
351 | nia = (CTPC & ~1); | |
352 | PSW = (CTPSW & (CPU)->psw_mask); | |
353 | TRACE_BRANCH1 (PSW); | |
354 | } | |
355 | ||
2aaed979 KB |
356 | |
357 | ||
c906108c SS |
358 | // CMOV |
359 | rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov | |
360 | *v850e | |
c5ea1d53 | 361 | *v850e1 |
2aaed979 KB |
362 | *v850e2 |
363 | *v850e2v3 | |
c906108c SS |
364 | "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>" |
365 | { | |
366 | int cond = condition_met (cccc); | |
367 | TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); | |
368 | GR[reg3] = cond ? GR[reg1] : GR[reg2]; | |
369 | TRACE_ALU_RESULT (GR[reg3]); | |
370 | } | |
371 | ||
372 | rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov | |
373 | *v850e | |
c5ea1d53 | 374 | *v850e1 |
2aaed979 KB |
375 | *v850e2 |
376 | *v850e2v3 | |
c906108c SS |
377 | "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>" |
378 | { | |
379 | int cond = condition_met (cccc); | |
380 | TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]); | |
381 | GR[reg3] = cond ? imm5 : GR[reg2]; | |
382 | TRACE_ALU_RESULT (GR[reg3]); | |
383 | } | |
384 | ||
2aaed979 KB |
385 | |
386 | ||
c906108c SS |
387 | // CMP |
388 | rrrrr,001111,RRRRR:I:::cmp | |
389 | "cmp r<reg1>, r<reg2>" | |
390 | { | |
391 | COMPAT_1 (OP_1E0 ()); | |
392 | } | |
393 | ||
394 | rrrrr,010011,iiiii:II:::cmp | |
395 | "cmp <imm5>, r<reg2>" | |
396 | { | |
397 | COMPAT_1 (OP_260 ()); | |
398 | } | |
399 | ||
400 | ||
401 | ||
402 | // DI | |
403 | 0000011111100000 + 0000000101100000:X:::di | |
404 | "di" | |
405 | { | |
406 | COMPAT_2 (OP_16007E0 ()); | |
407 | } | |
408 | ||
409 | ||
410 | ||
411 | // DISPOSE | |
412 | // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose | |
413 | // "dispose <imm5>, <list12>" | |
414 | 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose | |
415 | *v850e | |
c5ea1d53 | 416 | *v850e1 |
2aaed979 KB |
417 | *v850e2 |
418 | *v850e2v3 | |
c906108c SS |
419 | "dispose <imm5>, <list12>":RRRRR == 0 |
420 | "dispose <imm5>, <list12>, [reg1]" | |
421 | { | |
422 | int i; | |
423 | SAVE_2; | |
424 | ||
425 | trace_input ("dispose", OP_PUSHPOP1, 0); | |
426 | ||
427 | SP += (OP[3] & 0x3e) << 1; | |
428 | ||
429 | /* Load the registers with lower number registers being retrieved | |
430 | from higher addresses. */ | |
431 | for (i = 12; i--;) | |
432 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
433 | { | |
434 | State.regs[ 20 + i ] = load_mem (SP, 4); | |
435 | SP += 4; | |
436 | } | |
437 | ||
438 | if ((OP[3] & 0x1f0000) != 0) | |
439 | { | |
440 | nia = State.regs[ (OP[3] >> 16) & 0x1f]; | |
441 | } | |
442 | ||
443 | trace_output (OP_PUSHPOP1); | |
444 | } | |
445 | ||
446 | ||
2aaed979 | 447 | |
c906108c SS |
448 | // DIV |
449 | rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div | |
450 | *v850e | |
c5ea1d53 | 451 | *v850e1 |
2aaed979 KB |
452 | *v850e2 |
453 | *v850e2v3 | |
c906108c SS |
454 | "div r<reg1>, r<reg2>, r<reg3>" |
455 | { | |
456 | COMPAT_2 (OP_2C007E0 ()); | |
457 | } | |
458 | ||
459 | ||
460 | // DIVH | |
461 | rrrrr!0,000010,RRRRR!0:I:::divh | |
462 | "divh r<reg1>, r<reg2>" | |
463 | { | |
ebc115b7 NC |
464 | unsigned32 ov, s, z; |
465 | signed long int op0, op1, result; | |
466 | ||
467 | trace_input ("divh", OP_REG_REG, 0); | |
468 | ||
469 | PC = cia; | |
470 | OP[0] = instruction_0 & 0x1f; | |
471 | OP[1] = (instruction_0 >> 11) & 0x1f; | |
472 | ||
473 | /* Compute the result. */ | |
474 | op0 = EXTEND16 (State.regs[OP[0]]); | |
475 | op1 = State.regs[OP[1]]; | |
476 | ||
98e460c3 | 477 | if (op0 == -1 && op1 == 0x80000000) |
ebc115b7 | 478 | { |
c5fbc25b DD |
479 | PSW &= ~PSW_Z; |
480 | PSW |= PSW_OV | PSW_S; | |
481 | State.regs[OP[1]] = 0x80000000; | |
ebc115b7 | 482 | } |
c5fbc25b | 483 | else if (op0 == 0) |
ebc115b7 | 484 | { |
c5fbc25b | 485 | PSW |= PSW_OV; |
ebc115b7 NC |
486 | } |
487 | else | |
488 | { | |
98e460c3 | 489 | result = (signed32) op1 / op0; |
c5fbc25b DD |
490 | ov = 0; |
491 | ||
492 | /* Compute the condition codes. */ | |
493 | z = (result == 0); | |
494 | s = (result & 0x80000000); | |
ebc115b7 | 495 | |
c5fbc25b DD |
496 | /* Store the result and condition codes. */ |
497 | State.regs[OP[1]] = result; | |
498 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
499 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); | |
500 | } | |
ebc115b7 NC |
501 | |
502 | trace_output (OP_REG_REG); | |
503 | ||
504 | PC += 2; | |
505 | nia = PC; | |
c906108c SS |
506 | } |
507 | ||
508 | rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh | |
509 | *v850e | |
c5ea1d53 | 510 | *v850e1 |
2aaed979 KB |
511 | *v850e2 |
512 | *v850e2v3 | |
c906108c SS |
513 | "divh r<reg1>, r<reg2>, r<reg3>" |
514 | { | |
515 | COMPAT_2 (OP_28007E0 ()); | |
516 | } | |
517 | ||
518 | ||
519 | // DIVHU | |
520 | rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu | |
521 | *v850e | |
c5ea1d53 | 522 | *v850e1 |
2aaed979 KB |
523 | *v850e2 |
524 | *v850e2v3 | |
c906108c SS |
525 | "divhu r<reg1>, r<reg2>, r<reg3>" |
526 | { | |
527 | COMPAT_2 (OP_28207E0 ()); | |
528 | } | |
529 | ||
530 | ||
531 | // DIVU | |
532 | rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu | |
533 | *v850e | |
c5ea1d53 | 534 | *v850e1 |
2aaed979 KB |
535 | *v850e2 |
536 | *v850e2v3 | |
c906108c SS |
537 | "divu r<reg1>, r<reg2>, r<reg3>" |
538 | { | |
539 | COMPAT_2 (OP_2C207E0 ()); | |
540 | } | |
541 | ||
542 | ||
2aaed979 KB |
543 | // DIVQ |
544 | rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq | |
545 | *v850e2 | |
546 | *v850e2v3 | |
547 | "divq r<reg1>, r<reg2>, r<reg3>" | |
548 | { | |
549 | unsigned int quotient; | |
550 | unsigned int remainder; | |
551 | unsigned int divide_by; | |
552 | unsigned int divide_this; | |
553 | ||
554 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
555 | ||
556 | divide_by = GR[reg1]; | |
557 | divide_this = GR[reg2]; | |
558 | v850_div (sd, divide_by, divide_this, "ient, &remainder); | |
559 | GR[reg2] = quotient; | |
560 | GR[reg3] = remainder; | |
561 | ||
562 | TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]); | |
563 | } | |
564 | ||
565 | ||
566 | // DIVQU | |
567 | rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu | |
568 | *v850e2 | |
569 | *v850e2v3 | |
570 | "divq r<reg1>, r<reg2>, r<reg3>" | |
571 | { | |
572 | unsigned int quotient; | |
573 | unsigned int remainder; | |
574 | unsigned int divide_by; | |
575 | unsigned int divide_this; | |
576 | ||
577 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
578 | ||
579 | divide_by = GR[reg1]; | |
580 | divide_this = GR[reg2]; | |
581 | v850_divu (sd, divide_by, divide_this, "ient, &remainder); | |
582 | GR[reg2] = quotient; | |
583 | GR[reg3] = remainder; | |
584 | ||
585 | TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]); | |
586 | } | |
587 | ||
588 | ||
c906108c SS |
589 | // EI |
590 | 1000011111100000 + 0000000101100000:X:::ei | |
591 | "ei" | |
592 | { | |
593 | COMPAT_2 (OP_16087E0 ()); | |
594 | } | |
595 | ||
596 | ||
597 | ||
2aaed979 KB |
598 | // EIRET |
599 | 0000011111100000 + 0000000101001000:X:::eiret | |
600 | "eiret" | |
601 | *v850e2 | |
602 | *v850e2v3 | |
603 | { | |
604 | TRACE_ALU_INPUT1 (MPM & MPM_AUE); | |
605 | ||
606 | nia = EIPC; /* next PC */ | |
607 | if (MPM & MPM_AUE) | |
608 | { | |
609 | PSW = EIPSW; | |
610 | } | |
611 | else | |
612 | { | |
613 | PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP)) | |
614 | | (EIPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP)); | |
615 | } | |
616 | ||
617 | TRACE_ALU_RESULT1 (PSW); | |
618 | TRACE_BRANCH_RESULT (nia); | |
619 | } | |
620 | ||
621 | ||
622 | ||
623 | // FERET | |
624 | 0000011111100000 + 0000000101001010:X:::feret | |
625 | "feret" | |
626 | *v850e2 | |
627 | *v850e2v3 | |
628 | { | |
629 | TRACE_ALU_INPUT1 (MPM & MPM_AUE); | |
630 | ||
631 | nia = FEPC; /* next PC */ | |
632 | if (MPM & MPM_AUE) | |
633 | { | |
634 | PSW = FEPSW; | |
635 | } | |
636 | else | |
637 | { | |
638 | PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP)) | |
639 | | (FEPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP)); | |
640 | } | |
641 | ||
642 | TRACE_ALU_RESULT1 (PSW); | |
643 | TRACE_BRANCH_RESULT (nia); | |
644 | } | |
645 | ||
646 | ||
647 | // FETRAP | |
648 | 0,bbbb!0,00001000000:I:::fetrap | |
649 | "fetrap" | |
650 | *v850e2 | |
651 | *v850e2v3 | |
652 | { | |
653 | TRACE_ALU_INPUT0 (); | |
654 | ||
655 | FEPC = PC + 2; | |
656 | FEPSW = PSW; | |
657 | ECR &= ~ECR_FECC; | |
658 | ECR |= (0x30 + bit4) << 16; | |
659 | FEIC = 0x30 + bit4; | |
660 | PSW |= PSW_EP | PSW_ID | PSW_NP; | |
661 | nia = 0x30; /* next PC */ | |
662 | ||
663 | TRACE_ALU_RESULT1 (PSW); | |
664 | TRACE_BRANCH_RESULT (nia); | |
665 | } | |
666 | ||
667 | ||
c906108c SS |
668 | // HALT |
669 | 0000011111100000 + 0000000100100000:X:::halt | |
670 | "halt" | |
671 | { | |
672 | COMPAT_2 (OP_12007E0 ()); | |
673 | } | |
674 | ||
675 | ||
676 | ||
2aaed979 KB |
677 | // HSH |
678 | rrrrr,11111100000 + wwwww,01101000110:XII:::hsh | |
679 | *v850e2 | |
680 | *v850e2v3 | |
681 | "hsh r<reg2>, r<reg3>" | |
682 | { | |
683 | unsigned32 value; | |
684 | TRACE_ALU_INPUT1 (GR[reg2]); | |
685 | ||
686 | value = 0xffff & GR[reg2]; | |
687 | GR[reg3] = GR[reg2]; | |
688 | ||
689 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
690 | ||
691 | if (value == 0) { PSW |= PSW_Z; PSW |= PSW_CY; } | |
692 | if (value & 0x80000000) PSW |= PSW_S; | |
693 | ||
694 | TRACE_ALU_RESULT1 (GR[reg3]); | |
695 | } | |
696 | ||
697 | ||
c906108c SS |
698 | // HSW |
699 | rrrrr,11111100000 + wwwww,01101000100:XII:::hsw | |
700 | *v850e | |
c5ea1d53 | 701 | *v850e1 |
2aaed979 KB |
702 | *v850e2 |
703 | *v850e2v3 | |
c906108c SS |
704 | "hsw r<reg2>, r<reg3>" |
705 | { | |
706 | unsigned32 value; | |
707 | TRACE_ALU_INPUT1 (GR[reg2]); | |
708 | ||
709 | value = GR[reg2]; | |
710 | value >>= 16; | |
711 | value |= (GR[reg2] << 16); | |
712 | ||
713 | GR[reg3] = value; | |
714 | ||
715 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
716 | ||
717 | if (value == 0) PSW |= PSW_Z; | |
718 | if (value & 0x80000000) PSW |= PSW_S; | |
719 | if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY; | |
720 | ||
721 | TRACE_ALU_RESULT (GR[reg3]); | |
722 | } | |
723 | ||
724 | ||
725 | ||
726 | // JARL | |
727 | rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl | |
728 | "jarl <disp22>, r<reg2>" | |
729 | { | |
730 | GR[reg2] = nia; | |
731 | nia = cia + disp22; | |
732 | TRACE_BRANCH1 (GR[reg2]); | |
733 | } | |
734 | ||
2aaed979 KB |
735 | 00000010111,RRRRR!0 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jarl32 |
736 | *v850e2 | |
737 | *v850e2v3 | |
738 | "jarl <imm32>, r<reg1>" | |
739 | { | |
740 | GR[reg1] = nia; | |
741 | nia = (cia + imm32) & ~1; | |
742 | ||
743 | TRACE_BRANCH_RESULT (nia); | |
744 | } | |
c906108c SS |
745 | |
746 | ||
747 | // JMP | |
748 | 00000000011,RRRRR:I:::jmp | |
749 | "jmp [r<reg1>]" | |
750 | { | |
751 | nia = GR[reg1] & ~1; | |
752 | TRACE_BRANCH0 (); | |
753 | } | |
754 | ||
2aaed979 KB |
755 | 00000110111,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jmp32 |
756 | *v850e2 | |
757 | *v850e2v3 | |
758 | "jmp <imm32>[r<reg1>]" | |
759 | { | |
760 | nia = (GR[reg1] + imm32) & ~1; | |
761 | ||
762 | TRACE_BRANCH_RESULT (nia); | |
763 | } | |
c906108c SS |
764 | |
765 | ||
766 | // JR | |
767 | 0000011110,dddddd + ddddddddddddddd,0:V:::jr | |
768 | "jr <disp22>" | |
769 | { | |
770 | nia = cia + disp22; | |
771 | TRACE_BRANCH0 (); | |
772 | } | |
773 | ||
774 | ||
2aaed979 | 775 | // JR32 |
d99ff40f | 776 | 0000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32 |
2aaed979 KB |
777 | *v850e2 |
778 | *v850e2v3 | |
779 | "jr <imm32>" | |
780 | { | |
781 | nia = (cia + imm32) & ~1; | |
782 | ||
783 | TRACE_BRANCH_RESULT (nia); | |
784 | } | |
785 | ||
c906108c SS |
786 | |
787 | // LD | |
788 | rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b | |
789 | "ld.b <disp16>[r<reg1>], r<reg2>" | |
790 | { | |
791 | COMPAT_2 (OP_700 ()); | |
792 | } | |
793 | ||
2aaed979 KB |
794 | 00000111100,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.b |
795 | "ld.b <disp23>[r<reg1>], r<reg3>" | |
796 | *v850e2v3 | |
797 | { | |
798 | unsigned32 addr = GR[reg1] + disp23; | |
799 | unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1)); | |
800 | GR[reg3] = result; | |
801 | TRACE_LD (addr, result); | |
802 | } | |
803 | ||
c906108c SS |
804 | rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h |
805 | "ld.h <disp16>[r<reg1>], r<reg2>" | |
806 | { | |
807 | COMPAT_2 (OP_720 ()); | |
808 | } | |
809 | ||
2aaed979 KB |
810 | 00000111100,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.h |
811 | *v850e2v3 | |
812 | "ld.h <disp23>[r<reg1>], r<reg3>" | |
813 | { | |
814 | unsigned32 addr = GR[reg1] + disp23; | |
815 | unsigned32 result = EXTEND16 (load_data_mem (sd, addr, 2)); | |
816 | GR[reg3] = result; | |
817 | TRACE_LD (addr, result); | |
818 | } | |
819 | ||
c906108c SS |
820 | rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w |
821 | "ld.w <disp16>[r<reg1>], r<reg2>" | |
822 | { | |
823 | COMPAT_2 (OP_10720 ()); | |
824 | } | |
825 | ||
2aaed979 KB |
826 | 00000111100,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.w |
827 | *v850e2v3 | |
828 | "ld.w <disp23>[r<reg1>], r<reg3>" | |
829 | { | |
830 | unsigned32 addr = GR[reg1] + disp23; | |
831 | unsigned32 result = load_data_mem (sd, addr, 4); | |
832 | GR[reg3] = result; | |
833 | TRACE_LD (addr, result); | |
834 | } | |
835 | ||
c906108c SS |
836 | rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu |
837 | *v850e | |
c5ea1d53 | 838 | *v850e1 |
2aaed979 KB |
839 | *v850e2 |
840 | *v850e2v3 | |
c906108c SS |
841 | "ld.bu <disp16>[r<reg1>], r<reg2>" |
842 | { | |
843 | COMPAT_2 (OP_10780 ()); | |
844 | } | |
845 | ||
2aaed979 KB |
846 | 00000111101,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.bu |
847 | *v850e2v3 | |
848 | "ld.bu <disp23>[r<reg1>], r<reg3>" | |
849 | { | |
850 | unsigned32 addr = GR[reg1] + disp23; | |
851 | unsigned32 result = load_data_mem (sd, addr, 1); | |
852 | GR[reg3] = result; | |
853 | TRACE_LD (addr, result); | |
854 | } | |
855 | ||
c906108c SS |
856 | rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu |
857 | *v850e | |
c5ea1d53 | 858 | *v850e1 |
2aaed979 KB |
859 | *v850e2 |
860 | *v850e2v3 | |
c906108c SS |
861 | "ld.hu <disp16>[r<reg1>], r<reg2>" |
862 | { | |
863 | COMPAT_2 (OP_107E0 ()); | |
864 | } | |
865 | ||
2aaed979 KB |
866 | 00000111101,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.hu |
867 | *v850e2v3 | |
868 | "ld.hu <disp23>[r<reg1>], r<reg3>" | |
869 | { | |
870 | unsigned32 addr = GR[reg1] + disp23; | |
871 | unsigned32 result = load_data_mem (sd, addr, 2); | |
872 | GR[reg3] = result; | |
873 | TRACE_LD (addr, result); | |
874 | } | |
875 | ||
876 | ||
c906108c SS |
877 | |
878 | // LDSR | |
879 | regID,111111,RRRRR + 0000000000100000:IX:::ldsr | |
880 | "ldsr r<reg1>, s<regID>" | |
881 | { | |
2aaed979 | 882 | uint32 sreg = GR[reg1]; |
c906108c SS |
883 | TRACE_ALU_INPUT1 (GR[reg1]); |
884 | ||
2aaed979 KB |
885 | if ((idecode_issue == idecode_v850e2_issue |
886 | || idecode_issue == idecode_v850e2v3_issue) | |
887 | && regID < 28) | |
888 | { | |
889 | int protect_p = (PSW & PSW_NPV) ? 1 : 0; | |
890 | ||
891 | ||
892 | switch (BSEL & 0xffff) | |
893 | { | |
894 | case 0x0000: | |
895 | if ((PSW & PSW_NPV) | |
896 | && ((regID >= 8 && regID <= 12) | |
897 | || (regID >= 22 && regID <= 27) | |
898 | || regID == PSW_REGNO)) | |
899 | { | |
900 | protect_p = 0; | |
901 | } | |
902 | break; | |
903 | case 0x1000: /* MPU0 */ | |
904 | break; | |
905 | case 0x1001: /* MPU1 */ | |
906 | break; | |
907 | case 0x2000: /* FPU */ | |
908 | if ((PSW & PSW_NPV) | |
909 | && ((/* regID >= 0 && */ regID <= 5) | |
910 | || regID == 8 | |
911 | || regID == 9 | |
912 | || regID == 10 | |
913 | || (regID >= 11 && regID <= 26))) | |
914 | { | |
915 | protect_p = 0; | |
916 | } | |
917 | break; | |
918 | case 0xff00: | |
919 | if ((PSW & PSW_NPV) | |
920 | && (regID == 6 | |
921 | || regID == 7 | |
922 | || regID == 8 | |
923 | || regID == 9 | |
924 | || regID == 10 | |
925 | || (regID >= 11 && regID <= 15) | |
926 | || regID == 18 | |
927 | || regID == 19 | |
928 | || (regID >= 21 && regID <= 27))) | |
929 | { | |
930 | protect_p = 0; | |
931 | } | |
932 | break; | |
933 | case 0xffff: | |
934 | if ((PSW & PSW_NPV) | |
935 | && (regID == 6 | |
936 | || regID == 7 | |
937 | || regID == 8 | |
938 | || regID == 9 | |
939 | || regID == 10 | |
940 | || regID == 11 | |
941 | || regID == 12 | |
942 | || regID == 15 | |
943 | || regID == 18 | |
944 | || regID == 19 | |
945 | || (regID >= 21 && regID <= 27))) | |
946 | { | |
947 | protect_p = 0; | |
948 | } | |
949 | break; | |
950 | } | |
951 | ||
952 | if (!protect_p) | |
953 | { | |
954 | switch (BSEL & 0xffff) | |
955 | { | |
956 | case 0x0000: | |
957 | case 0xff00: /* user0 bank */ | |
958 | case 0xffff: /* user1 bank */ | |
959 | if(regID == PSW_REGNO) | |
960 | { | |
961 | SR[regID] = sreg & ((PSW & PSW_NPV) ? 0xf : ~0); | |
962 | } | |
963 | else | |
964 | { | |
965 | SR[regID] = sreg; | |
966 | } | |
967 | break; | |
968 | case 0x1000: | |
969 | MPU0_SR[regID] = sreg; | |
970 | break; | |
971 | case 0x1001: | |
972 | if (regID == MPC_REGNO) | |
973 | { | |
974 | PPC &= ~PPC_PPE; | |
975 | SPAL &= ~SPAL_SPE; | |
976 | IPA0L &= ~IPA_IPE; | |
977 | IPA1L &= ~IPA_IPE; | |
978 | IPA2L &= ~IPA_IPE; | |
979 | IPA3L &= ~IPA_IPE; | |
980 | DPA0L &= ~DPA_DPE; | |
981 | DPA1L &= ~DPA_DPE; | |
982 | DCC &= ~(DCC_DCE0 | DCC_DCE1); | |
983 | } | |
984 | else | |
985 | { | |
986 | MPU1_SR[regID] = sreg; | |
987 | } | |
988 | break; | |
989 | case 0x2000: /* FPU */ | |
990 | if (regID == FPST_REGNO) | |
991 | { | |
992 | unsigned int val = FPSR & ~(FPSR_PR | FPSR_XC | FPSR_XP); | |
993 | ||
994 | val |= ((sreg & FPST_PR) ? FPSR_PR : 0) | |
995 | | ((sreg & FPST_XCE) ? FPSR_XCE : 0) | |
996 | | ((sreg & FPST_XCV) ? FPSR_XCV : 0) | |
997 | | ((sreg & FPST_XCZ) ? FPSR_XCZ : 0) | |
998 | | ((sreg & FPST_XCO) ? FPSR_XCO : 0) | |
999 | | ((sreg & FPST_XCU) ? FPSR_XCU : 0) | |
1000 | | ((sreg & FPST_XCI) ? FPSR_XCI : 0) | |
1001 | | ((sreg & FPST_XPV) ? FPSR_XPV : 0) | |
1002 | | ((sreg & FPST_XPZ) ? FPSR_XPZ : 0) | |
1003 | | ((sreg & FPST_XPO) ? FPSR_XPO : 0) | |
1004 | | ((sreg & FPST_XPU) ? FPSR_XPU : 0) | |
1005 | | ((sreg & FPST_XPI) ? FPSR_XPI : 0); | |
1006 | FPSR = val; | |
1007 | } | |
1008 | else if (regID == FPCFG_REGNO) | |
1009 | { | |
1010 | unsigned int val = FPSR & ~(FPSR_RM | FPSR_XE); | |
1011 | ||
1012 | val |= (((sreg & FPCFG_RM) >> 7) << 18) | |
1013 | | ((sreg & FPCFG_XEV) ? FPSR_XEV : 0) | |
1014 | | ((sreg & FPCFG_XEZ) ? FPSR_XEZ : 0) | |
1015 | | ((sreg & FPCFG_XEO) ? FPSR_XEO : 0) | |
1016 | | ((sreg & FPCFG_XEU) ? FPSR_XEU : 0) | |
1017 | | ((sreg & FPCFG_XEI) ? FPSR_XEI : 0); | |
1018 | FPSR = val; | |
1019 | } | |
1020 | ||
1021 | FPU_SR[regID] = sreg; | |
1022 | break; | |
1023 | } | |
1024 | } | |
1025 | } | |
c906108c | 1026 | else |
2aaed979 KB |
1027 | { |
1028 | SR[regID] = sreg; | |
1029 | } | |
1030 | ||
1031 | TRACE_ALU_RESULT (sreg); | |
1032 | } | |
1033 | ||
1034 | ||
1035 | ||
1036 | // MAC | |
1037 | rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac | |
1038 | *v850e2 | |
1039 | *v850e2v3 | |
1040 | "mac r<reg1>, r<reg2>, r<reg3e>, r<reg4e>" | |
1041 | { | |
1042 | unsigned long op0; | |
1043 | unsigned long op1; | |
1044 | unsigned long op2; | |
1045 | unsigned long op2hi; | |
1046 | unsigned long lo; | |
1047 | unsigned long mid1; | |
1048 | unsigned long mid2; | |
1049 | unsigned long hi; | |
1050 | unsigned long RdLo; | |
1051 | unsigned long RdHi; | |
1052 | int carry; | |
1053 | bfd_boolean sign; | |
1054 | ||
1055 | op0 = GR[reg1]; | |
1056 | op1 = GR[reg2]; | |
1057 | op2 = GR[reg3e]; | |
1058 | op2hi = GR[reg3e+1]; | |
1059 | ||
1060 | TRACE_ALU_INPUT4 (op0, op1, op2, op2hi); | |
1061 | ||
1062 | sign = (op0 ^ op1) & 0x80000000; | |
1063 | ||
1064 | if (((signed long) op0) < 0) | |
1065 | op0 = - op0; | |
1066 | ||
1067 | if (((signed long) op1) < 0) | |
1068 | op1 = - op1; | |
1069 | ||
1070 | /* We can split the 32x32 into four 16x16 operations. This ensures | |
1071 | that we do not lose precision on 32bit only hosts: */ | |
1072 | lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); | |
1073 | mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
1074 | mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); | |
1075 | hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
1076 | ||
1077 | /* We now need to add all of these results together, taking care | |
1078 | to propogate the carries from the additions: */ | |
1079 | RdLo = Add32 (lo, (mid1 << 16), & carry); | |
1080 | RdHi = carry; | |
1081 | RdLo = Add32 (RdLo, (mid2 << 16), & carry); | |
1082 | RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); | |
1083 | ||
1084 | if (sign) | |
1085 | { | |
1086 | RdLo = ~ RdLo; | |
1087 | RdHi = ~ RdHi; | |
1088 | if (RdLo == 0xFFFFFFFF) | |
1089 | { | |
1090 | RdLo = 0; | |
1091 | RdHi += 1; | |
1092 | } | |
1093 | else | |
1094 | RdLo += 1; | |
1095 | } | |
1096 | ||
1097 | RdLo = Add32 (RdLo, op2, & carry); | |
1098 | RdHi += carry + op2hi; | |
1099 | ||
1100 | /* Store the result and condition codes. */ | |
1101 | GR[reg4e] = RdLo; | |
1102 | GR[reg4e + 1 ] = RdHi; | |
1103 | ||
1104 | TRACE_ALU_RESULT2 (RdLo, RdHi); | |
1105 | } | |
1106 | ||
1107 | ||
1108 | ||
1109 | // MACU | |
1110 | rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu | |
1111 | *v850e2 | |
1112 | *v850e2v3 | |
1113 | "macu r<reg1>, r<reg2>, r<reg3e>, r<reg4e>" | |
1114 | { | |
1115 | unsigned long op0; | |
1116 | unsigned long op1; | |
1117 | unsigned long op2; | |
1118 | unsigned long op2hi; | |
1119 | unsigned long lo; | |
1120 | unsigned long mid1; | |
1121 | unsigned long mid2; | |
1122 | unsigned long hi; | |
1123 | unsigned long RdLo; | |
1124 | unsigned long RdHi; | |
1125 | int carry; | |
1126 | ||
1127 | op0 = GR[reg1]; | |
1128 | op1 = GR[reg2]; | |
1129 | op2 = GR[reg3e]; | |
1130 | op2hi = GR[reg3e + 1]; | |
1131 | ||
1132 | TRACE_ALU_INPUT4 (op0, op1, op2, op2hi); | |
1133 | ||
1134 | /* We can split the 32x32 into four 16x16 operations. This ensures | |
1135 | that we do not lose precision on 32bit only hosts: */ | |
1136 | lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); | |
1137 | mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
1138 | mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); | |
1139 | hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
c906108c | 1140 | |
2aaed979 KB |
1141 | /* We now need to add all of these results together, taking care |
1142 | to propogate the carries from the additions: */ | |
1143 | RdLo = Add32 (lo, (mid1 << 16), & carry); | |
1144 | RdHi = carry; | |
1145 | RdLo = Add32 (RdLo, (mid2 << 16), & carry); | |
1146 | RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); | |
1147 | ||
1148 | RdLo = Add32 (RdLo, op2, & carry); | |
1149 | RdHi += carry + op2hi; | |
1150 | ||
1151 | /* Store the result and condition codes. */ | |
1152 | GR[reg4e] = RdLo; | |
1153 | GR[reg4e+1] = RdHi; | |
1154 | ||
1155 | TRACE_ALU_RESULT2 (RdLo, RdHi); | |
c906108c SS |
1156 | } |
1157 | ||
1158 | ||
1159 | ||
1160 | // MOV | |
1161 | rrrrr!0,000000,RRRRR:I:::mov | |
1162 | "mov r<reg1>, r<reg2>" | |
1163 | { | |
1164 | TRACE_ALU_INPUT0 (); | |
1165 | GR[reg2] = GR[reg1]; | |
1166 | TRACE_ALU_RESULT (GR[reg2]); | |
1167 | } | |
1168 | ||
c906108c SS |
1169 | rrrrr!0,010000,iiiii:II:::mov |
1170 | "mov <imm5>, r<reg2>" | |
1171 | { | |
1172 | COMPAT_1 (OP_200 ()); | |
1173 | } | |
1174 | ||
1175 | 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov | |
1176 | *v850e | |
c5ea1d53 | 1177 | *v850e1 |
2aaed979 KB |
1178 | *v850e2 |
1179 | *v850e2v3 | |
c906108c SS |
1180 | "mov <imm32>, r<reg1>" |
1181 | { | |
1182 | SAVE_2; | |
1183 | trace_input ("mov", OP_IMM_REG, 4); | |
1184 | State.regs[ OP[0] ] = load_mem (PC + 2, 4); | |
1185 | trace_output (OP_IMM_REG); | |
1186 | } | |
1187 | ||
1188 | ||
1189 | ||
1190 | // MOVEA | |
1191 | rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea | |
1192 | "movea <simm16>, r<reg1>, r<reg2>" | |
1193 | { | |
1194 | TRACE_ALU_INPUT2 (GR[reg1], simm16); | |
1195 | GR[reg2] = GR[reg1] + simm16; | |
1196 | TRACE_ALU_RESULT (GR[reg2]); | |
1197 | } | |
1198 | ||
1199 | ||
1200 | ||
1201 | // MOVHI | |
1202 | rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi | |
1203 | "movhi <uimm16>, r<reg1>, r<reg2>" | |
1204 | { | |
1205 | COMPAT_2 (OP_640 ()); | |
1206 | } | |
1207 | ||
1208 | ||
1209 | ||
1210 | // MUL | |
1211 | rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul | |
1212 | *v850e | |
c5ea1d53 | 1213 | *v850e1 |
2aaed979 KB |
1214 | *v850e2 |
1215 | *v850e2v3 | |
c906108c SS |
1216 | "mul r<reg1>, r<reg2>, r<reg3>" |
1217 | { | |
1218 | COMPAT_2 (OP_22007E0 ()); | |
1219 | } | |
1220 | ||
1221 | rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul | |
1222 | *v850e | |
c5ea1d53 | 1223 | *v850e1 |
2aaed979 KB |
1224 | *v850e2 |
1225 | *v850e2v3 | |
c906108c SS |
1226 | "mul <imm9>, r<reg2>, r<reg3>" |
1227 | { | |
1228 | COMPAT_2 (OP_24007E0 ()); | |
1229 | } | |
1230 | ||
1231 | ||
1232 | // MULH | |
1233 | rrrrr!0,000111,RRRRR:I:::mulh | |
1234 | "mulh r<reg1>, r<reg2>" | |
1235 | { | |
1236 | COMPAT_1 (OP_E0 ()); | |
1237 | } | |
1238 | ||
1239 | rrrrr!0,010111,iiiii:II:::mulh | |
1240 | "mulh <imm5>, r<reg2>" | |
1241 | { | |
1242 | COMPAT_1 (OP_2E0 ()); | |
1243 | } | |
1244 | ||
1245 | ||
1246 | ||
1247 | // MULHI | |
1248 | rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi | |
1249 | "mulhi <uimm16>, r<reg1>, r<reg2>" | |
1250 | { | |
1251 | COMPAT_2 (OP_6E0 ()); | |
1252 | } | |
1253 | ||
1254 | ||
1255 | ||
1256 | // MULU | |
1257 | rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu | |
1258 | *v850e | |
c5ea1d53 | 1259 | *v850e1 |
2aaed979 KB |
1260 | *v850e2 |
1261 | *v850e2v3 | |
c906108c SS |
1262 | "mulu r<reg1>, r<reg2>, r<reg3>" |
1263 | { | |
1264 | COMPAT_2 (OP_22207E0 ()); | |
1265 | } | |
1266 | ||
1267 | rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu | |
1268 | *v850e | |
c5ea1d53 | 1269 | *v850e1 |
2aaed979 KB |
1270 | *v850e2 |
1271 | *v850e2v3 | |
c906108c SS |
1272 | "mulu <imm9>, r<reg2>, r<reg3>" |
1273 | { | |
1274 | COMPAT_2 (OP_24207E0 ()); | |
1275 | } | |
1276 | ||
1277 | ||
1278 | ||
1279 | // NOP | |
1280 | 0000000000000000:I:::nop | |
1281 | "nop" | |
1282 | { | |
1283 | /* do nothing, trace nothing */ | |
1284 | } | |
1285 | ||
1286 | ||
1287 | ||
1288 | // NOT | |
1289 | rrrrr,000001,RRRRR:I:::not | |
1290 | "not r<reg1>, r<reg2>" | |
1291 | { | |
1292 | COMPAT_1 (OP_20 ()); | |
1293 | } | |
1294 | ||
1295 | ||
1296 | ||
1297 | // NOT1 | |
1298 | 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1 | |
1299 | "not1 <bit3>, <disp16>[r<reg1>]" | |
1300 | { | |
1301 | COMPAT_2 (OP_47C0 ()); | |
1302 | } | |
1303 | ||
1304 | rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 | |
1305 | *v850e | |
c5ea1d53 | 1306 | *v850e1 |
2aaed979 KB |
1307 | *v850e2 |
1308 | *v850e2v3 | |
c906108c SS |
1309 | "not1 r<reg2>, r<reg1>" |
1310 | { | |
1311 | COMPAT_2 (OP_E207E0 ()); | |
1312 | } | |
1313 | ||
1314 | ||
1315 | ||
1316 | // OR | |
1317 | rrrrr,001000,RRRRR:I:::or | |
1318 | "or r<reg1>, r<reg2>" | |
1319 | { | |
1320 | COMPAT_1 (OP_100 ()); | |
1321 | } | |
1322 | ||
1323 | ||
1324 | ||
1325 | // ORI | |
1326 | rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori | |
1327 | "ori <uimm16>, r<reg1>, r<reg2>" | |
1328 | { | |
1329 | COMPAT_2 (OP_680 ()); | |
1330 | } | |
1331 | ||
1332 | ||
1333 | ||
1334 | // PREPARE | |
1335 | 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare | |
1336 | *v850e | |
c5ea1d53 | 1337 | *v850e1 |
2aaed979 KB |
1338 | *v850e2 |
1339 | *v850e2v3 | |
c906108c SS |
1340 | "prepare <list12>, <imm5>" |
1341 | { | |
1342 | int i; | |
1343 | SAVE_2; | |
1344 | ||
1345 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
1346 | ||
1347 | /* Store the registers with lower number registers being placed at | |
1348 | higher addresses. */ | |
1349 | for (i = 0; i < 12; i++) | |
1350 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
1351 | { | |
1352 | SP -= 4; | |
1353 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
1354 | } | |
1355 | ||
1356 | SP -= (OP[3] & 0x3e) << 1; | |
1357 | ||
1358 | trace_output (OP_PUSHPOP1); | |
1359 | } | |
1360 | ||
1361 | ||
1362 | 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 | |
1363 | *v850e | |
c5ea1d53 | 1364 | *v850e1 |
2aaed979 KB |
1365 | *v850e2 |
1366 | *v850e2v3 | |
c906108c SS |
1367 | "prepare <list12>, <imm5>, sp" |
1368 | { | |
1369 | COMPAT_2 (OP_30780 ()); | |
1370 | } | |
1371 | ||
1372 | 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 | |
1373 | *v850e | |
c5ea1d53 | 1374 | *v850e1 |
2aaed979 KB |
1375 | *v850e2 |
1376 | *v850e2v3 | |
c906108c SS |
1377 | "prepare <list12>, <imm5>, <uimm16>" |
1378 | { | |
1379 | COMPAT_2 (OP_B0780 ()); | |
1380 | } | |
1381 | ||
1382 | 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 | |
1383 | *v850e | |
c5ea1d53 | 1384 | *v850e1 |
2aaed979 KB |
1385 | *v850e2 |
1386 | *v850e2v3 | |
c906108c SS |
1387 | "prepare <list12>, <imm5>, <uimm16>" |
1388 | { | |
1389 | COMPAT_2 (OP_130780 ()); | |
1390 | } | |
1391 | ||
1392 | 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 | |
1393 | *v850e | |
c5ea1d53 | 1394 | *v850e1 |
2aaed979 KB |
1395 | *v850e2 |
1396 | *v850e2v3 | |
c906108c SS |
1397 | "prepare <list12>, <imm5>, <uimm32>" |
1398 | { | |
1399 | COMPAT_2 (OP_1B0780 ()); | |
1400 | } | |
1401 | ||
1402 | ||
1403 | ||
1404 | // RETI | |
1405 | 0000011111100000 + 0000000101000000:X:::reti | |
1406 | "reti" | |
1407 | { | |
1408 | if ((PSW & PSW_EP)) | |
1409 | { | |
1410 | nia = (EIPC & ~1); | |
1411 | PSW = EIPSW; | |
1412 | } | |
1413 | else if ((PSW & PSW_NP)) | |
1414 | { | |
1415 | nia = (FEPC & ~1); | |
1416 | PSW = FEPSW; | |
1417 | } | |
1418 | else | |
1419 | { | |
1420 | nia = (EIPC & ~1); | |
1421 | PSW = EIPSW; | |
1422 | } | |
1423 | TRACE_BRANCH1 (PSW); | |
1424 | } | |
1425 | ||
1426 | ||
1427 | ||
1428 | // SAR | |
1429 | rrrrr,111111,RRRRR + 0000000010100000:IX:::sar | |
1430 | "sar r<reg1>, r<reg2>" | |
1431 | { | |
1432 | COMPAT_2 (OP_A007E0 ()); | |
1433 | } | |
1434 | ||
1435 | rrrrr,010101,iiiii:II:::sar | |
1436 | "sar <imm5>, r<reg2>" | |
1437 | { | |
1438 | COMPAT_1 (OP_2A0 ()); | |
1439 | } | |
1440 | ||
2aaed979 KB |
1441 | rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar |
1442 | *v850e2 | |
1443 | *v850e2v3 | |
1444 | "sar r<reg1>, r<reg2>, r<reg3>" | |
1445 | { | |
1446 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1447 | v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1448 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1449 | } | |
c906108c SS |
1450 | |
1451 | ||
1452 | // SASF | |
1453 | rrrrr,1111110,cccc + 0000001000000000:IX:::sasf | |
1454 | *v850e | |
c5ea1d53 | 1455 | *v850e1 |
2aaed979 KB |
1456 | *v850e2 |
1457 | *v850e2v3 | |
c906108c SS |
1458 | "sasf %s<cccc>, r<reg2>" |
1459 | { | |
1460 | COMPAT_2 (OP_20007E0 ()); | |
1461 | } | |
1462 | ||
1463 | ||
1464 | ||
c906108c SS |
1465 | // SATADD |
1466 | rrrrr!0,000110,RRRRR:I:::satadd | |
1467 | "satadd r<reg1>, r<reg2>" | |
1468 | { | |
1469 | COMPAT_1 (OP_C0 ()); | |
1470 | } | |
1471 | ||
1472 | rrrrr!0,010001,iiiii:II:::satadd | |
1473 | "satadd <imm5>, r<reg2>" | |
1474 | { | |
1475 | COMPAT_1 (OP_220 ()); | |
1476 | } | |
1477 | ||
2aaed979 KB |
1478 | rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd |
1479 | *v850e2 | |
1480 | *v850e2v3 | |
1481 | "satadd r<reg1>, r<reg2>, r<reg3>" | |
1482 | { | |
1483 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1484 | v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1485 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1486 | } | |
1487 | ||
c906108c SS |
1488 | |
1489 | ||
1490 | // SATSUB | |
1491 | rrrrr!0,000101,RRRRR:I:::satsub | |
1492 | "satsub r<reg1>, r<reg2>" | |
1493 | { | |
1494 | COMPAT_1 (OP_A0 ()); | |
1495 | } | |
1496 | ||
2aaed979 KB |
1497 | rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub |
1498 | *v850e2 | |
1499 | *v850e2v3 | |
1500 | "satsub r<reg1>, r<reg2>, r<reg3>" | |
1501 | { | |
1502 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1503 | v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1504 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1505 | } | |
1506 | ||
c906108c SS |
1507 | |
1508 | ||
1509 | // SATSUBI | |
1510 | rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi | |
1511 | "satsubi <simm16>, r<reg1>, r<reg2>" | |
1512 | { | |
1513 | COMPAT_2 (OP_660 ()); | |
1514 | } | |
1515 | ||
1516 | ||
1517 | ||
1518 | // SATSUBR | |
1519 | rrrrr!0,000100,RRRRR:I:::satsubr | |
1520 | "satsubr r<reg1>, r<reg2>" | |
1521 | { | |
1522 | COMPAT_1 (OP_80 ()); | |
1523 | } | |
1524 | ||
1525 | ||
1526 | ||
2aaed979 KB |
1527 | //SBF |
1528 | rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf | |
1529 | *v850e2 | |
1530 | *v850e2v3 | |
1531 | "sbf %s<cccc>, r<reg1>, r<reg2>, r<reg3>" | |
1532 | { | |
1533 | int cond = condition_met (cccc); | |
1534 | TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); | |
1535 | GR[reg3] = GR[reg2] - GR[reg1] - (cond ? 1 : 0); | |
1536 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1537 | } | |
1538 | ||
1539 | ||
1540 | ||
1541 | // SCH0L | |
1542 | rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l | |
1543 | *v850e2 | |
1544 | *v850e2v3 | |
1545 | "sch0l r<reg2>, r<reg3>" | |
1546 | { | |
1547 | unsigned int pos, op0; | |
1548 | ||
1549 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1550 | ||
1551 | op0 = GR[reg2]; | |
1552 | ||
1553 | if (op0 == 0xffffffff) | |
1554 | { | |
1555 | PSW &= ~PSW_CY; | |
1556 | PSW &= ~PSW_OV; | |
1557 | PSW &= ~PSW_S; | |
1558 | PSW |= PSW_Z; | |
1559 | pos = 0; | |
1560 | } | |
1561 | else if (op0 == 0xfffffffe) | |
1562 | { | |
1563 | PSW |= PSW_CY; | |
1564 | PSW &= ~PSW_OV; | |
1565 | PSW &= ~PSW_S; | |
1566 | PSW &= ~PSW_Z; | |
1567 | pos = 32; | |
1568 | } | |
1569 | else | |
1570 | { | |
1571 | pos = 1; | |
1572 | while (op0 & 0x80000000) | |
1573 | { | |
1574 | op0 <<= 1; | |
1575 | pos++; | |
1576 | } | |
1577 | PSW &= ~PSW_CY; | |
1578 | PSW &= ~PSW_OV; | |
1579 | PSW &= ~PSW_S; | |
1580 | PSW &= ~PSW_Z; | |
1581 | } | |
1582 | ||
1583 | GR[reg3] = pos; | |
1584 | ||
1585 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1586 | } | |
1587 | ||
1588 | ||
1589 | ||
1590 | // SCH0R | |
1591 | rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r | |
1592 | *v850e2 | |
1593 | *v850e2v3 | |
1594 | "sch0r r<reg2>, r<reg3>" | |
1595 | { | |
1596 | unsigned int pos, op0; | |
1597 | ||
1598 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1599 | ||
1600 | op0 = GR[reg2]; | |
1601 | ||
1602 | if (op0 == 0xffffffff) | |
1603 | { | |
1604 | PSW &= ~PSW_CY; | |
1605 | PSW &= ~PSW_OV; | |
1606 | PSW &= ~PSW_S; | |
1607 | PSW |= PSW_Z; | |
1608 | pos = 0; | |
1609 | } | |
1610 | else if (op0 == 0x7fffffff) | |
1611 | { | |
1612 | PSW |= PSW_CY; | |
1613 | PSW &= ~PSW_OV; | |
1614 | PSW &= ~PSW_S; | |
1615 | PSW &= ~PSW_Z; | |
1616 | pos = 32; | |
1617 | } | |
1618 | else | |
1619 | { | |
1620 | pos = 1; | |
1621 | while (op0 & 0x00000001) | |
1622 | { | |
1623 | op0 >>= 1; | |
1624 | pos++; | |
1625 | } | |
1626 | PSW &= ~PSW_CY; | |
1627 | PSW &= ~PSW_OV; | |
1628 | PSW &= ~PSW_S; | |
1629 | PSW &= ~PSW_Z; | |
1630 | } | |
1631 | ||
1632 | GR[reg3] = pos; | |
1633 | ||
1634 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1635 | } | |
1636 | ||
1637 | // SCH1L | |
1638 | rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l | |
1639 | *v850e2 | |
1640 | *v850e2v3 | |
1641 | "sch1l r<reg2>, r<reg3>" | |
1642 | { | |
1643 | unsigned int pos, op0; | |
1644 | ||
1645 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1646 | ||
1647 | op0 = GR[reg2]; | |
1648 | ||
1649 | if (op0 == 0x00000000) | |
1650 | { | |
1651 | PSW &= ~PSW_CY; | |
1652 | PSW &= ~PSW_OV; | |
1653 | PSW &= ~PSW_S; | |
1654 | PSW |= PSW_Z; | |
1655 | pos = 0; | |
1656 | } | |
1657 | else if (op0 == 0x00000001) | |
1658 | { | |
1659 | PSW |= PSW_CY; | |
1660 | PSW &= ~PSW_OV; | |
1661 | PSW &= ~PSW_S; | |
1662 | PSW &= ~PSW_Z; | |
1663 | pos = 32; | |
1664 | } | |
1665 | else | |
1666 | { | |
1667 | pos = 1; | |
1668 | while (!(op0 & 0x80000000)) | |
1669 | { | |
1670 | op0 <<= 1; | |
1671 | pos++; | |
1672 | } | |
1673 | PSW &= ~PSW_CY; | |
1674 | PSW &= ~PSW_OV; | |
1675 | PSW &= ~PSW_S; | |
1676 | PSW &= ~PSW_Z; | |
1677 | } | |
1678 | ||
1679 | GR[reg3] = pos; | |
1680 | ||
1681 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1682 | } | |
1683 | ||
1684 | // SCH1R | |
1685 | rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r | |
1686 | *v850e2 | |
1687 | *v850e2v3 | |
1688 | "sch1r r<reg2>, r<reg3>" | |
1689 | { | |
1690 | unsigned int pos, op0; | |
1691 | ||
1692 | TRACE_ALU_INPUT1 (GR[reg2]); | |
1693 | ||
1694 | op0 = GR[reg2]; | |
1695 | ||
1696 | if (op0 == 0x00000000) | |
1697 | { | |
1698 | PSW &= ~PSW_CY; | |
1699 | PSW &= ~PSW_OV; | |
1700 | PSW &= ~PSW_S; | |
1701 | PSW |= PSW_Z; | |
1702 | pos = 0; | |
1703 | } | |
1704 | else if (op0 == 0x80000000) | |
1705 | { | |
1706 | PSW |= PSW_CY; | |
1707 | PSW &= ~PSW_OV; | |
1708 | PSW &= ~PSW_S; | |
1709 | PSW &= ~PSW_Z; | |
1710 | pos = 32; | |
1711 | } | |
1712 | else | |
1713 | { | |
1714 | pos = 1; | |
1715 | while (!(op0 & 0x00000001)) | |
1716 | { | |
1717 | op0 >>= 1; | |
1718 | pos++; | |
1719 | } | |
1720 | PSW &= ~PSW_CY; | |
1721 | PSW &= ~PSW_OV; | |
1722 | PSW &= ~PSW_S; | |
1723 | PSW &= ~PSW_Z; | |
1724 | } | |
1725 | ||
1726 | GR[reg3] = pos; | |
1727 | ||
1728 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1729 | } | |
1730 | ||
1731 | //SHL | |
1732 | rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl | |
1733 | *v850e2 | |
1734 | *v850e2v3 | |
1735 | "shl r<reg1>, r<reg2>, r<reg3>" | |
1736 | { | |
1737 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1738 | v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1739 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1740 | } | |
1741 | ||
1742 | //SHR | |
1743 | rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr | |
1744 | *v850e2 | |
1745 | *v850e2v3 | |
1746 | "shr r<reg1>, r<reg2>, r<reg3>" | |
1747 | { | |
1748 | TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]); | |
1749 | v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]); | |
1750 | TRACE_ALU_RESULT1 (GR[reg3]); | |
1751 | } | |
1752 | ||
1753 | ||
1754 | ||
c906108c SS |
1755 | // SETF |
1756 | rrrrr,1111110,cccc + 0000000000000000:IX:::setf | |
1757 | "setf %s<cccc>, r<reg2>" | |
1758 | { | |
1759 | COMPAT_2 (OP_7E0 ()); | |
1760 | } | |
1761 | ||
1762 | ||
1763 | ||
1764 | // SET1 | |
1765 | 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1 | |
1766 | "set1 <bit3>, <disp16>[r<reg1>]" | |
1767 | { | |
1768 | COMPAT_2 (OP_7C0 ()); | |
1769 | } | |
1770 | ||
1771 | rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 | |
1772 | *v850e | |
c5ea1d53 | 1773 | *v850e1 |
2aaed979 KB |
1774 | *v850e2 |
1775 | *v850e2v3 | |
c906108c SS |
1776 | "set1 r<reg2>, [r<reg1>]" |
1777 | { | |
1778 | COMPAT_2 (OP_E007E0 ()); | |
1779 | } | |
1780 | ||
1781 | ||
1782 | ||
1783 | // SHL | |
1784 | rrrrr,111111,RRRRR + 0000000011000000:IX:::shl | |
1785 | "shl r<reg1>, r<reg2>" | |
1786 | { | |
1787 | COMPAT_2 (OP_C007E0 ()); | |
1788 | } | |
1789 | ||
1790 | rrrrr,010110,iiiii:II:::shl | |
1791 | "shl <imm5>, r<reg2>" | |
1792 | { | |
1793 | COMPAT_1 (OP_2C0 ()); | |
1794 | } | |
1795 | ||
1796 | ||
1797 | ||
1798 | // SHR | |
1799 | rrrrr,111111,RRRRR + 0000000010000000:IX:::shr | |
1800 | "shr r<reg1>, r<reg2>" | |
1801 | { | |
1802 | COMPAT_2 (OP_8007E0 ()); | |
1803 | } | |
1804 | ||
1805 | rrrrr,010100,iiiii:II:::shr | |
1806 | "shr <imm5>, r<reg2>" | |
1807 | { | |
1808 | COMPAT_1 (OP_280 ()); | |
1809 | } | |
1810 | ||
1811 | ||
1812 | ||
1813 | // SLD | |
1814 | rrrrr,0110,ddddddd:IV:::sld.b | |
1815 | "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US) | |
1816 | "sld.b <disp7>[ep], r<reg2>" | |
1817 | { | |
1818 | unsigned32 addr = EP + disp7; | |
1819 | unsigned32 result = load_mem (addr, 1); | |
1820 | if (PSW & PSW_US) | |
1821 | { | |
1822 | GR[reg2] = result; | |
1823 | TRACE_LD_NAME ("sld.bu", addr, result); | |
1824 | } | |
1825 | else | |
1826 | { | |
1827 | result = EXTEND8 (result); | |
1828 | GR[reg2] = result; | |
1829 | TRACE_LD (addr, result); | |
1830 | } | |
1831 | } | |
1832 | ||
1833 | rrrrr,1000,ddddddd:IV:::sld.h | |
1834 | "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US) | |
1835 | "sld.h <disp8>[ep], r<reg2>" | |
1836 | { | |
1837 | unsigned32 addr = EP + disp8; | |
1838 | unsigned32 result = load_mem (addr, 2); | |
1839 | if (PSW & PSW_US) | |
1840 | { | |
1841 | GR[reg2] = result; | |
1842 | TRACE_LD_NAME ("sld.hu", addr, result); | |
1843 | } | |
1844 | else | |
1845 | { | |
1846 | result = EXTEND16 (result); | |
1847 | GR[reg2] = result; | |
1848 | TRACE_LD (addr, result); | |
1849 | } | |
1850 | } | |
1851 | ||
1852 | rrrrr,1010,dddddd,0:IV:::sld.w | |
1853 | "sld.w <disp8>[ep], r<reg2>" | |
1854 | { | |
1855 | unsigned32 addr = EP + disp8; | |
1856 | unsigned32 result = load_mem (addr, 4); | |
1857 | GR[reg2] = result; | |
1858 | TRACE_LD (addr, result); | |
1859 | } | |
1860 | ||
1861 | rrrrr!0,0000110,dddd:IV:::sld.bu | |
1862 | *v850e | |
c5ea1d53 | 1863 | *v850e1 |
2aaed979 KB |
1864 | *v850e2 |
1865 | *v850e2v3 | |
c906108c SS |
1866 | "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US) |
1867 | "sld.bu <disp4>[ep], r<reg2>" | |
1868 | { | |
1869 | unsigned32 addr = EP + disp4; | |
1870 | unsigned32 result = load_mem (addr, 1); | |
1871 | if (PSW & PSW_US) | |
1872 | { | |
1873 | result = EXTEND8 (result); | |
1874 | GR[reg2] = result; | |
1875 | TRACE_LD_NAME ("sld.b", addr, result); | |
1876 | } | |
1877 | else | |
1878 | { | |
1879 | GR[reg2] = result; | |
1880 | TRACE_LD (addr, result); | |
1881 | } | |
1882 | } | |
1883 | ||
1884 | rrrrr!0,0000111,dddd:IV:::sld.hu | |
1885 | *v850e | |
c5ea1d53 | 1886 | *v850e1 |
2aaed979 KB |
1887 | *v850e2 |
1888 | *v850e2v3 | |
c906108c SS |
1889 | "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US) |
1890 | "sld.hu <disp5>[ep], r<reg2>" | |
1891 | { | |
1892 | unsigned32 addr = EP + disp5; | |
1893 | unsigned32 result = load_mem (addr, 2); | |
1894 | if (PSW & PSW_US) | |
1895 | { | |
1896 | result = EXTEND16 (result); | |
1897 | GR[reg2] = result; | |
1898 | TRACE_LD_NAME ("sld.h", addr, result); | |
1899 | } | |
1900 | else | |
1901 | { | |
1902 | GR[reg2] = result; | |
1903 | TRACE_LD (addr, result); | |
1904 | } | |
1905 | } | |
1906 | ||
2aaed979 KB |
1907 | |
1908 | ||
c906108c SS |
1909 | // SST |
1910 | rrrrr,0111,ddddddd:IV:::sst.b | |
1911 | "sst.b r<reg2>, <disp7>[ep]" | |
1912 | { | |
1913 | COMPAT_1 (OP_380 ()); | |
1914 | } | |
1915 | ||
1916 | rrrrr,1001,ddddddd:IV:::sst.h | |
1917 | "sst.h r<reg2>, <disp8>[ep]" | |
1918 | { | |
1919 | COMPAT_1 (OP_480 ()); | |
1920 | } | |
1921 | ||
1922 | rrrrr,1010,dddddd,1:IV:::sst.w | |
1923 | "sst.w r<reg2>, <disp8>[ep]" | |
1924 | { | |
1925 | COMPAT_1 (OP_501 ()); | |
1926 | } | |
1927 | ||
c906108c SS |
1928 | // ST |
1929 | rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b | |
1930 | "st.b r<reg2>, <disp16>[r<reg1>]" | |
1931 | { | |
1932 | COMPAT_2 (OP_740 ()); | |
1933 | } | |
1934 | ||
2aaed979 KB |
1935 | 00000111100,RRRRR + wwwww,ddddddd,1101 + dddddddddddddddd:XIV:::st.b |
1936 | *v850e2v3 | |
1937 | "st.b r<reg3>, <disp23>[r<reg1>]" | |
1938 | { | |
1939 | unsigned32 addr = GR[reg1] + disp23; | |
1940 | store_data_mem (sd, addr, 1, GR[reg3]); | |
1941 | TRACE_ST (addr, GR[reg3]); | |
1942 | } | |
1943 | ||
c906108c SS |
1944 | rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h |
1945 | "st.h r<reg2>, <disp16>[r<reg1>]" | |
1946 | { | |
1947 | COMPAT_2 (OP_760 ()); | |
1948 | } | |
1949 | ||
2aaed979 KB |
1950 | 00000111101,RRRRR+wwwww,dddddd,01101+dddddddddddddddd:XIV:::st.h |
1951 | *v850e2v3 | |
1952 | "st.h r<reg3>, <disp23>[r<reg1>]" | |
1953 | { | |
1954 | unsigned32 addr = GR[reg1] + disp23; | |
1955 | store_data_mem (sd, addr, 2, GR[reg3]); | |
1956 | TRACE_ST (addr, GR[reg3]); | |
1957 | } | |
1958 | ||
1959 | rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w | |
c906108c SS |
1960 | "st.w r<reg2>, <disp16>[r<reg1>]" |
1961 | { | |
1962 | COMPAT_2 (OP_10760 ()); | |
1963 | } | |
1964 | ||
2aaed979 KB |
1965 | 00000111100,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.w |
1966 | *v850e2v3 | |
1967 | "st.w r<reg3>, <disp23>[r<reg1>]" | |
1968 | { | |
1969 | unsigned32 addr = GR[reg1] + disp23; | |
1970 | store_data_mem (sd, addr, 4, GR[reg3]); | |
1971 | TRACE_ST (addr, GR[reg3]); | |
1972 | } | |
1973 | ||
1974 | ||
c906108c SS |
1975 | // STSR |
1976 | rrrrr,111111,regID + 0000000001000000:IX:::stsr | |
1977 | "stsr s<regID>, r<reg2>" | |
1978 | { | |
2aaed979 KB |
1979 | uint32 sreg = 0; |
1980 | ||
1981 | if ((idecode_issue == idecode_v850e2_issue | |
1982 | || idecode_issue == idecode_v850e2v3_issue) | |
1983 | && regID < 28) | |
1984 | { | |
1985 | switch (BSEL & 0xffff) | |
1986 | { | |
1987 | case 0x0000: | |
1988 | case 0xff00: /* USER 0 */ | |
1989 | case 0xffff: /* USER 1 */ | |
1990 | sreg = SR[regID]; | |
1991 | break; | |
1992 | case 0x1000: | |
1993 | sreg = MPU0_SR[regID]; | |
1994 | break; | |
1995 | case 0x1001: | |
1996 | sreg = MPU1_SR[regID]; | |
1997 | break; | |
1998 | case 0x2000: | |
1999 | if (regID == FPST_REGNO) | |
2000 | { | |
2001 | sreg = ((FPSR & FPSR_PR) ? FPST_PR : 0) | |
2002 | | ((FPSR & FPSR_XCE) ? FPST_XCE : 0) | |
2003 | | ((FPSR & FPSR_XCV) ? FPST_XCV : 0) | |
2004 | | ((FPSR & FPSR_XCZ) ? FPST_XCZ : 0) | |
2005 | | ((FPSR & FPSR_XCO) ? FPST_XCO : 0) | |
2006 | | ((FPSR & FPSR_XCU) ? FPST_XCU : 0) | |
2007 | | ((FPSR & FPSR_XCI) ? FPST_XCI : 0) | |
2008 | | ((FPSR & FPSR_XPV) ? FPST_XPV : 0) | |
2009 | | ((FPSR & FPSR_XPZ) ? FPST_XPZ : 0) | |
2010 | | ((FPSR & FPSR_XPO) ? FPST_XPO : 0) | |
2011 | | ((FPSR & FPSR_XPU) ? FPST_XPU : 0) | |
2012 | | ((FPSR & FPSR_XPI) ? FPST_XPI : 0); | |
2013 | } | |
2014 | else if (regID == FPCFG_REGNO) | |
2015 | { | |
2016 | sreg = (((FPSR & FPSR_RM) >> 18) << 7) | |
2017 | | ((FPSR & FPSR_XEV) ? FPCFG_XEV : 0) | |
2018 | | ((FPSR & FPSR_XEZ) ? FPCFG_XEZ : 0) | |
2019 | | ((FPSR & FPSR_XEO) ? FPCFG_XEO : 0) | |
2020 | | ((FPSR & FPSR_XEU) ? FPCFG_XEU : 0) | |
2021 | | ((FPSR & FPSR_XEI) ? FPCFG_XEI : 0); | |
2022 | } | |
2023 | else | |
2024 | { | |
2025 | sreg = FPU_SR[regID]; | |
2026 | } | |
2027 | break; | |
2028 | } | |
2029 | } | |
2030 | else | |
2031 | { | |
2032 | sreg = SR[regID]; | |
2033 | } | |
2034 | ||
2035 | TRACE_ALU_INPUT1 (sreg); | |
2036 | GR[reg2] = sreg; | |
c906108c SS |
2037 | TRACE_ALU_RESULT (GR[reg2]); |
2038 | } | |
2039 | ||
c906108c SS |
2040 | // SUB |
2041 | rrrrr,001101,RRRRR:I:::sub | |
2042 | "sub r<reg1>, r<reg2>" | |
2043 | { | |
2044 | COMPAT_1 (OP_1A0 ()); | |
2045 | } | |
2046 | ||
c906108c SS |
2047 | // SUBR |
2048 | rrrrr,001100,RRRRR:I:::subr | |
2049 | "subr r<reg1>, r<reg2>" | |
2050 | { | |
2051 | COMPAT_1 (OP_180 ()); | |
2052 | } | |
2053 | ||
c906108c SS |
2054 | // SWITCH |
2055 | 00000000010,RRRRR:I:::switch | |
2056 | *v850e | |
c5ea1d53 | 2057 | *v850e1 |
2aaed979 KB |
2058 | *v850e2 |
2059 | *v850e2v3 | |
c906108c SS |
2060 | "switch r<reg1>" |
2061 | { | |
2062 | unsigned long adr; | |
2063 | SAVE_1; | |
2064 | trace_input ("switch", OP_REG, 0); | |
2065 | adr = (cia + 2) + (State.regs[ reg1 ] << 1); | |
2066 | nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1); | |
2067 | trace_output (OP_REG); | |
2068 | } | |
2069 | ||
c906108c SS |
2070 | // SXB |
2071 | 00000000101,RRRRR:I:::sxb | |
2072 | *v850e | |
c5ea1d53 | 2073 | *v850e1 |
2aaed979 KB |
2074 | *v850e2 |
2075 | *v850e2v3 | |
c906108c SS |
2076 | "sxb r<reg1>" |
2077 | { | |
2078 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2079 | GR[reg1] = EXTEND8 (GR[reg1]); | |
2080 | TRACE_ALU_RESULT (GR[reg1]); | |
2081 | } | |
2082 | ||
2083 | // SXH | |
2084 | 00000000111,RRRRR:I:::sxh | |
2085 | *v850e | |
c5ea1d53 | 2086 | *v850e1 |
2aaed979 KB |
2087 | *v850e2 |
2088 | *v850e2v3 | |
c906108c SS |
2089 | "sxh r<reg1>" |
2090 | { | |
2091 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2092 | GR[reg1] = EXTEND16 (GR[reg1]); | |
2093 | TRACE_ALU_RESULT (GR[reg1]); | |
2094 | } | |
2095 | ||
c906108c SS |
2096 | // TRAP |
2097 | 00000111111,iiiii + 0000000100000000:X:::trap | |
2098 | "trap <vector>" | |
2099 | { | |
2100 | COMPAT_2 (OP_10007E0 ()); | |
2101 | } | |
2102 | ||
c906108c SS |
2103 | // TST |
2104 | rrrrr,001011,RRRRR:I:::tst | |
2105 | "tst r<reg1>, r<reg2>" | |
2106 | { | |
2107 | COMPAT_1 (OP_160 ()); | |
2108 | } | |
2109 | ||
c906108c SS |
2110 | // TST1 |
2111 | 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1 | |
2112 | "tst1 <bit3>, <disp16>[r<reg1>]" | |
2113 | { | |
2114 | COMPAT_2 (OP_C7C0 ()); | |
2115 | } | |
2116 | ||
2117 | rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 | |
2118 | *v850e | |
c5ea1d53 | 2119 | *v850e1 |
2aaed979 KB |
2120 | *v850e2 |
2121 | *v850e2v3 | |
c906108c SS |
2122 | "tst1 r<reg2>, [r<reg1>]" |
2123 | { | |
2124 | COMPAT_2 (OP_E607E0 ()); | |
2125 | } | |
2126 | ||
c906108c SS |
2127 | // XOR |
2128 | rrrrr,001001,RRRRR:I:::xor | |
2129 | "xor r<reg1>, r<reg2>" | |
2130 | { | |
2131 | COMPAT_1 (OP_120 ()); | |
2132 | } | |
2133 | ||
c906108c SS |
2134 | // XORI |
2135 | rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori | |
2136 | "xori <uimm16>, r<reg1>, r<reg2>" | |
2137 | { | |
2138 | COMPAT_2 (OP_6A0 ()); | |
2139 | } | |
2140 | ||
c906108c SS |
2141 | // ZXB |
2142 | 00000000100,RRRRR:I:::zxb | |
2143 | *v850e | |
c5ea1d53 | 2144 | *v850e1 |
2aaed979 KB |
2145 | *v850e2 |
2146 | *v850e2v3 | |
c906108c SS |
2147 | "zxb r<reg1>" |
2148 | { | |
2149 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2150 | GR[reg1] = GR[reg1] & 0xff; | |
2151 | TRACE_ALU_RESULT (GR[reg1]); | |
2152 | } | |
2153 | ||
2154 | // ZXH | |
2155 | 00000000110,RRRRR:I:::zxh | |
2156 | *v850e | |
c5ea1d53 | 2157 | *v850e1 |
2aaed979 KB |
2158 | *v850e2 |
2159 | *v850e2v3 | |
c906108c SS |
2160 | "zxh r<reg1>" |
2161 | { | |
2162 | TRACE_ALU_INPUT1 (GR[reg1]); | |
2163 | GR[reg1] = GR[reg1] & 0xffff; | |
2164 | TRACE_ALU_RESULT (GR[reg1]); | |
2165 | } | |
2166 | ||
c906108c SS |
2167 | // Right field must be zero so that it doesn't clash with DIVH |
2168 | // Left field must be non-zero so that it doesn't clash with SWITCH | |
2169 | 11111,000010,00000:I:::break | |
c5ea1d53 NC |
2170 | *v850 |
2171 | *v850e | |
c906108c SS |
2172 | { |
2173 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
2174 | } | |
2175 | ||
c5ea1d53 NC |
2176 | 11111,000010,00000:I:::dbtrap |
2177 | *v850e1 | |
2aaed979 KB |
2178 | *v850e2 |
2179 | *v850e2v3 | |
c5ea1d53 NC |
2180 | "dbtrap" |
2181 | { | |
2182 | DBPC = cia + 2; | |
2183 | DBPSW = PSW; | |
2184 | PSW = PSW | (PSW_NP | PSW_EP | PSW_ID); | |
2185 | PC = 0x00000060; | |
2186 | nia = 0x00000060; | |
2187 | TRACE_BRANCH0 (); | |
2188 | } | |
2189 | ||
de616bc7 FCE |
2190 | // New breakpoint: 0x7E0 0x7E0 |
2191 | 00000,111111,00000 + 00000,11111,100000:X:::ilgop | |
2192 | { | |
2193 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
2194 | } | |
c5ea1d53 NC |
2195 | |
2196 | // Return from debug trap: 0x146007e0 | |
2197 | 0000011111100000 + 0000000101000110:X:::dbret | |
2198 | *v850e1 | |
2aaed979 KB |
2199 | *v850e2 |
2200 | *v850e2v3 | |
c5ea1d53 NC |
2201 | "dbret" |
2202 | { | |
2203 | nia = DBPC; | |
2204 | PSW = DBPSW; | |
2205 | TRACE_BRANCH1 (PSW); | |
2206 | } | |
2aaed979 KB |
2207 | |
2208 | ||
2209 | // | |
2210 | // FLOAT | |
2211 | // | |
2212 | ||
2213 | // Map condition code to a string | |
2214 | :%s::::FFFF:int FFFF | |
2215 | { | |
2216 | switch (FFFF) | |
2217 | { | |
2218 | case 0: return "f"; | |
2219 | case 1: return "un"; | |
2220 | case 2: return "eq"; | |
2221 | case 3: return "ueq"; | |
2222 | case 4: return "olt"; | |
2223 | case 5: return "ult"; | |
2224 | case 6: return "ole"; | |
2225 | case 7: return "ule"; | |
2226 | case 8: return "sf"; | |
2227 | case 9: return "ngle"; | |
2228 | case 10: return "seq"; | |
2229 | case 11: return "ngl"; | |
2230 | case 12: return "lt"; | |
2231 | case 13: return "nge"; | |
2232 | case 14: return "le"; | |
2233 | case 15: return "ngt"; | |
2234 | } | |
2235 | return "(null)"; | |
2236 | } | |
2237 | ||
2238 | // ABSF.D | |
2239 | rrrr,011111100000 + wwww,010001011000:F_I:::absf_d | |
2240 | *v850e2v3 | |
2241 | "absf.d r<reg2e>, r<reg3e>" | |
2242 | { | |
2243 | sim_fpu ans, wop; | |
2244 | sim_fpu_status status; | |
2245 | ||
2246 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2247 | TRACE_FP_INPUT_FPU1 (&wop); | |
2248 | ||
2249 | status = sim_fpu_abs (&ans, &wop); | |
2250 | check_invalid_snan(sd, status, 1); | |
2251 | ||
2252 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2253 | ||
2254 | TRACE_FP_RESULT_FPU1 (&ans); | |
2255 | } | |
2256 | ||
2257 | // ABSF.S | |
2258 | rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s | |
2259 | *v850e2v3 | |
2260 | "absf.s r<reg2>, r<reg3>" | |
2261 | { | |
2262 | sim_fpu ans, wop; | |
2263 | sim_fpu_status status; | |
2264 | ||
2265 | sim_fpu_32to (&wop, GR[reg2]); | |
2266 | TRACE_FP_INPUT_FPU1 (&wop); | |
2267 | ||
2268 | status = sim_fpu_abs (&ans, &wop); | |
2269 | check_invalid_snan(sd, status, 0); | |
2270 | ||
2271 | sim_fpu_to32 (&GR[reg3], &ans); | |
2272 | TRACE_FP_RESULT_FPU1 (&ans); | |
2273 | } | |
2274 | ||
2275 | // ADDF.D | |
2276 | rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d | |
2277 | *v850e2v3 | |
2278 | "addf.d r<reg1e>, r<reg2e>, r<reg3e>" | |
2279 | { | |
2280 | sim_fpu ans, wop1, wop2; | |
2281 | sim_fpu_status status; | |
2282 | ||
2283 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2284 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2285 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2286 | ||
2287 | status = sim_fpu_add (&ans, &wop1, &wop2); | |
2288 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2289 | ||
2290 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
2291 | ||
2292 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2293 | TRACE_FP_RESULT_FPU1 (&ans); | |
2294 | } | |
2295 | ||
2296 | // ADDF.S | |
2297 | rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s | |
2298 | *v850e2v3 | |
2299 | "addf.s r<reg1>, r<reg2>, r<reg3>" | |
2300 | { | |
2301 | sim_fpu ans, wop1, wop2; | |
2302 | sim_fpu_status status; | |
2303 | ||
2304 | sim_fpu_32to (&wop1, GR[reg1]); | |
2305 | sim_fpu_32to (&wop2, GR[reg2]); | |
2306 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2307 | ||
2308 | status = sim_fpu_add (&ans, &wop1, &wop2); | |
2309 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2310 | ||
2311 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2312 | ||
2313 | sim_fpu_to32 (&GR[reg3], &ans); | |
2314 | TRACE_FP_RESULT_FPU1 (&ans); | |
2315 | } | |
2316 | ||
2317 | // CMOVF.D | |
2318 | rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d | |
2319 | *v850e2v3 | |
2320 | "cmovf.d <bbb>, r<reg1e>, r<reg2e>, r<reg3e>" | |
2321 | { | |
2322 | unsigned int ophi,oplow; | |
2323 | sim_fpu ans, wop1, wop2; | |
2324 | ||
2325 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2326 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2327 | TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2); | |
2328 | ||
2329 | if (TEST_FPCC(bbb)) | |
2330 | { | |
2331 | ophi = GR[reg1e+1]; | |
2332 | oplow = GR[reg1e]; | |
2333 | ans = wop1; | |
2334 | } | |
2335 | else | |
2336 | { | |
2337 | ophi = GR[reg2e+1]; | |
2338 | oplow = GR[reg2e]; | |
2339 | ans = wop2; | |
2340 | } | |
2341 | ||
2342 | GR[reg3e+1] = ophi; | |
2343 | GR[reg3e] = oplow; | |
2344 | TRACE_FP_RESULT_FPU1 (&ans);; | |
2345 | } | |
2346 | ||
2347 | // CMOVF.S | |
d99ff40f | 2348 | rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s |
2aaed979 KB |
2349 | *v850e2v3 |
2350 | "cmovf.d <bbb>, r<reg1>, r<reg2>, r<reg3>" | |
2351 | { | |
2352 | unsigned int op; | |
2353 | sim_fpu ans, wop1, wop2; | |
2354 | ||
2355 | sim_fpu_32to (&wop1, GR[reg1]); | |
2356 | sim_fpu_32to (&wop2, GR[reg2]); | |
2357 | TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2); | |
2358 | ||
2359 | if (TEST_FPCC(bbb)) | |
2360 | { | |
2361 | op = GR[reg1]; | |
2362 | ans = wop1; | |
2363 | } | |
2364 | else | |
2365 | { | |
2366 | op = GR[reg2]; | |
2367 | ans = wop2; | |
2368 | } | |
2369 | ||
2370 | GR[reg3] = op; | |
2371 | TRACE_FP_RESULT_FPU1 (&ans); | |
2372 | } | |
2373 | ||
2374 | // CMPF.D | |
2375 | rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d | |
2376 | *v850e2v3 | |
2377 | "cmpf.d %s<FFFF>, r<reg1e>, r<reg2e>":(bbb == 0) | |
2378 | "cmpf.d %s<FFFF>, r<reg1e>, r<reg2e>, <bbb>" | |
2379 | { | |
2380 | int result; | |
2381 | sim_fpu wop1; | |
2382 | sim_fpu wop2; | |
2383 | ||
2384 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2385 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2386 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2387 | ||
2388 | result = v850_float_compare(sd, FFFF, wop1, wop2, 1); | |
2389 | ||
2390 | if (result) | |
2391 | SET_FPCC(bbb); | |
2392 | else | |
2393 | CLEAR_FPCC(bbb); | |
2394 | ||
2395 | TRACE_FP_RESULT_BOOL (result); | |
2396 | } | |
2397 | ||
2398 | // CMPF.S | |
2399 | rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s | |
2400 | *v850e2v3 | |
2401 | "cmpf.s %s<FFFF>, r<reg1>, r<reg2>":(bbb == 0) | |
2402 | "cmpf.s %s<FFFF>, r<reg1>, r<reg2>, <bbb>" | |
2403 | { | |
2404 | int result; | |
2405 | sim_fpu wop1; | |
2406 | sim_fpu wop2; | |
2407 | ||
2408 | sim_fpu_32to( &wop1, GR[reg1] ); | |
2409 | sim_fpu_32to( &wop2, GR[reg2] ); | |
2410 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2411 | ||
2412 | result = v850_float_compare(sd, FFFF, wop1, wop2, 0); | |
2413 | ||
2414 | if (result) | |
2415 | SET_FPCC(bbb); | |
2416 | else | |
2417 | CLEAR_FPCC(bbb); | |
2418 | ||
2419 | TRACE_FP_RESULT_BOOL (result); | |
2420 | } | |
2421 | ||
2422 | // CVTF.DL | |
2423 | rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl | |
2424 | *v850e2v3 | |
2425 | "cvtf.dl r<reg2e>, r<reg3e>" | |
2426 | { | |
2427 | unsigned64 ans; | |
2428 | sim_fpu wop; | |
2429 | sim_fpu_status status; | |
2430 | ||
2431 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2432 | TRACE_FP_INPUT_FPU1 (&wop); | |
2433 | ||
2434 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2435 | status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND()); | |
2436 | ||
2437 | check_cvt_fi(sd, status, 1); | |
2438 | ||
2439 | GR[reg3e] = ans; | |
2440 | GR[reg3e+1] = ans>>32L; | |
2441 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
2442 | } | |
2443 | ||
2444 | // CVTF.DS | |
2445 | rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds | |
2446 | *v850e2v3 | |
2447 | "cvtf.ds r<reg2e>, r<reg3>" | |
2448 | { | |
2449 | sim_fpu wop; | |
2450 | sim_fpu_status status; | |
2451 | ||
2452 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2453 | TRACE_FP_INPUT_FPU1 (&wop); | |
2454 | ||
2455 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2456 | ||
2457 | check_cvt_fi(sd, status, 0); | |
2458 | ||
2459 | sim_fpu_to32 (&GR[reg3], &wop); | |
2460 | TRACE_FP_RESULT_FPU1 (&wop); | |
2461 | } | |
2462 | ||
2463 | // CVTF.DW | |
2464 | rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw | |
2465 | *v850e2v3 | |
2466 | "cvtf.dw r<reg2e>, r<reg3>" | |
2467 | { | |
2468 | uint32 ans; | |
2469 | sim_fpu wop; | |
2470 | sim_fpu_status status; | |
2471 | ||
2472 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2473 | TRACE_FP_INPUT_FPU1 (&wop); | |
2474 | ||
2475 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2476 | status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND()); | |
2477 | ||
2478 | check_cvt_fi(sd, status, 1); | |
2479 | ||
2480 | GR[reg3] = ans; | |
2481 | TRACE_FP_RESULT_WORD1 (ans); | |
2482 | } | |
2483 | ||
2484 | // CVTF.LD | |
2485 | rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld | |
2486 | *v850e2v3 | |
2487 | "cvtf.ld r<reg2e>, r<reg3e>" | |
2488 | { | |
2489 | signed64 op; | |
2490 | sim_fpu wop; | |
2491 | sim_fpu_status status; | |
2492 | ||
2493 | op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e]; | |
2494 | TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]); | |
2495 | ||
2496 | sim_fpu_i64to (&wop, op, FPSR_GET_ROUND()); | |
2497 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2498 | ||
2499 | check_cvt_if(sd, status, 1); | |
2500 | ||
2501 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); | |
2502 | TRACE_FP_RESULT_FPU1 (&wop); | |
2503 | } | |
2504 | ||
2505 | // CVTF.LS | |
2506 | rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls | |
2507 | *v850e2v3 | |
2508 | "cvtf.ls r<reg2e>, r<reg3>" | |
2509 | { | |
2510 | signed64 op; | |
2511 | sim_fpu wop; | |
2512 | sim_fpu_status status; | |
2513 | ||
2514 | op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e]; | |
2515 | TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]); | |
2516 | ||
2517 | sim_fpu_i64to (&wop, op, FPSR_GET_ROUND()); | |
2518 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2519 | ||
2520 | check_cvt_if(sd, status, 0); | |
2521 | ||
2522 | sim_fpu_to32 (&GR[reg3], &wop); | |
2523 | TRACE_FP_RESULT_FPU1 (&wop); | |
2524 | } | |
2525 | ||
2526 | // CVTF.SD | |
2527 | rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd | |
2528 | *v850e2v3 | |
2529 | "cvtf.sd r<reg2>, r<reg3e>" | |
2530 | { | |
2531 | sim_fpu wop; | |
2532 | sim_fpu_status status; | |
2533 | ||
2534 | sim_fpu_32to (&wop, GR[reg2]); | |
2535 | TRACE_FP_INPUT_FPU1 (&wop); | |
2536 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2537 | ||
2538 | check_cvt_ff(sd, status, 1); | |
2539 | ||
2540 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); | |
2541 | TRACE_FP_RESULT_FPU1 (&wop); | |
2542 | } | |
2543 | ||
2544 | // CVTF.SL | |
2545 | rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl | |
2546 | *v850e2v3 | |
2547 | "cvtf.sl r<reg2>, r<reg3e>" | |
2548 | { | |
2549 | signed64 ans; | |
2550 | sim_fpu wop; | |
2551 | sim_fpu_status status; | |
2552 | ||
2553 | sim_fpu_32to (&wop, GR[reg2]); | |
2554 | TRACE_FP_INPUT_FPU1 (&wop); | |
2555 | ||
2556 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2557 | status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND()); | |
2558 | ||
2559 | check_cvt_fi(sd, status, 0); | |
2560 | ||
2561 | GR[reg3e] = ans; | |
2562 | GR[reg3e+1] = ans >> 32L; | |
2563 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
2564 | } | |
2565 | ||
2566 | // CVTF.SW | |
2567 | rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw | |
2568 | *v850e2v3 | |
2569 | "cvtf.sw r<reg2>, r<reg3>" | |
2570 | { | |
2571 | uint32 ans; | |
2572 | sim_fpu wop; | |
2573 | sim_fpu_status status; | |
2574 | ||
2575 | sim_fpu_32to (&wop, GR[reg2]); | |
2576 | TRACE_FP_INPUT_FPU1 (&wop); | |
2577 | ||
2578 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2579 | status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); | |
2580 | ||
2581 | check_cvt_fi(sd, status, 0); | |
2582 | ||
2583 | GR[reg3] = ans; | |
2584 | TRACE_FP_RESULT_WORD1 (ans); | |
2585 | } | |
2586 | ||
2587 | // CVTF.WD | |
2588 | rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd | |
2589 | *v850e2v3 | |
2590 | "cvtf.wd r<reg2>, r<reg3e>" | |
2591 | { | |
2592 | sim_fpu wop; | |
2593 | sim_fpu_status status; | |
2594 | ||
2595 | TRACE_FP_INPUT_WORD1 (GR[reg2]); | |
2596 | sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND()); | |
2597 | status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2598 | ||
2599 | check_cvt_if(sd, status, 1); | |
2600 | ||
2601 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop); | |
2602 | TRACE_FP_RESULT_FPU1 (&wop); | |
2603 | } | |
2604 | ||
2605 | // CVTF.WS | |
2606 | rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws | |
2607 | *v850e2v3 | |
2608 | "cvtf.ws r<reg2>, r<reg3>" | |
2609 | { | |
2610 | sim_fpu wop; | |
2611 | sim_fpu_status status; | |
2612 | ||
2613 | TRACE_FP_INPUT_WORD1 (GR[reg2]); | |
2614 | sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND()); | |
2615 | status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero); | |
2616 | ||
2617 | check_cvt_if(sd, status, 0); | |
2618 | ||
2619 | sim_fpu_to32 (&GR[reg3], &wop); | |
2620 | TRACE_FP_RESULT_FPU1 (&wop); | |
2621 | } | |
2622 | ||
2623 | // DIVF.D | |
2624 | rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d | |
2625 | *v850e2v3 | |
2626 | "divf.d r<reg1e>, r<reg2e>, r<reg3e>" | |
2627 | { | |
2628 | sim_fpu ans, wop1, wop2; | |
2629 | sim_fpu_status status; | |
2630 | ||
2631 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2632 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2633 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2634 | ||
2635 | status = sim_fpu_div (&ans, &wop2, &wop1); | |
2636 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2637 | ||
2638 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
2639 | ||
2640 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2641 | TRACE_FP_RESULT_FPU1 (&ans); | |
2642 | } | |
2643 | ||
2644 | // DIVF.S | |
2645 | rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s | |
2646 | *v850e2v3 | |
2647 | "divf.s r<reg1>, r<reg2>, r<reg3>" | |
2648 | { | |
2649 | sim_fpu ans, wop1, wop2; | |
2650 | sim_fpu_status status; | |
2651 | ||
2652 | sim_fpu_32to (&wop1, GR[reg1]); | |
2653 | sim_fpu_32to (&wop2, GR[reg2]); | |
2654 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2655 | ||
2656 | status = sim_fpu_div (&ans, &wop2, &wop1); | |
2657 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2658 | ||
2659 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2660 | ||
2661 | sim_fpu_to32 (&GR[reg3], &ans); | |
2662 | TRACE_FP_RESULT_FPU1 (&ans); | |
2663 | } | |
2664 | ||
2665 | // MADDF.S | |
2666 | rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s | |
2667 | *v850e2v3 | |
2668 | "maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" | |
2669 | { | |
2670 | sim_fpu ans, wop1, wop2, wop3; | |
2671 | sim_fpu_status status; | |
2672 | ||
2673 | sim_fpu_32to (&wop1, GR[reg1]); | |
2674 | sim_fpu_32to (&wop2, GR[reg2]); | |
2675 | sim_fpu_32to (&wop3, GR[reg3]); | |
2676 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
2677 | ||
2678 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2aaed979 KB |
2679 | wop1 = ans; |
2680 | status |= sim_fpu_add (&ans, &wop1, &wop3); | |
2681 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2682 | ||
2683 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2684 | ||
2685 | sim_fpu_to32 (&GR[reg4], &ans); | |
2686 | TRACE_FP_RESULT_FPU1 (&ans); | |
2687 | } | |
2688 | ||
2689 | // MAXF.D | |
2690 | rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d | |
2691 | *v850e2v3 | |
2692 | "maxf.d r<reg1e>, r<reg2e>, r<reg3e>" | |
2693 | { | |
2694 | sim_fpu ans, wop1, wop2; | |
2695 | ||
2696 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2697 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2698 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2699 | ||
2700 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2701 | { | |
2702 | if (FPSR & FPSR_XEV) | |
2703 | { | |
2704 | SignalExceptionFPE(sd, 1); | |
2705 | } | |
2706 | else | |
2707 | { | |
2708 | ans = sim_fpu_qnan; | |
2709 | } | |
2710 | } | |
2711 | else if (FPSR & FPSR_FS | |
2712 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2713 | && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) | |
2714 | { | |
2715 | ans = sim_fpu_zero; | |
2716 | } | |
2717 | else | |
2718 | { | |
2719 | sim_fpu_max (&ans, &wop1, &wop2); | |
2720 | } | |
2721 | ||
2722 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2723 | TRACE_FP_RESULT_FPU1 (&ans); | |
2724 | } | |
2725 | ||
2726 | // MAXF.S | |
2727 | rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s | |
2728 | *v850e2v3 | |
2729 | "maxf.s r<reg1>, r<reg2>, r<reg3>" | |
2730 | { | |
2731 | sim_fpu ans, wop1, wop2; | |
2732 | ||
2733 | sim_fpu_32to (&wop1, GR[reg1]); | |
2734 | sim_fpu_32to (&wop2, GR[reg2]); | |
2735 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2736 | ||
2737 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2738 | { | |
2739 | if (FPSR & FPSR_XEV) | |
2740 | { | |
2741 | SignalExceptionFPE(sd, 0); | |
2742 | } | |
2743 | else | |
2744 | { | |
2745 | ans = sim_fpu_qnan; | |
2746 | } | |
2747 | } | |
2748 | else if ((FPSR & FPSR_FS) | |
2749 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2750 | && (sim_fpu_is_zero (&wop2)|| sim_fpu_is_denorm (&wop2)))) | |
2751 | { | |
2752 | ans = sim_fpu_zero; | |
2753 | } | |
2754 | else | |
2755 | { | |
2756 | sim_fpu_max (&ans, &wop1, &wop2); | |
2757 | } | |
2758 | ||
2759 | sim_fpu_to32 (&GR[reg3], &ans); | |
2760 | TRACE_FP_RESULT_FPU1 (&ans); | |
2761 | } | |
2762 | ||
2763 | // MINF.D | |
2764 | rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d | |
2765 | *v850e2v3 | |
2766 | "minf.d r<reg1e>, r<reg2e>, r<reg3e>" | |
2767 | { | |
2768 | sim_fpu ans, wop1, wop2; | |
2769 | ||
2770 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2771 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2772 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2773 | ||
2774 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2775 | { | |
2776 | if (FPSR & FPSR_XEV) | |
2777 | { | |
2778 | SignalExceptionFPE(sd, 1); | |
2779 | } | |
2780 | else | |
2781 | { | |
2782 | ans = sim_fpu_qnan; | |
2783 | } | |
2784 | } | |
2785 | else if (FPSR & FPSR_FS | |
2786 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2787 | && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) | |
2788 | { | |
2789 | ans = sim_fpu_zero; | |
2790 | } | |
2791 | else | |
2792 | { | |
2793 | sim_fpu_min (&ans, &wop1, &wop2); | |
2794 | } | |
2795 | ||
2796 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2797 | TRACE_FP_RESULT_FPU1 (&ans); | |
2798 | } | |
2799 | ||
2800 | // MINF.S | |
2801 | rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s | |
2802 | *v850e2v3 | |
2803 | "minf.s r<reg1>, r<reg2>, r<reg3>" | |
2804 | { | |
2805 | sim_fpu ans, wop1, wop2; | |
2806 | ||
2807 | sim_fpu_32to (&wop1, GR[reg1]); | |
2808 | sim_fpu_32to (&wop2, GR[reg2]); | |
2809 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2810 | ||
2811 | if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2)) | |
2812 | { | |
2813 | if (FPSR & FPSR_XEV) | |
2814 | { | |
2815 | SignalExceptionFPE(sd, 0); | |
2816 | } | |
2817 | else | |
2818 | { | |
2819 | ans = sim_fpu_qnan; | |
2820 | } | |
2821 | } | |
2822 | else if (FPSR & FPSR_FS | |
2823 | && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1)) | |
2824 | && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2)))) | |
2825 | { | |
2826 | ans = sim_fpu_zero; | |
2827 | } | |
2828 | else | |
2829 | { | |
2830 | sim_fpu_min (&ans, &wop1, &wop2); | |
2831 | } | |
2832 | ||
2833 | sim_fpu_to32 (&GR[reg3], &ans); | |
2834 | TRACE_FP_RESULT_FPU1 (&ans); | |
2835 | } | |
2836 | ||
2837 | // MSUBF.S | |
2838 | rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s | |
2839 | *v850e2v3 | |
2840 | "msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" | |
2841 | { | |
2842 | sim_fpu ans, wop1, wop2, wop3; | |
2843 | sim_fpu_status status; | |
2844 | ||
2845 | sim_fpu_32to (&wop1, GR[reg1]); | |
2846 | sim_fpu_32to (&wop2, GR[reg2]); | |
2847 | sim_fpu_32to (&wop3, GR[reg3]); | |
2848 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
2849 | ||
2850 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2851 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2852 | wop1 = ans; | |
2853 | status |= sim_fpu_sub (&ans, &wop1, &wop3); | |
2854 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2855 | ||
2856 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2857 | ||
2858 | sim_fpu_to32 (&GR[reg4], &ans); | |
2859 | TRACE_FP_RESULT_FPU1 (&ans); | |
2860 | } | |
2861 | ||
2862 | // MULF.D | |
2863 | rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d | |
2864 | *v850e2v3 | |
2865 | "mulf.d r<reg1e>, r<reg2e>, r<reg3e>" | |
2866 | { | |
2867 | sim_fpu ans, wop1, wop2; | |
2868 | sim_fpu_status status; | |
2869 | ||
2870 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
2871 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
2872 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2873 | ||
2874 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2875 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2876 | ||
2877 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
2878 | ||
2879 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2880 | TRACE_FP_RESULT_FPU1 (&ans); | |
2881 | } | |
2882 | ||
2883 | // MULF.S | |
2884 | rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s | |
2885 | *v850e2v3 | |
2886 | "mulf.s r<reg1>, r<reg2>, r<reg3>" | |
2887 | { | |
2888 | sim_fpu ans, wop1, wop2; | |
2889 | sim_fpu_status status; | |
2890 | ||
2891 | sim_fpu_32to (&wop1, GR[reg1]); | |
2892 | sim_fpu_32to (&wop2, GR[reg2]); | |
2893 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
2894 | ||
2895 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2896 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2897 | ||
2898 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2899 | ||
2900 | sim_fpu_to32 (&GR[reg3], &ans); | |
2901 | TRACE_FP_RESULT_FPU1 (&ans); | |
2902 | } | |
2903 | ||
2904 | // NEGF.D | |
2905 | rrrr,011111100001 + wwww,010001011000:F_I:::negf_d | |
2906 | *v850e2v3 | |
2907 | "negf.d r<reg2e>, r<reg3e>" | |
2908 | { | |
2909 | sim_fpu ans, wop; | |
2910 | sim_fpu_status status; | |
2911 | ||
2912 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
2913 | TRACE_FP_INPUT_FPU1 (&wop); | |
2914 | ||
2915 | status = sim_fpu_neg (&ans, &wop); | |
2916 | ||
2917 | check_invalid_snan(sd, status, 1); | |
2918 | ||
2919 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
2920 | TRACE_FP_RESULT_FPU1 (&ans); | |
2921 | } | |
2922 | ||
2923 | // NEGF.S | |
2924 | rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s | |
2925 | *v850e2v3 | |
2926 | "negf.s r<reg2>, r<reg3>" | |
2927 | { | |
2928 | sim_fpu ans, wop; | |
2929 | sim_fpu_status status; | |
2930 | ||
2931 | sim_fpu_32to (&wop, GR[reg2]); | |
2932 | TRACE_FP_INPUT_FPU1 (&wop); | |
2933 | ||
2934 | status = sim_fpu_neg (&ans, &wop); | |
2935 | ||
2936 | check_invalid_snan(sd, status, 0); | |
2937 | ||
2938 | sim_fpu_to32 (&GR[reg3], &ans); | |
2939 | TRACE_FP_RESULT_FPU1 (&ans); | |
2940 | } | |
2941 | ||
2942 | // NMADDF.S | |
2943 | rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s | |
2944 | *v850e2v3 | |
2945 | "nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" | |
2946 | { | |
2947 | sim_fpu ans, wop1, wop2, wop3; | |
2948 | sim_fpu_status status; | |
2949 | ||
2950 | sim_fpu_32to (&wop1, GR[reg1]); | |
2951 | sim_fpu_32to (&wop2, GR[reg2]); | |
2952 | sim_fpu_32to (&wop3, GR[reg3]); | |
2953 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
2954 | ||
2955 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2aaed979 KB |
2956 | wop1 = ans; |
2957 | status |= sim_fpu_add (&ans, &wop1, &wop3); | |
2958 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2959 | wop1 = ans; | |
2960 | status |= sim_fpu_neg (&ans, &wop1); | |
2961 | ||
2962 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2963 | ||
2964 | sim_fpu_to32 (&GR[reg4], &ans); | |
2965 | TRACE_FP_RESULT_FPU1 (&ans); | |
2966 | } | |
2967 | ||
2968 | // NMSUBF.S | |
2969 | rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s | |
2970 | *v850e2v3 | |
2971 | "nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>" | |
2972 | { | |
2973 | sim_fpu ans, wop1, wop2, wop3; | |
2974 | sim_fpu_status status; | |
2975 | ||
2976 | sim_fpu_32to (&wop1, GR[reg1]); | |
2977 | sim_fpu_32to (&wop2, GR[reg2]); | |
2978 | sim_fpu_32to (&wop3, GR[reg3]); | |
2979 | TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); | |
2980 | ||
2981 | status = sim_fpu_mul (&ans, &wop1, &wop2); | |
2982 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2983 | wop1 = ans; | |
2984 | status |= sim_fpu_sub (&ans, &wop1, &wop3); | |
2985 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
2986 | wop1 = ans; | |
2987 | status |= sim_fpu_neg (&ans, &wop1); | |
2988 | ||
2989 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
2990 | ||
2991 | sim_fpu_to32 (&GR[reg4], &ans); | |
2992 | TRACE_FP_RESULT_FPU1 (&ans); | |
2993 | } | |
2994 | ||
2995 | // RECIPF.D | |
2996 | rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d | |
2997 | *v850e2v3 | |
2998 | "recipf.d r<reg2e>, r<reg3e>" | |
2999 | { | |
3000 | sim_fpu ans, wop; | |
3001 | sim_fpu_status status; | |
3002 | ||
3003 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3004 | TRACE_FP_INPUT_FPU1 (&wop); | |
3005 | ||
3006 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3007 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3008 | ||
3009 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3010 | ||
3011 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3012 | TRACE_FP_RESULT_FPU1 (&ans); | |
3013 | } | |
3014 | ||
3015 | // RECIPF.S | |
3016 | rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s | |
3017 | *v850e2v3 | |
3018 | "recipf.s r<reg2>, r<reg3>" | |
3019 | { | |
3020 | sim_fpu ans, wop; | |
3021 | sim_fpu_status status; | |
3022 | ||
3023 | sim_fpu_32to (&wop, GR[reg2]); | |
3024 | TRACE_FP_INPUT_FPU1 (&wop); | |
3025 | ||
3026 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3027 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3028 | ||
3029 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3030 | ||
3031 | sim_fpu_to32 (&GR[reg3], &ans); | |
3032 | TRACE_FP_RESULT_FPU1 (&ans); | |
3033 | } | |
3034 | ||
3035 | // RSQRTF.D | |
3036 | rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d | |
3037 | *v850e2v3 | |
3038 | "rsqrtf.d r<reg2e>, r<reg3e>" | |
3039 | { | |
3040 | sim_fpu ans, wop; | |
3041 | sim_fpu_status status; | |
3042 | ||
3043 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3044 | TRACE_FP_INPUT_FPU1 (&wop); | |
3045 | ||
3046 | status = sim_fpu_sqrt (&ans, &wop); | |
3047 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3048 | wop = ans; | |
3049 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3050 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3051 | ||
3052 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3053 | ||
3054 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3055 | TRACE_FP_RESULT_FPU1 (&ans); | |
3056 | } | |
3057 | ||
3058 | // RSQRTF.S | |
3059 | rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s | |
3060 | *v850e2v3 | |
3061 | "rsqrtf.s r<reg2>, r<reg3>" | |
3062 | { | |
3063 | sim_fpu ans, wop; | |
3064 | sim_fpu_status status; | |
3065 | ||
3066 | sim_fpu_32to (&wop, GR[reg2]); | |
3067 | TRACE_FP_INPUT_FPU1 (&wop); | |
3068 | ||
3069 | status = sim_fpu_sqrt (&ans, &wop); | |
3070 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3071 | wop = ans; | |
3072 | status = sim_fpu_div (&ans, &sim_fpu_one, &wop); | |
3073 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3074 | ||
3075 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3076 | ||
3077 | sim_fpu_to32 (&GR[reg3], &ans); | |
3078 | TRACE_FP_RESULT_FPU1 (&ans); | |
3079 | } | |
3080 | ||
3081 | // SQRTF.D | |
3082 | rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d | |
3083 | *v850e2v3 | |
3084 | "sqrtf.d r<reg2e>, r<reg3e>" | |
3085 | { | |
3086 | sim_fpu ans, wop; | |
3087 | sim_fpu_status status; | |
3088 | ||
3089 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3090 | TRACE_FP_INPUT_FPU1 (&wop); | |
3091 | ||
3092 | status = sim_fpu_sqrt (&ans, &wop); | |
3093 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3094 | ||
3095 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1); | |
3096 | ||
3097 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3098 | TRACE_FP_RESULT_FPU1 (&ans); | |
3099 | } | |
3100 | ||
3101 | // SQRTF.S | |
3102 | rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s | |
3103 | *v850e2v3 | |
3104 | "sqrtf.s r<reg2>, r<reg3>" | |
3105 | { | |
3106 | sim_fpu ans, wop; | |
3107 | sim_fpu_status status; | |
3108 | ||
3109 | sim_fpu_32to (&wop, GR[reg2]); | |
3110 | TRACE_FP_INPUT_FPU1 (&wop); | |
3111 | ||
3112 | status = sim_fpu_sqrt (&ans, &wop); | |
3113 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3114 | ||
3115 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0); | |
3116 | ||
3117 | sim_fpu_to32 (&GR[reg3], &ans); | |
3118 | TRACE_FP_RESULT_FPU1 (&ans); | |
3119 | } | |
3120 | ||
3121 | // SUBF.D | |
3122 | rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d | |
3123 | *v850e2v3 | |
3124 | "subf.d r<reg1e>, r<reg2e>, r<reg3e>" | |
3125 | { | |
3126 | sim_fpu ans, wop1, wop2; | |
3127 | sim_fpu_status status; | |
3128 | ||
3129 | sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]); | |
3130 | sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]); | |
3131 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
3132 | ||
3133 | status = sim_fpu_sub (&ans, &wop2, &wop1); | |
3134 | status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3135 | ||
3136 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1); | |
3137 | ||
3138 | sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans); | |
3139 | TRACE_FP_RESULT_FPU1 (&ans); | |
3140 | } | |
3141 | ||
3142 | // SUBF.S | |
3143 | rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s | |
3144 | *v850e2v3 | |
3145 | "subf.s r<reg1>, r<reg2>, r<reg3>" | |
3146 | { | |
3147 | sim_fpu ans, wop1, wop2; | |
3148 | sim_fpu_status status; | |
3149 | ||
3150 | sim_fpu_32to (&wop1, GR[reg1]); | |
3151 | sim_fpu_32to (&wop2, GR[reg2]); | |
3152 | TRACE_FP_INPUT_FPU2 (&wop1, &wop2); | |
3153 | ||
3154 | status = sim_fpu_sub (&ans, &wop2, &wop1); | |
3155 | status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); | |
3156 | ||
3157 | update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0); | |
3158 | ||
3159 | sim_fpu_to32 (&GR[reg3], &ans); | |
3160 | TRACE_FP_RESULT_FPU1 (&ans); | |
3161 | } | |
3162 | ||
3163 | // TRFSR | |
3164 | 0000011111100000 + 000001000000,bbb,0:F_I:::trfsr | |
3165 | *v850e2v3 | |
3166 | "trfsr":(bbb == 0) | |
3167 | "trfsr <bbb>" | |
3168 | { | |
3169 | TRACE_ALU_INPUT1 (GET_FPCC()); | |
3170 | ||
3171 | if (TEST_FPCC (bbb)) | |
3172 | PSW |= PSW_Z; | |
3173 | else | |
3174 | PSW &= ~PSW_Z; | |
3175 | ||
3176 | TRACE_ALU_RESULT1 (PSW); | |
3177 | } | |
3178 | ||
3179 | // TRNCF.DL | |
3180 | rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl | |
3181 | *v850e2v3 | |
3182 | "trncf.dl r<reg2e>, r<reg3e>" | |
3183 | { | |
3184 | signed64 ans; | |
3185 | sim_fpu wop; | |
3186 | sim_fpu_status status; | |
3187 | ||
3188 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3189 | TRACE_FP_INPUT_FPU1 (&wop); | |
3190 | ||
d99ff40f | 3191 | status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3192 | |
3193 | check_cvt_fi(sd, status, 1); | |
3194 | ||
3195 | GR[reg3e] = ans; | |
3196 | GR[reg3e+1] = ans>>32L; | |
3197 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
3198 | } | |
3199 | ||
3200 | // TRNCF.DW | |
3201 | rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw | |
3202 | *v850e2v3 | |
3203 | "trncf.dw r<reg2e>, r<reg3>" | |
3204 | { | |
3205 | uint32 ans; | |
3206 | sim_fpu wop; | |
3207 | sim_fpu_status status; | |
3208 | ||
3209 | sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); | |
3210 | TRACE_FP_INPUT_FPU1 (&wop); | |
3211 | ||
d99ff40f | 3212 | status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3213 | |
3214 | check_cvt_fi(sd, status, 1); | |
3215 | ||
3216 | GR[reg3] = ans; | |
3217 | TRACE_FP_RESULT_WORD1 (ans); | |
3218 | } | |
3219 | ||
3220 | // TRNCF.SL | |
3221 | rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl | |
3222 | *v850e2v3 | |
3223 | "trncf.sl r<reg2>, r<reg3e>" | |
3224 | { | |
3225 | signed64 ans; | |
3226 | sim_fpu wop; | |
3227 | sim_fpu_status status; | |
3228 | ||
3229 | sim_fpu_32to (&wop, GR[reg2]); | |
3230 | TRACE_FP_INPUT_FPU1 (&wop); | |
3231 | ||
d99ff40f | 3232 | status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3233 | |
3234 | GR[reg3e] = ans; | |
3235 | GR[reg3e+1] = ans >> 32L; | |
3236 | TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]); | |
3237 | } | |
3238 | ||
3239 | // TRNCF.SW | |
3240 | rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw | |
3241 | *v850e2v3 | |
3242 | "trncf.sw r<reg2>, r<reg3>" | |
3243 | { | |
3244 | uint32 ans; | |
3245 | sim_fpu wop; | |
3246 | sim_fpu_status status; | |
3247 | ||
3248 | sim_fpu_32to (&wop, GR[reg2]); | |
3249 | TRACE_FP_INPUT_FPU1 (&wop); | |
3250 | ||
d99ff40f | 3251 | status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); |
2aaed979 KB |
3252 | |
3253 | check_cvt_fi(sd, status, 0); | |
3254 | ||
3255 | GR[reg3] = ans; | |
3256 | TRACE_FP_RESULT_WORD1 (ans); | |
3257 | } |