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1da177e4 LT |
1 | /* |
2 | * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge | |
3 | * Processor. | |
4 | * | |
5 | * Copyright 2004 Embedded Edge, LLC | |
6 | * dan@embeddededge.com | |
7 | * | |
8 | * Mostly copied from the au1000.c driver and some from the | |
9 | * PowerMac dbdma driver. | |
10 | * We assume the processor can do memory coherent DMA. | |
11 | * | |
12 | * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License as published by the | |
16 | * Free Software Foundation; either version 2 of the License, or (at your | |
17 | * option) any later version. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
20 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
21 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
22 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
24 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
25 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License along | |
31 | * with this program; if not, write to the Free Software Foundation, Inc., | |
32 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | */ | |
35 | ||
36 | #undef DEBUG | |
37 | ||
1da177e4 LT |
38 | #include <linux/module.h> |
39 | #include <linux/string.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/sound.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/soundcard.h> | |
46 | #include <linux/init.h> | |
47 | #include <linux/interrupt.h> | |
48 | #include <linux/kernel.h> | |
49 | #include <linux/poll.h> | |
50 | #include <linux/pci.h> | |
51 | #include <linux/bitops.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/smp_lock.h> | |
54 | #include <linux/ac97_codec.h> | |
55 | #include <asm/io.h> | |
56 | #include <asm/uaccess.h> | |
57 | #include <asm/hardirq.h> | |
58 | #include <asm/mach-au1x00/au1000.h> | |
59 | #include <asm/mach-au1x00/au1xxx_psc.h> | |
60 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
61 | ||
62 | #undef OSS_DOCUMENTED_MIXER_SEMANTICS | |
63 | ||
64 | /* misc stuff */ | |
65 | #define POLL_COUNT 0x50000 | |
66 | #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC) | |
67 | ||
68 | /* The number of DBDMA ring descriptors to allocate. No sense making | |
69 | * this too large....if you can't keep up with a few you aren't likely | |
70 | * to be able to with lots of them, either. | |
71 | */ | |
72 | #define NUM_DBDMA_DESCRIPTORS 4 | |
73 | ||
74 | #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg) | |
75 | ||
76 | /* Boot options | |
77 | * 0 = no VRA, 1 = use VRA if codec supports it | |
78 | */ | |
79 | static int vra = 1; | |
80 | MODULE_PARM(vra, "i"); | |
81 | MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it"); | |
82 | ||
83 | static struct au1550_state { | |
84 | /* soundcore stuff */ | |
85 | int dev_audio; | |
86 | ||
87 | struct ac97_codec *codec; | |
88 | unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */ | |
89 | unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */ | |
90 | int no_vra; /* do not use VRA */ | |
91 | ||
92 | spinlock_t lock; | |
93 | struct semaphore open_sem; | |
94 | struct semaphore sem; | |
95 | mode_t open_mode; | |
96 | wait_queue_head_t open_wait; | |
97 | ||
98 | struct dmabuf { | |
99 | u32 dmanr; | |
100 | unsigned sample_rate; | |
101 | unsigned src_factor; | |
102 | unsigned sample_size; | |
103 | int num_channels; | |
104 | int dma_bytes_per_sample; | |
105 | int user_bytes_per_sample; | |
106 | int cnt_factor; | |
107 | ||
108 | void *rawbuf; | |
109 | unsigned buforder; | |
110 | unsigned numfrag; | |
111 | unsigned fragshift; | |
112 | void *nextIn; | |
113 | void *nextOut; | |
114 | int count; | |
115 | unsigned total_bytes; | |
116 | unsigned error; | |
117 | wait_queue_head_t wait; | |
118 | ||
119 | /* redundant, but makes calculations easier */ | |
120 | unsigned fragsize; | |
121 | unsigned dma_fragsize; | |
122 | unsigned dmasize; | |
123 | unsigned dma_qcount; | |
124 | ||
125 | /* OSS stuff */ | |
126 | unsigned mapped:1; | |
127 | unsigned ready:1; | |
128 | unsigned stopped:1; | |
129 | unsigned ossfragshift; | |
130 | int ossmaxfrags; | |
131 | unsigned subdivision; | |
132 | } dma_dac, dma_adc; | |
133 | } au1550_state; | |
134 | ||
135 | static unsigned | |
136 | ld2(unsigned int x) | |
137 | { | |
138 | unsigned r = 0; | |
139 | ||
140 | if (x >= 0x10000) { | |
141 | x >>= 16; | |
142 | r += 16; | |
143 | } | |
144 | if (x >= 0x100) { | |
145 | x >>= 8; | |
146 | r += 8; | |
147 | } | |
148 | if (x >= 0x10) { | |
149 | x >>= 4; | |
150 | r += 4; | |
151 | } | |
152 | if (x >= 4) { | |
153 | x >>= 2; | |
154 | r += 2; | |
155 | } | |
156 | if (x >= 2) | |
157 | r++; | |
158 | return r; | |
159 | } | |
160 | ||
161 | static void | |
162 | au1550_delay(int msec) | |
163 | { | |
164 | unsigned long tmo; | |
165 | signed long tmo2; | |
166 | ||
167 | if (in_interrupt()) | |
168 | return; | |
169 | ||
170 | tmo = jiffies + (msec * HZ) / 1000; | |
171 | for (;;) { | |
172 | tmo2 = tmo - jiffies; | |
173 | if (tmo2 <= 0) | |
174 | break; | |
175 | schedule_timeout(tmo2); | |
176 | } | |
177 | } | |
178 | ||
179 | static u16 | |
180 | rdcodec(struct ac97_codec *codec, u8 addr) | |
181 | { | |
182 | struct au1550_state *s = (struct au1550_state *)codec->private_data; | |
183 | unsigned long flags; | |
184 | u32 cmd, val; | |
185 | u16 data; | |
186 | int i; | |
187 | ||
188 | spin_lock_irqsave(&s->lock, flags); | |
189 | ||
190 | for (i = 0; i < POLL_COUNT; i++) { | |
191 | val = au_readl(PSC_AC97STAT); | |
192 | au_sync(); | |
193 | if (!(val & PSC_AC97STAT_CP)) | |
194 | break; | |
195 | } | |
196 | if (i == POLL_COUNT) | |
197 | err("rdcodec: codec cmd pending expired!"); | |
198 | ||
199 | cmd = (u32)PSC_AC97CDC_INDX(addr); | |
200 | cmd |= PSC_AC97CDC_RD; /* read command */ | |
201 | au_writel(cmd, PSC_AC97CDC); | |
202 | au_sync(); | |
203 | ||
204 | /* now wait for the data | |
205 | */ | |
206 | for (i = 0; i < POLL_COUNT; i++) { | |
207 | val = au_readl(PSC_AC97STAT); | |
208 | au_sync(); | |
209 | if (!(val & PSC_AC97STAT_CP)) | |
210 | break; | |
211 | } | |
212 | if (i == POLL_COUNT) { | |
213 | err("rdcodec: read poll expired!"); | |
214 | return 0; | |
215 | } | |
216 | ||
217 | /* wait for command done? | |
218 | */ | |
219 | for (i = 0; i < POLL_COUNT; i++) { | |
220 | val = au_readl(PSC_AC97EVNT); | |
221 | au_sync(); | |
222 | if (val & PSC_AC97EVNT_CD) | |
223 | break; | |
224 | } | |
225 | if (i == POLL_COUNT) { | |
226 | err("rdcodec: read cmdwait expired!"); | |
227 | return 0; | |
228 | } | |
229 | ||
230 | data = au_readl(PSC_AC97CDC) & 0xffff; | |
231 | au_sync(); | |
232 | ||
233 | /* Clear command done event. | |
234 | */ | |
235 | au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT); | |
236 | au_sync(); | |
237 | ||
238 | spin_unlock_irqrestore(&s->lock, flags); | |
239 | ||
240 | return data; | |
241 | } | |
242 | ||
243 | ||
244 | static void | |
245 | wrcodec(struct ac97_codec *codec, u8 addr, u16 data) | |
246 | { | |
247 | struct au1550_state *s = (struct au1550_state *)codec->private_data; | |
248 | unsigned long flags; | |
249 | u32 cmd, val; | |
250 | int i; | |
251 | ||
252 | spin_lock_irqsave(&s->lock, flags); | |
253 | ||
254 | for (i = 0; i < POLL_COUNT; i++) { | |
255 | val = au_readl(PSC_AC97STAT); | |
256 | au_sync(); | |
257 | if (!(val & PSC_AC97STAT_CP)) | |
258 | break; | |
259 | } | |
260 | if (i == POLL_COUNT) | |
261 | err("wrcodec: codec cmd pending expired!"); | |
262 | ||
263 | cmd = (u32)PSC_AC97CDC_INDX(addr); | |
264 | cmd |= (u32)data; | |
265 | au_writel(cmd, PSC_AC97CDC); | |
266 | au_sync(); | |
267 | ||
268 | for (i = 0; i < POLL_COUNT; i++) { | |
269 | val = au_readl(PSC_AC97STAT); | |
270 | au_sync(); | |
271 | if (!(val & PSC_AC97STAT_CP)) | |
272 | break; | |
273 | } | |
274 | if (i == POLL_COUNT) | |
275 | err("wrcodec: codec cmd pending expired!"); | |
276 | ||
277 | for (i = 0; i < POLL_COUNT; i++) { | |
278 | val = au_readl(PSC_AC97EVNT); | |
279 | au_sync(); | |
280 | if (val & PSC_AC97EVNT_CD) | |
281 | break; | |
282 | } | |
283 | if (i == POLL_COUNT) | |
284 | err("wrcodec: read cmdwait expired!"); | |
285 | ||
286 | /* Clear command done event. | |
287 | */ | |
288 | au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT); | |
289 | au_sync(); | |
290 | ||
291 | spin_unlock_irqrestore(&s->lock, flags); | |
292 | } | |
293 | ||
294 | static void | |
295 | waitcodec(struct ac97_codec *codec) | |
296 | { | |
297 | u16 temp; | |
298 | u32 val; | |
299 | int i; | |
300 | ||
301 | /* codec_wait is used to wait for a ready state after | |
302 | * an AC97C_RESET. | |
303 | */ | |
304 | au1550_delay(10); | |
305 | ||
306 | /* first poll the CODEC_READY tag bit | |
307 | */ | |
308 | for (i = 0; i < POLL_COUNT; i++) { | |
309 | val = au_readl(PSC_AC97STAT); | |
310 | au_sync(); | |
311 | if (val & PSC_AC97STAT_CR) | |
312 | break; | |
313 | } | |
314 | if (i == POLL_COUNT) { | |
315 | err("waitcodec: CODEC_READY poll expired!"); | |
316 | return; | |
317 | } | |
318 | ||
319 | /* get AC'97 powerdown control/status register | |
320 | */ | |
321 | temp = rdcodec(codec, AC97_POWER_CONTROL); | |
322 | ||
323 | /* If anything is powered down, power'em up | |
324 | */ | |
325 | if (temp & 0x7f00) { | |
326 | /* Power on | |
327 | */ | |
328 | wrcodec(codec, AC97_POWER_CONTROL, 0); | |
329 | au1550_delay(100); | |
330 | ||
331 | /* Reread | |
332 | */ | |
333 | temp = rdcodec(codec, AC97_POWER_CONTROL); | |
334 | } | |
335 | ||
336 | /* Check if Codec REF,ANL,DAC,ADC ready | |
337 | */ | |
338 | if ((temp & 0x7f0f) != 0x000f) | |
339 | err("codec reg 26 status (0x%x) not ready!!", temp); | |
340 | } | |
341 | ||
342 | /* stop the ADC before calling */ | |
343 | static void | |
344 | set_adc_rate(struct au1550_state *s, unsigned rate) | |
345 | { | |
346 | struct dmabuf *adc = &s->dma_adc; | |
347 | struct dmabuf *dac = &s->dma_dac; | |
348 | unsigned adc_rate, dac_rate; | |
349 | u16 ac97_extstat; | |
350 | ||
351 | if (s->no_vra) { | |
352 | /* calc SRC factor | |
353 | */ | |
354 | adc->src_factor = ((96000 / rate) + 1) >> 1; | |
355 | adc->sample_rate = 48000 / adc->src_factor; | |
356 | return; | |
357 | } | |
358 | ||
359 | adc->src_factor = 1; | |
360 | ||
361 | ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS); | |
362 | ||
363 | rate = rate > 48000 ? 48000 : rate; | |
364 | ||
365 | /* enable VRA | |
366 | */ | |
367 | wrcodec(s->codec, AC97_EXTENDED_STATUS, | |
368 | ac97_extstat | AC97_EXTSTAT_VRA); | |
369 | ||
370 | /* now write the sample rate | |
371 | */ | |
372 | wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate); | |
373 | ||
374 | /* read it back for actual supported rate | |
375 | */ | |
376 | adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE); | |
377 | ||
378 | pr_debug("set_adc_rate: set to %d Hz\n", adc_rate); | |
379 | ||
380 | /* some codec's don't allow unequal DAC and ADC rates, in which case | |
381 | * writing one rate reg actually changes both. | |
382 | */ | |
383 | dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE); | |
384 | if (dac->num_channels > 2) | |
385 | wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate); | |
386 | if (dac->num_channels > 4) | |
387 | wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate); | |
388 | ||
389 | adc->sample_rate = adc_rate; | |
390 | dac->sample_rate = dac_rate; | |
391 | } | |
392 | ||
393 | /* stop the DAC before calling */ | |
394 | static void | |
395 | set_dac_rate(struct au1550_state *s, unsigned rate) | |
396 | { | |
397 | struct dmabuf *dac = &s->dma_dac; | |
398 | struct dmabuf *adc = &s->dma_adc; | |
399 | unsigned adc_rate, dac_rate; | |
400 | u16 ac97_extstat; | |
401 | ||
402 | if (s->no_vra) { | |
403 | /* calc SRC factor | |
404 | */ | |
405 | dac->src_factor = ((96000 / rate) + 1) >> 1; | |
406 | dac->sample_rate = 48000 / dac->src_factor; | |
407 | return; | |
408 | } | |
409 | ||
410 | dac->src_factor = 1; | |
411 | ||
412 | ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS); | |
413 | ||
414 | rate = rate > 48000 ? 48000 : rate; | |
415 | ||
416 | /* enable VRA | |
417 | */ | |
418 | wrcodec(s->codec, AC97_EXTENDED_STATUS, | |
419 | ac97_extstat | AC97_EXTSTAT_VRA); | |
420 | ||
421 | /* now write the sample rate | |
422 | */ | |
423 | wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate); | |
424 | ||
425 | /* I don't support different sample rates for multichannel, | |
426 | * so make these channels the same. | |
427 | */ | |
428 | if (dac->num_channels > 2) | |
429 | wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate); | |
430 | if (dac->num_channels > 4) | |
431 | wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate); | |
432 | /* read it back for actual supported rate | |
433 | */ | |
434 | dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE); | |
435 | ||
436 | pr_debug("set_dac_rate: set to %d Hz\n", dac_rate); | |
437 | ||
438 | /* some codec's don't allow unequal DAC and ADC rates, in which case | |
439 | * writing one rate reg actually changes both. | |
440 | */ | |
441 | adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE); | |
442 | ||
443 | dac->sample_rate = dac_rate; | |
444 | adc->sample_rate = adc_rate; | |
445 | } | |
446 | ||
447 | static void | |
448 | stop_dac(struct au1550_state *s) | |
449 | { | |
450 | struct dmabuf *db = &s->dma_dac; | |
451 | u32 stat; | |
452 | unsigned long flags; | |
453 | ||
454 | if (db->stopped) | |
455 | return; | |
456 | ||
457 | spin_lock_irqsave(&s->lock, flags); | |
458 | ||
459 | au_writel(PSC_AC97PCR_TP, PSC_AC97PCR); | |
460 | au_sync(); | |
461 | ||
462 | /* Wait for Transmit Busy to show disabled. | |
463 | */ | |
464 | do { | |
05090fc9 | 465 | stat = au_readl(PSC_AC97STAT); |
1da177e4 LT |
466 | au_sync(); |
467 | } while ((stat & PSC_AC97STAT_TB) != 0); | |
468 | ||
469 | au1xxx_dbdma_reset(db->dmanr); | |
470 | ||
471 | db->stopped = 1; | |
472 | ||
473 | spin_unlock_irqrestore(&s->lock, flags); | |
474 | } | |
475 | ||
476 | static void | |
477 | stop_adc(struct au1550_state *s) | |
478 | { | |
479 | struct dmabuf *db = &s->dma_adc; | |
480 | unsigned long flags; | |
481 | u32 stat; | |
482 | ||
483 | if (db->stopped) | |
484 | return; | |
485 | ||
486 | spin_lock_irqsave(&s->lock, flags); | |
487 | ||
488 | au_writel(PSC_AC97PCR_RP, PSC_AC97PCR); | |
489 | au_sync(); | |
490 | ||
491 | /* Wait for Receive Busy to show disabled. | |
492 | */ | |
493 | do { | |
05090fc9 | 494 | stat = au_readl(PSC_AC97STAT); |
1da177e4 LT |
495 | au_sync(); |
496 | } while ((stat & PSC_AC97STAT_RB) != 0); | |
497 | ||
498 | au1xxx_dbdma_reset(db->dmanr); | |
499 | ||
500 | db->stopped = 1; | |
501 | ||
502 | spin_unlock_irqrestore(&s->lock, flags); | |
503 | } | |
504 | ||
505 | ||
506 | static void | |
507 | set_xmit_slots(int num_channels) | |
508 | { | |
509 | u32 ac97_config, stat; | |
510 | ||
511 | ac97_config = au_readl(PSC_AC97CFG); | |
512 | au_sync(); | |
513 | ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE); | |
514 | au_writel(ac97_config, PSC_AC97CFG); | |
515 | au_sync(); | |
516 | ||
517 | switch (num_channels) { | |
518 | case 6: /* stereo with surround and center/LFE, | |
519 | * slots 3,4,6,7,8,9 | |
520 | */ | |
521 | ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6); | |
522 | ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9); | |
523 | ||
524 | case 4: /* stereo with surround, slots 3,4,7,8 */ | |
525 | ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7); | |
526 | ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8); | |
527 | ||
528 | case 2: /* stereo, slots 3,4 */ | |
529 | case 1: /* mono */ | |
530 | ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3); | |
531 | ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4); | |
532 | } | |
533 | ||
534 | au_writel(ac97_config, PSC_AC97CFG); | |
535 | au_sync(); | |
536 | ||
537 | ac97_config |= PSC_AC97CFG_DE_ENABLE; | |
538 | au_writel(ac97_config, PSC_AC97CFG); | |
539 | au_sync(); | |
540 | ||
541 | /* Wait for Device ready. | |
542 | */ | |
543 | do { | |
05090fc9 | 544 | stat = au_readl(PSC_AC97STAT); |
1da177e4 LT |
545 | au_sync(); |
546 | } while ((stat & PSC_AC97STAT_DR) == 0); | |
547 | } | |
548 | ||
549 | static void | |
550 | set_recv_slots(int num_channels) | |
551 | { | |
552 | u32 ac97_config, stat; | |
553 | ||
554 | ac97_config = au_readl(PSC_AC97CFG); | |
555 | au_sync(); | |
556 | ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE); | |
557 | au_writel(ac97_config, PSC_AC97CFG); | |
558 | au_sync(); | |
559 | ||
560 | /* Always enable slots 3 and 4 (stereo). Slot 6 is | |
561 | * optional Mic ADC, which we don't support yet. | |
562 | */ | |
563 | ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3); | |
564 | ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4); | |
565 | ||
566 | au_writel(ac97_config, PSC_AC97CFG); | |
567 | au_sync(); | |
568 | ||
569 | ac97_config |= PSC_AC97CFG_DE_ENABLE; | |
570 | au_writel(ac97_config, PSC_AC97CFG); | |
571 | au_sync(); | |
572 | ||
573 | /* Wait for Device ready. | |
574 | */ | |
575 | do { | |
05090fc9 | 576 | stat = au_readl(PSC_AC97STAT); |
1da177e4 LT |
577 | au_sync(); |
578 | } while ((stat & PSC_AC97STAT_DR) == 0); | |
579 | } | |
580 | ||
7b666653 | 581 | /* Hold spinlock for both start_dac() and start_adc() calls */ |
1da177e4 LT |
582 | static void |
583 | start_dac(struct au1550_state *s) | |
584 | { | |
585 | struct dmabuf *db = &s->dma_dac; | |
1da177e4 LT |
586 | |
587 | if (!db->stopped) | |
588 | return; | |
589 | ||
1da177e4 LT |
590 | set_xmit_slots(db->num_channels); |
591 | au_writel(PSC_AC97PCR_TC, PSC_AC97PCR); | |
592 | au_sync(); | |
593 | au_writel(PSC_AC97PCR_TS, PSC_AC97PCR); | |
594 | au_sync(); | |
595 | ||
596 | au1xxx_dbdma_start(db->dmanr); | |
597 | ||
598 | db->stopped = 0; | |
1da177e4 LT |
599 | } |
600 | ||
601 | static void | |
602 | start_adc(struct au1550_state *s) | |
603 | { | |
604 | struct dmabuf *db = &s->dma_adc; | |
605 | int i; | |
606 | ||
607 | if (!db->stopped) | |
608 | return; | |
609 | ||
610 | /* Put two buffers on the ring to get things started. | |
611 | */ | |
612 | for (i=0; i<2; i++) { | |
613 | au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize); | |
614 | ||
615 | db->nextIn += db->dma_fragsize; | |
616 | if (db->nextIn >= db->rawbuf + db->dmasize) | |
617 | db->nextIn -= db->dmasize; | |
618 | } | |
619 | ||
620 | set_recv_slots(db->num_channels); | |
621 | au1xxx_dbdma_start(db->dmanr); | |
622 | au_writel(PSC_AC97PCR_RC, PSC_AC97PCR); | |
623 | au_sync(); | |
624 | au_writel(PSC_AC97PCR_RS, PSC_AC97PCR); | |
625 | au_sync(); | |
626 | ||
627 | db->stopped = 0; | |
628 | } | |
629 | ||
630 | static int | |
631 | prog_dmabuf(struct au1550_state *s, struct dmabuf *db) | |
632 | { | |
633 | unsigned user_bytes_per_sec; | |
634 | unsigned bufs; | |
635 | unsigned rate = db->sample_rate; | |
636 | ||
637 | if (!db->rawbuf) { | |
638 | db->ready = db->mapped = 0; | |
639 | db->buforder = 5; /* 32 * PAGE_SIZE */ | |
640 | db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL); | |
641 | if (!db->rawbuf) | |
642 | return -ENOMEM; | |
643 | } | |
644 | ||
645 | db->cnt_factor = 1; | |
646 | if (db->sample_size == 8) | |
647 | db->cnt_factor *= 2; | |
648 | if (db->num_channels == 1) | |
649 | db->cnt_factor *= 2; | |
650 | db->cnt_factor *= db->src_factor; | |
651 | ||
652 | db->count = 0; | |
653 | db->dma_qcount = 0; | |
654 | db->nextIn = db->nextOut = db->rawbuf; | |
655 | ||
656 | db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels; | |
657 | db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ? | |
658 | 2 : db->num_channels); | |
659 | ||
660 | user_bytes_per_sec = rate * db->user_bytes_per_sample; | |
661 | bufs = PAGE_SIZE << db->buforder; | |
662 | if (db->ossfragshift) { | |
663 | if ((1000 << db->ossfragshift) < user_bytes_per_sec) | |
664 | db->fragshift = ld2(user_bytes_per_sec/1000); | |
665 | else | |
666 | db->fragshift = db->ossfragshift; | |
667 | } else { | |
668 | db->fragshift = ld2(user_bytes_per_sec / 100 / | |
669 | (db->subdivision ? db->subdivision : 1)); | |
670 | if (db->fragshift < 3) | |
671 | db->fragshift = 3; | |
672 | } | |
673 | ||
674 | db->fragsize = 1 << db->fragshift; | |
675 | db->dma_fragsize = db->fragsize * db->cnt_factor; | |
676 | db->numfrag = bufs / db->dma_fragsize; | |
677 | ||
678 | while (db->numfrag < 4 && db->fragshift > 3) { | |
679 | db->fragshift--; | |
680 | db->fragsize = 1 << db->fragshift; | |
681 | db->dma_fragsize = db->fragsize * db->cnt_factor; | |
682 | db->numfrag = bufs / db->dma_fragsize; | |
683 | } | |
684 | ||
685 | if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag) | |
686 | db->numfrag = db->ossmaxfrags; | |
687 | ||
688 | db->dmasize = db->dma_fragsize * db->numfrag; | |
689 | memset(db->rawbuf, 0, bufs); | |
690 | ||
691 | pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n", | |
692 | rate, db->sample_size, db->num_channels); | |
693 | pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n", | |
694 | db->fragsize, db->cnt_factor, db->dma_fragsize); | |
695 | pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize); | |
696 | ||
697 | db->ready = 1; | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static int | |
702 | prog_dmabuf_adc(struct au1550_state *s) | |
703 | { | |
704 | stop_adc(s); | |
705 | return prog_dmabuf(s, &s->dma_adc); | |
706 | ||
707 | } | |
708 | ||
709 | static int | |
710 | prog_dmabuf_dac(struct au1550_state *s) | |
711 | { | |
712 | stop_dac(s); | |
713 | return prog_dmabuf(s, &s->dma_dac); | |
714 | } | |
715 | ||
716 | ||
1da177e4 LT |
717 | static void |
718 | dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
719 | { | |
720 | struct au1550_state *s = (struct au1550_state *) dev_id; | |
721 | struct dmabuf *db = &s->dma_dac; | |
722 | u32 ac97c_stat; | |
723 | ||
7b666653 SS |
724 | spin_lock(&s->lock); |
725 | ||
1da177e4 LT |
726 | ac97c_stat = au_readl(PSC_AC97STAT); |
727 | if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE)) | |
728 | pr_debug("AC97C status = 0x%08x\n", ac97c_stat); | |
729 | db->dma_qcount--; | |
730 | ||
731 | if (db->count >= db->fragsize) { | |
732 | if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, | |
733 | db->fragsize) == 0) { | |
734 | err("qcount < 2 and no ring room!"); | |
735 | } | |
736 | db->nextOut += db->fragsize; | |
737 | if (db->nextOut >= db->rawbuf + db->dmasize) | |
738 | db->nextOut -= db->dmasize; | |
739 | db->count -= db->fragsize; | |
740 | db->total_bytes += db->dma_fragsize; | |
741 | db->dma_qcount++; | |
742 | } | |
743 | ||
744 | /* wake up anybody listening */ | |
745 | if (waitqueue_active(&db->wait)) | |
746 | wake_up(&db->wait); | |
7b666653 SS |
747 | |
748 | spin_unlock(&s->lock); | |
1da177e4 LT |
749 | } |
750 | ||
751 | ||
752 | static void | |
753 | adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
754 | { | |
755 | struct au1550_state *s = (struct au1550_state *)dev_id; | |
756 | struct dmabuf *dp = &s->dma_adc; | |
757 | u32 obytes; | |
758 | char *obuf; | |
759 | ||
7b666653 SS |
760 | spin_lock(&s->lock); |
761 | ||
1da177e4 LT |
762 | /* Pull the buffer from the dma queue. |
763 | */ | |
764 | au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes); | |
765 | ||
766 | if ((dp->count + obytes) > dp->dmasize) { | |
767 | /* Overrun. Stop ADC and log the error | |
768 | */ | |
7b666653 | 769 | spin_unlock(&s->lock); |
1da177e4 LT |
770 | stop_adc(s); |
771 | dp->error++; | |
772 | err("adc overrun"); | |
773 | return; | |
774 | } | |
775 | ||
776 | /* Put a new empty buffer on the destination DMA. | |
777 | */ | |
778 | au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize); | |
779 | ||
780 | dp->nextIn += dp->dma_fragsize; | |
781 | if (dp->nextIn >= dp->rawbuf + dp->dmasize) | |
782 | dp->nextIn -= dp->dmasize; | |
783 | ||
784 | dp->count += obytes; | |
785 | dp->total_bytes += obytes; | |
786 | ||
787 | /* wake up anybody listening | |
788 | */ | |
789 | if (waitqueue_active(&dp->wait)) | |
790 | wake_up(&dp->wait); | |
791 | ||
7b666653 | 792 | spin_unlock(&s->lock); |
1da177e4 LT |
793 | } |
794 | ||
795 | static loff_t | |
796 | au1550_llseek(struct file *file, loff_t offset, int origin) | |
797 | { | |
798 | return -ESPIPE; | |
799 | } | |
800 | ||
801 | ||
802 | static int | |
803 | au1550_open_mixdev(struct inode *inode, struct file *file) | |
804 | { | |
805 | file->private_data = &au1550_state; | |
806 | return 0; | |
807 | } | |
808 | ||
809 | static int | |
810 | au1550_release_mixdev(struct inode *inode, struct file *file) | |
811 | { | |
812 | return 0; | |
813 | } | |
814 | ||
815 | static int | |
816 | mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, | |
817 | unsigned long arg) | |
818 | { | |
819 | return codec->mixer_ioctl(codec, cmd, arg); | |
820 | } | |
821 | ||
822 | static int | |
823 | au1550_ioctl_mixdev(struct inode *inode, struct file *file, | |
824 | unsigned int cmd, unsigned long arg) | |
825 | { | |
826 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
827 | struct ac97_codec *codec = s->codec; | |
828 | ||
829 | return mixdev_ioctl(codec, cmd, arg); | |
830 | } | |
831 | ||
832 | static /*const */ struct file_operations au1550_mixer_fops = { | |
833 | owner:THIS_MODULE, | |
834 | llseek:au1550_llseek, | |
835 | ioctl:au1550_ioctl_mixdev, | |
836 | open:au1550_open_mixdev, | |
837 | release:au1550_release_mixdev, | |
838 | }; | |
839 | ||
840 | static int | |
841 | drain_dac(struct au1550_state *s, int nonblock) | |
842 | { | |
843 | unsigned long flags; | |
844 | int count, tmo; | |
845 | ||
846 | if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped) | |
847 | return 0; | |
848 | ||
849 | for (;;) { | |
850 | spin_lock_irqsave(&s->lock, flags); | |
851 | count = s->dma_dac.count; | |
852 | spin_unlock_irqrestore(&s->lock, flags); | |
853 | if (count <= s->dma_dac.fragsize) | |
854 | break; | |
855 | if (signal_pending(current)) | |
856 | break; | |
857 | if (nonblock) | |
858 | return -EBUSY; | |
859 | tmo = 1000 * count / (s->no_vra ? | |
860 | 48000 : s->dma_dac.sample_rate); | |
861 | tmo /= s->dma_dac.dma_bytes_per_sample; | |
862 | au1550_delay(tmo); | |
863 | } | |
864 | if (signal_pending(current)) | |
865 | return -ERESTARTSYS; | |
866 | return 0; | |
867 | } | |
868 | ||
869 | static inline u8 S16_TO_U8(s16 ch) | |
870 | { | |
871 | return (u8) (ch >> 8) + 0x80; | |
872 | } | |
873 | static inline s16 U8_TO_S16(u8 ch) | |
874 | { | |
875 | return (s16) (ch - 0x80) << 8; | |
876 | } | |
877 | ||
878 | /* | |
879 | * Translates user samples to dma buffer suitable for AC'97 DAC data: | |
880 | * If mono, copy left channel to right channel in dma buffer. | |
881 | * If 8 bit samples, cvt to 16-bit before writing to dma buffer. | |
882 | * If interpolating (no VRA), duplicate every audio frame src_factor times. | |
883 | */ | |
884 | static int | |
885 | translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf, | |
886 | int dmacount) | |
887 | { | |
888 | int sample, i; | |
889 | int interp_bytes_per_sample; | |
890 | int num_samples; | |
891 | int mono = (db->num_channels == 1); | |
892 | char usersample[12]; | |
893 | s16 ch, dmasample[6]; | |
894 | ||
895 | if (db->sample_size == 16 && !mono && db->src_factor == 1) { | |
896 | /* no translation necessary, just copy | |
897 | */ | |
898 | if (copy_from_user(dmabuf, userbuf, dmacount)) | |
899 | return -EFAULT; | |
900 | return dmacount; | |
901 | } | |
902 | ||
903 | interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor; | |
904 | num_samples = dmacount / interp_bytes_per_sample; | |
905 | ||
906 | for (sample = 0; sample < num_samples; sample++) { | |
907 | if (copy_from_user(usersample, userbuf, | |
908 | db->user_bytes_per_sample)) { | |
909 | return -EFAULT; | |
910 | } | |
911 | ||
912 | for (i = 0; i < db->num_channels; i++) { | |
913 | if (db->sample_size == 8) | |
914 | ch = U8_TO_S16(usersample[i]); | |
915 | else | |
916 | ch = *((s16 *) (&usersample[i * 2])); | |
917 | dmasample[i] = ch; | |
918 | if (mono) | |
919 | dmasample[i + 1] = ch; /* right channel */ | |
920 | } | |
921 | ||
922 | /* duplicate every audio frame src_factor times | |
923 | */ | |
924 | for (i = 0; i < db->src_factor; i++) | |
925 | memcpy(dmabuf, dmasample, db->dma_bytes_per_sample); | |
926 | ||
927 | userbuf += db->user_bytes_per_sample; | |
928 | dmabuf += interp_bytes_per_sample; | |
929 | } | |
930 | ||
931 | return num_samples * interp_bytes_per_sample; | |
932 | } | |
933 | ||
934 | /* | |
935 | * Translates AC'97 ADC samples to user buffer: | |
936 | * If mono, send only left channel to user buffer. | |
937 | * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer. | |
938 | * If decimating (no VRA), skip over src_factor audio frames. | |
939 | */ | |
940 | static int | |
941 | translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf, | |
942 | int dmacount) | |
943 | { | |
944 | int sample, i; | |
945 | int interp_bytes_per_sample; | |
946 | int num_samples; | |
947 | int mono = (db->num_channels == 1); | |
948 | char usersample[12]; | |
949 | ||
950 | if (db->sample_size == 16 && !mono && db->src_factor == 1) { | |
951 | /* no translation necessary, just copy | |
952 | */ | |
953 | if (copy_to_user(userbuf, dmabuf, dmacount)) | |
954 | return -EFAULT; | |
955 | return dmacount; | |
956 | } | |
957 | ||
958 | interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor; | |
959 | num_samples = dmacount / interp_bytes_per_sample; | |
960 | ||
961 | for (sample = 0; sample < num_samples; sample++) { | |
962 | for (i = 0; i < db->num_channels; i++) { | |
963 | if (db->sample_size == 8) | |
964 | usersample[i] = | |
965 | S16_TO_U8(*((s16 *) (&dmabuf[i * 2]))); | |
966 | else | |
967 | *((s16 *) (&usersample[i * 2])) = | |
968 | *((s16 *) (&dmabuf[i * 2])); | |
969 | } | |
970 | ||
971 | if (copy_to_user(userbuf, usersample, | |
972 | db->user_bytes_per_sample)) { | |
973 | return -EFAULT; | |
974 | } | |
975 | ||
976 | userbuf += db->user_bytes_per_sample; | |
977 | dmabuf += interp_bytes_per_sample; | |
978 | } | |
979 | ||
980 | return num_samples * interp_bytes_per_sample; | |
981 | } | |
982 | ||
983 | /* | |
984 | * Copy audio data to/from user buffer from/to dma buffer, taking care | |
985 | * that we wrap when reading/writing the dma buffer. Returns actual byte | |
986 | * count written to or read from the dma buffer. | |
987 | */ | |
988 | static int | |
989 | copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user) | |
990 | { | |
991 | char *bufptr = to_user ? db->nextOut : db->nextIn; | |
992 | char *bufend = db->rawbuf + db->dmasize; | |
993 | int cnt, ret; | |
994 | ||
995 | if (bufptr + count > bufend) { | |
996 | int partial = (int) (bufend - bufptr); | |
997 | if (to_user) { | |
998 | if ((cnt = translate_to_user(db, userbuf, | |
999 | bufptr, partial)) < 0) | |
1000 | return cnt; | |
1001 | ret = cnt; | |
1002 | if ((cnt = translate_to_user(db, userbuf + partial, | |
1003 | db->rawbuf, | |
1004 | count - partial)) < 0) | |
1005 | return cnt; | |
1006 | ret += cnt; | |
1007 | } else { | |
1008 | if ((cnt = translate_from_user(db, bufptr, userbuf, | |
1009 | partial)) < 0) | |
1010 | return cnt; | |
1011 | ret = cnt; | |
1012 | if ((cnt = translate_from_user(db, db->rawbuf, | |
1013 | userbuf + partial, | |
1014 | count - partial)) < 0) | |
1015 | return cnt; | |
1016 | ret += cnt; | |
1017 | } | |
1018 | } else { | |
1019 | if (to_user) | |
1020 | ret = translate_to_user(db, userbuf, bufptr, count); | |
1021 | else | |
1022 | ret = translate_from_user(db, bufptr, userbuf, count); | |
1023 | } | |
1024 | ||
1025 | return ret; | |
1026 | } | |
1027 | ||
1028 | ||
1029 | static ssize_t | |
1030 | au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos) | |
1031 | { | |
1032 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
1033 | struct dmabuf *db = &s->dma_adc; | |
1034 | DECLARE_WAITQUEUE(wait, current); | |
1035 | ssize_t ret; | |
1036 | unsigned long flags; | |
1037 | int cnt, usercnt, avail; | |
1038 | ||
1039 | if (db->mapped) | |
1040 | return -ENXIO; | |
1041 | if (!access_ok(VERIFY_WRITE, buffer, count)) | |
1042 | return -EFAULT; | |
1043 | ret = 0; | |
1044 | ||
1045 | count *= db->cnt_factor; | |
1046 | ||
1047 | down(&s->sem); | |
1048 | add_wait_queue(&db->wait, &wait); | |
1049 | ||
1050 | while (count > 0) { | |
1051 | /* wait for samples in ADC dma buffer | |
1052 | */ | |
1053 | do { | |
7b666653 | 1054 | spin_lock_irqsave(&s->lock, flags); |
1da177e4 LT |
1055 | if (db->stopped) |
1056 | start_adc(s); | |
1da177e4 LT |
1057 | avail = db->count; |
1058 | if (avail <= 0) | |
1059 | __set_current_state(TASK_INTERRUPTIBLE); | |
1060 | spin_unlock_irqrestore(&s->lock, flags); | |
1061 | if (avail <= 0) { | |
1062 | if (file->f_flags & O_NONBLOCK) { | |
1063 | if (!ret) | |
1064 | ret = -EAGAIN; | |
1065 | goto out; | |
1066 | } | |
1067 | up(&s->sem); | |
1068 | schedule(); | |
1069 | if (signal_pending(current)) { | |
1070 | if (!ret) | |
1071 | ret = -ERESTARTSYS; | |
1072 | goto out2; | |
1073 | } | |
1074 | down(&s->sem); | |
1075 | } | |
1076 | } while (avail <= 0); | |
1077 | ||
1078 | /* copy from nextOut to user | |
1079 | */ | |
1080 | if ((cnt = copy_dmabuf_user(db, buffer, | |
1081 | count > avail ? | |
1082 | avail : count, 1)) < 0) { | |
1083 | if (!ret) | |
1084 | ret = -EFAULT; | |
1085 | goto out; | |
1086 | } | |
1087 | ||
1088 | spin_lock_irqsave(&s->lock, flags); | |
1089 | db->count -= cnt; | |
1090 | db->nextOut += cnt; | |
1091 | if (db->nextOut >= db->rawbuf + db->dmasize) | |
1092 | db->nextOut -= db->dmasize; | |
1093 | spin_unlock_irqrestore(&s->lock, flags); | |
1094 | ||
1095 | count -= cnt; | |
1096 | usercnt = cnt / db->cnt_factor; | |
1097 | buffer += usercnt; | |
1098 | ret += usercnt; | |
1099 | } /* while (count > 0) */ | |
1100 | ||
1101 | out: | |
1102 | up(&s->sem); | |
1103 | out2: | |
1104 | remove_wait_queue(&db->wait, &wait); | |
1105 | set_current_state(TASK_RUNNING); | |
1106 | return ret; | |
1107 | } | |
1108 | ||
1109 | static ssize_t | |
1110 | au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos) | |
1111 | { | |
1112 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
1113 | struct dmabuf *db = &s->dma_dac; | |
1114 | DECLARE_WAITQUEUE(wait, current); | |
1115 | ssize_t ret = 0; | |
1116 | unsigned long flags; | |
1117 | int cnt, usercnt, avail; | |
1118 | ||
1119 | pr_debug("write: count=%d\n", count); | |
1120 | ||
1121 | if (db->mapped) | |
1122 | return -ENXIO; | |
1123 | if (!access_ok(VERIFY_READ, buffer, count)) | |
1124 | return -EFAULT; | |
1125 | ||
1126 | count *= db->cnt_factor; | |
1127 | ||
1128 | down(&s->sem); | |
1129 | add_wait_queue(&db->wait, &wait); | |
1130 | ||
1131 | while (count > 0) { | |
1132 | /* wait for space in playback buffer | |
1133 | */ | |
1134 | do { | |
1135 | spin_lock_irqsave(&s->lock, flags); | |
1136 | avail = (int) db->dmasize - db->count; | |
1137 | if (avail <= 0) | |
1138 | __set_current_state(TASK_INTERRUPTIBLE); | |
1139 | spin_unlock_irqrestore(&s->lock, flags); | |
1140 | if (avail <= 0) { | |
1141 | if (file->f_flags & O_NONBLOCK) { | |
1142 | if (!ret) | |
1143 | ret = -EAGAIN; | |
1144 | goto out; | |
1145 | } | |
1146 | up(&s->sem); | |
1147 | schedule(); | |
1148 | if (signal_pending(current)) { | |
1149 | if (!ret) | |
1150 | ret = -ERESTARTSYS; | |
1151 | goto out2; | |
1152 | } | |
1153 | down(&s->sem); | |
1154 | } | |
1155 | } while (avail <= 0); | |
1156 | ||
1157 | /* copy from user to nextIn | |
1158 | */ | |
1159 | if ((cnt = copy_dmabuf_user(db, (char *) buffer, | |
1160 | count > avail ? | |
1161 | avail : count, 0)) < 0) { | |
1162 | if (!ret) | |
1163 | ret = -EFAULT; | |
1164 | goto out; | |
1165 | } | |
1166 | ||
1167 | spin_lock_irqsave(&s->lock, flags); | |
1168 | db->count += cnt; | |
1169 | db->nextIn += cnt; | |
1170 | if (db->nextIn >= db->rawbuf + db->dmasize) | |
1171 | db->nextIn -= db->dmasize; | |
1172 | ||
1173 | /* If the data is available, we want to keep two buffers | |
1174 | * on the dma queue. If the queue count reaches zero, | |
1175 | * we know the dma has stopped. | |
1176 | */ | |
1177 | while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) { | |
1178 | if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, | |
1179 | db->fragsize) == 0) { | |
1180 | err("qcount < 2 and no ring room!"); | |
1181 | } | |
1182 | db->nextOut += db->fragsize; | |
1183 | if (db->nextOut >= db->rawbuf + db->dmasize) | |
1184 | db->nextOut -= db->dmasize; | |
1185 | db->total_bytes += db->dma_fragsize; | |
1186 | if (db->dma_qcount == 0) | |
1187 | start_dac(s); | |
1188 | db->dma_qcount++; | |
1189 | } | |
1190 | spin_unlock_irqrestore(&s->lock, flags); | |
1191 | ||
1192 | count -= cnt; | |
1193 | usercnt = cnt / db->cnt_factor; | |
1194 | buffer += usercnt; | |
1195 | ret += usercnt; | |
1196 | } /* while (count > 0) */ | |
1197 | ||
1198 | out: | |
1199 | up(&s->sem); | |
1200 | out2: | |
1201 | remove_wait_queue(&db->wait, &wait); | |
1202 | set_current_state(TASK_RUNNING); | |
1203 | return ret; | |
1204 | } | |
1205 | ||
1206 | ||
1207 | /* No kernel lock - we have our own spinlock */ | |
1208 | static unsigned int | |
1209 | au1550_poll(struct file *file, struct poll_table_struct *wait) | |
1210 | { | |
1211 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
1212 | unsigned long flags; | |
1213 | unsigned int mask = 0; | |
1214 | ||
1215 | if (file->f_mode & FMODE_WRITE) { | |
1216 | if (!s->dma_dac.ready) | |
1217 | return 0; | |
1218 | poll_wait(file, &s->dma_dac.wait, wait); | |
1219 | } | |
1220 | if (file->f_mode & FMODE_READ) { | |
1221 | if (!s->dma_adc.ready) | |
1222 | return 0; | |
1223 | poll_wait(file, &s->dma_adc.wait, wait); | |
1224 | } | |
1225 | ||
1226 | spin_lock_irqsave(&s->lock, flags); | |
1227 | ||
1228 | if (file->f_mode & FMODE_READ) { | |
1229 | if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize) | |
1230 | mask |= POLLIN | POLLRDNORM; | |
1231 | } | |
1232 | if (file->f_mode & FMODE_WRITE) { | |
1233 | if (s->dma_dac.mapped) { | |
1234 | if (s->dma_dac.count >= | |
1235 | (signed)s->dma_dac.dma_fragsize) | |
1236 | mask |= POLLOUT | POLLWRNORM; | |
1237 | } else { | |
1238 | if ((signed) s->dma_dac.dmasize >= | |
1239 | s->dma_dac.count + (signed)s->dma_dac.dma_fragsize) | |
1240 | mask |= POLLOUT | POLLWRNORM; | |
1241 | } | |
1242 | } | |
1243 | spin_unlock_irqrestore(&s->lock, flags); | |
1244 | return mask; | |
1245 | } | |
1246 | ||
1247 | static int | |
1248 | au1550_mmap(struct file *file, struct vm_area_struct *vma) | |
1249 | { | |
1250 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
1251 | struct dmabuf *db; | |
1252 | unsigned long size; | |
1253 | int ret = 0; | |
1254 | ||
1255 | lock_kernel(); | |
1256 | down(&s->sem); | |
1257 | if (vma->vm_flags & VM_WRITE) | |
1258 | db = &s->dma_dac; | |
1259 | else if (vma->vm_flags & VM_READ) | |
1260 | db = &s->dma_adc; | |
1261 | else { | |
1262 | ret = -EINVAL; | |
1263 | goto out; | |
1264 | } | |
1265 | if (vma->vm_pgoff != 0) { | |
1266 | ret = -EINVAL; | |
1267 | goto out; | |
1268 | } | |
1269 | size = vma->vm_end - vma->vm_start; | |
1270 | if (size > (PAGE_SIZE << db->buforder)) { | |
1271 | ret = -EINVAL; | |
1272 | goto out; | |
1273 | } | |
1274 | if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)), | |
1275 | size, vma->vm_page_prot)) { | |
1276 | ret = -EAGAIN; | |
1277 | goto out; | |
1278 | } | |
1279 | vma->vm_flags &= ~VM_IO; | |
1280 | db->mapped = 1; | |
1281 | out: | |
1282 | up(&s->sem); | |
1283 | unlock_kernel(); | |
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | #ifdef DEBUG | |
1288 | static struct ioctl_str_t { | |
1289 | unsigned int cmd; | |
1290 | const char *str; | |
1291 | } ioctl_str[] = { | |
1292 | {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"}, | |
1293 | {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"}, | |
1294 | {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"}, | |
1295 | {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"}, | |
1296 | {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"}, | |
1297 | {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"}, | |
1298 | {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"}, | |
1299 | {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"}, | |
1300 | {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"}, | |
1301 | {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"}, | |
1302 | {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"}, | |
1303 | {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"}, | |
1304 | {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"}, | |
1305 | {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"}, | |
1306 | {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"}, | |
1307 | {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"}, | |
1308 | {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"}, | |
1309 | {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"}, | |
1310 | {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"}, | |
1311 | {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"}, | |
1312 | {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"}, | |
1313 | {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"}, | |
1314 | {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"}, | |
1315 | {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"}, | |
1316 | {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"}, | |
1317 | {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"}, | |
1318 | {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"}, | |
1319 | {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"}, | |
1320 | {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"}, | |
1321 | {OSS_GETVERSION, "OSS_GETVERSION"}, | |
1322 | {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"}, | |
1323 | {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"}, | |
1324 | {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"}, | |
1325 | {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"} | |
1326 | }; | |
1327 | #endif | |
1328 | ||
1329 | static int | |
1330 | dma_count_done(struct dmabuf *db) | |
1331 | { | |
1332 | if (db->stopped) | |
1333 | return 0; | |
1334 | ||
1335 | return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr); | |
1336 | } | |
1337 | ||
1338 | ||
1339 | static int | |
1340 | au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |
1341 | unsigned long arg) | |
1342 | { | |
1343 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
1344 | unsigned long flags; | |
1345 | audio_buf_info abinfo; | |
1346 | count_info cinfo; | |
1347 | int count; | |
1348 | int val, mapped, ret, diff; | |
1349 | ||
1350 | mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) || | |
1351 | ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); | |
1352 | ||
1353 | #ifdef DEBUG | |
1354 | for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) { | |
1355 | if (ioctl_str[count].cmd == cmd) | |
1356 | break; | |
1357 | } | |
1358 | if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0])) | |
1359 | pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg); | |
1360 | else | |
1361 | pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg); | |
1362 | #endif | |
1363 | ||
1364 | switch (cmd) { | |
1365 | case OSS_GETVERSION: | |
1366 | return put_user(SOUND_VERSION, (int *) arg); | |
1367 | ||
1368 | case SNDCTL_DSP_SYNC: | |
1369 | if (file->f_mode & FMODE_WRITE) | |
1370 | return drain_dac(s, file->f_flags & O_NONBLOCK); | |
1371 | return 0; | |
1372 | ||
1373 | case SNDCTL_DSP_SETDUPLEX: | |
1374 | return 0; | |
1375 | ||
1376 | case SNDCTL_DSP_GETCAPS: | |
1377 | return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | | |
1378 | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg); | |
1379 | ||
1380 | case SNDCTL_DSP_RESET: | |
1381 | if (file->f_mode & FMODE_WRITE) { | |
1382 | stop_dac(s); | |
1383 | synchronize_irq(); | |
1384 | s->dma_dac.count = s->dma_dac.total_bytes = 0; | |
1385 | s->dma_dac.nextIn = s->dma_dac.nextOut = | |
1386 | s->dma_dac.rawbuf; | |
1387 | } | |
1388 | if (file->f_mode & FMODE_READ) { | |
1389 | stop_adc(s); | |
1390 | synchronize_irq(); | |
1391 | s->dma_adc.count = s->dma_adc.total_bytes = 0; | |
1392 | s->dma_adc.nextIn = s->dma_adc.nextOut = | |
1393 | s->dma_adc.rawbuf; | |
1394 | } | |
1395 | return 0; | |
1396 | ||
1397 | case SNDCTL_DSP_SPEED: | |
1398 | if (get_user(val, (int *) arg)) | |
1399 | return -EFAULT; | |
1400 | if (val >= 0) { | |
1401 | if (file->f_mode & FMODE_READ) { | |
1402 | stop_adc(s); | |
1403 | set_adc_rate(s, val); | |
1404 | } | |
1405 | if (file->f_mode & FMODE_WRITE) { | |
1406 | stop_dac(s); | |
1407 | set_dac_rate(s, val); | |
1408 | } | |
1409 | if (s->open_mode & FMODE_READ) | |
1410 | if ((ret = prog_dmabuf_adc(s))) | |
1411 | return ret; | |
1412 | if (s->open_mode & FMODE_WRITE) | |
1413 | if ((ret = prog_dmabuf_dac(s))) | |
1414 | return ret; | |
1415 | } | |
1416 | return put_user((file->f_mode & FMODE_READ) ? | |
1417 | s->dma_adc.sample_rate : | |
1418 | s->dma_dac.sample_rate, | |
1419 | (int *)arg); | |
1420 | ||
1421 | case SNDCTL_DSP_STEREO: | |
1422 | if (get_user(val, (int *) arg)) | |
1423 | return -EFAULT; | |
1424 | if (file->f_mode & FMODE_READ) { | |
1425 | stop_adc(s); | |
1426 | s->dma_adc.num_channels = val ? 2 : 1; | |
1427 | if ((ret = prog_dmabuf_adc(s))) | |
1428 | return ret; | |
1429 | } | |
1430 | if (file->f_mode & FMODE_WRITE) { | |
1431 | stop_dac(s); | |
1432 | s->dma_dac.num_channels = val ? 2 : 1; | |
1433 | if (s->codec_ext_caps & AC97_EXT_DACS) { | |
1434 | /* disable surround and center/lfe in AC'97 | |
1435 | */ | |
1436 | u16 ext_stat = rdcodec(s->codec, | |
1437 | AC97_EXTENDED_STATUS); | |
1438 | wrcodec(s->codec, AC97_EXTENDED_STATUS, | |
1439 | ext_stat | (AC97_EXTSTAT_PRI | | |
1440 | AC97_EXTSTAT_PRJ | | |
1441 | AC97_EXTSTAT_PRK)); | |
1442 | } | |
1443 | if ((ret = prog_dmabuf_dac(s))) | |
1444 | return ret; | |
1445 | } | |
1446 | return 0; | |
1447 | ||
1448 | case SNDCTL_DSP_CHANNELS: | |
1449 | if (get_user(val, (int *) arg)) | |
1450 | return -EFAULT; | |
1451 | if (val != 0) { | |
1452 | if (file->f_mode & FMODE_READ) { | |
1453 | if (val < 0 || val > 2) | |
1454 | return -EINVAL; | |
1455 | stop_adc(s); | |
1456 | s->dma_adc.num_channels = val; | |
1457 | if ((ret = prog_dmabuf_adc(s))) | |
1458 | return ret; | |
1459 | } | |
1460 | if (file->f_mode & FMODE_WRITE) { | |
1461 | switch (val) { | |
1462 | case 1: | |
1463 | case 2: | |
1464 | break; | |
1465 | case 3: | |
1466 | case 5: | |
1467 | return -EINVAL; | |
1468 | case 4: | |
1469 | if (!(s->codec_ext_caps & | |
1470 | AC97_EXTID_SDAC)) | |
1471 | return -EINVAL; | |
1472 | break; | |
1473 | case 6: | |
1474 | if ((s->codec_ext_caps & | |
1475 | AC97_EXT_DACS) != AC97_EXT_DACS) | |
1476 | return -EINVAL; | |
1477 | break; | |
1478 | default: | |
1479 | return -EINVAL; | |
1480 | } | |
1481 | ||
1482 | stop_dac(s); | |
1483 | if (val <= 2 && | |
1484 | (s->codec_ext_caps & AC97_EXT_DACS)) { | |
1485 | /* disable surround and center/lfe | |
1486 | * channels in AC'97 | |
1487 | */ | |
1488 | u16 ext_stat = | |
1489 | rdcodec(s->codec, | |
1490 | AC97_EXTENDED_STATUS); | |
1491 | wrcodec(s->codec, | |
1492 | AC97_EXTENDED_STATUS, | |
1493 | ext_stat | (AC97_EXTSTAT_PRI | | |
1494 | AC97_EXTSTAT_PRJ | | |
1495 | AC97_EXTSTAT_PRK)); | |
1496 | } else if (val >= 4) { | |
1497 | /* enable surround, center/lfe | |
1498 | * channels in AC'97 | |
1499 | */ | |
1500 | u16 ext_stat = | |
1501 | rdcodec(s->codec, | |
1502 | AC97_EXTENDED_STATUS); | |
1503 | ext_stat &= ~AC97_EXTSTAT_PRJ; | |
1504 | if (val == 6) | |
1505 | ext_stat &= | |
1506 | ~(AC97_EXTSTAT_PRI | | |
1507 | AC97_EXTSTAT_PRK); | |
1508 | wrcodec(s->codec, | |
1509 | AC97_EXTENDED_STATUS, | |
1510 | ext_stat); | |
1511 | } | |
1512 | ||
1513 | s->dma_dac.num_channels = val; | |
1514 | if ((ret = prog_dmabuf_dac(s))) | |
1515 | return ret; | |
1516 | } | |
1517 | } | |
1518 | return put_user(val, (int *) arg); | |
1519 | ||
1520 | case SNDCTL_DSP_GETFMTS: /* Returns a mask */ | |
1521 | return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg); | |
1522 | ||
1523 | case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */ | |
1524 | if (get_user(val, (int *) arg)) | |
1525 | return -EFAULT; | |
1526 | if (val != AFMT_QUERY) { | |
1527 | if (file->f_mode & FMODE_READ) { | |
1528 | stop_adc(s); | |
1529 | if (val == AFMT_S16_LE) | |
1530 | s->dma_adc.sample_size = 16; | |
1531 | else { | |
1532 | val = AFMT_U8; | |
1533 | s->dma_adc.sample_size = 8; | |
1534 | } | |
1535 | if ((ret = prog_dmabuf_adc(s))) | |
1536 | return ret; | |
1537 | } | |
1538 | if (file->f_mode & FMODE_WRITE) { | |
1539 | stop_dac(s); | |
1540 | if (val == AFMT_S16_LE) | |
1541 | s->dma_dac.sample_size = 16; | |
1542 | else { | |
1543 | val = AFMT_U8; | |
1544 | s->dma_dac.sample_size = 8; | |
1545 | } | |
1546 | if ((ret = prog_dmabuf_dac(s))) | |
1547 | return ret; | |
1548 | } | |
1549 | } else { | |
1550 | if (file->f_mode & FMODE_READ) | |
1551 | val = (s->dma_adc.sample_size == 16) ? | |
1552 | AFMT_S16_LE : AFMT_U8; | |
1553 | else | |
1554 | val = (s->dma_dac.sample_size == 16) ? | |
1555 | AFMT_S16_LE : AFMT_U8; | |
1556 | } | |
1557 | return put_user(val, (int *) arg); | |
1558 | ||
1559 | case SNDCTL_DSP_POST: | |
1560 | return 0; | |
1561 | ||
1562 | case SNDCTL_DSP_GETTRIGGER: | |
1563 | val = 0; | |
1564 | spin_lock_irqsave(&s->lock, flags); | |
1565 | if (file->f_mode & FMODE_READ && !s->dma_adc.stopped) | |
1566 | val |= PCM_ENABLE_INPUT; | |
1567 | if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped) | |
1568 | val |= PCM_ENABLE_OUTPUT; | |
1569 | spin_unlock_irqrestore(&s->lock, flags); | |
1570 | return put_user(val, (int *) arg); | |
1571 | ||
1572 | case SNDCTL_DSP_SETTRIGGER: | |
1573 | if (get_user(val, (int *) arg)) | |
1574 | return -EFAULT; | |
1575 | if (file->f_mode & FMODE_READ) { | |
7b666653 SS |
1576 | if (val & PCM_ENABLE_INPUT) { |
1577 | spin_lock_irqsave(&s->lock, flags); | |
1da177e4 | 1578 | start_adc(s); |
7b666653 SS |
1579 | spin_unlock_irqrestore(&s->lock, flags); |
1580 | } else | |
1da177e4 LT |
1581 | stop_adc(s); |
1582 | } | |
1583 | if (file->f_mode & FMODE_WRITE) { | |
7b666653 SS |
1584 | if (val & PCM_ENABLE_OUTPUT) { |
1585 | spin_lock_irqsave(&s->lock, flags); | |
1da177e4 | 1586 | start_dac(s); |
7b666653 SS |
1587 | spin_unlock_irqrestore(&s->lock, flags); |
1588 | } else | |
1da177e4 LT |
1589 | stop_dac(s); |
1590 | } | |
1591 | return 0; | |
1592 | ||
1593 | case SNDCTL_DSP_GETOSPACE: | |
1594 | if (!(file->f_mode & FMODE_WRITE)) | |
1595 | return -EINVAL; | |
1596 | abinfo.fragsize = s->dma_dac.fragsize; | |
1597 | spin_lock_irqsave(&s->lock, flags); | |
1598 | count = s->dma_dac.count; | |
1599 | count -= dma_count_done(&s->dma_dac); | |
1600 | spin_unlock_irqrestore(&s->lock, flags); | |
1601 | if (count < 0) | |
1602 | count = 0; | |
1603 | abinfo.bytes = (s->dma_dac.dmasize - count) / | |
1604 | s->dma_dac.cnt_factor; | |
1605 | abinfo.fragstotal = s->dma_dac.numfrag; | |
1606 | abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; | |
1607 | pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments); | |
1608 | return copy_to_user((void *) arg, &abinfo, | |
1609 | sizeof(abinfo)) ? -EFAULT : 0; | |
1610 | ||
1611 | case SNDCTL_DSP_GETISPACE: | |
1612 | if (!(file->f_mode & FMODE_READ)) | |
1613 | return -EINVAL; | |
1614 | abinfo.fragsize = s->dma_adc.fragsize; | |
1615 | spin_lock_irqsave(&s->lock, flags); | |
1616 | count = s->dma_adc.count; | |
1617 | count += dma_count_done(&s->dma_adc); | |
1618 | spin_unlock_irqrestore(&s->lock, flags); | |
1619 | if (count < 0) | |
1620 | count = 0; | |
1621 | abinfo.bytes = count / s->dma_adc.cnt_factor; | |
1622 | abinfo.fragstotal = s->dma_adc.numfrag; | |
1623 | abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift; | |
1624 | return copy_to_user((void *) arg, &abinfo, | |
1625 | sizeof(abinfo)) ? -EFAULT : 0; | |
1626 | ||
1627 | case SNDCTL_DSP_NONBLOCK: | |
1628 | file->f_flags |= O_NONBLOCK; | |
1629 | return 0; | |
1630 | ||
1631 | case SNDCTL_DSP_GETODELAY: | |
1632 | if (!(file->f_mode & FMODE_WRITE)) | |
1633 | return -EINVAL; | |
1634 | spin_lock_irqsave(&s->lock, flags); | |
1635 | count = s->dma_dac.count; | |
1636 | count -= dma_count_done(&s->dma_dac); | |
1637 | spin_unlock_irqrestore(&s->lock, flags); | |
1638 | if (count < 0) | |
1639 | count = 0; | |
1640 | count /= s->dma_dac.cnt_factor; | |
1641 | return put_user(count, (int *) arg); | |
1642 | ||
1643 | case SNDCTL_DSP_GETIPTR: | |
1644 | if (!(file->f_mode & FMODE_READ)) | |
1645 | return -EINVAL; | |
1646 | spin_lock_irqsave(&s->lock, flags); | |
1647 | cinfo.bytes = s->dma_adc.total_bytes; | |
1648 | count = s->dma_adc.count; | |
1649 | if (!s->dma_adc.stopped) { | |
1650 | diff = dma_count_done(&s->dma_adc); | |
1651 | count += diff; | |
1652 | cinfo.bytes += diff; | |
1653 | cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff - | |
1654 | virt_to_phys(s->dma_adc.rawbuf); | |
1655 | } else | |
1656 | cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) - | |
1657 | virt_to_phys(s->dma_adc.rawbuf); | |
1658 | if (s->dma_adc.mapped) | |
1659 | s->dma_adc.count &= (s->dma_adc.dma_fragsize-1); | |
1660 | spin_unlock_irqrestore(&s->lock, flags); | |
1661 | if (count < 0) | |
1662 | count = 0; | |
1663 | cinfo.blocks = count >> s->dma_adc.fragshift; | |
1664 | return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)); | |
1665 | ||
1666 | case SNDCTL_DSP_GETOPTR: | |
1667 | if (!(file->f_mode & FMODE_READ)) | |
1668 | return -EINVAL; | |
1669 | spin_lock_irqsave(&s->lock, flags); | |
1670 | cinfo.bytes = s->dma_dac.total_bytes; | |
1671 | count = s->dma_dac.count; | |
1672 | if (!s->dma_dac.stopped) { | |
1673 | diff = dma_count_done(&s->dma_dac); | |
1674 | count -= diff; | |
1675 | cinfo.bytes += diff; | |
1676 | cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff - | |
1677 | virt_to_phys(s->dma_dac.rawbuf); | |
1678 | } else | |
1679 | cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) - | |
1680 | virt_to_phys(s->dma_dac.rawbuf); | |
1681 | if (s->dma_dac.mapped) | |
1682 | s->dma_dac.count &= (s->dma_dac.dma_fragsize-1); | |
1683 | spin_unlock_irqrestore(&s->lock, flags); | |
1684 | if (count < 0) | |
1685 | count = 0; | |
1686 | cinfo.blocks = count >> s->dma_dac.fragshift; | |
1687 | return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)); | |
1688 | ||
1689 | case SNDCTL_DSP_GETBLKSIZE: | |
1690 | if (file->f_mode & FMODE_WRITE) | |
1691 | return put_user(s->dma_dac.fragsize, (int *) arg); | |
1692 | else | |
1693 | return put_user(s->dma_adc.fragsize, (int *) arg); | |
1694 | ||
1695 | case SNDCTL_DSP_SETFRAGMENT: | |
1696 | if (get_user(val, (int *) arg)) | |
1697 | return -EFAULT; | |
1698 | if (file->f_mode & FMODE_READ) { | |
1699 | stop_adc(s); | |
1700 | s->dma_adc.ossfragshift = val & 0xffff; | |
1701 | s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff; | |
1702 | if (s->dma_adc.ossfragshift < 4) | |
1703 | s->dma_adc.ossfragshift = 4; | |
1704 | if (s->dma_adc.ossfragshift > 15) | |
1705 | s->dma_adc.ossfragshift = 15; | |
1706 | if (s->dma_adc.ossmaxfrags < 4) | |
1707 | s->dma_adc.ossmaxfrags = 4; | |
1708 | if ((ret = prog_dmabuf_adc(s))) | |
1709 | return ret; | |
1710 | } | |
1711 | if (file->f_mode & FMODE_WRITE) { | |
1712 | stop_dac(s); | |
1713 | s->dma_dac.ossfragshift = val & 0xffff; | |
1714 | s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff; | |
1715 | if (s->dma_dac.ossfragshift < 4) | |
1716 | s->dma_dac.ossfragshift = 4; | |
1717 | if (s->dma_dac.ossfragshift > 15) | |
1718 | s->dma_dac.ossfragshift = 15; | |
1719 | if (s->dma_dac.ossmaxfrags < 4) | |
1720 | s->dma_dac.ossmaxfrags = 4; | |
1721 | if ((ret = prog_dmabuf_dac(s))) | |
1722 | return ret; | |
1723 | } | |
1724 | return 0; | |
1725 | ||
1726 | case SNDCTL_DSP_SUBDIVIDE: | |
1727 | if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) || | |
1728 | (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision)) | |
1729 | return -EINVAL; | |
1730 | if (get_user(val, (int *) arg)) | |
1731 | return -EFAULT; | |
1732 | if (val != 1 && val != 2 && val != 4) | |
1733 | return -EINVAL; | |
1734 | if (file->f_mode & FMODE_READ) { | |
1735 | stop_adc(s); | |
1736 | s->dma_adc.subdivision = val; | |
1737 | if ((ret = prog_dmabuf_adc(s))) | |
1738 | return ret; | |
1739 | } | |
1740 | if (file->f_mode & FMODE_WRITE) { | |
1741 | stop_dac(s); | |
1742 | s->dma_dac.subdivision = val; | |
1743 | if ((ret = prog_dmabuf_dac(s))) | |
1744 | return ret; | |
1745 | } | |
1746 | return 0; | |
1747 | ||
1748 | case SOUND_PCM_READ_RATE: | |
1749 | return put_user((file->f_mode & FMODE_READ) ? | |
1750 | s->dma_adc.sample_rate : | |
1751 | s->dma_dac.sample_rate, | |
1752 | (int *)arg); | |
1753 | ||
1754 | case SOUND_PCM_READ_CHANNELS: | |
1755 | if (file->f_mode & FMODE_READ) | |
1756 | return put_user(s->dma_adc.num_channels, (int *)arg); | |
1757 | else | |
1758 | return put_user(s->dma_dac.num_channels, (int *)arg); | |
1759 | ||
1760 | case SOUND_PCM_READ_BITS: | |
1761 | if (file->f_mode & FMODE_READ) | |
1762 | return put_user(s->dma_adc.sample_size, (int *)arg); | |
1763 | else | |
1764 | return put_user(s->dma_dac.sample_size, (int *)arg); | |
1765 | ||
1766 | case SOUND_PCM_WRITE_FILTER: | |
1767 | case SNDCTL_DSP_SETSYNCRO: | |
1768 | case SOUND_PCM_READ_FILTER: | |
1769 | return -EINVAL; | |
1770 | } | |
1771 | ||
1772 | return mixdev_ioctl(s->codec, cmd, arg); | |
1773 | } | |
1774 | ||
1775 | ||
1776 | static int | |
1777 | au1550_open(struct inode *inode, struct file *file) | |
1778 | { | |
1779 | int minor = MINOR(inode->i_rdev); | |
1780 | DECLARE_WAITQUEUE(wait, current); | |
1781 | struct au1550_state *s = &au1550_state; | |
1782 | int ret; | |
1783 | ||
1784 | #ifdef DEBUG | |
1785 | if (file->f_flags & O_NONBLOCK) | |
1786 | pr_debug("open: non-blocking\n"); | |
1787 | else | |
1788 | pr_debug("open: blocking\n"); | |
1789 | #endif | |
1790 | ||
1791 | file->private_data = s; | |
1792 | /* wait for device to become free */ | |
1793 | down(&s->open_sem); | |
1794 | while (s->open_mode & file->f_mode) { | |
1795 | if (file->f_flags & O_NONBLOCK) { | |
1796 | up(&s->open_sem); | |
1797 | return -EBUSY; | |
1798 | } | |
1799 | add_wait_queue(&s->open_wait, &wait); | |
1800 | __set_current_state(TASK_INTERRUPTIBLE); | |
1801 | up(&s->open_sem); | |
1802 | schedule(); | |
1803 | remove_wait_queue(&s->open_wait, &wait); | |
1804 | set_current_state(TASK_RUNNING); | |
1805 | if (signal_pending(current)) | |
1806 | return -ERESTARTSYS; | |
1807 | down(&s->open_sem); | |
1808 | } | |
1809 | ||
1810 | stop_dac(s); | |
1811 | stop_adc(s); | |
1812 | ||
1813 | if (file->f_mode & FMODE_READ) { | |
1814 | s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = | |
1815 | s->dma_adc.subdivision = s->dma_adc.total_bytes = 0; | |
1816 | s->dma_adc.num_channels = 1; | |
1817 | s->dma_adc.sample_size = 8; | |
1818 | set_adc_rate(s, 8000); | |
1819 | if ((minor & 0xf) == SND_DEV_DSP16) | |
1820 | s->dma_adc.sample_size = 16; | |
1821 | } | |
1822 | ||
1823 | if (file->f_mode & FMODE_WRITE) { | |
1824 | s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = | |
1825 | s->dma_dac.subdivision = s->dma_dac.total_bytes = 0; | |
1826 | s->dma_dac.num_channels = 1; | |
1827 | s->dma_dac.sample_size = 8; | |
1828 | set_dac_rate(s, 8000); | |
1829 | if ((minor & 0xf) == SND_DEV_DSP16) | |
1830 | s->dma_dac.sample_size = 16; | |
1831 | } | |
1832 | ||
1833 | if (file->f_mode & FMODE_READ) { | |
1834 | if ((ret = prog_dmabuf_adc(s))) | |
1835 | return ret; | |
1836 | } | |
1837 | if (file->f_mode & FMODE_WRITE) { | |
1838 | if ((ret = prog_dmabuf_dac(s))) | |
1839 | return ret; | |
1840 | } | |
1841 | ||
1842 | s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); | |
1843 | up(&s->open_sem); | |
1844 | init_MUTEX(&s->sem); | |
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | static int | |
1849 | au1550_release(struct inode *inode, struct file *file) | |
1850 | { | |
1851 | struct au1550_state *s = (struct au1550_state *)file->private_data; | |
1852 | ||
1853 | lock_kernel(); | |
1854 | ||
1855 | if (file->f_mode & FMODE_WRITE) { | |
1856 | unlock_kernel(); | |
1857 | drain_dac(s, file->f_flags & O_NONBLOCK); | |
1858 | lock_kernel(); | |
1859 | } | |
1860 | ||
1861 | down(&s->open_sem); | |
1862 | if (file->f_mode & FMODE_WRITE) { | |
1863 | stop_dac(s); | |
1864 | kfree(s->dma_dac.rawbuf); | |
1865 | s->dma_dac.rawbuf = NULL; | |
1866 | } | |
1867 | if (file->f_mode & FMODE_READ) { | |
1868 | stop_adc(s); | |
1869 | kfree(s->dma_adc.rawbuf); | |
1870 | s->dma_adc.rawbuf = NULL; | |
1871 | } | |
1872 | s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE)); | |
1873 | up(&s->open_sem); | |
1874 | wake_up(&s->open_wait); | |
1875 | unlock_kernel(); | |
1876 | return 0; | |
1877 | } | |
1878 | ||
1879 | static /*const */ struct file_operations au1550_audio_fops = { | |
1880 | owner: THIS_MODULE, | |
1881 | llseek: au1550_llseek, | |
1882 | read: au1550_read, | |
1883 | write: au1550_write, | |
1884 | poll: au1550_poll, | |
1885 | ioctl: au1550_ioctl, | |
1886 | mmap: au1550_mmap, | |
1887 | open: au1550_open, | |
1888 | release: au1550_release, | |
1889 | }; | |
1890 | ||
1891 | MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com"); | |
1892 | MODULE_DESCRIPTION("Au1550 AC97 Audio Driver"); | |
1893 | ||
1894 | static int __devinit | |
1895 | au1550_probe(void) | |
1896 | { | |
1897 | struct au1550_state *s = &au1550_state; | |
1898 | int val; | |
1899 | ||
1900 | memset(s, 0, sizeof(struct au1550_state)); | |
1901 | ||
1902 | init_waitqueue_head(&s->dma_adc.wait); | |
1903 | init_waitqueue_head(&s->dma_dac.wait); | |
1904 | init_waitqueue_head(&s->open_wait); | |
1905 | init_MUTEX(&s->open_sem); | |
1906 | spin_lock_init(&s->lock); | |
1907 | ||
1908 | s->codec = ac97_alloc_codec(); | |
1909 | if(s->codec == NULL) { | |
1910 | err("Out of memory"); | |
1911 | return -1; | |
1912 | } | |
1913 | s->codec->private_data = s; | |
1914 | s->codec->id = 0; | |
1915 | s->codec->codec_read = rdcodec; | |
1916 | s->codec->codec_write = wrcodec; | |
1917 | s->codec->codec_wait = waitcodec; | |
1918 | ||
1919 | if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL), | |
1920 | 0x30, "Au1550 AC97")) { | |
1921 | err("AC'97 ports in use"); | |
1922 | } | |
1923 | ||
1924 | /* Allocate the DMA Channels | |
1925 | */ | |
1926 | if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN, | |
1927 | DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) { | |
1928 | err("Can't get DAC DMA"); | |
1929 | goto err_dma1; | |
1930 | } | |
1931 | au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16); | |
1932 | if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr, | |
1933 | NUM_DBDMA_DESCRIPTORS) == 0) { | |
1934 | err("Can't get DAC DMA descriptors"); | |
1935 | goto err_dma1; | |
1936 | } | |
1937 | ||
1938 | if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN, | |
1939 | DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) { | |
1940 | err("Can't get ADC DMA"); | |
1941 | goto err_dma2; | |
1942 | } | |
1943 | au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16); | |
1944 | if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr, | |
1945 | NUM_DBDMA_DESCRIPTORS) == 0) { | |
1946 | err("Can't get ADC DMA descriptors"); | |
1947 | goto err_dma2; | |
1948 | } | |
1949 | ||
1950 | pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN); | |
1951 | ||
1952 | /* register devices */ | |
1953 | ||
1954 | if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0) | |
1955 | goto err_dev1; | |
1956 | if ((s->codec->dev_mixer = | |
1957 | register_sound_mixer(&au1550_mixer_fops, -1)) < 0) | |
1958 | goto err_dev2; | |
1959 | ||
1960 | /* The GPIO for the appropriate PSC was configured by the | |
1961 | * board specific start up. | |
1962 | * | |
1963 | * configure PSC for AC'97 | |
1964 | */ | |
1965 | au_writel(0, AC97_PSC_CTRL); /* Disable PSC */ | |
1966 | au_sync(); | |
1967 | au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL); | |
1968 | au_sync(); | |
1969 | ||
1970 | /* cold reset the AC'97 | |
1971 | */ | |
1972 | au_writel(PSC_AC97RST_RST, PSC_AC97RST); | |
1973 | au_sync(); | |
1974 | au1550_delay(10); | |
1975 | au_writel(0, PSC_AC97RST); | |
1976 | au_sync(); | |
1977 | ||
1978 | /* need to delay around 500msec(bleech) to give | |
1979 | some CODECs enough time to wakeup */ | |
1980 | au1550_delay(500); | |
1981 | ||
1982 | /* warm reset the AC'97 to start the bitclk | |
1983 | */ | |
1984 | au_writel(PSC_AC97RST_SNC, PSC_AC97RST); | |
1985 | au_sync(); | |
1986 | udelay(100); | |
1987 | au_writel(0, PSC_AC97RST); | |
1988 | au_sync(); | |
1989 | ||
1990 | /* Enable PSC | |
1991 | */ | |
1992 | au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL); | |
1993 | au_sync(); | |
1994 | ||
1995 | /* Wait for PSC ready. | |
1996 | */ | |
1997 | do { | |
05090fc9 | 1998 | val = au_readl(PSC_AC97STAT); |
1da177e4 LT |
1999 | au_sync(); |
2000 | } while ((val & PSC_AC97STAT_SR) == 0); | |
2001 | ||
2002 | /* Configure AC97 controller. | |
2003 | * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size. | |
2004 | */ | |
2005 | val = PSC_AC97CFG_SET_LEN(16); | |
2006 | val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8; | |
2007 | ||
2008 | /* Enable device so we can at least | |
2009 | * talk over the AC-link. | |
2010 | */ | |
2011 | au_writel(val, PSC_AC97CFG); | |
2012 | au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK); | |
2013 | au_sync(); | |
2014 | val |= PSC_AC97CFG_DE_ENABLE; | |
2015 | au_writel(val, PSC_AC97CFG); | |
2016 | au_sync(); | |
2017 | ||
2018 | /* Wait for Device ready. | |
2019 | */ | |
2020 | do { | |
05090fc9 | 2021 | val = au_readl(PSC_AC97STAT); |
1da177e4 LT |
2022 | au_sync(); |
2023 | } while ((val & PSC_AC97STAT_DR) == 0); | |
2024 | ||
2025 | /* codec init */ | |
2026 | if (!ac97_probe_codec(s->codec)) | |
2027 | goto err_dev3; | |
2028 | ||
2029 | s->codec_base_caps = rdcodec(s->codec, AC97_RESET); | |
2030 | s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID); | |
2031 | pr_info("AC'97 Base/Extended ID = %04x/%04x", | |
2032 | s->codec_base_caps, s->codec_ext_caps); | |
2033 | ||
2034 | if (!(s->codec_ext_caps & AC97_EXTID_VRA)) { | |
2035 | /* codec does not support VRA | |
2036 | */ | |
2037 | s->no_vra = 1; | |
2038 | } else if (!vra) { | |
2039 | /* Boot option says disable VRA | |
2040 | */ | |
2041 | u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS); | |
2042 | wrcodec(s->codec, AC97_EXTENDED_STATUS, | |
2043 | ac97_extstat & ~AC97_EXTSTAT_VRA); | |
2044 | s->no_vra = 1; | |
2045 | } | |
2046 | if (s->no_vra) | |
2047 | pr_info("no VRA, interpolating and decimating"); | |
2048 | ||
2049 | /* set mic to be the recording source */ | |
2050 | val = SOUND_MASK_MIC; | |
2051 | mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, | |
2052 | (unsigned long) &val); | |
2053 | ||
2054 | return 0; | |
2055 | ||
2056 | err_dev3: | |
2057 | unregister_sound_mixer(s->codec->dev_mixer); | |
2058 | err_dev2: | |
2059 | unregister_sound_dsp(s->dev_audio); | |
2060 | err_dev1: | |
2061 | au1xxx_dbdma_chan_free(s->dma_adc.dmanr); | |
2062 | err_dma2: | |
2063 | au1xxx_dbdma_chan_free(s->dma_dac.dmanr); | |
2064 | err_dma1: | |
2065 | release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30); | |
2066 | ||
2067 | ac97_release_codec(s->codec); | |
2068 | return -1; | |
2069 | } | |
2070 | ||
2071 | static void __devinit | |
2072 | au1550_remove(void) | |
2073 | { | |
2074 | struct au1550_state *s = &au1550_state; | |
2075 | ||
2076 | if (!s) | |
2077 | return; | |
2078 | synchronize_irq(); | |
2079 | au1xxx_dbdma_chan_free(s->dma_adc.dmanr); | |
2080 | au1xxx_dbdma_chan_free(s->dma_dac.dmanr); | |
2081 | release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30); | |
2082 | unregister_sound_dsp(s->dev_audio); | |
2083 | unregister_sound_mixer(s->codec->dev_mixer); | |
2084 | ac97_release_codec(s->codec); | |
2085 | } | |
2086 | ||
2087 | static int __init | |
2088 | init_au1550(void) | |
2089 | { | |
2090 | return au1550_probe(); | |
2091 | } | |
2092 | ||
2093 | static void __exit | |
2094 | cleanup_au1550(void) | |
2095 | { | |
2096 | au1550_remove(); | |
2097 | } | |
2098 | ||
2099 | module_init(init_au1550); | |
2100 | module_exit(cleanup_au1550); | |
2101 | ||
2102 | #ifndef MODULE | |
2103 | ||
2104 | static int __init | |
2105 | au1550_setup(char *options) | |
2106 | { | |
2107 | char *this_opt; | |
2108 | ||
2109 | if (!options || !*options) | |
2110 | return 0; | |
2111 | ||
2112 | while ((this_opt = strsep(&options, ","))) { | |
2113 | if (!*this_opt) | |
2114 | continue; | |
2115 | if (!strncmp(this_opt, "vra", 3)) { | |
2116 | vra = 1; | |
2117 | } | |
2118 | } | |
2119 | ||
2120 | return 1; | |
2121 | } | |
2122 | ||
2123 | __setup("au1550_audio=", au1550_setup); | |
2124 | ||
2125 | #endif /* MODULE */ |