Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers | |
3 | * | |
4 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
1da177e4 LT |
22 | #include <asm/io.h> |
23 | #include <linux/delay.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/slab.h> | |
65a77217 | 28 | #include <linux/module.h> |
62932df8 | 29 | #include <linux/mutex.h> |
1da177e4 LT |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/info.h> | |
34 | #include <sound/ac97_codec.h> | |
35 | #include <sound/initval.h> | |
36 | ||
37 | MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); | |
38 | MODULE_DESCRIPTION("ATI IXP AC97 controller"); | |
39 | MODULE_LICENSE("GPL"); | |
f4446ea0 | 40 | MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400/600}}"); |
1da177e4 | 41 | |
b7fe4622 CL |
42 | static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ |
43 | static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ | |
44 | static int ac97_clock = 48000; | |
45 | static char *ac97_quirk; | |
a67ff6a5 | 46 | static bool spdif_aclink = 1; |
14e1d357 | 47 | static int ac97_codec = -1; |
b7fe4622 CL |
48 | |
49 | module_param(index, int, 0444); | |
1da177e4 | 50 | MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); |
b7fe4622 | 51 | module_param(id, charp, 0444); |
1da177e4 | 52 | MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); |
b7fe4622 | 53 | module_param(ac97_clock, int, 0444); |
1da177e4 | 54 | MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); |
b7fe4622 | 55 | module_param(ac97_quirk, charp, 0444); |
1da177e4 | 56 | MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); |
14e1d357 DC |
57 | module_param(ac97_codec, int, 0444); |
58 | MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing."); | |
b7fe4622 | 59 | module_param(spdif_aclink, bool, 0444); |
1da177e4 LT |
60 | MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); |
61 | ||
2b3e584b | 62 | /* just for backward compatibility */ |
a67ff6a5 | 63 | static bool enable; |
698444f3 | 64 | module_param(enable, bool, 0444); |
2b3e584b | 65 | |
1da177e4 LT |
66 | |
67 | /* | |
68 | */ | |
69 | ||
70 | #define ATI_REG_ISR 0x00 /* interrupt source */ | |
71 | #define ATI_REG_ISR_IN_XRUN (1U<<0) | |
72 | #define ATI_REG_ISR_IN_STATUS (1U<<1) | |
73 | #define ATI_REG_ISR_OUT_XRUN (1U<<2) | |
74 | #define ATI_REG_ISR_OUT_STATUS (1U<<3) | |
75 | #define ATI_REG_ISR_SPDF_XRUN (1U<<4) | |
76 | #define ATI_REG_ISR_SPDF_STATUS (1U<<5) | |
77 | #define ATI_REG_ISR_PHYS_INTR (1U<<8) | |
78 | #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) | |
79 | #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) | |
80 | #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) | |
81 | #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) | |
82 | #define ATI_REG_ISR_NEW_FRAME (1U<<13) | |
83 | ||
84 | #define ATI_REG_IER 0x04 /* interrupt enable */ | |
85 | #define ATI_REG_IER_IN_XRUN_EN (1U<<0) | |
86 | #define ATI_REG_IER_IO_STATUS_EN (1U<<1) | |
87 | #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) | |
88 | #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) | |
89 | #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) | |
90 | #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) | |
91 | #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) | |
92 | #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) | |
93 | #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) | |
94 | #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) | |
95 | #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) | |
96 | #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ | |
97 | #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ | |
98 | ||
99 | #define ATI_REG_CMD 0x08 /* command */ | |
100 | #define ATI_REG_CMD_POWERDOWN (1U<<0) | |
101 | #define ATI_REG_CMD_RECEIVE_EN (1U<<1) | |
102 | #define ATI_REG_CMD_SEND_EN (1U<<2) | |
103 | #define ATI_REG_CMD_STATUS_MEM (1U<<3) | |
104 | #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) | |
105 | #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) | |
106 | #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) | |
107 | #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 | |
108 | #define ATI_REG_CMD_IN_DMA_EN (1U<<8) | |
109 | #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) | |
110 | #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) | |
111 | #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) | |
112 | #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) | |
113 | #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) | |
114 | #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) | |
115 | #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) | |
116 | #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) | |
117 | #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) | |
118 | #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) | |
119 | #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) | |
120 | #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) | |
121 | #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) | |
122 | #define ATI_REG_CMD_PACKED_DIS (1U<<24) | |
123 | #define ATI_REG_CMD_BURST_EN (1U<<25) | |
124 | #define ATI_REG_CMD_PANIC_EN (1U<<26) | |
125 | #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) | |
126 | #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) | |
127 | #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) | |
128 | #define ATI_REG_CMD_AC_SYNC (1U<<30) | |
129 | #define ATI_REG_CMD_AC_RESET (1U<<31) | |
130 | ||
131 | #define ATI_REG_PHYS_OUT_ADDR 0x0c | |
132 | #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) | |
133 | #define ATI_REG_PHYS_OUT_RW (1U<<2) | |
134 | #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) | |
135 | #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 | |
136 | #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 | |
137 | ||
138 | #define ATI_REG_PHYS_IN_ADDR 0x10 | |
139 | #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) | |
140 | #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 | |
141 | #define ATI_REG_PHYS_IN_DATA_SHIFT 16 | |
142 | ||
143 | #define ATI_REG_SLOTREQ 0x14 | |
144 | ||
145 | #define ATI_REG_COUNTER 0x18 | |
146 | #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ | |
147 | #define ATI_REG_COUNTER_BITCLOCK (31U<<8) | |
148 | ||
149 | #define ATI_REG_IN_FIFO_THRESHOLD 0x1c | |
150 | ||
151 | #define ATI_REG_IN_DMA_LINKPTR 0x20 | |
152 | #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ | |
153 | #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ | |
154 | #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ | |
155 | #define ATI_REG_IN_DMA_DT_SIZE 0x30 | |
156 | ||
157 | #define ATI_REG_OUT_DMA_SLOT 0x34 | |
158 | #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) | |
159 | #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff | |
160 | #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 | |
161 | #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 | |
162 | ||
163 | #define ATI_REG_OUT_DMA_LINKPTR 0x38 | |
164 | #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ | |
165 | #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ | |
166 | #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ | |
167 | #define ATI_REG_OUT_DMA_DT_SIZE 0x48 | |
168 | ||
169 | #define ATI_REG_SPDF_CMD 0x4c | |
170 | #define ATI_REG_SPDF_CMD_LFSR (1U<<4) | |
171 | #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) | |
172 | #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ | |
173 | ||
174 | #define ATI_REG_SPDF_DMA_LINKPTR 0x50 | |
175 | #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ | |
176 | #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ | |
177 | #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ | |
178 | #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 | |
179 | ||
180 | #define ATI_REG_MODEM_MIRROR 0x7c | |
181 | #define ATI_REG_AUDIO_MIRROR 0x80 | |
182 | ||
183 | #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ | |
184 | #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ | |
185 | ||
186 | #define ATI_REG_FIFO_FLUSH 0x88 | |
187 | #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) | |
188 | #define ATI_REG_FIFO_IN_FLUSH (1U<<1) | |
189 | ||
190 | /* LINKPTR */ | |
191 | #define ATI_REG_LINKPTR_EN (1U<<0) | |
192 | ||
193 | /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ | |
194 | #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) | |
195 | #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) | |
196 | #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) | |
197 | #define ATI_REG_DMA_STATE (7U<<26) | |
198 | ||
199 | ||
200 | #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ | |
201 | ||
202 | ||
74ee4ff1 | 203 | struct atiixp; |
1da177e4 LT |
204 | |
205 | /* | |
206 | * DMA packate descriptor | |
207 | */ | |
208 | ||
74ee4ff1 | 209 | struct atiixp_dma_desc { |
1da177e4 LT |
210 | u32 addr; /* DMA buffer address */ |
211 | u16 status; /* status bits */ | |
212 | u16 size; /* size of the packet in dwords */ | |
213 | u32 next; /* address of the next packet descriptor */ | |
74ee4ff1 | 214 | }; |
1da177e4 LT |
215 | |
216 | /* | |
217 | * stream enum | |
218 | */ | |
219 | enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */ | |
220 | enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */ | |
221 | enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */ | |
222 | ||
223 | #define NUM_ATI_CODECS 3 | |
224 | ||
225 | ||
226 | /* | |
227 | * constants and callbacks for each DMA type | |
228 | */ | |
74ee4ff1 | 229 | struct atiixp_dma_ops { |
1da177e4 LT |
230 | int type; /* ATI_DMA_XXX */ |
231 | unsigned int llp_offset; /* LINKPTR offset */ | |
232 | unsigned int dt_cur; /* DT_CUR offset */ | |
74ee4ff1 TI |
233 | /* called from open callback */ |
234 | void (*enable_dma)(struct atiixp *chip, int on); | |
235 | /* called from trigger (START/STOP) */ | |
236 | void (*enable_transfer)(struct atiixp *chip, int on); | |
237 | /* called from trigger (STOP only) */ | |
238 | void (*flush_dma)(struct atiixp *chip); | |
1da177e4 LT |
239 | }; |
240 | ||
241 | /* | |
242 | * DMA stream | |
243 | */ | |
74ee4ff1 TI |
244 | struct atiixp_dma { |
245 | const struct atiixp_dma_ops *ops; | |
1da177e4 | 246 | struct snd_dma_buffer desc_buf; |
74ee4ff1 | 247 | struct snd_pcm_substream *substream; /* assigned PCM substream */ |
1da177e4 LT |
248 | unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ |
249 | unsigned int period_bytes, periods; | |
250 | int opened; | |
251 | int running; | |
41e4845c | 252 | int suspended; |
1da177e4 LT |
253 | int pcm_open_flag; |
254 | int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ | |
255 | unsigned int saved_curptr; | |
256 | }; | |
257 | ||
258 | /* | |
259 | * ATI IXP chip | |
260 | */ | |
74ee4ff1 TI |
261 | struct atiixp { |
262 | struct snd_card *card; | |
1da177e4 LT |
263 | struct pci_dev *pci; |
264 | ||
265 | unsigned long addr; | |
266 | void __iomem *remap_addr; | |
267 | int irq; | |
268 | ||
74ee4ff1 TI |
269 | struct snd_ac97_bus *ac97_bus; |
270 | struct snd_ac97 *ac97[NUM_ATI_CODECS]; | |
1da177e4 LT |
271 | |
272 | spinlock_t reg_lock; | |
273 | ||
74ee4ff1 | 274 | struct atiixp_dma dmas[NUM_ATI_DMAS]; |
1da177e4 | 275 | struct ac97_pcm *pcms[NUM_ATI_PCMS]; |
74ee4ff1 | 276 | struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS]; |
1da177e4 LT |
277 | |
278 | int max_channels; /* max. channels for PCM out */ | |
279 | ||
280 | unsigned int codec_not_ready_bits; /* for codec detection */ | |
281 | ||
282 | int spdif_over_aclink; /* passed from the module option */ | |
62932df8 | 283 | struct mutex open_mutex; /* playback open mutex */ |
1da177e4 LT |
284 | }; |
285 | ||
286 | ||
287 | /* | |
288 | */ | |
9baa3c34 | 289 | static const struct pci_device_id snd_atiixp_ids[] = { |
28d27aae JP |
290 | { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */ |
291 | { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */ | |
292 | { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */ | |
293 | { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */ | |
1da177e4 LT |
294 | { 0, } |
295 | }; | |
296 | ||
297 | MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); | |
298 | ||
e23e7a14 | 299 | static struct snd_pci_quirk atiixp_quirks[] = { |
dfb12eeb | 300 | SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0), |
f41bea84 TI |
301 | SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0), |
302 | { } /* terminator */ | |
14e1d357 | 303 | }; |
1da177e4 LT |
304 | |
305 | /* | |
306 | * lowlevel functions | |
307 | */ | |
308 | ||
309 | /* | |
310 | * update the bits of the given register. | |
311 | * return 1 if the bits changed. | |
312 | */ | |
74ee4ff1 | 313 | static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg, |
1da177e4 LT |
314 | unsigned int mask, unsigned int value) |
315 | { | |
316 | void __iomem *addr = chip->remap_addr + reg; | |
317 | unsigned int data, old_data; | |
318 | old_data = data = readl(addr); | |
319 | data &= ~mask; | |
320 | data |= value; | |
321 | if (old_data == data) | |
322 | return 0; | |
323 | writel(data, addr); | |
324 | return 1; | |
325 | } | |
326 | ||
327 | /* | |
328 | * macros for easy use | |
329 | */ | |
330 | #define atiixp_write(chip,reg,value) \ | |
331 | writel(value, chip->remap_addr + ATI_REG_##reg) | |
332 | #define atiixp_read(chip,reg) \ | |
333 | readl(chip->remap_addr + ATI_REG_##reg) | |
334 | #define atiixp_update(chip,reg,mask,val) \ | |
335 | snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) | |
336 | ||
1da177e4 LT |
337 | /* |
338 | * handling DMA packets | |
339 | * | |
340 | * we allocate a linear buffer for the DMA, and split it to each packet. | |
341 | * in a future version, a scatter-gather buffer should be implemented. | |
342 | */ | |
343 | ||
344 | #define ATI_DESC_LIST_SIZE \ | |
74ee4ff1 | 345 | PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc)) |
1da177e4 LT |
346 | |
347 | /* | |
348 | * build packets ring for the given buffer size. | |
349 | * | |
350 | * IXP handles the buffer descriptors, which are connected as a linked | |
351 | * list. although we can change the list dynamically, in this version, | |
352 | * a static RING of buffer descriptors is used. | |
353 | * | |
354 | * the ring is built in this function, and is set up to the hardware. | |
355 | */ | |
74ee4ff1 TI |
356 | static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, |
357 | struct snd_pcm_substream *substream, | |
358 | unsigned int periods, | |
359 | unsigned int period_bytes) | |
1da177e4 LT |
360 | { |
361 | unsigned int i; | |
362 | u32 addr, desc_addr; | |
363 | unsigned long flags; | |
364 | ||
365 | if (periods > ATI_MAX_DESCRIPTORS) | |
366 | return -ENOMEM; | |
367 | ||
368 | if (dma->desc_buf.area == NULL) { | |
74ee4ff1 TI |
369 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
370 | snd_dma_pci_data(chip->pci), | |
371 | ATI_DESC_LIST_SIZE, | |
372 | &dma->desc_buf) < 0) | |
1da177e4 LT |
373 | return -ENOMEM; |
374 | dma->period_bytes = dma->periods = 0; /* clear */ | |
375 | } | |
376 | ||
377 | if (dma->periods == periods && dma->period_bytes == period_bytes) | |
378 | return 0; | |
379 | ||
380 | /* reset DMA before changing the descriptor table */ | |
381 | spin_lock_irqsave(&chip->reg_lock, flags); | |
382 | writel(0, chip->remap_addr + dma->ops->llp_offset); | |
383 | dma->ops->enable_dma(chip, 0); | |
384 | dma->ops->enable_dma(chip, 1); | |
385 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
386 | ||
387 | /* fill the entries */ | |
388 | addr = (u32)substream->runtime->dma_addr; | |
389 | desc_addr = (u32)dma->desc_buf.addr; | |
390 | for (i = 0; i < periods; i++) { | |
74ee4ff1 TI |
391 | struct atiixp_dma_desc *desc; |
392 | desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i]; | |
1da177e4 LT |
393 | desc->addr = cpu_to_le32(addr); |
394 | desc->status = 0; | |
395 | desc->size = period_bytes >> 2; /* in dwords */ | |
74ee4ff1 | 396 | desc_addr += sizeof(struct atiixp_dma_desc); |
1da177e4 LT |
397 | if (i == periods - 1) |
398 | desc->next = cpu_to_le32((u32)dma->desc_buf.addr); | |
399 | else | |
400 | desc->next = cpu_to_le32(desc_addr); | |
401 | addr += period_bytes; | |
402 | } | |
403 | ||
404 | writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, | |
405 | chip->remap_addr + dma->ops->llp_offset); | |
406 | ||
407 | dma->period_bytes = period_bytes; | |
408 | dma->periods = periods; | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | /* | |
414 | * remove the ring buffer and release it if assigned | |
415 | */ | |
74ee4ff1 TI |
416 | static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, |
417 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
418 | { |
419 | if (dma->desc_buf.area) { | |
420 | writel(0, chip->remap_addr + dma->ops->llp_offset); | |
421 | snd_dma_free_pages(&dma->desc_buf); | |
422 | dma->desc_buf.area = NULL; | |
423 | } | |
424 | } | |
425 | ||
426 | /* | |
427 | * AC97 interface | |
428 | */ | |
74ee4ff1 | 429 | static int snd_atiixp_acquire_codec(struct atiixp *chip) |
1da177e4 LT |
430 | { |
431 | int timeout = 1000; | |
432 | ||
433 | while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { | |
434 | if (! timeout--) { | |
25135fdc | 435 | dev_warn(chip->card->dev, "codec acquire timeout\n"); |
1da177e4 LT |
436 | return -EBUSY; |
437 | } | |
438 | udelay(1); | |
439 | } | |
440 | return 0; | |
441 | } | |
442 | ||
74ee4ff1 | 443 | static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg) |
1da177e4 LT |
444 | { |
445 | unsigned int data; | |
446 | int timeout; | |
447 | ||
448 | if (snd_atiixp_acquire_codec(chip) < 0) | |
449 | return 0xffff; | |
450 | data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | | |
451 | ATI_REG_PHYS_OUT_ADDR_EN | | |
452 | ATI_REG_PHYS_OUT_RW | | |
453 | codec; | |
454 | atiixp_write(chip, PHYS_OUT_ADDR, data); | |
455 | if (snd_atiixp_acquire_codec(chip) < 0) | |
456 | return 0xffff; | |
457 | timeout = 1000; | |
458 | do { | |
459 | data = atiixp_read(chip, PHYS_IN_ADDR); | |
460 | if (data & ATI_REG_PHYS_IN_READ_FLAG) | |
461 | return data >> ATI_REG_PHYS_IN_DATA_SHIFT; | |
462 | udelay(1); | |
463 | } while (--timeout); | |
464 | /* time out may happen during reset */ | |
465 | if (reg < 0x7c) | |
25135fdc | 466 | dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); |
1da177e4 LT |
467 | return 0xffff; |
468 | } | |
469 | ||
470 | ||
74ee4ff1 TI |
471 | static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec, |
472 | unsigned short reg, unsigned short val) | |
1da177e4 LT |
473 | { |
474 | unsigned int data; | |
475 | ||
476 | if (snd_atiixp_acquire_codec(chip) < 0) | |
477 | return; | |
478 | data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | | |
479 | ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | | |
480 | ATI_REG_PHYS_OUT_ADDR_EN | codec; | |
481 | atiixp_write(chip, PHYS_OUT_ADDR, data); | |
482 | } | |
483 | ||
484 | ||
74ee4ff1 TI |
485 | static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97, |
486 | unsigned short reg) | |
1da177e4 | 487 | { |
74ee4ff1 | 488 | struct atiixp *chip = ac97->private_data; |
1da177e4 LT |
489 | return snd_atiixp_codec_read(chip, ac97->num, reg); |
490 | ||
491 | } | |
492 | ||
74ee4ff1 TI |
493 | static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
494 | unsigned short val) | |
1da177e4 | 495 | { |
74ee4ff1 | 496 | struct atiixp *chip = ac97->private_data; |
1da177e4 LT |
497 | snd_atiixp_codec_write(chip, ac97->num, reg, val); |
498 | } | |
499 | ||
500 | /* | |
501 | * reset AC link | |
502 | */ | |
74ee4ff1 | 503 | static int snd_atiixp_aclink_reset(struct atiixp *chip) |
1da177e4 LT |
504 | { |
505 | int timeout; | |
506 | ||
507 | /* reset powerdoewn */ | |
508 | if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) | |
509 | udelay(10); | |
510 | ||
511 | /* perform a software reset */ | |
512 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); | |
513 | atiixp_read(chip, CMD); | |
514 | udelay(10); | |
515 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); | |
516 | ||
517 | timeout = 10; | |
518 | while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { | |
519 | /* do a hard reset */ | |
520 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, | |
521 | ATI_REG_CMD_AC_SYNC); | |
522 | atiixp_read(chip, CMD); | |
74ee4ff1 | 523 | mdelay(1); |
1da177e4 | 524 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); |
7e79443c | 525 | if (!--timeout) { |
25135fdc | 526 | dev_err(chip->card->dev, "codec reset timeout\n"); |
1da177e4 LT |
527 | break; |
528 | } | |
529 | } | |
530 | ||
531 | /* deassert RESET and assert SYNC to make sure */ | |
532 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, | |
533 | ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
c7561cd8 | 538 | #ifdef CONFIG_PM_SLEEP |
74ee4ff1 | 539 | static int snd_atiixp_aclink_down(struct atiixp *chip) |
1da177e4 LT |
540 | { |
541 | // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ | |
542 | // return -EBUSY; | |
543 | atiixp_update(chip, CMD, | |
544 | ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, | |
545 | ATI_REG_CMD_POWERDOWN); | |
546 | return 0; | |
547 | } | |
548 | #endif | |
549 | ||
550 | /* | |
551 | * auto-detection of codecs | |
552 | * | |
553 | * the IXP chip can generate interrupts for the non-existing codecs. | |
554 | * NEW_FRAME interrupt is used to make sure that the interrupt is generated | |
555 | * even if all three codecs are connected. | |
556 | */ | |
557 | ||
558 | #define ALL_CODEC_NOT_READY \ | |
559 | (ATI_REG_ISR_CODEC0_NOT_READY |\ | |
560 | ATI_REG_ISR_CODEC1_NOT_READY |\ | |
561 | ATI_REG_ISR_CODEC2_NOT_READY) | |
562 | #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) | |
563 | ||
e23e7a14 | 564 | static int ac97_probing_bugs(struct pci_dev *pci) |
14e1d357 | 565 | { |
f41bea84 TI |
566 | const struct snd_pci_quirk *q; |
567 | ||
568 | q = snd_pci_quirk_lookup(pci, atiixp_quirks); | |
569 | if (q) { | |
25135fdc TI |
570 | dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n", |
571 | snd_pci_quirk_name(q), q->value); | |
f41bea84 | 572 | return q->value; |
14e1d357 DC |
573 | } |
574 | /* this hardware doesn't need workarounds. Probe for codec */ | |
575 | return -1; | |
576 | } | |
577 | ||
e23e7a14 | 578 | static int snd_atiixp_codec_detect(struct atiixp *chip) |
1da177e4 LT |
579 | { |
580 | int timeout; | |
581 | ||
582 | chip->codec_not_ready_bits = 0; | |
14e1d357 DC |
583 | if (ac97_codec == -1) |
584 | ac97_codec = ac97_probing_bugs(chip->pci); | |
585 | if (ac97_codec >= 0) { | |
586 | chip->codec_not_ready_bits |= | |
587 | CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10)); | |
588 | return 0; | |
589 | } | |
590 | ||
1da177e4 LT |
591 | atiixp_write(chip, IER, CODEC_CHECK_BITS); |
592 | /* wait for the interrupts */ | |
bfdcbace | 593 | timeout = 50; |
1da177e4 | 594 | while (timeout-- > 0) { |
74ee4ff1 | 595 | mdelay(1); |
1da177e4 LT |
596 | if (chip->codec_not_ready_bits) |
597 | break; | |
598 | } | |
599 | atiixp_write(chip, IER, 0); /* disable irqs */ | |
600 | ||
601 | if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { | |
25135fdc | 602 | dev_err(chip->card->dev, "no codec detected!\n"); |
1da177e4 LT |
603 | return -ENXIO; |
604 | } | |
605 | return 0; | |
606 | } | |
607 | ||
608 | ||
609 | /* | |
610 | * enable DMA and irqs | |
611 | */ | |
74ee4ff1 | 612 | static int snd_atiixp_chip_start(struct atiixp *chip) |
1da177e4 LT |
613 | { |
614 | unsigned int reg; | |
615 | ||
616 | /* set up spdif, enable burst mode */ | |
617 | reg = atiixp_read(chip, CMD); | |
618 | reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; | |
619 | reg |= ATI_REG_CMD_BURST_EN; | |
620 | atiixp_write(chip, CMD, reg); | |
621 | ||
622 | reg = atiixp_read(chip, SPDF_CMD); | |
623 | reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); | |
624 | atiixp_write(chip, SPDF_CMD, reg); | |
625 | ||
626 | /* clear all interrupt source */ | |
627 | atiixp_write(chip, ISR, 0xffffffff); | |
628 | /* enable irqs */ | |
629 | atiixp_write(chip, IER, | |
630 | ATI_REG_IER_IO_STATUS_EN | | |
631 | ATI_REG_IER_IN_XRUN_EN | | |
632 | ATI_REG_IER_OUT_XRUN_EN | | |
633 | ATI_REG_IER_SPDF_XRUN_EN | | |
634 | ATI_REG_IER_SPDF_STATUS_EN); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | ||
639 | /* | |
640 | * disable DMA and IRQs | |
641 | */ | |
74ee4ff1 | 642 | static int snd_atiixp_chip_stop(struct atiixp *chip) |
1da177e4 LT |
643 | { |
644 | /* clear interrupt source */ | |
645 | atiixp_write(chip, ISR, atiixp_read(chip, ISR)); | |
646 | /* disable irqs */ | |
647 | atiixp_write(chip, IER, 0); | |
648 | return 0; | |
649 | } | |
650 | ||
651 | ||
652 | /* | |
653 | * PCM section | |
654 | */ | |
655 | ||
656 | /* | |
657 | * pointer callback simplly reads XXX_DMA_DT_CUR register as the current | |
658 | * position. when SG-buffer is implemented, the offset must be calculated | |
659 | * correctly... | |
660 | */ | |
74ee4ff1 | 661 | static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 662 | { |
74ee4ff1 TI |
663 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
664 | struct snd_pcm_runtime *runtime = substream->runtime; | |
665 | struct atiixp_dma *dma = runtime->private_data; | |
1da177e4 LT |
666 | unsigned int curptr; |
667 | int timeout = 1000; | |
668 | ||
669 | while (timeout--) { | |
670 | curptr = readl(chip->remap_addr + dma->ops->dt_cur); | |
671 | if (curptr < dma->buf_addr) | |
672 | continue; | |
673 | curptr -= dma->buf_addr; | |
674 | if (curptr >= dma->buf_bytes) | |
675 | continue; | |
676 | return bytes_to_frames(runtime, curptr); | |
677 | } | |
25135fdc | 678 | dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n", |
1da177e4 LT |
679 | readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); |
680 | return 0; | |
681 | } | |
682 | ||
683 | /* | |
684 | * XRUN detected, and stop the PCM substream | |
685 | */ | |
74ee4ff1 | 686 | static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma) |
1da177e4 LT |
687 | { |
688 | if (! dma->substream || ! dma->running) | |
689 | return; | |
25135fdc | 690 | dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type); |
cc7282b8 | 691 | snd_pcm_stream_lock(dma->substream); |
1da177e4 | 692 | snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN); |
cc7282b8 | 693 | snd_pcm_stream_unlock(dma->substream); |
1da177e4 LT |
694 | } |
695 | ||
696 | /* | |
697 | * the period ack. update the substream. | |
698 | */ | |
74ee4ff1 | 699 | static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma) |
1da177e4 LT |
700 | { |
701 | if (! dma->substream || ! dma->running) | |
702 | return; | |
703 | snd_pcm_period_elapsed(dma->substream); | |
704 | } | |
705 | ||
706 | /* set BUS_BUSY interrupt bit if any DMA is running */ | |
707 | /* call with spinlock held */ | |
74ee4ff1 | 708 | static void snd_atiixp_check_bus_busy(struct atiixp *chip) |
1da177e4 LT |
709 | { |
710 | unsigned int bus_busy; | |
711 | if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN | | |
712 | ATI_REG_CMD_RECEIVE_EN | | |
713 | ATI_REG_CMD_SPDF_OUT_EN)) | |
714 | bus_busy = ATI_REG_IER_SET_BUS_BUSY; | |
715 | else | |
716 | bus_busy = 0; | |
717 | atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy); | |
718 | } | |
719 | ||
720 | /* common trigger callback | |
721 | * calling the lowlevel callbacks in it | |
722 | */ | |
74ee4ff1 | 723 | static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 724 | { |
74ee4ff1 TI |
725 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
726 | struct atiixp_dma *dma = substream->runtime->private_data; | |
1da177e4 LT |
727 | int err = 0; |
728 | ||
da3cec35 TI |
729 | if (snd_BUG_ON(!dma->ops->enable_transfer || |
730 | !dma->ops->flush_dma)) | |
731 | return -EINVAL; | |
1da177e4 LT |
732 | |
733 | spin_lock(&chip->reg_lock); | |
734 | switch (cmd) { | |
735 | case SNDRV_PCM_TRIGGER_START: | |
41e4845c JK |
736 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
737 | case SNDRV_PCM_TRIGGER_RESUME: | |
1da177e4 LT |
738 | dma->ops->enable_transfer(chip, 1); |
739 | dma->running = 1; | |
41e4845c | 740 | dma->suspended = 0; |
1da177e4 LT |
741 | break; |
742 | case SNDRV_PCM_TRIGGER_STOP: | |
41e4845c JK |
743 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
744 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1da177e4 LT |
745 | dma->ops->enable_transfer(chip, 0); |
746 | dma->running = 0; | |
41e4845c | 747 | dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND; |
1da177e4 LT |
748 | break; |
749 | default: | |
750 | err = -EINVAL; | |
751 | break; | |
752 | } | |
753 | if (! err) { | |
754 | snd_atiixp_check_bus_busy(chip); | |
755 | if (cmd == SNDRV_PCM_TRIGGER_STOP) { | |
756 | dma->ops->flush_dma(chip); | |
757 | snd_atiixp_check_bus_busy(chip); | |
758 | } | |
759 | } | |
760 | spin_unlock(&chip->reg_lock); | |
761 | return err; | |
762 | } | |
763 | ||
764 | ||
765 | /* | |
766 | * lowlevel callbacks for each DMA type | |
767 | * | |
768 | * every callback is supposed to be called in chip->reg_lock spinlock | |
769 | */ | |
770 | ||
771 | /* flush FIFO of analog OUT DMA */ | |
74ee4ff1 | 772 | static void atiixp_out_flush_dma(struct atiixp *chip) |
1da177e4 LT |
773 | { |
774 | atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH); | |
775 | } | |
776 | ||
777 | /* enable/disable analog OUT DMA */ | |
74ee4ff1 | 778 | static void atiixp_out_enable_dma(struct atiixp *chip, int on) |
1da177e4 LT |
779 | { |
780 | unsigned int data; | |
781 | data = atiixp_read(chip, CMD); | |
782 | if (on) { | |
783 | if (data & ATI_REG_CMD_OUT_DMA_EN) | |
784 | return; | |
785 | atiixp_out_flush_dma(chip); | |
786 | data |= ATI_REG_CMD_OUT_DMA_EN; | |
787 | } else | |
788 | data &= ~ATI_REG_CMD_OUT_DMA_EN; | |
789 | atiixp_write(chip, CMD, data); | |
790 | } | |
791 | ||
792 | /* start/stop transfer over OUT DMA */ | |
74ee4ff1 | 793 | static void atiixp_out_enable_transfer(struct atiixp *chip, int on) |
1da177e4 LT |
794 | { |
795 | atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN, | |
796 | on ? ATI_REG_CMD_SEND_EN : 0); | |
797 | } | |
798 | ||
799 | /* enable/disable analog IN DMA */ | |
74ee4ff1 | 800 | static void atiixp_in_enable_dma(struct atiixp *chip, int on) |
1da177e4 LT |
801 | { |
802 | atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN, | |
803 | on ? ATI_REG_CMD_IN_DMA_EN : 0); | |
804 | } | |
805 | ||
806 | /* start/stop analog IN DMA */ | |
74ee4ff1 | 807 | static void atiixp_in_enable_transfer(struct atiixp *chip, int on) |
1da177e4 LT |
808 | { |
809 | if (on) { | |
810 | unsigned int data = atiixp_read(chip, CMD); | |
811 | if (! (data & ATI_REG_CMD_RECEIVE_EN)) { | |
812 | data |= ATI_REG_CMD_RECEIVE_EN; | |
813 | #if 0 /* FIXME: this causes the endless loop */ | |
814 | /* wait until slot 3/4 are finished */ | |
815 | while ((atiixp_read(chip, COUNTER) & | |
816 | ATI_REG_COUNTER_SLOT) != 5) | |
817 | ; | |
818 | #endif | |
819 | atiixp_write(chip, CMD, data); | |
820 | } | |
821 | } else | |
822 | atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0); | |
823 | } | |
824 | ||
825 | /* flush FIFO of analog IN DMA */ | |
74ee4ff1 | 826 | static void atiixp_in_flush_dma(struct atiixp *chip) |
1da177e4 LT |
827 | { |
828 | atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH); | |
829 | } | |
830 | ||
831 | /* enable/disable SPDIF OUT DMA */ | |
74ee4ff1 | 832 | static void atiixp_spdif_enable_dma(struct atiixp *chip, int on) |
1da177e4 LT |
833 | { |
834 | atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN, | |
835 | on ? ATI_REG_CMD_SPDF_DMA_EN : 0); | |
836 | } | |
837 | ||
838 | /* start/stop SPDIF OUT DMA */ | |
74ee4ff1 | 839 | static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on) |
1da177e4 LT |
840 | { |
841 | unsigned int data; | |
842 | data = atiixp_read(chip, CMD); | |
843 | if (on) | |
844 | data |= ATI_REG_CMD_SPDF_OUT_EN; | |
845 | else | |
846 | data &= ~ATI_REG_CMD_SPDF_OUT_EN; | |
847 | atiixp_write(chip, CMD, data); | |
848 | } | |
849 | ||
850 | /* flush FIFO of SPDIF OUT DMA */ | |
74ee4ff1 | 851 | static void atiixp_spdif_flush_dma(struct atiixp *chip) |
1da177e4 LT |
852 | { |
853 | int timeout; | |
854 | ||
855 | /* DMA off, transfer on */ | |
856 | atiixp_spdif_enable_dma(chip, 0); | |
857 | atiixp_spdif_enable_transfer(chip, 1); | |
858 | ||
859 | timeout = 100; | |
860 | do { | |
861 | if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED)) | |
862 | break; | |
863 | udelay(1); | |
864 | } while (timeout-- > 0); | |
865 | ||
866 | atiixp_spdif_enable_transfer(chip, 0); | |
867 | } | |
868 | ||
869 | /* set up slots and formats for SPDIF OUT */ | |
74ee4ff1 | 870 | static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 871 | { |
74ee4ff1 | 872 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
873 | |
874 | spin_lock_irq(&chip->reg_lock); | |
875 | if (chip->spdif_over_aclink) { | |
876 | unsigned int data; | |
877 | /* enable slots 10/11 */ | |
878 | atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, | |
879 | ATI_REG_CMD_SPDF_CONFIG_01); | |
880 | data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; | |
881 | data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | | |
882 | ATI_REG_OUT_DMA_SLOT_BIT(11); | |
883 | data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; | |
884 | atiixp_write(chip, OUT_DMA_SLOT, data); | |
885 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, | |
886 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? | |
887 | ATI_REG_CMD_INTERLEAVE_OUT : 0); | |
888 | } else { | |
889 | atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0); | |
890 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0); | |
891 | } | |
892 | spin_unlock_irq(&chip->reg_lock); | |
893 | return 0; | |
894 | } | |
895 | ||
896 | /* set up slots and formats for analog OUT */ | |
74ee4ff1 | 897 | static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 898 | { |
74ee4ff1 | 899 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
900 | unsigned int data; |
901 | ||
902 | spin_lock_irq(&chip->reg_lock); | |
903 | data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; | |
904 | switch (substream->runtime->channels) { | |
905 | case 8: | |
906 | data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | | |
907 | ATI_REG_OUT_DMA_SLOT_BIT(11); | |
908 | /* fallthru */ | |
909 | case 6: | |
910 | data |= ATI_REG_OUT_DMA_SLOT_BIT(7) | | |
911 | ATI_REG_OUT_DMA_SLOT_BIT(8); | |
912 | /* fallthru */ | |
913 | case 4: | |
914 | data |= ATI_REG_OUT_DMA_SLOT_BIT(6) | | |
915 | ATI_REG_OUT_DMA_SLOT_BIT(9); | |
916 | /* fallthru */ | |
917 | default: | |
918 | data |= ATI_REG_OUT_DMA_SLOT_BIT(3) | | |
919 | ATI_REG_OUT_DMA_SLOT_BIT(4); | |
920 | break; | |
921 | } | |
922 | ||
923 | /* set output threshold */ | |
924 | data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; | |
925 | atiixp_write(chip, OUT_DMA_SLOT, data); | |
926 | ||
927 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, | |
928 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? | |
929 | ATI_REG_CMD_INTERLEAVE_OUT : 0); | |
930 | ||
931 | /* | |
932 | * enable 6 channel re-ordering bit if needed | |
933 | */ | |
934 | atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN, | |
935 | substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0); | |
936 | ||
937 | spin_unlock_irq(&chip->reg_lock); | |
938 | return 0; | |
939 | } | |
940 | ||
941 | /* set up slots and formats for analog IN */ | |
74ee4ff1 | 942 | static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 943 | { |
74ee4ff1 | 944 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
945 | |
946 | spin_lock_irq(&chip->reg_lock); | |
947 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN, | |
948 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? | |
949 | ATI_REG_CMD_INTERLEAVE_IN : 0); | |
950 | spin_unlock_irq(&chip->reg_lock); | |
951 | return 0; | |
952 | } | |
953 | ||
954 | /* | |
955 | * hw_params - allocate the buffer and set up buffer descriptors | |
956 | */ | |
74ee4ff1 TI |
957 | static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream, |
958 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 959 | { |
74ee4ff1 TI |
960 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
961 | struct atiixp_dma *dma = substream->runtime->private_data; | |
1da177e4 LT |
962 | int err; |
963 | ||
964 | err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
965 | if (err < 0) | |
966 | return err; | |
967 | dma->buf_addr = substream->runtime->dma_addr; | |
968 | dma->buf_bytes = params_buffer_bytes(hw_params); | |
969 | ||
970 | err = atiixp_build_dma_packets(chip, dma, substream, | |
971 | params_periods(hw_params), | |
972 | params_period_bytes(hw_params)); | |
973 | if (err < 0) | |
974 | return err; | |
975 | ||
976 | if (dma->ac97_pcm_type >= 0) { | |
977 | struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; | |
978 | /* PCM is bound to AC97 codec(s) | |
979 | * set up the AC97 codecs | |
980 | */ | |
981 | if (dma->pcm_open_flag) { | |
982 | snd_ac97_pcm_close(pcm); | |
983 | dma->pcm_open_flag = 0; | |
984 | } | |
985 | err = snd_ac97_pcm_open(pcm, params_rate(hw_params), | |
986 | params_channels(hw_params), | |
987 | pcm->r[0].slots); | |
988 | if (err >= 0) | |
989 | dma->pcm_open_flag = 1; | |
990 | } | |
991 | ||
992 | return err; | |
993 | } | |
994 | ||
74ee4ff1 | 995 | static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 996 | { |
74ee4ff1 TI |
997 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
998 | struct atiixp_dma *dma = substream->runtime->private_data; | |
1da177e4 LT |
999 | |
1000 | if (dma->pcm_open_flag) { | |
1001 | struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; | |
1002 | snd_ac97_pcm_close(pcm); | |
1003 | dma->pcm_open_flag = 0; | |
1004 | } | |
1005 | atiixp_clear_dma_packets(chip, dma, substream); | |
1006 | snd_pcm_lib_free_pages(substream); | |
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | ||
1011 | /* | |
1012 | * pcm hardware definition, identical for all DMA types | |
1013 | */ | |
74ee4ff1 | 1014 | static struct snd_pcm_hardware snd_atiixp_pcm_hw = |
1da177e4 LT |
1015 | { |
1016 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1017 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
41e4845c | 1018 | SNDRV_PCM_INFO_PAUSE | |
1da177e4 LT |
1019 | SNDRV_PCM_INFO_RESUME | |
1020 | SNDRV_PCM_INFO_MMAP_VALID), | |
1021 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
1022 | .rates = SNDRV_PCM_RATE_48000, | |
1023 | .rate_min = 48000, | |
1024 | .rate_max = 48000, | |
1025 | .channels_min = 2, | |
1026 | .channels_max = 2, | |
1027 | .buffer_bytes_max = 256 * 1024, | |
1028 | .period_bytes_min = 32, | |
1029 | .period_bytes_max = 128 * 1024, | |
1030 | .periods_min = 2, | |
1031 | .periods_max = ATI_MAX_DESCRIPTORS, | |
1032 | }; | |
1033 | ||
74ee4ff1 TI |
1034 | static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream, |
1035 | struct atiixp_dma *dma, int pcm_type) | |
1da177e4 | 1036 | { |
74ee4ff1 TI |
1037 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1038 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1039 | int err; |
1040 | ||
da3cec35 TI |
1041 | if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) |
1042 | return -EINVAL; | |
1da177e4 LT |
1043 | |
1044 | if (dma->opened) | |
1045 | return -EBUSY; | |
1046 | dma->substream = substream; | |
1047 | runtime->hw = snd_atiixp_pcm_hw; | |
1048 | dma->ac97_pcm_type = pcm_type; | |
1049 | if (pcm_type >= 0) { | |
1050 | runtime->hw.rates = chip->pcms[pcm_type]->rates; | |
1051 | snd_pcm_limit_hw_rates(runtime); | |
1052 | } else { | |
1053 | /* direct SPDIF */ | |
1054 | runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; | |
1055 | } | |
1056 | if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) | |
1057 | return err; | |
1058 | runtime->private_data = dma; | |
1059 | ||
1060 | /* enable DMA bits */ | |
1061 | spin_lock_irq(&chip->reg_lock); | |
1062 | dma->ops->enable_dma(chip, 1); | |
1063 | spin_unlock_irq(&chip->reg_lock); | |
1064 | dma->opened = 1; | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
74ee4ff1 TI |
1069 | static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream, |
1070 | struct atiixp_dma *dma) | |
1da177e4 | 1071 | { |
74ee4ff1 | 1072 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 1073 | /* disable DMA bits */ |
da3cec35 TI |
1074 | if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) |
1075 | return -EINVAL; | |
1da177e4 LT |
1076 | spin_lock_irq(&chip->reg_lock); |
1077 | dma->ops->enable_dma(chip, 0); | |
1078 | spin_unlock_irq(&chip->reg_lock); | |
1079 | dma->substream = NULL; | |
1080 | dma->opened = 0; | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | /* | |
1085 | */ | |
74ee4ff1 | 1086 | static int snd_atiixp_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 1087 | { |
74ee4ff1 | 1088 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1089 | int err; |
1090 | ||
62932df8 | 1091 | mutex_lock(&chip->open_mutex); |
1da177e4 | 1092 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); |
62932df8 | 1093 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1094 | if (err < 0) |
1095 | return err; | |
1096 | substream->runtime->hw.channels_max = chip->max_channels; | |
1097 | if (chip->max_channels > 2) | |
1098 | /* channels must be even */ | |
1099 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1100 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1101 | return 0; | |
1102 | } | |
1103 | ||
74ee4ff1 | 1104 | static int snd_atiixp_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1105 | { |
74ee4ff1 | 1106 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 1107 | int err; |
62932df8 | 1108 | mutex_lock(&chip->open_mutex); |
1da177e4 | 1109 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); |
62932df8 | 1110 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1111 | return err; |
1112 | } | |
1113 | ||
74ee4ff1 | 1114 | static int snd_atiixp_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1115 | { |
74ee4ff1 | 1116 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1117 | return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); |
1118 | } | |
1119 | ||
74ee4ff1 | 1120 | static int snd_atiixp_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1121 | { |
74ee4ff1 | 1122 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1123 | return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); |
1124 | } | |
1125 | ||
74ee4ff1 | 1126 | static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1127 | { |
74ee4ff1 | 1128 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 1129 | int err; |
62932df8 | 1130 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1131 | if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */ |
1132 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2); | |
1133 | else | |
1134 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1); | |
62932df8 | 1135 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1136 | return err; |
1137 | } | |
1138 | ||
74ee4ff1 | 1139 | static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1140 | { |
74ee4ff1 | 1141 | struct atiixp *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 1142 | int err; |
62932df8 | 1143 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1144 | if (chip->spdif_over_aclink) |
1145 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1146 | else | |
1147 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]); | |
62932df8 | 1148 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1149 | return err; |
1150 | } | |
1151 | ||
1152 | /* AC97 playback */ | |
74ee4ff1 | 1153 | static struct snd_pcm_ops snd_atiixp_playback_ops = { |
1da177e4 LT |
1154 | .open = snd_atiixp_playback_open, |
1155 | .close = snd_atiixp_playback_close, | |
1156 | .ioctl = snd_pcm_lib_ioctl, | |
1157 | .hw_params = snd_atiixp_pcm_hw_params, | |
1158 | .hw_free = snd_atiixp_pcm_hw_free, | |
1159 | .prepare = snd_atiixp_playback_prepare, | |
1160 | .trigger = snd_atiixp_pcm_trigger, | |
1161 | .pointer = snd_atiixp_pcm_pointer, | |
1162 | }; | |
1163 | ||
1164 | /* AC97 capture */ | |
74ee4ff1 | 1165 | static struct snd_pcm_ops snd_atiixp_capture_ops = { |
1da177e4 LT |
1166 | .open = snd_atiixp_capture_open, |
1167 | .close = snd_atiixp_capture_close, | |
1168 | .ioctl = snd_pcm_lib_ioctl, | |
1169 | .hw_params = snd_atiixp_pcm_hw_params, | |
1170 | .hw_free = snd_atiixp_pcm_hw_free, | |
1171 | .prepare = snd_atiixp_capture_prepare, | |
1172 | .trigger = snd_atiixp_pcm_trigger, | |
1173 | .pointer = snd_atiixp_pcm_pointer, | |
1174 | }; | |
1175 | ||
1176 | /* SPDIF playback */ | |
74ee4ff1 | 1177 | static struct snd_pcm_ops snd_atiixp_spdif_ops = { |
1da177e4 LT |
1178 | .open = snd_atiixp_spdif_open, |
1179 | .close = snd_atiixp_spdif_close, | |
1180 | .ioctl = snd_pcm_lib_ioctl, | |
1181 | .hw_params = snd_atiixp_pcm_hw_params, | |
1182 | .hw_free = snd_atiixp_pcm_hw_free, | |
1183 | .prepare = snd_atiixp_spdif_prepare, | |
1184 | .trigger = snd_atiixp_pcm_trigger, | |
1185 | .pointer = snd_atiixp_pcm_pointer, | |
1186 | }; | |
1187 | ||
e23e7a14 | 1188 | static struct ac97_pcm atiixp_pcm_defs[] = { |
1da177e4 LT |
1189 | /* front PCM */ |
1190 | { | |
1191 | .exclusive = 1, | |
1192 | .r = { { | |
1193 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1194 | (1 << AC97_SLOT_PCM_RIGHT) | | |
1195 | (1 << AC97_SLOT_PCM_CENTER) | | |
1196 | (1 << AC97_SLOT_PCM_SLEFT) | | |
1197 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
1198 | (1 << AC97_SLOT_LFE) | |
1199 | } | |
1200 | } | |
1201 | }, | |
1202 | /* PCM IN #1 */ | |
1203 | { | |
1204 | .stream = 1, | |
1205 | .exclusive = 1, | |
1206 | .r = { { | |
1207 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1208 | (1 << AC97_SLOT_PCM_RIGHT) | |
1209 | } | |
1210 | } | |
1211 | }, | |
1212 | /* S/PDIF OUT (optional) */ | |
1213 | { | |
1214 | .exclusive = 1, | |
1215 | .spdif = 1, | |
1216 | .r = { { | |
1217 | .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | | |
1218 | (1 << AC97_SLOT_SPDIF_RIGHT2) | |
1219 | } | |
1220 | } | |
1221 | }, | |
1222 | }; | |
1223 | ||
74ee4ff1 | 1224 | static struct atiixp_dma_ops snd_atiixp_playback_dma_ops = { |
1da177e4 LT |
1225 | .type = ATI_DMA_PLAYBACK, |
1226 | .llp_offset = ATI_REG_OUT_DMA_LINKPTR, | |
1227 | .dt_cur = ATI_REG_OUT_DMA_DT_CUR, | |
1228 | .enable_dma = atiixp_out_enable_dma, | |
1229 | .enable_transfer = atiixp_out_enable_transfer, | |
1230 | .flush_dma = atiixp_out_flush_dma, | |
1231 | }; | |
1232 | ||
74ee4ff1 | 1233 | static struct atiixp_dma_ops snd_atiixp_capture_dma_ops = { |
1da177e4 LT |
1234 | .type = ATI_DMA_CAPTURE, |
1235 | .llp_offset = ATI_REG_IN_DMA_LINKPTR, | |
1236 | .dt_cur = ATI_REG_IN_DMA_DT_CUR, | |
1237 | .enable_dma = atiixp_in_enable_dma, | |
1238 | .enable_transfer = atiixp_in_enable_transfer, | |
1239 | .flush_dma = atiixp_in_flush_dma, | |
1240 | }; | |
1241 | ||
74ee4ff1 | 1242 | static struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = { |
1da177e4 LT |
1243 | .type = ATI_DMA_SPDIF, |
1244 | .llp_offset = ATI_REG_SPDF_DMA_LINKPTR, | |
1245 | .dt_cur = ATI_REG_SPDF_DMA_DT_CUR, | |
1246 | .enable_dma = atiixp_spdif_enable_dma, | |
1247 | .enable_transfer = atiixp_spdif_enable_transfer, | |
1248 | .flush_dma = atiixp_spdif_flush_dma, | |
1249 | }; | |
1250 | ||
1251 | ||
e23e7a14 | 1252 | static int snd_atiixp_pcm_new(struct atiixp *chip) |
1da177e4 | 1253 | { |
74ee4ff1 | 1254 | struct snd_pcm *pcm; |
e36e3b86 | 1255 | struct snd_pcm_chmap *chmap; |
74ee4ff1 | 1256 | struct snd_ac97_bus *pbus = chip->ac97_bus; |
1da177e4 LT |
1257 | int err, i, num_pcms; |
1258 | ||
1259 | /* initialize constants */ | |
1260 | chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; | |
1261 | chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; | |
1262 | if (! chip->spdif_over_aclink) | |
1263 | chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops; | |
1264 | ||
1265 | /* assign AC97 pcm */ | |
1266 | if (chip->spdif_over_aclink) | |
1267 | num_pcms = 3; | |
1268 | else | |
1269 | num_pcms = 2; | |
1270 | err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs); | |
1271 | if (err < 0) | |
1272 | return err; | |
1273 | for (i = 0; i < num_pcms; i++) | |
1274 | chip->pcms[i] = &pbus->pcms[i]; | |
1275 | ||
1276 | chip->max_channels = 2; | |
1277 | if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
1278 | if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE)) | |
1279 | chip->max_channels = 6; | |
1280 | else | |
1281 | chip->max_channels = 4; | |
1282 | } | |
1283 | ||
1284 | /* PCM #0: analog I/O */ | |
74ee4ff1 TI |
1285 | err = snd_pcm_new(chip->card, "ATI IXP AC97", |
1286 | ATI_PCMDEV_ANALOG, 1, 1, &pcm); | |
1da177e4 LT |
1287 | if (err < 0) |
1288 | return err; | |
1289 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); | |
1290 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); | |
1291 | pcm->private_data = chip; | |
1292 | strcpy(pcm->name, "ATI IXP AC97"); | |
1293 | chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; | |
1294 | ||
1295 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
74ee4ff1 TI |
1296 | snd_dma_pci_data(chip->pci), |
1297 | 64*1024, 128*1024); | |
1da177e4 | 1298 | |
e36e3b86 TI |
1299 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, |
1300 | snd_pcm_alt_chmaps, chip->max_channels, 0, | |
1301 | &chmap); | |
1302 | if (err < 0) | |
1303 | return err; | |
1304 | chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; | |
1305 | chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; | |
1306 | ||
1da177e4 LT |
1307 | /* no SPDIF support on codec? */ |
1308 | if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates) | |
1309 | return 0; | |
1310 | ||
1311 | /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */ | |
1312 | if (chip->pcms[ATI_PCM_SPDIF]) | |
1313 | chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000; | |
1314 | ||
1315 | /* PCM #1: spdif playback */ | |
74ee4ff1 TI |
1316 | err = snd_pcm_new(chip->card, "ATI IXP IEC958", |
1317 | ATI_PCMDEV_DIGITAL, 1, 0, &pcm); | |
1da177e4 LT |
1318 | if (err < 0) |
1319 | return err; | |
1320 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops); | |
1321 | pcm->private_data = chip; | |
1322 | if (chip->spdif_over_aclink) | |
1323 | strcpy(pcm->name, "ATI IXP IEC958 (AC97)"); | |
1324 | else | |
1325 | strcpy(pcm->name, "ATI IXP IEC958 (Direct)"); | |
1326 | chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm; | |
1327 | ||
1328 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
74ee4ff1 TI |
1329 | snd_dma_pci_data(chip->pci), |
1330 | 64*1024, 128*1024); | |
1da177e4 LT |
1331 | |
1332 | /* pre-select AC97 SPDIF slots 10/11 */ | |
1333 | for (i = 0; i < NUM_ATI_CODECS; i++) { | |
1334 | if (chip->ac97[i]) | |
74ee4ff1 TI |
1335 | snd_ac97_update_bits(chip->ac97[i], |
1336 | AC97_EXTENDED_STATUS, | |
1337 | 0x03 << 4, 0x03 << 4); | |
1da177e4 LT |
1338 | } |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | ||
1344 | ||
1345 | /* | |
1346 | * interrupt handler | |
1347 | */ | |
7d12e780 | 1348 | static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id) |
1da177e4 | 1349 | { |
74ee4ff1 | 1350 | struct atiixp *chip = dev_id; |
1da177e4 LT |
1351 | unsigned int status; |
1352 | ||
1353 | status = atiixp_read(chip, ISR); | |
1354 | ||
1355 | if (! status) | |
1356 | return IRQ_NONE; | |
1357 | ||
1358 | /* process audio DMA */ | |
1359 | if (status & ATI_REG_ISR_OUT_XRUN) | |
1360 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1361 | else if (status & ATI_REG_ISR_OUT_STATUS) | |
1362 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1363 | if (status & ATI_REG_ISR_IN_XRUN) | |
1364 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); | |
1365 | else if (status & ATI_REG_ISR_IN_STATUS) | |
1366 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); | |
1367 | if (! chip->spdif_over_aclink) { | |
1368 | if (status & ATI_REG_ISR_SPDF_XRUN) | |
1369 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); | |
1370 | else if (status & ATI_REG_ISR_SPDF_STATUS) | |
1371 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); | |
1372 | } | |
1373 | ||
1374 | /* for codec detection */ | |
1375 | if (status & CODEC_CHECK_BITS) { | |
1376 | unsigned int detected; | |
1377 | detected = status & CODEC_CHECK_BITS; | |
1378 | spin_lock(&chip->reg_lock); | |
1379 | chip->codec_not_ready_bits |= detected; | |
1380 | atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ | |
1381 | spin_unlock(&chip->reg_lock); | |
1382 | } | |
1383 | ||
1384 | /* ack */ | |
1385 | atiixp_write(chip, ISR, status); | |
1386 | ||
1387 | return IRQ_HANDLED; | |
1388 | } | |
1389 | ||
1390 | ||
1391 | /* | |
1392 | * ac97 mixer section | |
1393 | */ | |
1394 | ||
e23e7a14 | 1395 | static struct ac97_quirk ac97_quirks[] = { |
1da177e4 | 1396 | { |
69ad07cf JK |
1397 | .subvendor = 0x103c, |
1398 | .subdevice = 0x006b, | |
1da177e4 LT |
1399 | .name = "HP Pavilion ZV5030US", |
1400 | .type = AC97_TUNE_MUTE_LED | |
1401 | }, | |
a0faefed MG |
1402 | { |
1403 | .subvendor = 0x103c, | |
1404 | .subdevice = 0x308b, | |
1405 | .name = "HP nx6125", | |
1406 | .type = AC97_TUNE_MUTE_LED | |
1407 | }, | |
e3ba906a DC |
1408 | { |
1409 | .subvendor = 0x103c, | |
1410 | .subdevice = 0x3091, | |
1411 | .name = "unknown HP", | |
1412 | .type = AC97_TUNE_MUTE_LED | |
1413 | }, | |
1da177e4 LT |
1414 | { } /* terminator */ |
1415 | }; | |
1416 | ||
e23e7a14 BP |
1417 | static int snd_atiixp_mixer_new(struct atiixp *chip, int clock, |
1418 | const char *quirk_override) | |
1da177e4 | 1419 | { |
74ee4ff1 TI |
1420 | struct snd_ac97_bus *pbus; |
1421 | struct snd_ac97_template ac97; | |
1da177e4 LT |
1422 | int i, err; |
1423 | int codec_count; | |
74ee4ff1 | 1424 | static struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
1425 | .write = snd_atiixp_ac97_write, |
1426 | .read = snd_atiixp_ac97_read, | |
1427 | }; | |
1428 | static unsigned int codec_skip[NUM_ATI_CODECS] = { | |
1429 | ATI_REG_ISR_CODEC0_NOT_READY, | |
1430 | ATI_REG_ISR_CODEC1_NOT_READY, | |
1431 | ATI_REG_ISR_CODEC2_NOT_READY, | |
1432 | }; | |
1433 | ||
1434 | if (snd_atiixp_codec_detect(chip) < 0) | |
1435 | return -ENXIO; | |
1436 | ||
1437 | if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) | |
1438 | return err; | |
1439 | pbus->clock = clock; | |
1da177e4 LT |
1440 | chip->ac97_bus = pbus; |
1441 | ||
1442 | codec_count = 0; | |
1443 | for (i = 0; i < NUM_ATI_CODECS; i++) { | |
1444 | if (chip->codec_not_ready_bits & codec_skip[i]) | |
1445 | continue; | |
1446 | memset(&ac97, 0, sizeof(ac97)); | |
1447 | ac97.private_data = chip; | |
1448 | ac97.pci = chip->pci; | |
1449 | ac97.num = i; | |
f1a63a38 | 1450 | ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; |
1da177e4 LT |
1451 | if (! chip->spdif_over_aclink) |
1452 | ac97.scaps |= AC97_SCAP_NO_SPDIF; | |
1453 | if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { | |
1454 | chip->ac97[i] = NULL; /* to be sure */ | |
25135fdc TI |
1455 | dev_dbg(chip->card->dev, |
1456 | "codec %d not available for audio\n", i); | |
1da177e4 LT |
1457 | continue; |
1458 | } | |
1459 | codec_count++; | |
1460 | } | |
1461 | ||
1462 | if (! codec_count) { | |
25135fdc | 1463 | dev_err(chip->card->dev, "no codec available\n"); |
1da177e4 LT |
1464 | return -ENODEV; |
1465 | } | |
1466 | ||
1467 | snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); | |
1468 | ||
1469 | return 0; | |
1470 | } | |
1471 | ||
1472 | ||
c7561cd8 | 1473 | #ifdef CONFIG_PM_SLEEP |
1da177e4 LT |
1474 | /* |
1475 | * power management | |
1476 | */ | |
68cb2b55 | 1477 | static int snd_atiixp_suspend(struct device *dev) |
1da177e4 | 1478 | { |
68cb2b55 TI |
1479 | struct pci_dev *pci = to_pci_dev(dev); |
1480 | struct snd_card *card = dev_get_drvdata(dev); | |
92304cc7 | 1481 | struct atiixp *chip = card->private_data; |
1da177e4 LT |
1482 | int i; |
1483 | ||
92304cc7 | 1484 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 LT |
1485 | for (i = 0; i < NUM_ATI_PCMDEVS; i++) |
1486 | if (chip->pcmdevs[i]) { | |
74ee4ff1 | 1487 | struct atiixp_dma *dma = &chip->dmas[i]; |
1da177e4 | 1488 | if (dma->substream && dma->running) |
74ee4ff1 TI |
1489 | dma->saved_curptr = readl(chip->remap_addr + |
1490 | dma->ops->dt_cur); | |
1da177e4 LT |
1491 | snd_pcm_suspend_all(chip->pcmdevs[i]); |
1492 | } | |
1493 | for (i = 0; i < NUM_ATI_CODECS; i++) | |
92304cc7 | 1494 | snd_ac97_suspend(chip->ac97[i]); |
1da177e4 LT |
1495 | snd_atiixp_aclink_down(chip); |
1496 | snd_atiixp_chip_stop(chip); | |
1497 | ||
92304cc7 TI |
1498 | pci_disable_device(pci); |
1499 | pci_save_state(pci); | |
68cb2b55 | 1500 | pci_set_power_state(pci, PCI_D3hot); |
1da177e4 LT |
1501 | return 0; |
1502 | } | |
1503 | ||
68cb2b55 | 1504 | static int snd_atiixp_resume(struct device *dev) |
1da177e4 | 1505 | { |
68cb2b55 TI |
1506 | struct pci_dev *pci = to_pci_dev(dev); |
1507 | struct snd_card *card = dev_get_drvdata(dev); | |
92304cc7 | 1508 | struct atiixp *chip = card->private_data; |
1da177e4 LT |
1509 | int i; |
1510 | ||
92304cc7 | 1511 | pci_set_power_state(pci, PCI_D0); |
30b35399 TI |
1512 | pci_restore_state(pci); |
1513 | if (pci_enable_device(pci) < 0) { | |
25135fdc | 1514 | dev_err(dev, "pci_enable_device failed, disabling device\n"); |
30b35399 TI |
1515 | snd_card_disconnect(card); |
1516 | return -EIO; | |
1517 | } | |
92304cc7 | 1518 | pci_set_master(pci); |
1da177e4 LT |
1519 | |
1520 | snd_atiixp_aclink_reset(chip); | |
1521 | snd_atiixp_chip_start(chip); | |
1522 | ||
1523 | for (i = 0; i < NUM_ATI_CODECS; i++) | |
92304cc7 | 1524 | snd_ac97_resume(chip->ac97[i]); |
1da177e4 LT |
1525 | |
1526 | for (i = 0; i < NUM_ATI_PCMDEVS; i++) | |
1527 | if (chip->pcmdevs[i]) { | |
74ee4ff1 | 1528 | struct atiixp_dma *dma = &chip->dmas[i]; |
41e4845c | 1529 | if (dma->substream && dma->suspended) { |
1da177e4 | 1530 | dma->ops->enable_dma(chip, 1); |
8e3d759d | 1531 | dma->substream->ops->prepare(dma->substream); |
1da177e4 LT |
1532 | writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, |
1533 | chip->remap_addr + dma->ops->llp_offset); | |
74ee4ff1 TI |
1534 | writel(dma->saved_curptr, chip->remap_addr + |
1535 | dma->ops->dt_cur); | |
1da177e4 LT |
1536 | } |
1537 | } | |
1538 | ||
92304cc7 | 1539 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
1540 | return 0; |
1541 | } | |
68cb2b55 TI |
1542 | |
1543 | static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume); | |
1544 | #define SND_ATIIXP_PM_OPS &snd_atiixp_pm | |
1545 | #else | |
1546 | #define SND_ATIIXP_PM_OPS NULL | |
c7561cd8 | 1547 | #endif /* CONFIG_PM_SLEEP */ |
1da177e4 LT |
1548 | |
1549 | ||
adf1b3d2 | 1550 | #ifdef CONFIG_PROC_FS |
1da177e4 LT |
1551 | /* |
1552 | * proc interface for register dump | |
1553 | */ | |
1554 | ||
74ee4ff1 TI |
1555 | static void snd_atiixp_proc_read(struct snd_info_entry *entry, |
1556 | struct snd_info_buffer *buffer) | |
1da177e4 | 1557 | { |
74ee4ff1 | 1558 | struct atiixp *chip = entry->private_data; |
1da177e4 LT |
1559 | int i; |
1560 | ||
1561 | for (i = 0; i < 256; i += 4) | |
1562 | snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); | |
1563 | } | |
1564 | ||
e23e7a14 | 1565 | static void snd_atiixp_proc_init(struct atiixp *chip) |
1da177e4 | 1566 | { |
74ee4ff1 | 1567 | struct snd_info_entry *entry; |
1da177e4 LT |
1568 | |
1569 | if (! snd_card_proc_new(chip->card, "atiixp", &entry)) | |
bf850204 | 1570 | snd_info_set_text_ops(entry, chip, snd_atiixp_proc_read); |
1da177e4 | 1571 | } |
adf1b3d2 TI |
1572 | #else /* !CONFIG_PROC_FS */ |
1573 | #define snd_atiixp_proc_init(chip) | |
1574 | #endif | |
1da177e4 LT |
1575 | |
1576 | ||
1577 | /* | |
1578 | * destructor | |
1579 | */ | |
1580 | ||
74ee4ff1 | 1581 | static int snd_atiixp_free(struct atiixp *chip) |
1da177e4 LT |
1582 | { |
1583 | if (chip->irq < 0) | |
1584 | goto __hw_end; | |
1585 | snd_atiixp_chip_stop(chip); | |
f000fd80 | 1586 | |
1da177e4 LT |
1587 | __hw_end: |
1588 | if (chip->irq >= 0) | |
74ee4ff1 | 1589 | free_irq(chip->irq, chip); |
1da177e4 LT |
1590 | if (chip->remap_addr) |
1591 | iounmap(chip->remap_addr); | |
1592 | pci_release_regions(chip->pci); | |
1593 | pci_disable_device(chip->pci); | |
1594 | kfree(chip); | |
1595 | return 0; | |
1596 | } | |
1597 | ||
74ee4ff1 | 1598 | static int snd_atiixp_dev_free(struct snd_device *device) |
1da177e4 | 1599 | { |
74ee4ff1 | 1600 | struct atiixp *chip = device->device_data; |
1da177e4 LT |
1601 | return snd_atiixp_free(chip); |
1602 | } | |
1603 | ||
1604 | /* | |
1605 | * constructor for chip instance | |
1606 | */ | |
e23e7a14 BP |
1607 | static int snd_atiixp_create(struct snd_card *card, |
1608 | struct pci_dev *pci, | |
1609 | struct atiixp **r_chip) | |
1da177e4 | 1610 | { |
74ee4ff1 | 1611 | static struct snd_device_ops ops = { |
1da177e4 LT |
1612 | .dev_free = snd_atiixp_dev_free, |
1613 | }; | |
74ee4ff1 | 1614 | struct atiixp *chip; |
1da177e4 LT |
1615 | int err; |
1616 | ||
1617 | if ((err = pci_enable_device(pci)) < 0) | |
1618 | return err; | |
1619 | ||
e560d8d8 | 1620 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
1621 | if (chip == NULL) { |
1622 | pci_disable_device(pci); | |
1623 | return -ENOMEM; | |
1624 | } | |
1625 | ||
1626 | spin_lock_init(&chip->reg_lock); | |
62932df8 | 1627 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
1628 | chip->card = card; |
1629 | chip->pci = pci; | |
1630 | chip->irq = -1; | |
1631 | if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) { | |
1632 | pci_disable_device(pci); | |
1633 | kfree(chip); | |
1634 | return err; | |
1635 | } | |
1636 | chip->addr = pci_resource_start(pci, 0); | |
2f5ad54e | 1637 | chip->remap_addr = pci_ioremap_bar(pci, 0); |
1da177e4 | 1638 | if (chip->remap_addr == NULL) { |
25135fdc | 1639 | dev_err(card->dev, "AC'97 space ioremap problem\n"); |
1da177e4 LT |
1640 | snd_atiixp_free(chip); |
1641 | return -EIO; | |
1642 | } | |
1643 | ||
437a5a46 | 1644 | if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED, |
934c2b6d | 1645 | KBUILD_MODNAME, chip)) { |
25135fdc | 1646 | dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
1647 | snd_atiixp_free(chip); |
1648 | return -EBUSY; | |
1649 | } | |
1650 | chip->irq = pci->irq; | |
1651 | pci_set_master(pci); | |
1652 | synchronize_irq(chip->irq); | |
1653 | ||
1654 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { | |
1655 | snd_atiixp_free(chip); | |
1656 | return err; | |
1657 | } | |
1658 | ||
1da177e4 LT |
1659 | *r_chip = chip; |
1660 | return 0; | |
1661 | } | |
1662 | ||
1663 | ||
e23e7a14 BP |
1664 | static int snd_atiixp_probe(struct pci_dev *pci, |
1665 | const struct pci_device_id *pci_id) | |
1da177e4 | 1666 | { |
74ee4ff1 TI |
1667 | struct snd_card *card; |
1668 | struct atiixp *chip; | |
1da177e4 LT |
1669 | int err; |
1670 | ||
60c5772b | 1671 | err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); |
e58de7ba TI |
1672 | if (err < 0) |
1673 | return err; | |
1da177e4 | 1674 | |
b7fe4622 | 1675 | strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA"); |
1da177e4 LT |
1676 | strcpy(card->shortname, "ATI IXP"); |
1677 | if ((err = snd_atiixp_create(card, pci, &chip)) < 0) | |
1678 | goto __error; | |
92304cc7 | 1679 | card->private_data = chip; |
1da177e4 LT |
1680 | |
1681 | if ((err = snd_atiixp_aclink_reset(chip)) < 0) | |
1682 | goto __error; | |
1683 | ||
b7fe4622 | 1684 | chip->spdif_over_aclink = spdif_aclink; |
1da177e4 | 1685 | |
b7fe4622 | 1686 | if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0) |
1da177e4 LT |
1687 | goto __error; |
1688 | ||
1689 | if ((err = snd_atiixp_pcm_new(chip)) < 0) | |
1690 | goto __error; | |
1691 | ||
1692 | snd_atiixp_proc_init(chip); | |
1693 | ||
1694 | snd_atiixp_chip_start(chip); | |
1695 | ||
1696 | snprintf(card->longname, sizeof(card->longname), | |
44c10138 AK |
1697 | "%s rev %x with %s at %#lx, irq %i", card->shortname, |
1698 | pci->revision, | |
1da177e4 LT |
1699 | chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?", |
1700 | chip->addr, chip->irq); | |
1701 | ||
1da177e4 LT |
1702 | if ((err = snd_card_register(card)) < 0) |
1703 | goto __error; | |
1704 | ||
1705 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
1706 | return 0; |
1707 | ||
1708 | __error: | |
1709 | snd_card_free(card); | |
1710 | return err; | |
1711 | } | |
1712 | ||
e23e7a14 | 1713 | static void snd_atiixp_remove(struct pci_dev *pci) |
1da177e4 LT |
1714 | { |
1715 | snd_card_free(pci_get_drvdata(pci)); | |
1da177e4 LT |
1716 | } |
1717 | ||
e9f66d9b | 1718 | static struct pci_driver atiixp_driver = { |
3733e424 | 1719 | .name = KBUILD_MODNAME, |
1da177e4 LT |
1720 | .id_table = snd_atiixp_ids, |
1721 | .probe = snd_atiixp_probe, | |
e23e7a14 | 1722 | .remove = snd_atiixp_remove, |
68cb2b55 TI |
1723 | .driver = { |
1724 | .pm = SND_ATIIXP_PM_OPS, | |
1725 | }, | |
1da177e4 LT |
1726 | }; |
1727 | ||
e9f66d9b | 1728 | module_pci_driver(atiixp_driver); |