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8cc72361 WYC |
1 | /** |
2 | * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. | |
3 | * | |
4 | * This source file is released under GPL v2 license (no other versions). | |
5 | * See the COPYING file included in the main directory of this source | |
6 | * distribution for the license terms and conditions. | |
7 | */ | |
8 | ||
9 | #ifndef CT20K1REG_H | |
ee3043b2 | 10 | #define CT20K1REG_H |
8cc72361 WYC |
11 | |
12 | /* 20k1 registers */ | |
13 | #define DSPXRAM_START 0x000000 | |
14 | #define DSPXRAM_END 0x013FFC | |
15 | #define DSPAXRAM_START 0x020000 | |
16 | #define DSPAXRAM_END 0x023FFC | |
17 | #define DSPYRAM_START 0x040000 | |
18 | #define DSPYRAM_END 0x04FFFC | |
19 | #define DSPAYRAM_START 0x020000 | |
20 | #define DSPAYRAM_END 0x063FFC | |
21 | #define DSPMICRO_START 0x080000 | |
22 | #define DSPMICRO_END 0x0B3FFC | |
23 | #define DSP0IO_START 0x100000 | |
24 | #define DSP0IO_END 0x101FFC | |
25 | #define AUDIORINGIPDSP0_START 0x100000 | |
26 | #define AUDIORINGIPDSP0_END 0x1003FC | |
27 | #define AUDIORINGOPDSP0_START 0x100400 | |
28 | #define AUDIORINGOPDSP0_END 0x1007FC | |
29 | #define AUDPARARINGIODSP0_START 0x100800 | |
30 | #define AUDPARARINGIODSP0_END 0x100BFC | |
31 | #define DSP0LOCALHWREG_START 0x100C00 | |
32 | #define DSP0LOCALHWREG_END 0x100C3C | |
33 | #define DSP0XYRAMAGINDEX_START 0x100C40 | |
34 | #define DSP0XYRAMAGINDEX_END 0x100C5C | |
35 | #define DSP0XYRAMAGMDFR_START 0x100C60 | |
36 | #define DSP0XYRAMAGMDFR_END 0x100C7C | |
37 | #define DSP0INTCONTLVEC_START 0x100C80 | |
38 | #define DSP0INTCONTLVEC_END 0x100CD8 | |
39 | #define INTCONTLGLOBALREG_START 0x100D1C | |
40 | #define INTCONTLGLOBALREG_END 0x100D3C | |
41 | #define HOSTINTFPORTADDRCONTDSP0 0x100D40 | |
42 | #define HOSTINTFPORTDATADSP0 0x100D44 | |
43 | #define TIME0PERENBDSP0 0x100D60 | |
44 | #define TIME0COUNTERDSP0 0x100D64 | |
45 | #define TIME1PERENBDSP0 0x100D68 | |
46 | #define TIME1COUNTERDSP0 0x100D6C | |
47 | #define TIME2PERENBDSP0 0x100D70 | |
48 | #define TIME2COUNTERDSP0 0x100D74 | |
49 | #define TIME3PERENBDSP0 0x100D78 | |
50 | #define TIME3COUNTERDSP0 0x100D7C | |
51 | #define XRAMINDOPERREFNOUP_STARTDSP0 0x100D80 | |
52 | #define XRAMINDOPERREFNOUP_ENDDSP0 0x100D9C | |
53 | #define XRAMINDOPERREFUP_STARTDSP0 0x100DA0 | |
54 | #define XRAMINDOPERREFUP_ENDDSP0 0x100DBC | |
55 | #define YRAMINDOPERREFNOUP_STARTDSP0 0x100DC0 | |
56 | #define YRAMINDOPERREFNOUP_ENDDSP0 0x100DDC | |
57 | #define YRAMINDOPERREFUP_STARTDSP0 0x100DE0 | |
58 | #define YRAMINDOPERREFUP_ENDDSP0 0x100DFC | |
59 | #define DSP0CONDCODE 0x100E00 | |
60 | #define DSP0STACKFLAG 0x100E04 | |
61 | #define DSP0PROGCOUNTSTACKPTREG 0x100E08 | |
62 | #define DSP0PROGCOUNTSTACKDATAREG 0x100E0C | |
63 | #define DSP0CURLOOPADDRREG 0x100E10 | |
64 | #define DSP0CURLOOPCOUNT 0x100E14 | |
65 | #define DSP0TOPLOOPCOUNTSTACK 0x100E18 | |
66 | #define DSP0TOPLOOPADDRSTACK 0x100E1C | |
67 | #define DSP0LOOPSTACKPTR 0x100E20 | |
68 | #define DSP0STASSTACKDATAREG 0x100E24 | |
69 | #define DSP0STASSTACKPTR 0x100E28 | |
70 | #define DSP0PROGCOUNT 0x100E2C | |
71 | #define GLOBDSPDEBGREG 0x100E30 | |
72 | #define GLOBDSPBREPTRREG 0x100E30 | |
73 | #define DSP0XYRAMBASE_START 0x100EA0 | |
74 | #define DSP0XYRAMBASE_END 0x100EBC | |
75 | #define DSP0XYRAMLENG_START 0x100EC0 | |
76 | #define DSP0XYRAMLENG_END 0x100EDC | |
77 | #define SEMAPHOREREGDSP0 0x100EE0 | |
78 | #define DSP0INTCONTMASKREG 0x100EE4 | |
79 | #define DSP0INTCONTPENDREG 0x100EE8 | |
80 | #define DSP0INTCONTSERVINT 0x100EEC | |
81 | #define DSPINTCONTEXTINTMODREG 0x100EEC | |
82 | #define GPIODSP0 0x100EFC | |
83 | #define DMADSPBASEADDRREG_STARTDSP0 0x100F00 | |
84 | #define DMADSPBASEADDRREG_ENDDSP0 0x100F1C | |
85 | #define DMAHOSTBASEADDRREG_STARTDSP0 0x100F20 | |
86 | #define DMAHOSTBASEADDRREG_ENDDSP0 0x100F3C | |
87 | #define DMADSPCURADDRREG_STARTDSP0 0x100F40 | |
88 | #define DMADSPCURADDRREG_ENDDSP0 0x100F5C | |
89 | #define DMAHOSTCURADDRREG_STARTDSP0 0x100F60 | |
90 | #define DMAHOSTCURADDRREG_ENDDSP0 0x100F7C | |
91 | #define DMATANXCOUNTREG_STARTDSP0 0x100F80 | |
92 | #define DMATANXCOUNTREG_ENDDSP0 0x100F9C | |
93 | #define DMATIMEBUGREG_STARTDSP0 0x100FA0 | |
94 | #define DMATIMEBUGREG_ENDDSP0 0x100FAC | |
95 | #define DMACNTLMODFREG_STARTDSP0 0x100FA0 | |
96 | #define DMACNTLMODFREG_ENDDSP0 0x100FAC | |
97 | ||
98 | #define DMAGLOBSTATSREGDSP0 0x100FEC | |
99 | #define DSP0XGPRAM_START 0x101000 | |
100 | #define DSP0XGPRAM_END 0x1017FC | |
101 | #define DSP0YGPRAM_START 0x101800 | |
102 | #define DSP0YGPRAM_END 0x101FFC | |
103 | ||
104 | ||
105 | ||
106 | ||
107 | #define AUDIORINGIPDSP1_START 0x102000 | |
108 | #define AUDIORINGIPDSP1_END 0x1023FC | |
109 | #define AUDIORINGOPDSP1_START 0x102400 | |
110 | #define AUDIORINGOPDSP1_END 0x1027FC | |
111 | #define AUDPARARINGIODSP1_START 0x102800 | |
112 | #define AUDPARARINGIODSP1_END 0x102BFC | |
113 | #define DSP1LOCALHWREG_START 0x102C00 | |
114 | #define DSP1LOCALHWREG_END 0x102C3C | |
115 | #define DSP1XYRAMAGINDEX_START 0x102C40 | |
116 | #define DSP1XYRAMAGINDEX_END 0x102C5C | |
117 | #define DSP1XYRAMAGMDFR_START 0x102C60 | |
118 | #define DSP1XYRAMAGMDFR_END 0x102C7C | |
119 | #define DSP1INTCONTLVEC_START 0x102C80 | |
120 | #define DSP1INTCONTLVEC_END 0x102CD8 | |
121 | #define HOSTINTFPORTADDRCONTDSP1 0x102D40 | |
122 | #define HOSTINTFPORTDATADSP1 0x102D44 | |
123 | #define TIME0PERENBDSP1 0x102D60 | |
124 | #define TIME0COUNTERDSP1 0x102D64 | |
125 | #define TIME1PERENBDSP1 0x102D68 | |
126 | #define TIME1COUNTERDSP1 0x102D6C | |
127 | #define TIME2PERENBDSP1 0x102D70 | |
128 | #define TIME2COUNTERDSP1 0x102D74 | |
129 | #define TIME3PERENBDSP1 0x102D78 | |
130 | #define TIME3COUNTERDSP1 0x102D7C | |
131 | #define XRAMINDOPERREFNOUP_STARTDSP1 0x102D80 | |
132 | #define XRAMINDOPERREFNOUP_ENDDSP1 0x102D9C | |
133 | #define XRAMINDOPERREFUP_STARTDSP1 0x102DA0 | |
134 | #define XRAMINDOPERREFUP_ENDDSP1 0x102DBC | |
135 | #define YRAMINDOPERREFNOUP_STARTDSP1 0x102DC0 | |
136 | #define YRAMINDOPERREFNOUP_ENDDSP1 0x102DDC | |
137 | #define YRAMINDOPERREFUP_STARTDSP1 0x102DE0 | |
138 | #define YRAMINDOPERREFUP_ENDDSP1 0x102DFC | |
139 | ||
140 | #define DSP1CONDCODE 0x102E00 | |
141 | #define DSP1STACKFLAG 0x102E04 | |
142 | #define DSP1PROGCOUNTSTACKPTREG 0x102E08 | |
143 | #define DSP1PROGCOUNTSTACKDATAREG 0x102E0C | |
144 | #define DSP1CURLOOPADDRREG 0x102E10 | |
145 | #define DSP1CURLOOPCOUNT 0x102E14 | |
146 | #define DSP1TOPLOOPCOUNTSTACK 0x102E18 | |
147 | #define DSP1TOPLOOPADDRSTACK 0x102E1C | |
148 | #define DSP1LOOPSTACKPTR 0x102E20 | |
149 | #define DSP1STASSTACKDATAREG 0x102E24 | |
150 | #define DSP1STASSTACKPTR 0x102E28 | |
151 | #define DSP1PROGCOUNT 0x102E2C | |
152 | #define DSP1XYRAMBASE_START 0x102EA0 | |
153 | #define DSP1XYRAMBASE_END 0x102EBC | |
154 | #define DSP1XYRAMLENG_START 0x102EC0 | |
155 | #define DSP1XYRAMLENG_END 0x102EDC | |
156 | #define SEMAPHOREREGDSP1 0x102EE0 | |
157 | #define DSP1INTCONTMASKREG 0x102EE4 | |
158 | #define DSP1INTCONTPENDREG 0x102EE8 | |
159 | #define DSP1INTCONTSERVINT 0x102EEC | |
160 | #define GPIODSP1 0x102EFC | |
161 | #define DMADSPBASEADDRREG_STARTDSP1 0x102F00 | |
162 | #define DMADSPBASEADDRREG_ENDDSP1 0x102F1C | |
163 | #define DMAHOSTBASEADDRREG_STARTDSP1 0x102F20 | |
164 | #define DMAHOSTBASEADDRREG_ENDDSP1 0x102F3C | |
165 | #define DMADSPCURADDRREG_STARTDSP1 0x102F40 | |
166 | #define DMADSPCURADDRREG_ENDDSP1 0x102F5C | |
167 | #define DMAHOSTCURADDRREG_STARTDSP1 0x102F60 | |
168 | #define DMAHOSTCURADDRREG_ENDDSP1 0x102F7C | |
169 | #define DMATANXCOUNTREG_STARTDSP1 0x102F80 | |
170 | #define DMATANXCOUNTREG_ENDDSP1 0x102F9C | |
171 | #define DMATIMEBUGREG_STARTDSP1 0x102FA0 | |
172 | #define DMATIMEBUGREG_ENDDSP1 0x102FAC | |
173 | #define DMACNTLMODFREG_STARTDSP1 0x102FA0 | |
174 | #define DMACNTLMODFREG_ENDDSP1 0x102FAC | |
175 | ||
176 | #define DMAGLOBSTATSREGDSP1 0x102FEC | |
177 | #define DSP1XGPRAM_START 0x103000 | |
178 | #define DSP1XGPRAM_END 0x1033FC | |
179 | #define DSP1YGPRAM_START 0x103400 | |
180 | #define DSP1YGPRAM_END 0x1037FC | |
181 | ||
182 | ||
183 | ||
184 | #define AUDIORINGIPDSP2_START 0x104000 | |
185 | #define AUDIORINGIPDSP2_END 0x1043FC | |
186 | #define AUDIORINGOPDSP2_START 0x104400 | |
187 | #define AUDIORINGOPDSP2_END 0x1047FC | |
188 | #define AUDPARARINGIODSP2_START 0x104800 | |
189 | #define AUDPARARINGIODSP2_END 0x104BFC | |
190 | #define DSP2LOCALHWREG_START 0x104C00 | |
191 | #define DSP2LOCALHWREG_END 0x104C3C | |
192 | #define DSP2XYRAMAGINDEX_START 0x104C40 | |
193 | #define DSP2XYRAMAGINDEX_END 0x104C5C | |
194 | #define DSP2XYRAMAGMDFR_START 0x104C60 | |
195 | #define DSP2XYRAMAGMDFR_END 0x104C7C | |
196 | #define DSP2INTCONTLVEC_START 0x104C80 | |
197 | #define DSP2INTCONTLVEC_END 0x104CD8 | |
198 | #define HOSTINTFPORTADDRCONTDSP2 0x104D40 | |
199 | #define HOSTINTFPORTDATADSP2 0x104D44 | |
200 | #define TIME0PERENBDSP2 0x104D60 | |
201 | #define TIME0COUNTERDSP2 0x104D64 | |
202 | #define TIME1PERENBDSP2 0x104D68 | |
203 | #define TIME1COUNTERDSP2 0x104D6C | |
204 | #define TIME2PERENBDSP2 0x104D70 | |
205 | #define TIME2COUNTERDSP2 0x104D74 | |
206 | #define TIME3PERENBDSP2 0x104D78 | |
207 | #define TIME3COUNTERDSP2 0x104D7C | |
208 | #define XRAMINDOPERREFNOUP_STARTDSP2 0x104D80 | |
209 | #define XRAMINDOPERREFNOUP_ENDDSP2 0x104D9C | |
210 | #define XRAMINDOPERREFUP_STARTDSP2 0x104DA0 | |
211 | #define XRAMINDOPERREFUP_ENDDSP2 0x104DBC | |
212 | #define YRAMINDOPERREFNOUP_STARTDSP2 0x104DC0 | |
213 | #define YRAMINDOPERREFNOUP_ENDDSP2 0x104DDC | |
214 | #define YRAMINDOPERREFUP_STARTDSP2 0x104DE0 | |
215 | #define YRAMINDOPERREFUP_ENDDSP2 0x104DFC | |
216 | #define DSP2CONDCODE 0x104E00 | |
217 | #define DSP2STACKFLAG 0x104E04 | |
218 | #define DSP2PROGCOUNTSTACKPTREG 0x104E08 | |
219 | #define DSP2PROGCOUNTSTACKDATAREG 0x104E0C | |
220 | #define DSP2CURLOOPADDRREG 0x104E10 | |
221 | #define DSP2CURLOOPCOUNT 0x104E14 | |
222 | #define DSP2TOPLOOPCOUNTSTACK 0x104E18 | |
223 | #define DSP2TOPLOOPADDRSTACK 0x104E1C | |
224 | #define DSP2LOOPSTACKPTR 0x104E20 | |
225 | #define DSP2STASSTACKDATAREG 0x104E24 | |
226 | #define DSP2STASSTACKPTR 0x104E28 | |
227 | #define DSP2PROGCOUNT 0x104E2C | |
228 | #define DSP2XYRAMBASE_START 0x104EA0 | |
229 | #define DSP2XYRAMBASE_END 0x104EBC | |
230 | #define DSP2XYRAMLENG_START 0x104EC0 | |
231 | #define DSP2XYRAMLENG_END 0x104EDC | |
232 | #define SEMAPHOREREGDSP2 0x104EE0 | |
233 | #define DSP2INTCONTMASKREG 0x104EE4 | |
234 | #define DSP2INTCONTPENDREG 0x104EE8 | |
235 | #define DSP2INTCONTSERVINT 0x104EEC | |
236 | #define GPIODSP2 0x104EFC | |
237 | #define DMADSPBASEADDRREG_STARTDSP2 0x104F00 | |
238 | #define DMADSPBASEADDRREG_ENDDSP2 0x104F1C | |
239 | #define DMAHOSTBASEADDRREG_STARTDSP2 0x104F20 | |
240 | #define DMAHOSTBASEADDRREG_ENDDSP2 0x104F3C | |
241 | #define DMADSPCURADDRREG_STARTDSP2 0x104F40 | |
242 | #define DMADSPCURADDRREG_ENDDSP2 0x104F5C | |
243 | #define DMAHOSTCURADDRREG_STARTDSP2 0x104F60 | |
244 | #define DMAHOSTCURADDRREG_ENDDSP2 0x104F7C | |
245 | #define DMATANXCOUNTREG_STARTDSP2 0x104F80 | |
246 | #define DMATANXCOUNTREG_ENDDSP2 0x104F9C | |
247 | #define DMATIMEBUGREG_STARTDSP2 0x104FA0 | |
248 | #define DMATIMEBUGREG_ENDDSP2 0x104FAC | |
249 | #define DMACNTLMODFREG_STARTDSP2 0x104FA0 | |
250 | #define DMACNTLMODFREG_ENDDSP2 0x104FAC | |
251 | ||
252 | #define DMAGLOBSTATSREGDSP2 0x104FEC | |
253 | #define DSP2XGPRAM_START 0x105000 | |
254 | #define DSP2XGPRAM_END 0x1051FC | |
255 | #define DSP2YGPRAM_START 0x105800 | |
256 | #define DSP2YGPRAM_END 0x1059FC | |
257 | ||
258 | ||
259 | ||
260 | #define AUDIORINGIPDSP3_START 0x106000 | |
261 | #define AUDIORINGIPDSP3_END 0x1063FC | |
262 | #define AUDIORINGOPDSP3_START 0x106400 | |
263 | #define AUDIORINGOPDSP3_END 0x1067FC | |
264 | #define AUDPARARINGIODSP3_START 0x106800 | |
265 | #define AUDPARARINGIODSP3_END 0x106BFC | |
266 | #define DSP3LOCALHWREG_START 0x106C00 | |
267 | #define DSP3LOCALHWREG_END 0x106C3C | |
268 | #define DSP3XYRAMAGINDEX_START 0x106C40 | |
269 | #define DSP3XYRAMAGINDEX_END 0x106C5C | |
270 | #define DSP3XYRAMAGMDFR_START 0x106C60 | |
271 | #define DSP3XYRAMAGMDFR_END 0x106C7C | |
272 | #define DSP3INTCONTLVEC_START 0x106C80 | |
273 | #define DSP3INTCONTLVEC_END 0x106CD8 | |
274 | #define HOSTINTFPORTADDRCONTDSP3 0x106D40 | |
275 | #define HOSTINTFPORTDATADSP3 0x106D44 | |
276 | #define TIME0PERENBDSP3 0x106D60 | |
277 | #define TIME0COUNTERDSP3 0x106D64 | |
278 | #define TIME1PERENBDSP3 0x106D68 | |
279 | #define TIME1COUNTERDSP3 0x106D6C | |
280 | #define TIME2PERENBDSP3 0x106D70 | |
281 | #define TIME2COUNTERDSP3 0x106D74 | |
282 | #define TIME3PERENBDSP3 0x106D78 | |
283 | #define TIME3COUNTERDSP3 0x106D7C | |
284 | #define XRAMINDOPERREFNOUP_STARTDSP3 0x106D80 | |
285 | #define XRAMINDOPERREFNOUP_ENDDSP3 0x106D9C | |
286 | #define XRAMINDOPERREFUP_STARTDSP3 0x106DA0 | |
287 | #define XRAMINDOPERREFUP_ENDDSP3 0x106DBC | |
288 | #define YRAMINDOPERREFNOUP_STARTDSP3 0x106DC0 | |
289 | #define YRAMINDOPERREFNOUP_ENDDSP3 0x106DDC | |
290 | #define YRAMINDOPERREFUP_STARTDSP3 0x106DE0 | |
291 | #define YRAMINDOPERREFUP_ENDDSP3 0x100DFC | |
292 | ||
293 | #define DSP3CONDCODE 0x106E00 | |
294 | #define DSP3STACKFLAG 0x106E04 | |
295 | #define DSP3PROGCOUNTSTACKPTREG 0x106E08 | |
296 | #define DSP3PROGCOUNTSTACKDATAREG 0x106E0C | |
297 | #define DSP3CURLOOPADDRREG 0x106E10 | |
298 | #define DSP3CURLOOPCOUNT 0x106E14 | |
299 | #define DSP3TOPLOOPCOUNTSTACK 0x106E18 | |
300 | #define DSP3TOPLOOPADDRSTACK 0x106E1C | |
301 | #define DSP3LOOPSTACKPTR 0x106E20 | |
302 | #define DSP3STASSTACKDATAREG 0x106E24 | |
303 | #define DSP3STASSTACKPTR 0x106E28 | |
304 | #define DSP3PROGCOUNT 0x106E2C | |
305 | #define DSP3XYRAMBASE_START 0x106EA0 | |
306 | #define DSP3XYRAMBASE_END 0x106EBC | |
307 | #define DSP3XYRAMLENG_START 0x106EC0 | |
308 | #define DSP3XYRAMLENG_END 0x106EDC | |
309 | #define SEMAPHOREREGDSP3 0x106EE0 | |
310 | #define DSP3INTCONTMASKREG 0x106EE4 | |
311 | #define DSP3INTCONTPENDREG 0x106EE8 | |
312 | #define DSP3INTCONTSERVINT 0x106EEC | |
313 | #define GPIODSP3 0x106EFC | |
314 | #define DMADSPBASEADDRREG_STARTDSP3 0x106F00 | |
315 | #define DMADSPBASEADDRREG_ENDDSP3 0x106F1C | |
316 | #define DMAHOSTBASEADDRREG_STARTDSP3 0x106F20 | |
317 | #define DMAHOSTBASEADDRREG_ENDDSP3 0x106F3C | |
318 | #define DMADSPCURADDRREG_STARTDSP3 0x106F40 | |
319 | #define DMADSPCURADDRREG_ENDDSP3 0x106F5C | |
320 | #define DMAHOSTCURADDRREG_STARTDSP3 0x106F60 | |
321 | #define DMAHOSTCURADDRREG_ENDDSP3 0x106F7C | |
322 | #define DMATANXCOUNTREG_STARTDSP3 0x106F80 | |
323 | #define DMATANXCOUNTREG_ENDDSP3 0x106F9C | |
324 | #define DMATIMEBUGREG_STARTDSP3 0x106FA0 | |
325 | #define DMATIMEBUGREG_ENDDSP3 0x106FAC | |
326 | #define DMACNTLMODFREG_STARTDSP3 0x106FA0 | |
327 | #define DMACNTLMODFREG_ENDDSP3 0x106FAC | |
328 | ||
329 | #define DMAGLOBSTATSREGDSP3 0x106FEC | |
330 | #define DSP3XGPRAM_START 0x107000 | |
331 | #define DSP3XGPRAM_END 0x1071FC | |
332 | #define DSP3YGPRAM_START 0x107800 | |
333 | #define DSP3YGPRAM_END 0x1079FC | |
334 | ||
335 | /* end of DSP reg definitions */ | |
336 | ||
337 | #define DSPAIMAP_START 0x108000 | |
338 | #define DSPAIMAP_END 0x1083FC | |
339 | #define DSPPIMAP_START 0x108400 | |
340 | #define DSPPIMAP_END 0x1087FC | |
341 | #define DSPPOMAP_START 0x108800 | |
342 | #define DSPPOMAP_END 0x108BFC | |
343 | #define DSPPOCTL 0x108C00 | |
344 | #define TKCTL_START 0x110000 | |
345 | #define TKCTL_END 0x110FFC | |
346 | #define TKCC_START 0x111000 | |
347 | #define TKCC_END 0x111FFC | |
348 | #define TKIMAP_START 0x112000 | |
349 | #define TKIMAP_END 0x112FFC | |
350 | #define TKDCTR16 0x113000 | |
351 | #define TKPB16 0x113004 | |
352 | #define TKBS16 0x113008 | |
353 | #define TKDCTR32 0x11300C | |
354 | #define TKPB32 0x113010 | |
355 | #define TKBS32 0x113014 | |
356 | #define ICDCTR16 0x113018 | |
357 | #define ITBS16 0x11301C | |
358 | #define ICDCTR32 0x113020 | |
359 | #define ITBS32 0x113024 | |
360 | #define ITSTART 0x113028 | |
361 | #define TKSQ 0x11302C | |
362 | ||
363 | #define TKSCCTL_START 0x114000 | |
364 | #define TKSCCTL_END 0x11403C | |
365 | #define TKSCADR_START 0x114100 | |
366 | #define TKSCADR_END 0x11413C | |
367 | #define TKSCDATAX_START 0x114800 | |
368 | #define TKSCDATAX_END 0x1149FC | |
369 | #define TKPCDATAX_START 0x120000 | |
370 | #define TKPCDATAX_END 0x12FFFC | |
371 | ||
372 | #define MALSA 0x130000 | |
373 | #define MAPPHA 0x130004 | |
374 | #define MAPPLA 0x130008 | |
375 | #define MALSB 0x130010 | |
376 | #define MAPPHB 0x130014 | |
377 | #define MAPPLB 0x130018 | |
378 | ||
379 | #define TANSPORTMAPABREGS_START 0x130020 | |
380 | #define TANSPORTMAPABREGS_END 0x13A2FC | |
381 | ||
382 | #define PTPAHX 0x13B000 | |
383 | #define PTPALX 0x13B004 | |
384 | ||
385 | #define TANSPPAGETABLEPHYADDR015_START 0x13B008 | |
386 | #define TANSPPAGETABLEPHYADDR015_END 0x13B07C | |
387 | #define TRNQADRX_START 0x13B100 | |
388 | #define TRNQADRX_END 0x13B13C | |
389 | #define TRNQTIMX_START 0x13B200 | |
390 | #define TRNQTIMX_END 0x13B23C | |
391 | #define TRNQAPARMX_START 0x13B300 | |
392 | #define TRNQAPARMX_END 0x13B33C | |
393 | ||
394 | #define TRNQCNT 0x13B400 | |
395 | #define TRNCTL 0x13B404 | |
396 | #define TRNIS 0x13B408 | |
397 | #define TRNCURTS 0x13B40C | |
398 | ||
399 | #define AMOP_START 0x140000 | |
400 | #define AMOPLO 0x140000 | |
401 | #define AMOPHI 0x140004 | |
402 | #define AMOP_END 0x147FFC | |
403 | #define PMOP_START 0x148000 | |
404 | #define PMOPLO 0x148000 | |
405 | #define PMOPHI 0x148004 | |
406 | #define PMOP_END 0x14FFFC | |
407 | #define PCURR_START 0x150000 | |
408 | #define PCURR_END 0x153FFC | |
409 | #define PTRAG_START 0x154000 | |
410 | #define PTRAG_END 0x157FFC | |
411 | #define PSR_START 0x158000 | |
412 | #define PSR_END 0x15BFFC | |
413 | ||
414 | #define PFSTAT4SEG_START 0x160000 | |
415 | #define PFSTAT4SEG_END 0x160BFC | |
416 | #define PFSTAT2SEG_START 0x160C00 | |
417 | #define PFSTAT2SEG_END 0x1617FC | |
418 | #define PFTARG4SEG_START 0x164000 | |
419 | #define PFTARG4SEG_END 0x164BFC | |
420 | #define PFTARG2SEG_START 0x164C00 | |
421 | #define PFTARG2SEG_END 0x1657FC | |
422 | #define PFSR4SEG_START 0x168000 | |
423 | #define PFSR4SEG_END 0x168BFC | |
424 | #define PFSR2SEG_START 0x168C00 | |
425 | #define PFSR2SEG_END 0x1697FC | |
426 | #define PCURRMS4SEG_START 0x16C000 | |
427 | #define PCURRMS4SEG_END 0x16CCFC | |
428 | #define PCURRMS2SEG_START 0x16CC00 | |
429 | #define PCURRMS2SEG_END 0x16D7FC | |
430 | #define PTARGMS4SEG_START 0x170000 | |
431 | #define PTARGMS4SEG_END 0x172FFC | |
432 | #define PTARGMS2SEG_START 0x173000 | |
433 | #define PTARGMS2SEG_END 0x1747FC | |
434 | #define PSRMS4SEG_START 0x170000 | |
435 | #define PSRMS4SEG_END 0x172FFC | |
436 | #define PSRMS2SEG_START 0x173000 | |
437 | #define PSRMS2SEG_END 0x1747FC | |
438 | ||
439 | #define PRING_LO_START 0x190000 | |
440 | #define PRING_LO_END 0x193FFC | |
441 | #define PRING_HI_START 0x194000 | |
442 | #define PRING_HI_END 0x197FFC | |
443 | #define PRING_LO_HI_START 0x198000 | |
444 | #define PRING_LO_HI 0x198000 | |
445 | #define PRING_LO_HI_END 0x19BFFC | |
446 | ||
447 | #define PINTFIFO 0x1A0000 | |
448 | #define SRCCTL 0x1B0000 | |
449 | #define SRCCCR 0x1B0004 | |
450 | #define SRCIMAP 0x1B0008 | |
451 | #define SRCODDC 0x1B000C | |
452 | #define SRCCA 0x1B0010 | |
453 | #define SRCCF 0x1B0014 | |
454 | #define SRCSA 0x1B0018 | |
455 | #define SRCLA 0x1B001C | |
456 | #define SRCCTLSWR 0x1B0020 | |
457 | ||
458 | /* SRC HERE */ | |
459 | #define SRCALBA 0x1B002C | |
460 | #define SRCMCTL 0x1B012C | |
461 | #define SRCCERR 0x1B022C | |
462 | #define SRCITB 0x1B032C | |
463 | #define SRCIPM 0x1B082C | |
464 | #define SRCIP 0x1B102C | |
465 | #define SRCENBSTAT 0x1B202C | |
466 | #define SRCENBLO 0x1B212C | |
467 | #define SRCENBHI 0x1B222C | |
468 | #define SRCENBS 0x1B232C | |
469 | #define SRCENB 0x1B282C | |
470 | #define SRCENB07 0x1B282C | |
471 | #define SRCENBS07 0x1B302C | |
472 | ||
473 | #define SRCDN0Z 0x1B0030 | |
474 | #define SRCDN0Z0 0x1B0030 | |
475 | #define SRCDN0Z1 0x1B0034 | |
476 | #define SRCDN0Z2 0x1B0038 | |
477 | #define SRCDN0Z3 0x1B003C | |
478 | #define SRCDN1Z 0x1B0040 | |
479 | #define SRCDN1Z0 0x1B0040 | |
480 | #define SRCDN1Z1 0x1B0044 | |
481 | #define SRCDN1Z2 0x1B0048 | |
482 | #define SRCDN1Z3 0x1B004C | |
483 | #define SRCDN1Z4 0x1B0050 | |
484 | #define SRCDN1Z5 0x1B0054 | |
485 | #define SRCDN1Z6 0x1B0058 | |
486 | #define SRCDN1Z7 0x1B005C | |
487 | #define SRCUPZ 0x1B0060 | |
488 | #define SRCUPZ0 0x1B0060 | |
489 | #define SRCUPZ1 0x1B0064 | |
490 | #define SRCUPZ2 0x1B0068 | |
491 | #define SRCUPZ3 0x1B006C | |
492 | #define SRCUPZ4 0x1B0070 | |
493 | #define SRCUPZ5 0x1B0074 | |
494 | #define SRCUPZ6 0x1B0078 | |
495 | #define SRCUPZ7 0x1B007C | |
496 | #define SRCCD0 0x1B0080 | |
497 | #define SRCCD1 0x1B0084 | |
498 | #define SRCCD2 0x1B0088 | |
499 | #define SRCCD3 0x1B008C | |
500 | #define SRCCD4 0x1B0090 | |
501 | #define SRCCD5 0x1B0094 | |
502 | #define SRCCD6 0x1B0098 | |
503 | #define SRCCD7 0x1B009C | |
504 | #define SRCCD8 0x1B00A0 | |
505 | #define SRCCD9 0x1B00A4 | |
506 | #define SRCCDA 0x1B00A8 | |
507 | #define SRCCDB 0x1B00AC | |
508 | #define SRCCDC 0x1B00B0 | |
509 | #define SRCCDD 0x1B00B4 | |
510 | #define SRCCDE 0x1B00B8 | |
511 | #define SRCCDF 0x1B00BC | |
512 | #define SRCCD10 0x1B00C0 | |
513 | #define SRCCD11 0x1B00C4 | |
514 | #define SRCCD12 0x1B00C8 | |
515 | #define SRCCD13 0x1B00CC | |
516 | #define SRCCD14 0x1B00D0 | |
517 | #define SRCCD15 0x1B00D4 | |
518 | #define SRCCD16 0x1B00D8 | |
519 | #define SRCCD17 0x1B00DC | |
520 | #define SRCCD18 0x1B00E0 | |
521 | #define SRCCD19 0x1B00E4 | |
522 | #define SRCCD1A 0x1B00E8 | |
523 | #define SRCCD1B 0x1B00EC | |
524 | #define SRCCD1C 0x1B00F0 | |
525 | #define SRCCD1D 0x1B00F4 | |
526 | #define SRCCD1E 0x1B00F8 | |
527 | #define SRCCD1F 0x1B00FC | |
528 | ||
529 | #define SRCCONTRBLOCK_START 0x1B0100 | |
530 | #define SRCCONTRBLOCK_END 0x1BFFFC | |
531 | #define FILTOP_START 0x1C0000 | |
532 | #define FILTOP_END 0x1C05FC | |
533 | #define FILTIMAP_START 0x1C0800 | |
534 | #define FILTIMAP_END 0x1C0DFC | |
535 | #define FILTZ1_START 0x1C1000 | |
536 | #define FILTZ1_END 0x1C15FC | |
537 | #define FILTZ2_START 0x1C1800 | |
538 | #define FILTZ2_END 0x1C1DFC | |
539 | #define DAOIMAP_START 0x1C5000 | |
540 | #define DAOIMAP 0x1C5000 | |
541 | #define DAOIMAP_END 0x1C5124 | |
542 | ||
543 | #define AC97D 0x1C5400 | |
544 | #define AC97A 0x1C5404 | |
545 | #define AC97CTL 0x1C5408 | |
546 | #define I2SCTL 0x1C5420 | |
547 | ||
548 | #define SPOS 0x1C5440 | |
549 | #define SPOSA 0x1C5440 | |
550 | #define SPOSB 0x1C5444 | |
551 | #define SPOSC 0x1C5448 | |
552 | #define SPOSD 0x1C544C | |
553 | ||
554 | #define SPISA 0x1C5450 | |
555 | #define SPISB 0x1C5454 | |
556 | #define SPISC 0x1C5458 | |
557 | #define SPISD 0x1C545C | |
558 | ||
559 | #define SPFSCTL 0x1C5460 | |
560 | ||
561 | #define SPFS0 0x1C5468 | |
562 | #define SPFS1 0x1C546C | |
563 | #define SPFS2 0x1C5470 | |
564 | #define SPFS3 0x1C5474 | |
565 | #define SPFS4 0x1C5478 | |
566 | #define SPFS5 0x1C547C | |
567 | ||
568 | #define SPOCTL 0x1C5480 | |
569 | #define SPICTL 0x1C5484 | |
570 | #define SPISTS 0x1C5488 | |
571 | #define SPINTP 0x1C548C | |
572 | #define SPINTE 0x1C5490 | |
573 | #define SPUTCTLAB 0x1C5494 | |
574 | #define SPUTCTLCD 0x1C5498 | |
575 | ||
576 | #define SRTSPA 0x1C54C0 | |
577 | #define SRTSPB 0x1C54C4 | |
578 | #define SRTSPC 0x1C54C8 | |
579 | #define SRTSPD 0x1C54CC | |
580 | ||
581 | #define SRTSCTL 0x1C54D0 | |
582 | #define SRTSCTLA 0x1C54D0 | |
583 | #define SRTSCTLB 0x1C54D4 | |
584 | #define SRTSCTLC 0x1C54D8 | |
585 | #define SRTSCTLD 0x1C54DC | |
586 | ||
587 | #define SRTI2S 0x1C54E0 | |
588 | #define SRTICTL 0x1C54F0 | |
589 | ||
590 | #define WC 0x1C6000 | |
591 | #define TIMR 0x1C6004 | |
b7bbf876 TI |
592 | # define TIMR_IE (1<<15) |
593 | # define TIMR_IP (1<<14) | |
8cc72361 WYC |
594 | |
595 | #define GIP 0x1C6010 | |
596 | #define GIE 0x1C6014 | |
597 | #define DIE 0x1C6018 | |
598 | #define DIC 0x1C601C | |
599 | #define GPIO 0x1C6020 | |
600 | #define GPIOCTL 0x1C6024 | |
601 | #define GPIP 0x1C6028 | |
602 | #define GPIE 0x1C602C | |
603 | #define DSPINT0 0x1C6030 | |
604 | #define DSPEIOC 0x1C6034 | |
605 | #define MUADAT 0x1C6040 | |
606 | #define MUACMD 0x1C6044 | |
607 | #define MUASTAT 0x1C6044 | |
608 | #define MUBDAT 0x1C6048 | |
609 | #define MUBCMD 0x1C604C | |
610 | #define MUBSTAT 0x1C604C | |
611 | #define UARTCMA 0x1C6050 | |
612 | #define UARTCMB 0x1C6054 | |
613 | #define UARTIP 0x1C6058 | |
614 | #define UARTIE 0x1C605C | |
615 | #define PLLCTL 0x1C6060 | |
616 | #define PLLDCD 0x1C6064 | |
617 | #define GCTL 0x1C6070 | |
618 | #define ID0 0x1C6080 | |
619 | #define ID1 0x1C6084 | |
620 | #define ID2 0x1C6088 | |
621 | #define ID3 0x1C608C | |
622 | #define SDRCTL 0x1C7000 | |
623 | ||
624 | ||
625 | #define I2SA_L 0x0L | |
626 | #define I2SA_R 0x1L | |
627 | #define I2SB_L 0x8L | |
628 | #define I2SB_R 0x9L | |
629 | #define I2SC_L 0x10L | |
630 | #define I2SC_R 0x11L | |
631 | #define I2SD_L 0x18L | |
632 | #define I2SD_R 0x19L | |
633 | ||
634 | #endif /* CT20K1REG_H */ |