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ALSA: ctxfi - Add missing inclusion of linux/delay.h
[deliverable/linux.git] / sound / pci / ctxfi / cthw20k2.c
CommitLineData
8cc72361
WYC		 1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k2.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord for 20k2.
12 *
13 * @Author Liu Chun
14 * @Date May 14 2008
15 *
16 */
17
18#include "cthw20k2.h"
19#include "ct20k2reg.h"
20#include <linux/types.h>
21#include <linux/slab.h>
22#include <linux/pci.h>
23#include <linux/io.h>
24#include <linux/string.h>
25#include <linux/kernel.h>
26#include <linux/interrupt.h>
d0da727e 27#include <linux/delay.h>
8cc72361
WYC		 28
29#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bits */
30
31static u32 hw_read_20kx(struct hw *hw, u32 reg);
32static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
33
34/*
35 * Type definition block.
36 * The layout of control structures can be directly applied on 20k2 chip.
37 */
38
39/*
40 * SRC control block definitions.
41 */
42
43/* SRC resource control block */
44#define SRCCTL_STATE 0x00000007
45#define SRCCTL_BM 0x00000008
46#define SRCCTL_RSR 0x00000030
47#define SRCCTL_SF 0x000001C0
48#define SRCCTL_WR 0x00000200
49#define SRCCTL_PM 0x00000400
50#define SRCCTL_ROM 0x00001800
51#define SRCCTL_VO 0x00002000
52#define SRCCTL_ST 0x00004000
53#define SRCCTL_IE 0x00008000
54#define SRCCTL_ILSZ 0x000F0000
55#define SRCCTL_BP 0x00100000
56
57#define SRCCCR_CISZ 0x000007FF
58#define SRCCCR_CWA 0x001FF800
59#define SRCCCR_D 0x00200000
60#define SRCCCR_RS 0x01C00000
61#define SRCCCR_NAL 0x3E000000
62#define SRCCCR_RA 0xC0000000
63
64#define SRCCA_CA 0x0FFFFFFF
65#define SRCCA_RS 0xE0000000
66
67#define SRCSA_SA 0x0FFFFFFF
68
69#define SRCLA_LA 0x0FFFFFFF
70
71/* Mixer Parameter Ring ram Low and Hight register.
72 * Fixed-point value in 8.24 format for parameter channel */
73#define MPRLH_PITCH 0xFFFFFFFF
74
75/* SRC resource register dirty flags */
76union src_dirty {
77 struct {
78 u16 ctl:1;
79 u16 ccr:1;
80 u16 sa:1;
81 u16 la:1;
82 u16 ca:1;
83 u16 mpr:1;
84 u16 czbfs:1; /* Clear Z-Buffers */
85 u16 rsv:9;
86 } bf;
87 u16 data;
88};
89
90struct src_rsc_ctrl_blk {
91 unsigned int ctl;
92 unsigned int ccr;
93 unsigned int ca;
94 unsigned int sa;
95 unsigned int la;
96 unsigned int mpr;
97 union src_dirty dirty;
98};
99
100/* SRC manager control block */
101union src_mgr_dirty {
102 struct {
103 u16 enb0:1;
104 u16 enb1:1;
105 u16 enb2:1;
106 u16 enb3:1;
107 u16 enb4:1;
108 u16 enb5:1;
109 u16 enb6:1;
110 u16 enb7:1;
111 u16 enbsa:1;
112 u16 rsv:7;
113 } bf;
114 u16 data;
115};
116
117struct src_mgr_ctrl_blk {
118 unsigned int enbsa;
119 unsigned int enb[8];
120 union src_mgr_dirty dirty;
121};
122
123/* SRCIMP manager control block */
124#define SRCAIM_ARC 0x00000FFF
125#define SRCAIM_NXT 0x00FF0000
126#define SRCAIM_SRC 0xFF000000
127
128struct srcimap {
129 unsigned int srcaim;
130 unsigned int idx;
131};
132
133/* SRCIMP manager register dirty flags */
134union srcimp_mgr_dirty {
135 struct {
136 u16 srcimap:1;
137 u16 rsv:15;
138 } bf;
139 u16 data;
140};
141
142struct srcimp_mgr_ctrl_blk {
143 struct srcimap srcimap;
144 union srcimp_mgr_dirty dirty;
145};
146
147/*
148 * Function implementation block.
149 */
150
151static int src_get_rsc_ctrl_blk(void **rblk)
152{
153 struct src_rsc_ctrl_blk *blk;
154
155 *rblk = NULL;
156 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
157 if (NULL == blk)
158 return -ENOMEM;
159
160 *rblk = blk;
161
162 return 0;
163}
164
165static int src_put_rsc_ctrl_blk(void *blk)
166{
167 kfree((struct src_rsc_ctrl_blk *)blk);
168
169 return 0;
170}
171
172static int src_set_state(void *blk, unsigned int state)
173{
174 struct src_rsc_ctrl_blk *ctl = blk;
175
176 set_field(&ctl->ctl, SRCCTL_STATE, state);
177 ctl->dirty.bf.ctl = 1;
178 return 0;
179}
180
181static int src_set_bm(void *blk, unsigned int bm)
182{
183 struct src_rsc_ctrl_blk *ctl = blk;
184
185 set_field(&ctl->ctl, SRCCTL_BM, bm);
186 ctl->dirty.bf.ctl = 1;
187 return 0;
188}
189
190static int src_set_rsr(void *blk, unsigned int rsr)
191{
192 struct src_rsc_ctrl_blk *ctl = blk;
193
194 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
195 ctl->dirty.bf.ctl = 1;
196 return 0;
197}
198
199static int src_set_sf(void *blk, unsigned int sf)
200{
201 struct src_rsc_ctrl_blk *ctl = blk;
202
203 set_field(&ctl->ctl, SRCCTL_SF, sf);
204 ctl->dirty.bf.ctl = 1;
205 return 0;
206}
207
208static int src_set_wr(void *blk, unsigned int wr)
209{
210 struct src_rsc_ctrl_blk *ctl = blk;
211
212 set_field(&ctl->ctl, SRCCTL_WR, wr);
213 ctl->dirty.bf.ctl = 1;
214 return 0;
215}
216
217static int src_set_pm(void *blk, unsigned int pm)
218{
219 struct src_rsc_ctrl_blk *ctl = blk;
220
221 set_field(&ctl->ctl, SRCCTL_PM, pm);
222 ctl->dirty.bf.ctl = 1;
223 return 0;
224}
225
226static int src_set_rom(void *blk, unsigned int rom)
227{
228 struct src_rsc_ctrl_blk *ctl = blk;
229
230 set_field(&ctl->ctl, SRCCTL_ROM, rom);
231 ctl->dirty.bf.ctl = 1;
232 return 0;
233}
234
235static int src_set_vo(void *blk, unsigned int vo)
236{
237 struct src_rsc_ctrl_blk *ctl = blk;
238
239 set_field(&ctl->ctl, SRCCTL_VO, vo);
240 ctl->dirty.bf.ctl = 1;
241 return 0;
242}
243
244static int src_set_st(void *blk, unsigned int st)
245{
246 struct src_rsc_ctrl_blk *ctl = blk;
247
248 set_field(&ctl->ctl, SRCCTL_ST, st);
249 ctl->dirty.bf.ctl = 1;
250 return 0;
251}
252
253static int src_set_ie(void *blk, unsigned int ie)
254{
255 struct src_rsc_ctrl_blk *ctl = blk;
256
257 set_field(&ctl->ctl, SRCCTL_IE, ie);
258 ctl->dirty.bf.ctl = 1;
259 return 0;
260}
261
262static int src_set_ilsz(void *blk, unsigned int ilsz)
263{
264 struct src_rsc_ctrl_blk *ctl = blk;
265
266 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
267 ctl->dirty.bf.ctl = 1;
268 return 0;
269}
270
271static int src_set_bp(void *blk, unsigned int bp)
272{
273 struct src_rsc_ctrl_blk *ctl = blk;
274
275 set_field(&ctl->ctl, SRCCTL_BP, bp);
276 ctl->dirty.bf.ctl = 1;
277 return 0;
278}
279
280static int src_set_cisz(void *blk, unsigned int cisz)
281{
282 struct src_rsc_ctrl_blk *ctl = blk;
283
284 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
285 ctl->dirty.bf.ccr = 1;
286 return 0;
287}
288
289static int src_set_ca(void *blk, unsigned int ca)
290{
291 struct src_rsc_ctrl_blk *ctl = blk;
292
293 set_field(&ctl->ca, SRCCA_CA, ca);
294 ctl->dirty.bf.ca = 1;
295 return 0;
296}
297
298static int src_set_sa(void *blk, unsigned int sa)
299{
300 struct src_rsc_ctrl_blk *ctl = blk;
301
302 set_field(&ctl->sa, SRCSA_SA, sa);
303 ctl->dirty.bf.sa = 1;
304 return 0;
305}
306
307static int src_set_la(void *blk, unsigned int la)
308{
309 struct src_rsc_ctrl_blk *ctl = blk;
310
311 set_field(&ctl->la, SRCLA_LA, la);
312 ctl->dirty.bf.la = 1;
313 return 0;
314}
315
316static int src_set_pitch(void *blk, unsigned int pitch)
317{
318 struct src_rsc_ctrl_blk *ctl = blk;
319
320 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
321 ctl->dirty.bf.mpr = 1;
322 return 0;
323}
324
325static int src_set_clear_zbufs(void *blk, unsigned int clear)
326{
327 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
328 return 0;
329}
330
331static int src_set_dirty(void *blk, unsigned int flags)
332{
333 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
334 return 0;
335}
336
337static int src_set_dirty_all(void *blk)
338{
339 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
340 return 0;
341}
342
343#define AR_SLOT_SIZE 4096
344#define AR_SLOT_BLOCK_SIZE 16
345#define AR_PTS_PITCH 6
346#define AR_PARAM_SRC_OFFSET 0x60
347
348static unsigned int src_param_pitch_mixer(unsigned int src_idx)
349{
350 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
351 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
352
353}
354
355static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
356{
357 struct src_rsc_ctrl_blk *ctl = blk;
358 int i = 0;
359
360 if (ctl->dirty.bf.czbfs) {
361 /* Clear Z-Buffer registers */
362 for (i = 0; i < 8; i++)
363 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
364
365 for (i = 0; i < 4; i++)
366 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
367
368 for (i = 0; i < 8; i++)
369 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
370
371 ctl->dirty.bf.czbfs = 0;
372 }
373 if (ctl->dirty.bf.mpr) {
374 /* Take the parameter mixer resource in the same group as that
375 * the idx src is in for simplicity. Unlike src, all conjugate
376 * parameter mixer resources must be programmed for
377 * corresponding conjugate src resources. */
378 unsigned int pm_idx = src_param_pitch_mixer(idx);
379 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
380 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
381 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
382 ctl->dirty.bf.mpr = 0;
383 }
384 if (ctl->dirty.bf.sa) {
385 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
386 ctl->dirty.bf.sa = 0;
387 }
388 if (ctl->dirty.bf.la) {
389 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
390 ctl->dirty.bf.la = 0;
391 }
392 if (ctl->dirty.bf.ca) {
393 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
394 ctl->dirty.bf.ca = 0;
395 }
396
397 /* Write srccf register */
398 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
399
400 if (ctl->dirty.bf.ccr) {
401 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
402 ctl->dirty.bf.ccr = 0;
403 }
404 if (ctl->dirty.bf.ctl) {
405 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
406 ctl->dirty.bf.ctl = 0;
407 }
408
409 return 0;
410}
411
412static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
413{
414 struct src_rsc_ctrl_blk *ctl = blk;
415
416 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
417 ctl->dirty.bf.ca = 0;
418
419 return get_field(ctl->ca, SRCCA_CA);
420}
421
422static unsigned int src_get_dirty(void *blk)
423{
424 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
425}
426
427static unsigned int src_dirty_conj_mask(void)
428{
429 return 0x20;
430}
431
432static int src_mgr_enbs_src(void *blk, unsigned int idx)
433{
434 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
435 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
436 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
437 return 0;
438}
439
440static int src_mgr_enb_src(void *blk, unsigned int idx)
441{
442 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
443 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
444 return 0;
445}
446
447static int src_mgr_dsb_src(void *blk, unsigned int idx)
448{
449 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
450 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
451 return 0;
452}
453
454static int src_mgr_commit_write(struct hw *hw, void *blk)
455{
456 struct src_mgr_ctrl_blk *ctl = blk;
457 int i = 0;
458 unsigned int ret = 0;
459
460 if (ctl->dirty.bf.enbsa) {
461 do {
462 ret = hw_read_20kx(hw, SRC_ENBSTAT);
463 } while (ret & 0x1);
464 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
465 ctl->dirty.bf.enbsa = 0;
466 }
467 for (i = 0; i < 8; i++) {
468 if ((ctl->dirty.data & (0x1 << i))) {
469 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
470 ctl->dirty.data &= ~(0x1 << i);
471 }
472 }
473
474 return 0;
475}
476
477static int src_mgr_get_ctrl_blk(void **rblk)
478{
479 struct src_mgr_ctrl_blk *blk;
480
481 *rblk = NULL;
482 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
483 if (NULL == blk)
484 return -ENOMEM;
485
486 *rblk = blk;
487
488 return 0;
489}
490
491static int src_mgr_put_ctrl_blk(void *blk)
492{
493 kfree((struct src_mgr_ctrl_blk *)blk);
494
495 return 0;
496}
497
498static int srcimp_mgr_get_ctrl_blk(void **rblk)
499{
500 struct srcimp_mgr_ctrl_blk *blk;
501
502 *rblk = NULL;
503 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
504 if (NULL == blk)
505 return -ENOMEM;
506
507 *rblk = blk;
508
509 return 0;
510}
511
512static int srcimp_mgr_put_ctrl_blk(void *blk)
513{
514 kfree((struct srcimp_mgr_ctrl_blk *)blk);
515
516 return 0;
517}
518
519static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
520{
521 struct srcimp_mgr_ctrl_blk *ctl = blk;
522
523 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
524 ctl->dirty.bf.srcimap = 1;
525 return 0;
526}
527
528static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
529{
530 struct srcimp_mgr_ctrl_blk *ctl = blk;
531
532 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
533 ctl->dirty.bf.srcimap = 1;
534 return 0;
535}
536
537static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
538{
539 struct srcimp_mgr_ctrl_blk *ctl = blk;
540
541 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
542 ctl->dirty.bf.srcimap = 1;
543 return 0;
544}
545
546static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
547{
548 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
549 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
550 return 0;
551}
552
553static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
554{
555 struct srcimp_mgr_ctrl_blk *ctl = blk;
556
557 if (ctl->dirty.bf.srcimap) {
558 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
559 ctl->srcimap.srcaim);
560 ctl->dirty.bf.srcimap = 0;
561 }
562
563 return 0;
564}
565
566/*
567 * AMIXER control block definitions.
568 */
569
570#define AMOPLO_M 0x00000003
571#define AMOPLO_IV 0x00000004
572#define AMOPLO_X 0x0003FFF0
573#define AMOPLO_Y 0xFFFC0000
574
575#define AMOPHI_SADR 0x000000FF
576#define AMOPHI_SE 0x80000000
577
578/* AMIXER resource register dirty flags */
579union amixer_dirty {
580 struct {
581 u16 amoplo:1;
582 u16 amophi:1;
583 u16 rsv:14;
584 } bf;
585 u16 data;
586};
587
588/* AMIXER resource control block */
589struct amixer_rsc_ctrl_blk {
590 unsigned int amoplo;
591 unsigned int amophi;
592 union amixer_dirty dirty;
593};
594
595static int amixer_set_mode(void *blk, unsigned int mode)
596{
597 struct amixer_rsc_ctrl_blk *ctl = blk;
598
599 set_field(&ctl->amoplo, AMOPLO_M, mode);
600 ctl->dirty.bf.amoplo = 1;
601 return 0;
602}
603
604static int amixer_set_iv(void *blk, unsigned int iv)
605{
606 struct amixer_rsc_ctrl_blk *ctl = blk;
607
608 set_field(&ctl->amoplo, AMOPLO_IV, iv);
609 ctl->dirty.bf.amoplo = 1;
610 return 0;
611}
612
613static int amixer_set_x(void *blk, unsigned int x)
614{
615 struct amixer_rsc_ctrl_blk *ctl = blk;
616
617 set_field(&ctl->amoplo, AMOPLO_X, x);
618 ctl->dirty.bf.amoplo = 1;
619 return 0;
620}
621
622static int amixer_set_y(void *blk, unsigned int y)
623{
624 struct amixer_rsc_ctrl_blk *ctl = blk;
625
626 set_field(&ctl->amoplo, AMOPLO_Y, y);
627 ctl->dirty.bf.amoplo = 1;
628 return 0;
629}
630
631static int amixer_set_sadr(void *blk, unsigned int sadr)
632{
633 struct amixer_rsc_ctrl_blk *ctl = blk;
634
635 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
636 ctl->dirty.bf.amophi = 1;
637 return 0;
638}
639
640static int amixer_set_se(void *blk, unsigned int se)
641{
642 struct amixer_rsc_ctrl_blk *ctl = blk;
643
644 set_field(&ctl->amophi, AMOPHI_SE, se);
645 ctl->dirty.bf.amophi = 1;
646 return 0;
647}
648
649static int amixer_set_dirty(void *blk, unsigned int flags)
650{
651 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
652 return 0;
653}
654
655static int amixer_set_dirty_all(void *blk)
656{
657 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
658 return 0;
659}
660
661static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
662{
663 struct amixer_rsc_ctrl_blk *ctl = blk;
664
665 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
666 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
667 ctl->dirty.bf.amoplo = 0;
668 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
669 ctl->dirty.bf.amophi = 0;
670 }
671
672 return 0;
673}
674
675static int amixer_get_y(void *blk)
676{
677 struct amixer_rsc_ctrl_blk *ctl = blk;
678
679 return get_field(ctl->amoplo, AMOPLO_Y);
680}
681
682static unsigned int amixer_get_dirty(void *blk)
683{
684 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
685}
686
687static int amixer_rsc_get_ctrl_blk(void **rblk)
688{
689 struct amixer_rsc_ctrl_blk *blk;
690
691 *rblk = NULL;
692 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
693 if (NULL == blk)
694 return -ENOMEM;
695
696 *rblk = blk;
697
698 return 0;
699}
700
701static int amixer_rsc_put_ctrl_blk(void *blk)
702{
703 kfree((struct amixer_rsc_ctrl_blk *)blk);
704
705 return 0;
706}
707
708static int amixer_mgr_get_ctrl_blk(void **rblk)
709{
710 *rblk = NULL;
711
712 return 0;
713}
714
715static int amixer_mgr_put_ctrl_blk(void *blk)
716{
717 return 0;
718}
719
720/*
721 * DAIO control block definitions.
722 */
723
724/* Receiver Sample Rate Tracker Control register */
725#define SRTCTL_SRCO 0x000000FF
726#define SRTCTL_SRCM 0x0000FF00
727#define SRTCTL_RSR 0x00030000
728#define SRTCTL_DRAT 0x00300000
729#define SRTCTL_EC 0x01000000
730#define SRTCTL_ET 0x10000000
731
732/* DAIO Receiver register dirty flags */
733union dai_dirty {
734 struct {
735 u16 srt:1;
736 u16 rsv:15;
737 } bf;
738 u16 data;
739};
740
741/* DAIO Receiver control block */
742struct dai_ctrl_blk {
743 unsigned int srt;
744 union dai_dirty dirty;
745};
746
747/* Audio Input Mapper RAM */
748#define AIM_ARC 0x00000FFF
749#define AIM_NXT 0x007F0000
750
751struct daoimap {
752 unsigned int aim;
753 unsigned int idx;
754};
755
756/* Audio Transmitter Control and Status register */
757#define ATXCTL_EN 0x00000001
758#define ATXCTL_MODE 0x00000010
759#define ATXCTL_CD 0x00000020
760#define ATXCTL_RAW 0x00000100
761#define ATXCTL_MT 0x00000200
762#define ATXCTL_NUC 0x00003000
763#define ATXCTL_BEN 0x00010000
764#define ATXCTL_BMUX 0x00700000
765#define ATXCTL_B24 0x01000000
766#define ATXCTL_CPF 0x02000000
767#define ATXCTL_RIV 0x10000000
768#define ATXCTL_LIV 0x20000000
769#define ATXCTL_RSAT 0x40000000
770#define ATXCTL_LSAT 0x80000000
771
772/* XDIF Transmitter register dirty flags */
773union dao_dirty {
774 struct {
775 u16 atxcsl:1;
776 u16 rsv:15;
777 } bf;
778 u16 data;
779};
780
781/* XDIF Transmitter control block */
782struct dao_ctrl_blk {
783 /* XDIF Transmitter Channel Status Low Register */
784 unsigned int atxcsl;
785 union dao_dirty dirty;
786};
787
788/* Audio Receiver Control register */
789#define ARXCTL_EN 0x00000001
790
791/* DAIO manager register dirty flags */
792union daio_mgr_dirty {
793 struct {
794 u32 atxctl:8;
795 u32 arxctl:8;
796 u32 daoimap:1;
797 u32 rsv:15;
798 } bf;
799 u32 data;
800};
801
802/* DAIO manager control block */
803struct daio_mgr_ctrl_blk {
804 struct daoimap daoimap;
805 unsigned int txctl[8];
806 unsigned int rxctl[8];
807 union daio_mgr_dirty dirty;
808};
809
810static int dai_srt_set_srco(void *blk, unsigned int src)
811{
812 struct dai_ctrl_blk *ctl = blk;
813
814 set_field(&ctl->srt, SRTCTL_SRCO, src);
815 ctl->dirty.bf.srt = 1;
816 return 0;
817}
818
819static int dai_srt_set_srcm(void *blk, unsigned int src)
820{
821 struct dai_ctrl_blk *ctl = blk;
822
823 set_field(&ctl->srt, SRTCTL_SRCM, src);
824 ctl->dirty.bf.srt = 1;
825 return 0;
826}
827
828static int dai_srt_set_rsr(void *blk, unsigned int rsr)
829{
830 struct dai_ctrl_blk *ctl = blk;
831
832 set_field(&ctl->srt, SRTCTL_RSR, rsr);
833 ctl->dirty.bf.srt = 1;
834 return 0;
835}
836
837static int dai_srt_set_drat(void *blk, unsigned int drat)
838{
839 struct dai_ctrl_blk *ctl = blk;
840
841 set_field(&ctl->srt, SRTCTL_DRAT, drat);
842 ctl->dirty.bf.srt = 1;
843 return 0;
844}
845
846static int dai_srt_set_ec(void *blk, unsigned int ec)
847{
848 struct dai_ctrl_blk *ctl = blk;
849
850 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
851 ctl->dirty.bf.srt = 1;
852 return 0;
853}
854
855static int dai_srt_set_et(void *blk, unsigned int et)
856{
857 struct dai_ctrl_blk *ctl = blk;
858
859 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
860 ctl->dirty.bf.srt = 1;
861 return 0;
862}
863
864static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
865{
866 struct dai_ctrl_blk *ctl = blk;
867
868 if (ctl->dirty.bf.srt) {
869 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
870 ctl->dirty.bf.srt = 0;
871 }
872
873 return 0;
874}
875
876static int dai_get_ctrl_blk(void **rblk)
877{
878 struct dai_ctrl_blk *blk;
879
880 *rblk = NULL;
881 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
882 if (NULL == blk)
883 return -ENOMEM;
884
885 *rblk = blk;
886
887 return 0;
888}
889
890static int dai_put_ctrl_blk(void *blk)
891{
892 kfree((struct dai_ctrl_blk *)blk);
893
894 return 0;
895}
896
897static int dao_set_spos(void *blk, unsigned int spos)
898{
899 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
900 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
901 return 0;
902}
903
904static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
905{
906 struct dao_ctrl_blk *ctl = blk;
907
908 if (ctl->dirty.bf.atxcsl) {
909 if (idx < 4) {
910 /* S/PDIF SPOSx */
911 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
912 ctl->atxcsl);
913 }
914 ctl->dirty.bf.atxcsl = 0;
915 }
916
917 return 0;
918}
919
920static int dao_get_spos(void *blk, unsigned int *spos)
921{
922 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
923 return 0;
924}
925
926static int dao_get_ctrl_blk(void **rblk)
927{
928 struct dao_ctrl_blk *blk;
929
930 *rblk = NULL;
931 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
932 if (NULL == blk)
933 return -ENOMEM;
934
935 *rblk = blk;
936
937 return 0;
938}
939
940static int dao_put_ctrl_blk(void *blk)
941{
942 kfree((struct dao_ctrl_blk *)blk);
943
944 return 0;
945}
946
947static int daio_mgr_enb_dai(void *blk, unsigned int idx)
948{
949 struct daio_mgr_ctrl_blk *ctl = blk;
950
951 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
952 ctl->dirty.bf.arxctl |= (0x1 << idx);
953 return 0;
954}
955
956static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
957{
958 struct daio_mgr_ctrl_blk *ctl = blk;
959
960 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
961
962 ctl->dirty.bf.arxctl |= (0x1 << idx);
963 return 0;
964}
965
966static int daio_mgr_enb_dao(void *blk, unsigned int idx)
967{
968 struct daio_mgr_ctrl_blk *ctl = blk;
969
970 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
971 ctl->dirty.bf.atxctl |= (0x1 << idx);
972 return 0;
973}
974
975static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
976{
977 struct daio_mgr_ctrl_blk *ctl = blk;
978
979 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
980 ctl->dirty.bf.atxctl |= (0x1 << idx);
981 return 0;
982}
983
984static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
985{
986 struct daio_mgr_ctrl_blk *ctl = blk;
987
988 if (idx < 4) {
989 /* S/PDIF output */
990 switch ((conf & 0x7)) {
991 case 1:
992 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
993 break;
994 case 2:
995 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
996 break;
997 case 4:
998 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
999 break;
1000 case 8:
1001 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1002 break;
1003 default:
1004 break;
1005 }
1006 /* CDIF */
1007 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1008 /* Non-audio */
1009 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1010 /* Non-audio */
1011 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1012 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1013 ((conf >> 3) & 0x1) ? 0 : 0);
1014 ctl->dirty.bf.atxctl |= (0x1 << idx);
1015 } else {
1016 /* I2S output */
1017 /*idx %= 4; */
1018 }
1019 return 0;
1020}
1021
1022static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1023{
1024 struct daio_mgr_ctrl_blk *ctl = blk;
1025
1026 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1027 ctl->dirty.bf.daoimap = 1;
1028 return 0;
1029}
1030
1031static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1032{
1033 struct daio_mgr_ctrl_blk *ctl = blk;
1034
1035 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1036 ctl->dirty.bf.daoimap = 1;
1037 return 0;
1038}
1039
1040static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1041{
1042 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1043 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1044 return 0;
1045}
1046
1047static int daio_mgr_commit_write(struct hw *hw, void *blk)
1048{
1049 struct daio_mgr_ctrl_blk *ctl = blk;
1050 unsigned int data = 0;
1051 int i = 0;
1052
1053 for (i = 0; i < 8; i++) {
1054 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1055 data = ctl->txctl[i];
1056 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1057 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1058 mdelay(1);
1059 }
1060 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1061 data = ctl->rxctl[i];
1062 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1063 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1064 mdelay(1);
1065 }
1066 }
1067 if (ctl->dirty.bf.daoimap) {
1068 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1069 ctl->daoimap.aim);
1070 ctl->dirty.bf.daoimap = 0;
1071 }
1072
1073 return 0;
1074}
1075
1076static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1077{
1078 struct daio_mgr_ctrl_blk *blk;
1079 int i = 0;
1080
1081 *rblk = NULL;
1082 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1083 if (NULL == blk)
1084 return -ENOMEM;
1085
1086 for (i = 0; i < 8; i++) {
1087 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1088 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1089 }
1090
1091 *rblk = blk;
1092
1093 return 0;
1094}
1095
1096static int daio_mgr_put_ctrl_blk(void *blk)
1097{
1098 kfree((struct daio_mgr_ctrl_blk *)blk);
1099
1100 return 0;
1101}
1102
1103/* Card hardware initialization block */
1104struct dac_conf {
1105 unsigned int msr; /* master sample rate in rsrs */
1106};
1107
1108struct adc_conf {
1109 unsigned int msr; /* master sample rate in rsrs */
1110 unsigned char input; /* the input source of ADC */
1111 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1112};
1113
1114struct daio_conf {
1115 unsigned int msr; /* master sample rate in rsrs */
1116};
1117
1118struct trn_conf {
1119 unsigned long vm_pgt_phys;
1120};
1121
1122static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1123{
1124 u32 dwData = 0;
1125 int i;
1126
1127 /* Program I2S with proper sample rate and enable the correct I2S
1128 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1129 if (1 == info->msr) {
1130 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1131 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1132 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1133 } else if (2 == info->msr) {
1134 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1135 /* Specify all playing 96khz
1136 * EA [0] - Enabled
1137 * RTA [4:5] - 96kHz
1138 * EB [8] - Enabled
1139 * RTB [12:13] - 96kHz
1140 * EC [16] - Enabled
1141 * RTC [20:21] - 96kHz
1142 * ED [24] - Enabled
1143 * RTD [28:29] - 96kHz */
1144 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1145 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1146 } else {
1147 printk(KERN_ALERT "ERROR!!! Invalid sampling rate!!!\n");
1148 return -EINVAL;
1149 }
1150
1151 for (i = 0; i < 8; i++) {
1152 if (i <= 3) {
1153 /* 1st 3 channels are SPDIFs (SB0960) */
1154 if (i == 3)
1155 dwData = 0x1001001;
1156 else
1157 dwData = 0x1000001;
1158
1159 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData);
1160 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData);
1161
1162 /* Initialize the SPDIF Out Channel status registers.
1163 * The value specified here is based on the typical
1164 * values provided in the specification, namely: Clock
1165 * Accuracy of 1000ppm, Sample Rate of 48KHz,
1166 * unspecified source number, Generation status = 1,
1167 * Category code = 0x12 (Digital Signal Mixer),
1168 * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1169 * (indicating that we're transmitting digital audio,
1170 * and the Professional Use bit is 0. */
1171
1172 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1173 0x02109204); /* Default to 48kHz */
1174
1175 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1176 } else {
1177 /* Next 5 channels are I2S (SB0960) */
1178 dwData = 0x11;
1179 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData);
1180 if (2 == info->msr) {
1181 /* Four channels per sample period */
1182 dwData |= 0x1000;
1183 }
1184 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData);
1185 }
1186 }
1187
1188 return 0;
1189}
1190
1191/* TRANSPORT operations */
1192static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1193{
1194 u32 vmctl = 0, data = 0;
1195 unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1196 int i = 0;
1197
1198 /* Set up device page table */
1199 if ((~0UL) == info->vm_pgt_phys) {
1200 printk(KERN_ALERT "Wrong device page table page address!!!\n");
1201 return -1;
1202 }
1203
1204 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
1205#if BITS_PER_LONG == 64
1206 ptp_phys_low = info->vm_pgt_phys & ((1UL<<32)-1);
1207 ptp_phys_high = (info->vm_pgt_phys>>32) & ((1UL<<32)-1);
1208 vmctl |= (3<<8);
1209#elif BITS_PER_LONG == 32
1210 ptp_phys_low = info->vm_pgt_phys & (~0UL);
1211 ptp_phys_high = 0;
1212#else
1213# error "Unknown BITS_PER_LONG!"
1214#endif
1215#if PAGE_SIZE == 8192
1216# error "Don't support 8k-page!"
1217#endif
1218 /* Write page table physical address to all PTPAL registers */
1219 for (i = 0; i < 64; i++) {
1220 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1221 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1222 }
1223 /* Enable virtual memory transfer */
1224 hw_write_20kx(hw, VMEM_CTL, vmctl);
1225 /* Enable transport bus master and queueing of request */
1226 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1227 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1228 /* Enable transport ring */
1229 data = hw_read_20kx(hw, TRANSPORT_ENB);
1230 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1231
1232 return 0;
1233}
1234
1235/* Card initialization */
1236#define GCTL_AIE 0x00000001
1237#define GCTL_UAA 0x00000002
1238#define GCTL_DPC 0x00000004
1239#define GCTL_DBP 0x00000008
1240#define GCTL_ABP 0x00000010
1241#define GCTL_TBP 0x00000020
1242#define GCTL_SBP 0x00000040
1243#define GCTL_FBP 0x00000080
1244#define GCTL_ME 0x00000100
1245#define GCTL_AID 0x00001000
1246
1247#define PLLCTL_SRC 0x00000007
1248#define PLLCTL_SPE 0x00000008
1249#define PLLCTL_RD 0x000000F0
1250#define PLLCTL_FD 0x0001FF00
1251#define PLLCTL_OD 0x00060000
1252#define PLLCTL_B 0x00080000
1253#define PLLCTL_AS 0x00100000
1254#define PLLCTL_LF 0x03E00000
1255#define PLLCTL_SPS 0x1C000000
1256#define PLLCTL_AD 0x60000000
1257
1258#define PLLSTAT_CCS 0x00000007
1259#define PLLSTAT_SPL 0x00000008
1260#define PLLSTAT_CRD 0x000000F0
1261#define PLLSTAT_CFD 0x0001FF00
1262#define PLLSTAT_SL 0x00020000
1263#define PLLSTAT_FAS 0x00040000
1264#define PLLSTAT_B 0x00080000
1265#define PLLSTAT_PD 0x00100000
1266#define PLLSTAT_OCA 0x00200000
1267#define PLLSTAT_NCA 0x00400000
1268
1269static int hw_pll_init(struct hw *hw, unsigned int rsr)
1270{
1271 unsigned int pllenb;
1272 unsigned int pllctl;
1273 unsigned int pllstat;
1274 int i;
1275
1276 pllenb = 0xB;
1277 hw_write_20kx(hw, PLL_ENB, pllenb);
1278 pllctl = 0x20D00000;
1279 set_field(&pllctl, PLLCTL_FD, 16 - 4);
1280 hw_write_20kx(hw, PLL_CTL, pllctl);
1281 mdelay(40);
1282 pllctl = hw_read_20kx(hw, PLL_CTL);
1283 set_field(&pllctl, PLLCTL_B, 0);
1284 if (48000 == rsr) {
1285 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1286 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1287 } else { /* 44100 */
1288 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1289 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1290 }
1291 hw_write_20kx(hw, PLL_CTL, pllctl);
1292 mdelay(40);
1293 for (i = 0; i < 1000; i++) {
1294 pllstat = hw_read_20kx(hw, PLL_STAT);
1295 if (get_field(pllstat, PLLSTAT_PD))
1296 continue;
1297
1298 if (get_field(pllstat, PLLSTAT_B) !=
1299 get_field(pllctl, PLLCTL_B))
1300 continue;
1301
1302 if (get_field(pllstat, PLLSTAT_CCS) !=
1303 get_field(pllctl, PLLCTL_SRC))
1304 continue;
1305
1306 if (get_field(pllstat, PLLSTAT_CRD) !=
1307 get_field(pllctl, PLLCTL_RD))
1308 continue;
1309
1310 if (get_field(pllstat, PLLSTAT_CFD) !=
1311 get_field(pllctl, PLLCTL_FD))
1312 continue;
1313
1314 break;
1315 }
1316 if (i >= 1000) {
1317 printk(KERN_ALERT "PLL initialization failed!!!\n");
1318 return -EBUSY;
1319 }
1320
1321 return 0;
1322}
1323
1324static int hw_auto_init(struct hw *hw)
1325{
1326 unsigned int gctl;
1327 int i;
1328
1329 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1330 set_field(&gctl, GCTL_AIE, 0);
1331 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1332 set_field(&gctl, GCTL_AIE, 1);
1333 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1334 mdelay(10);
1335 for (i = 0; i < 400000; i++) {
1336 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1337 if (get_field(gctl, GCTL_AID))
1338 break;
1339 }
1340 if (!get_field(gctl, GCTL_AID)) {
1341 printk(KERN_ALERT "Card Auto-init failed!!!\n");
1342 return -EBUSY;
1343 }
1344
1345 return 0;
1346}
1347
1348/* DAC operations */
1349
1350#define CS4382_MC1 0x1
1351#define CS4382_MC2 0x2
1352#define CS4382_MC3 0x3
1353#define CS4382_FC 0x4
1354#define CS4382_IC 0x5
1355#define CS4382_XC1 0x6
1356#define CS4382_VCA1 0x7
1357#define CS4382_VCB1 0x8
1358#define CS4382_XC2 0x9
1359#define CS4382_VCA2 0xA
1360#define CS4382_VCB2 0xB
1361#define CS4382_XC3 0xC
1362#define CS4382_VCA3 0xD
1363#define CS4382_VCB3 0xE
1364#define CS4382_XC4 0xF
1365#define CS4382_VCA4 0x10
1366#define CS4382_VCB4 0x11
1367#define CS4382_CREV 0x12
1368
1369/* I2C status */
1370#define STATE_LOCKED 0x00
1371#define STATE_UNLOCKED 0xAA
1372#define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1373#define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1374
1375#define I2C_STATUS_DCM 0x00000001
1376#define I2C_STATUS_BC 0x00000006
1377#define I2C_STATUS_APD 0x00000008
1378#define I2C_STATUS_AB 0x00010000
1379#define I2C_STATUS_DR 0x00800000
1380
1381#define I2C_ADDRESS_PTAD 0x0000FFFF
1382#define I2C_ADDRESS_SLAD 0x007F0000
1383
1384struct REGS_CS4382 {
1385 u32 dwModeControl_1;
1386 u32 dwModeControl_2;
1387 u32 dwModeControl_3;
1388
1389 u32 dwFilterControl;
1390 u32 dwInvertControl;
1391
1392 u32 dwMixControl_P1;
1393 u32 dwVolControl_A1;
1394 u32 dwVolControl_B1;
1395
1396 u32 dwMixControl_P2;
1397 u32 dwVolControl_A2;
1398 u32 dwVolControl_B2;
1399
1400 u32 dwMixControl_P3;
1401 u32 dwVolControl_A3;
1402 u32 dwVolControl_B3;
1403
1404 u32 dwMixControl_P4;
1405 u32 dwVolControl_A4;
1406 u32 dwVolControl_B4;
1407};
1408
1409static u8 m_bAddressSize, m_bDataSize, m_bDeviceID;
1410
1411static int I2CUnlockFullAccess(struct hw *hw)
1412{
1413 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1414
1415 /* Send keys for forced BIOS mode */
1416 hw_write_20kx(hw, I2C_IF_WLOCK,
1417 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1418 hw_write_20kx(hw, I2C_IF_WLOCK,
1419 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1420 /* Check whether the chip is unlocked */
1421 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1422 return 0;
1423
1424 return -1;
1425}
1426
1427static int I2CLockChip(struct hw *hw)
1428{
1429 /* Write twice */
1430 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1431 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1432 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1433 return 0;
1434
1435 return -1;
1436}
1437
1438static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize)
1439{
1440 int err = 0;
1441 unsigned int RegI2CStatus;
1442 unsigned int RegI2CAddress;
1443
1444 err = I2CUnlockFullAccess(hw);
1445 if (err < 0)
1446 return err;
1447
1448 m_bAddressSize = bAddressSize;
1449 m_bDataSize = bDataSize;
1450 m_bDeviceID = bDeviceID;
1451
1452 RegI2CAddress = 0;
1453 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID);
1454
1455 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1456
1457 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1458
1459 set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */
1460
1461 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1462
1463 return 0;
1464}
1465
1466static int I2CUninit(struct hw *hw)
1467{
1468 unsigned int RegI2CStatus;
1469 unsigned int RegI2CAddress;
1470
1471 RegI2CAddress = 0;
1472 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1473
1474 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1475
1476 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1477
1478 set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */
1479
1480 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1481
1482 return I2CLockChip(hw);
1483}
1484
1485static int I2CWaitDataReady(struct hw *hw)
1486{
1487 int i = 0x400000;
1488 unsigned int ret = 0;
1489
1490 do {
1491 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1492 } while ((!(ret & DATA_READY)) && --i);
1493
1494 return i;
1495}
1496
1497static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData)
1498{
1499 unsigned int RegI2CStatus;
1500
1501 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1502 set_field(&RegI2CStatus, I2C_STATUS_BC,
1503 (4 == m_bAddressSize) ? 0 : m_bAddressSize);
1504 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1505 if (!I2CWaitDataReady(hw))
1506 return -1;
1507
1508 hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress);
1509 if (!I2CWaitDataReady(hw))
1510 return -1;
1511
1512 /* Force a read operation */
1513 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1514 if (!I2CWaitDataReady(hw))
1515 return -1;
1516
1517 *pdwData = hw_read_20kx(hw, I2C_IF_RDATA);
1518
1519 return 0;
1520}
1521
1522static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
1523{
1524 unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress;
1525 unsigned int RegI2CStatus;
1526
1527 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1528
1529 set_field(&RegI2CStatus, I2C_STATUS_BC,
1530 (4 == (m_bAddressSize + m_bDataSize)) ?
1531 0 : (m_bAddressSize + m_bDataSize));
1532
1533 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1534 I2CWaitDataReady(hw);
1535 /* Dummy write to trigger the write oprtation */
1536 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1537 I2CWaitDataReady(hw);
1538
1539 /* This is the real data */
1540 hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData);
1541 I2CWaitDataReady(hw);
1542
1543 return 0;
1544}
1545
1546static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1547{
1548 int err = 0;
1549 u32 dwData = 0;
1550 int i = 0;
1551 struct REGS_CS4382 cs4382_Read = {0};
1552 struct REGS_CS4382 cs4382_Def = {
1553 0x00000001, /* Mode Control 1 */
1554 0x00000000, /* Mode Control 2 */
1555 0x00000084, /* Mode Control 3 */
1556 0x00000000, /* Filter Control */
1557 0x00000000, /* Invert Control */
1558 0x00000024, /* Mixing Control Pair 1 */
1559 0x00000000, /* Vol Control A1 */
1560 0x00000000, /* Vol Control B1 */
1561 0x00000024, /* Mixing Control Pair 2 */
1562 0x00000000, /* Vol Control A2 */
1563 0x00000000, /* Vol Control B2 */
1564 0x00000024, /* Mixing Control Pair 3 */
1565 0x00000000, /* Vol Control A3 */
1566 0x00000000, /* Vol Control B3 */
1567 0x00000024, /* Mixing Control Pair 4 */
1568 0x00000000, /* Vol Control A4 */
1569 0x00000000 /* Vol Control B4 */
1570 };
1571
1572 /* Set DAC reset bit as output */
1573 dwData = hw_read_20kx(hw, GPIO_CTRL);
1574 dwData |= 0x02;
1575 hw_write_20kx(hw, GPIO_CTRL, dwData);
1576
1577 err = I2CInit(hw, 0x18, 1, 1);
1578 if (err < 0)
1579 goto End;
1580
1581 for (i = 0; i < 2; i++) {
1582 /* Reset DAC twice just in-case the chip
1583 * didn't initialized properly */
1584 dwData = hw_read_20kx(hw, GPIO_DATA);
1585 /* GPIO data bit 1 */
1586 dwData &= 0xFFFFFFFD;
1587 hw_write_20kx(hw, GPIO_DATA, dwData);
1588 mdelay(10);
1589 dwData |= 0x2;
1590 hw_write_20kx(hw, GPIO_DATA, dwData);
1591 mdelay(50);
1592
1593 /* Reset the 2nd time */
1594 dwData &= 0xFFFFFFFD;
1595 hw_write_20kx(hw, GPIO_DATA, dwData);
1596 mdelay(10);
1597 dwData |= 0x2;
1598 hw_write_20kx(hw, GPIO_DATA, dwData);
1599 mdelay(50);
1600
1601 if (I2CRead(hw, CS4382_MC1, &cs4382_Read.dwModeControl_1))
1602 continue;
1603
1604 if (I2CRead(hw, CS4382_MC2, &cs4382_Read.dwModeControl_2))
1605 continue;
1606
1607 if (I2CRead(hw, CS4382_MC3, &cs4382_Read.dwModeControl_3))
1608 continue;
1609
1610 if (I2CRead(hw, CS4382_FC, &cs4382_Read.dwFilterControl))
1611 continue;
1612
1613 if (I2CRead(hw, CS4382_IC, &cs4382_Read.dwInvertControl))
1614 continue;
1615
1616 if (I2CRead(hw, CS4382_XC1, &cs4382_Read.dwMixControl_P1))
1617 continue;
1618
1619 if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1))
1620 continue;
1621
1622 if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1))
1623 continue;
1624
1625 if (I2CRead(hw, CS4382_XC2, &cs4382_Read.dwMixControl_P2))
1626 continue;
1627
1628 if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2))
1629 continue;
1630
1631 if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2))
1632 continue;
1633
1634 if (I2CRead(hw, CS4382_XC3, &cs4382_Read.dwMixControl_P3))
1635 continue;
1636
1637 if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3))
1638 continue;
1639
1640 if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3))
1641 continue;
1642
1643 if (I2CRead(hw, CS4382_XC4, &cs4382_Read.dwMixControl_P4))
1644 continue;
1645
1646 if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4))
1647 continue;
1648
1649 if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4))
1650 continue;
1651
1652 if (memcmp(&cs4382_Read, &cs4382_Def,
1653 sizeof(struct REGS_CS4382)))
1654 continue;
1655 else
1656 break;
1657 }
1658
1659 if (i >= 2)
1660 goto End;
1661
1662 /* Note: Every I2C write must have some delay.
1663 * This is not a requirement but the delay works here... */
1664 I2CWrite(hw, CS4382_MC1, 0x80);
1665 I2CWrite(hw, CS4382_MC2, 0x10);
1666 if (1 == info->msr) {
1667 I2CWrite(hw, CS4382_XC1, 0x24);
1668 I2CWrite(hw, CS4382_XC2, 0x24);
1669 I2CWrite(hw, CS4382_XC3, 0x24);
1670 I2CWrite(hw, CS4382_XC4, 0x24);
1671 } else if (2 == info->msr) {
1672 I2CWrite(hw, CS4382_XC1, 0x25);
1673 I2CWrite(hw, CS4382_XC2, 0x25);
1674 I2CWrite(hw, CS4382_XC3, 0x25);
1675 I2CWrite(hw, CS4382_XC4, 0x25);
1676 } else {
1677 I2CWrite(hw, CS4382_XC1, 0x26);
1678 I2CWrite(hw, CS4382_XC2, 0x26);
1679 I2CWrite(hw, CS4382_XC3, 0x26);
1680 I2CWrite(hw, CS4382_XC4, 0x26);
1681 }
1682
1683 return 0;
1684End:
1685
1686 I2CUninit(hw);
1687 return -1;
1688}
1689
1690/* ADC operations */
1691#define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1692#define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1693
1694#define WM8775_IC 0x0B
1695#define WM8775_MMC 0x0C
1696#define WM8775_AADCL 0x0E
1697#define WM8775_AADCR 0x0F
1698#define WM8775_ADCMC 0x15
1699#define WM8775_RESET 0x17
1700
1701static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1702{
1703 u32 data = 0;
1704
1705 data = hw_read_20kx(hw, GPIO_DATA);
1706 switch (type) {
1707 case ADC_MICIN:
1708 data = (data & (0x1 << 14)) ? 1 : 0;
1709 break;
1710 case ADC_LINEIN:
1711 data = (data & (0x1 << 14)) ? 0 : 1;
1712 break;
1713 default:
1714 data = 0;
1715 }
1716 return data;
1717}
1718
1719static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1720{
1721 u32 data = 0;
1722
1723 data = hw_read_20kx(hw, GPIO_DATA);
1724 switch (type) {
1725 case ADC_MICIN:
1726 data |= (0x1 << 14);
1727 hw_write_20kx(hw, GPIO_DATA, data);
1728 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1729 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1730 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1731 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1732 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1733 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1734 break;
1735 case ADC_LINEIN:
1736 data &= ~(0x1 << 14);
1737 hw_write_20kx(hw, GPIO_DATA, data);
1738 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1739 MAKE_WM8775_DATA(0x102)); /* Line-in */
1740 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1741 MAKE_WM8775_DATA(0xCF)); /* No boost */
1742 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1743 MAKE_WM8775_DATA(0xCF)); /* No boost */
1744 break;
1745 default:
1746 break;
1747 }
1748
1749 return 0;
1750}
1751
1752static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1753{
1754 int err = 0;
1755 u32 dwMux = 2, dwData = 0, dwCtl = 0;
1756
1757 /* Set ADC reset bit as output */
1758 dwData = hw_read_20kx(hw, GPIO_CTRL);
1759 dwData |= (0x1 << 15);
1760 hw_write_20kx(hw, GPIO_CTRL, dwData);
1761
1762 /* Initialize I2C */
1763 err = I2CInit(hw, 0x1A, 1, 1);
1764 if (err < 0) {
1765 printk(KERN_ALERT "Failure to acquire I2C!!!\n");
1766 goto error;
1767 }
1768
1769 /* Make ADC in normal operation */
1770 dwData = hw_read_20kx(hw, GPIO_DATA);
1771 dwData &= ~(0x1 << 15);
1772 mdelay(10);
1773 dwData |= (0x1 << 15);
1774 hw_write_20kx(hw, GPIO_DATA, dwData);
1775 mdelay(50);
1776
1777 /* Set the master mode (256fs) */
1778 if (1 == info->msr) {
1779 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1780 MAKE_WM8775_DATA(0x02));
1781 } else if (2 == info->msr) {
1782 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1783 MAKE_WM8775_DATA(0x0A));
1784 } else {
1785 printk(KERN_ALERT "Invalid master sampling "
1786 "rate (msr %d)!!!\n", info->msr);
1787 err = -EINVAL;
1788 goto error;
1789 }
1790
1791 /* Configure GPIO bit 14 change to line-in/mic-in */
1792 dwCtl = hw_read_20kx(hw, GPIO_CTRL);
1793 dwCtl |= 0x1<<14;
1794 hw_write_20kx(hw, GPIO_CTRL, dwCtl);
1795
1796 /* Check using Mic-in or Line-in */
1797 dwData = hw_read_20kx(hw, GPIO_DATA);
1798
1799 if (dwMux == 1) {
1800 /* Configures GPIO data to select Mic-in */
1801 dwData |= 0x1<<14;
1802 hw_write_20kx(hw, GPIO_DATA, dwData);
1803
1804 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1805 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1806 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1807 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1808 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1809 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1810 } else if (dwMux == 2) {
1811 /* Configures GPIO data to select Line-in */
1812 dwData &= ~(0x1<<14);
1813 hw_write_20kx(hw, GPIO_DATA, dwData);
1814
1815 /* Setup ADC */
1816 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1817 MAKE_WM8775_DATA(0x102)); /* Line-in */
1818 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1819 MAKE_WM8775_DATA(0xCF)); /* No boost */
1820 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1821 MAKE_WM8775_DATA(0xCF)); /* No boost */
1822 } else {
1823 printk(KERN_ALERT "ERROR!!! Invalid input mux!!!\n");
1824 err = -EINVAL;
1825 goto error;
1826 }
1827
1828 return 0;
1829
1830error:
1831 I2CUninit(hw);
1832 return err;
1833}
1834
1835static int hw_have_digit_io_switch(struct hw *hw)
1836{
1837 return 0;
1838}
1839
1840static int hw_card_start(struct hw *hw)
1841{
1842 int err = 0;
1843 struct pci_dev *pci = hw->pci;
1844 unsigned int gctl;
1845 unsigned int dma_mask = 0;
1846
1847 err = pci_enable_device(pci);
1848 if (err < 0)
1849 return err;
1850
1851 /* Set DMA transfer mask */
1852 dma_mask = CT_XFI_DMA_MASK;
1853 if (pci_set_dma_mask(pci, dma_mask) < 0 ||
1854 pci_set_consistent_dma_mask(pci, dma_mask) < 0) {
1855 printk(KERN_ERR "architecture does not support PCI "
1856 "busmaster DMA with mask 0x%x\n", dma_mask);
1857 err = -ENXIO;
1858 goto error1;
1859 }
1860
1861 err = pci_request_regions(pci, "XFi");
1862 if (err < 0)
1863 goto error1;
1864
1865 hw->io_base = pci_resource_start(hw->pci, 2);
1866 hw->mem_base = (unsigned long)ioremap(hw->io_base,
1867 pci_resource_len(hw->pci, 2));
1868 if (NULL == (void *)hw->mem_base) {
1869 err = -ENOENT;
1870 goto error2;
1871 }
1872
1873 /* Switch to 20k2 mode from UAA mode. */
1874 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1875 set_field(&gctl, GCTL_UAA, 0);
1876 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1877
1878 /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1879 atc->chip_details->nm_card, hw))) {
1880 goto error3;
1881 }
1882 hw->irq = pci->irq;
1883 */
1884
1885 pci_set_master(pci);
1886
1887 return 0;
1888
1889/*error3:
1890 iounmap((void *)hw->mem_base);
1891 hw->mem_base = (unsigned long)NULL;*/
1892error2:
1893 pci_release_regions(pci);
1894 hw->io_base = 0;
1895error1:
1896 pci_disable_device(pci);
1897 return err;
1898}
1899
1900static int hw_card_stop(struct hw *hw)
1901{
1902 /* TODO: Disable interrupt and so on... */
1903 return 0;
1904}
1905
1906static int hw_card_shutdown(struct hw *hw)
1907{
1908 if (hw->irq >= 0)
1909 free_irq(hw->irq, hw);
1910
1911 hw->irq = -1;
1912
1913 if (NULL != ((void *)hw->mem_base))
1914 iounmap((void *)hw->mem_base);
1915
1916 hw->mem_base = (unsigned long)NULL;
1917
1918 if (hw->io_base)
1919 pci_release_regions(hw->pci);
1920
1921 hw->io_base = 0;
1922
1923 pci_disable_device(hw->pci);
1924
1925 return 0;
1926}
1927
1928static int hw_card_init(struct hw *hw, struct card_conf *info)
1929{
1930 int err;
1931 unsigned int gctl;
1932 u32 data = 0;
1933 struct dac_conf dac_info = {0};
1934 struct adc_conf adc_info = {0};
1935 struct daio_conf daio_info = {0};
1936 struct trn_conf trn_info = {0};
1937
1938 /* Get PCI io port/memory base address and
1939 * do 20kx core switch if needed. */
1940 if (!hw->io_base) {
1941 err = hw_card_start(hw);
1942 if (err)
1943 return err;
1944 }
1945
1946 /* PLL init */
1947 err = hw_pll_init(hw, info->rsr);
1948 if (err < 0)
1949 return err;
1950
1951 /* kick off auto-init */
1952 err = hw_auto_init(hw);
1953 if (err < 0)
1954 return err;
1955
1956 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1957 set_field(&gctl, GCTL_DBP, 1);
1958 set_field(&gctl, GCTL_TBP, 1);
1959 set_field(&gctl, GCTL_FBP, 1);
1960 set_field(&gctl, GCTL_DPC, 0);
1961 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1962
1963 /* Reset all global pending interrupts */
1964 hw_write_20kx(hw, INTERRUPT_GIE, 0);
1965 /* Reset all SRC pending interrupts */
1966 hw_write_20kx(hw, SRC_IP, 0);
1967
1968 /* TODO: detect the card ID and configure GPIO accordingly. */
1969 /* Configures GPIO (0xD802 0x98028) */
1970 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1971 /* Configures GPIO (SB0880) */
1972 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1973 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1974
1975 /* Enable audio ring */
1976 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1977
1978 trn_info.vm_pgt_phys = info->vm_pgt_phys;
1979 err = hw_trn_init(hw, &trn_info);
1980 if (err < 0)
1981 return err;
1982
1983 daio_info.msr = info->msr;
1984 err = hw_daio_init(hw, &daio_info);
1985 if (err < 0)
1986 return err;
1987
1988 dac_info.msr = info->msr;
1989 err = hw_dac_init(hw, &dac_info);
1990 if (err < 0)
1991 return err;
1992
1993 adc_info.msr = info->msr;
1994 adc_info.input = ADC_LINEIN;
1995 adc_info.mic20db = 0;
1996 err = hw_adc_init(hw, &adc_info);
1997 if (err < 0)
1998 return err;
1999
2000 data = hw_read_20kx(hw, SRC_MCTL);
2001 data |= 0x1; /* Enables input from the audio ring */
2002 hw_write_20kx(hw, SRC_MCTL, data);
2003
2004 return 0;
2005}
2006
2007static u32 hw_read_20kx(struct hw *hw, u32 reg)
2008{
2009 return readl((void *)(hw->mem_base + reg));
2010}
2011
2012static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2013{
2014 writel(data, (void *)(hw->mem_base + reg));
2015}
2016
2017int create_20k2_hw_obj(struct hw **rhw)
2018{
2019 struct hw *hw;
2020
2021 *rhw = NULL;
2022 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
2023 if (NULL == hw)
2024 return -ENOMEM;
2025
2026 hw->io_base = 0;
2027 hw->mem_base = (unsigned long)NULL;
2028 hw->irq = -1;
2029
2030 hw->card_init = hw_card_init;
2031 hw->card_stop = hw_card_stop;
2032 hw->pll_init = hw_pll_init;
2033 hw->is_adc_source_selected = hw_is_adc_input_selected;
2034 hw->select_adc_source = hw_adc_input_select;
2035 hw->have_digit_io_switch = hw_have_digit_io_switch;
2036
2037 hw->src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk;
2038 hw->src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk;
2039 hw->src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk;
2040 hw->src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk;
2041 hw->src_set_state = src_set_state;
2042 hw->src_set_bm = src_set_bm;
2043 hw->src_set_rsr = src_set_rsr;
2044 hw->src_set_sf = src_set_sf;
2045 hw->src_set_wr = src_set_wr;
2046 hw->src_set_pm = src_set_pm;
2047 hw->src_set_rom = src_set_rom;
2048 hw->src_set_vo = src_set_vo;
2049 hw->src_set_st = src_set_st;
2050 hw->src_set_ie = src_set_ie;
2051 hw->src_set_ilsz = src_set_ilsz;
2052 hw->src_set_bp = src_set_bp;
2053 hw->src_set_cisz = src_set_cisz;
2054 hw->src_set_ca = src_set_ca;
2055 hw->src_set_sa = src_set_sa;
2056 hw->src_set_la = src_set_la;
2057 hw->src_set_pitch = src_set_pitch;
2058 hw->src_set_dirty = src_set_dirty;
2059 hw->src_set_clear_zbufs = src_set_clear_zbufs;
2060 hw->src_set_dirty_all = src_set_dirty_all;
2061 hw->src_commit_write = src_commit_write;
2062 hw->src_get_ca = src_get_ca;
2063 hw->src_get_dirty = src_get_dirty;
2064 hw->src_dirty_conj_mask = src_dirty_conj_mask;
2065 hw->src_mgr_enbs_src = src_mgr_enbs_src;
2066 hw->src_mgr_enb_src = src_mgr_enb_src;
2067 hw->src_mgr_dsb_src = src_mgr_dsb_src;
2068 hw->src_mgr_commit_write = src_mgr_commit_write;
2069
2070 hw->srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk;
2071 hw->srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk;
2072 hw->srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc;
2073 hw->srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser;
2074 hw->srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt;
2075 hw->srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr;
2076 hw->srcimp_mgr_commit_write = srcimp_mgr_commit_write;
2077
2078 hw->amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk;
2079 hw->amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk;
2080 hw->amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk;
2081 hw->amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk;
2082 hw->amixer_set_mode = amixer_set_mode;
2083 hw->amixer_set_iv = amixer_set_iv;
2084 hw->amixer_set_x = amixer_set_x;
2085 hw->amixer_set_y = amixer_set_y;
2086 hw->amixer_set_sadr = amixer_set_sadr;
2087 hw->amixer_set_se = amixer_set_se;
2088 hw->amixer_set_dirty = amixer_set_dirty;
2089 hw->amixer_set_dirty_all = amixer_set_dirty_all;
2090 hw->amixer_commit_write = amixer_commit_write;
2091 hw->amixer_get_y = amixer_get_y;
2092 hw->amixer_get_dirty = amixer_get_dirty;
2093
2094 hw->dai_get_ctrl_blk = dai_get_ctrl_blk;
2095 hw->dai_put_ctrl_blk = dai_put_ctrl_blk;
2096 hw->dai_srt_set_srco = dai_srt_set_srco;
2097 hw->dai_srt_set_srcm = dai_srt_set_srcm;
2098 hw->dai_srt_set_rsr = dai_srt_set_rsr;
2099 hw->dai_srt_set_drat = dai_srt_set_drat;
2100 hw->dai_srt_set_ec = dai_srt_set_ec;
2101 hw->dai_srt_set_et = dai_srt_set_et;
2102 hw->dai_commit_write = dai_commit_write;
2103
2104 hw->dao_get_ctrl_blk = dao_get_ctrl_blk;
2105 hw->dao_put_ctrl_blk = dao_put_ctrl_blk;
2106 hw->dao_set_spos = dao_set_spos;
2107 hw->dao_commit_write = dao_commit_write;
2108 hw->dao_get_spos = dao_get_spos;
2109
2110 hw->daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk;
2111 hw->daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk;
2112 hw->daio_mgr_enb_dai = daio_mgr_enb_dai;
2113 hw->daio_mgr_dsb_dai = daio_mgr_dsb_dai;
2114 hw->daio_mgr_enb_dao = daio_mgr_enb_dao;
2115 hw->daio_mgr_dsb_dao = daio_mgr_dsb_dao;
2116 hw->daio_mgr_dao_init = daio_mgr_dao_init;
2117 hw->daio_mgr_set_imaparc = daio_mgr_set_imaparc;
2118 hw->daio_mgr_set_imapnxt = daio_mgr_set_imapnxt;
2119 hw->daio_mgr_set_imapaddr = daio_mgr_set_imapaddr;
2120 hw->daio_mgr_commit_write = daio_mgr_commit_write;
2121
2122 *rhw = hw;
2123
2124 return 0;
2125}
2126
2127int destroy_20k2_hw_obj(struct hw *hw)
2128{
2129 if (hw->io_base)
2130 hw_card_shutdown(hw);
2131
2132 kfree(hw);
2133 return 0;
2134}
Linux kernel - Deliverables
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