ALSA: usb-audio: UAC2: support read-only freq control
[deliverable/linux.git] / sound / pci / hda / hda_codec.h
CommitLineData
1da177e4
LT
1/*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59
18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef __SOUND_HDA_CODEC_H
22#define __SOUND_HDA_CODEC_H
23
24#include <sound/info.h>
25#include <sound/control.h>
26#include <sound/pcm.h>
2807314d 27#include <sound/hwdep.h>
1da177e4
LT
28
29/*
30 * nodes
31 */
32#define AC_NODE_ROOT 0x00
33
34/*
35 * function group types
36 */
37enum {
38 AC_GRP_AUDIO_FUNCTION = 0x01,
39 AC_GRP_MODEM_FUNCTION = 0x02,
40};
41
42/*
43 * widget types
44 */
45enum {
46 AC_WID_AUD_OUT, /* Audio Out */
47 AC_WID_AUD_IN, /* Audio In */
48 AC_WID_AUD_MIX, /* Audio Mixer */
49 AC_WID_AUD_SEL, /* Audio Selector */
50 AC_WID_PIN, /* Pin Complex */
51 AC_WID_POWER, /* Power */
52 AC_WID_VOL_KNB, /* Volume Knob */
53 AC_WID_BEEP, /* Beep Generator */
54 AC_WID_VENDOR = 0x0f /* Vendor specific */
55};
56
57/*
58 * GET verbs
59 */
60#define AC_VERB_GET_STREAM_FORMAT 0x0a00
61#define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
62#define AC_VERB_GET_PROC_COEF 0x0c00
63#define AC_VERB_GET_COEF_INDEX 0x0d00
64#define AC_VERB_PARAMETERS 0x0f00
65#define AC_VERB_GET_CONNECT_SEL 0x0f01
66#define AC_VERB_GET_CONNECT_LIST 0x0f02
67#define AC_VERB_GET_PROC_STATE 0x0f03
68#define AC_VERB_GET_SDI_SELECT 0x0f04
69#define AC_VERB_GET_POWER_STATE 0x0f05
70#define AC_VERB_GET_CONV 0x0f06
71#define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07
72#define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08
73#define AC_VERB_GET_PIN_SENSE 0x0f09
74#define AC_VERB_GET_BEEP_CONTROL 0x0f0a
75#define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c
3982d17e 76#define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d
a1855d80 77#define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */
1da177e4
LT
78#define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f
79/* f10-f1a: GPIO */
16ded525
TI
80#define AC_VERB_GET_GPIO_DATA 0x0f15
81#define AC_VERB_GET_GPIO_MASK 0x0f16
82#define AC_VERB_GET_GPIO_DIRECTION 0x0f17
797760ab 83#define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18
3982d17e 84#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19
797760ab 85#define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a
1da177e4 86#define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c
86284e45
TI
87/* f20: AFG/MFG */
88#define AC_VERB_GET_SUBSYSTEM_ID 0x0f20
955d2488
TI
89#define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d
90#define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e
91#define AC_VERB_GET_HDMI_ELDD 0x0f2f
92#define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30
93#define AC_VERB_GET_HDMI_DIP_DATA 0x0f31
94#define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32
95#define AC_VERB_GET_HDMI_CP_CTRL 0x0f33
96#define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34
1da177e4
LT
97
98/*
99 * SET verbs
100 */
101#define AC_VERB_SET_STREAM_FORMAT 0x200
102#define AC_VERB_SET_AMP_GAIN_MUTE 0x300
103#define AC_VERB_SET_PROC_COEF 0x400
104#define AC_VERB_SET_COEF_INDEX 0x500
105#define AC_VERB_SET_CONNECT_SEL 0x701
106#define AC_VERB_SET_PROC_STATE 0x703
107#define AC_VERB_SET_SDI_SELECT 0x704
108#define AC_VERB_SET_POWER_STATE 0x705
109#define AC_VERB_SET_CHANNEL_STREAMID 0x706
110#define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707
111#define AC_VERB_SET_UNSOLICITED_ENABLE 0x708
112#define AC_VERB_SET_PIN_SENSE 0x709
113#define AC_VERB_SET_BEEP_CONTROL 0x70a
a2a20939 114#define AC_VERB_SET_EAPD_BTLENABLE 0x70c
1da177e4
LT
115#define AC_VERB_SET_DIGI_CONVERT_1 0x70d
116#define AC_VERB_SET_DIGI_CONVERT_2 0x70e
117#define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f
16ded525
TI
118#define AC_VERB_SET_GPIO_DATA 0x715
119#define AC_VERB_SET_GPIO_MASK 0x716
120#define AC_VERB_SET_GPIO_DIRECTION 0x717
797760ab 121#define AC_VERB_SET_GPIO_WAKE_MASK 0x718
3982d17e 122#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719
797760ab 123#define AC_VERB_SET_GPIO_STICKY_MASK 0x71a
1da177e4
LT
124#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c
125#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d
126#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e
127#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f
d0513fc6 128#define AC_VERB_SET_EAPD 0x788
1da177e4 129#define AC_VERB_SET_CODEC_RESET 0x7ff
955d2488
TI
130#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d
131#define AC_VERB_SET_HDMI_DIP_INDEX 0x730
132#define AC_VERB_SET_HDMI_DIP_DATA 0x731
133#define AC_VERB_SET_HDMI_DIP_XMIT 0x732
134#define AC_VERB_SET_HDMI_CP_CTRL 0x733
135#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734
1da177e4
LT
136
137/*
138 * Parameter IDs
139 */
140#define AC_PAR_VENDOR_ID 0x00
141#define AC_PAR_SUBSYSTEM_ID 0x01
142#define AC_PAR_REV_ID 0x02
143#define AC_PAR_NODE_COUNT 0x04
144#define AC_PAR_FUNCTION_TYPE 0x05
145#define AC_PAR_AUDIO_FG_CAP 0x08
146#define AC_PAR_AUDIO_WIDGET_CAP 0x09
147#define AC_PAR_PCM 0x0a
148#define AC_PAR_STREAM 0x0b
149#define AC_PAR_PIN_CAP 0x0c
150#define AC_PAR_AMP_IN_CAP 0x0d
151#define AC_PAR_CONNLIST_LEN 0x0e
152#define AC_PAR_POWER_STATE 0x0f
153#define AC_PAR_PROC_CAP 0x10
154#define AC_PAR_GPIO_CAP 0x11
155#define AC_PAR_AMP_OUT_CAP 0x12
e1716139 156#define AC_PAR_VOL_KNB_CAP 0x13
955d2488 157#define AC_PAR_HDMI_LPCM_CAP 0x20
1da177e4
LT
158
159/*
160 * AC_VERB_PARAMETERS results (32bit)
161 */
162
163/* Function Group Type */
164#define AC_FGT_TYPE (0xff<<0)
165#define AC_FGT_TYPE_SHIFT 0
166#define AC_FGT_UNSOL_CAP (1<<8)
167
168/* Audio Function Group Capabilities */
169#define AC_AFG_OUT_DELAY (0xf<<0)
170#define AC_AFG_IN_DELAY (0xf<<8)
171#define AC_AFG_BEEP_GEN (1<<16)
172
173/* Audio Widget Capabilities */
174#define AC_WCAP_STEREO (1<<0) /* stereo I/O */
175#define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
176#define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
177#define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
178#define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */
179#define AC_WCAP_STRIPE (1<<5) /* stripe */
180#define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */
181#define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */
182#define AC_WCAP_CONN_LIST (1<<8) /* connection list */
183#define AC_WCAP_DIGITAL (1<<9) /* digital I/O */
184#define AC_WCAP_POWER (1<<10) /* power control */
185#define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */
955d2488
TI
186#define AC_WCAP_CP_CAPS (1<<12) /* content protection */
187#define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */
1da177e4
LT
188#define AC_WCAP_DELAY (0xf<<16)
189#define AC_WCAP_DELAY_SHIFT 16
190#define AC_WCAP_TYPE (0xf<<20)
191#define AC_WCAP_TYPE_SHIFT 20
192
193/* supported PCM rates and bits */
194#define AC_SUPPCM_RATES (0xfff << 0)
195#define AC_SUPPCM_BITS_8 (1<<16)
196#define AC_SUPPCM_BITS_16 (1<<17)
197#define AC_SUPPCM_BITS_20 (1<<18)
198#define AC_SUPPCM_BITS_24 (1<<19)
199#define AC_SUPPCM_BITS_32 (1<<20)
200
201/* supported PCM stream format */
202#define AC_SUPFMT_PCM (1<<0)
203#define AC_SUPFMT_FLOAT32 (1<<1)
204#define AC_SUPFMT_AC3 (1<<2)
205
797760ab
AP
206/* GP I/O count */
207#define AC_GPIO_IO_COUNT (0xff<<0)
208#define AC_GPIO_O_COUNT (0xff<<8)
209#define AC_GPIO_O_COUNT_SHIFT 8
210#define AC_GPIO_I_COUNT (0xff<<16)
211#define AC_GPIO_I_COUNT_SHIFT 16
212#define AC_GPIO_UNSOLICITED (1<<30)
213#define AC_GPIO_WAKE (1<<31)
214
215/* Converter stream, channel */
216#define AC_CONV_CHANNEL (0xf<<0)
217#define AC_CONV_STREAM (0xf<<4)
218#define AC_CONV_STREAM_SHIFT 4
219
220/* Input converter SDI select */
221#define AC_SDI_SELECT (0xf<<0)
222
92f10b3f
TI
223/* stream format id */
224#define AC_FMT_CHAN_SHIFT 0
225#define AC_FMT_CHAN_MASK (0x0f << 0)
226#define AC_FMT_BITS_SHIFT 4
227#define AC_FMT_BITS_MASK (7 << 4)
228#define AC_FMT_BITS_8 (0 << 4)
229#define AC_FMT_BITS_16 (1 << 4)
230#define AC_FMT_BITS_20 (2 << 4)
231#define AC_FMT_BITS_24 (3 << 4)
232#define AC_FMT_BITS_32 (4 << 4)
233#define AC_FMT_DIV_SHIFT 8
234#define AC_FMT_DIV_MASK (7 << 8)
235#define AC_FMT_MULT_SHIFT 11
236#define AC_FMT_MULT_MASK (7 << 11)
237#define AC_FMT_BASE_SHIFT 14
238#define AC_FMT_BASE_48K (0 << 14)
239#define AC_FMT_BASE_44K (1 << 14)
240#define AC_FMT_TYPE_SHIFT 15
241#define AC_FMT_TYPE_PCM (0 << 15)
242#define AC_FMT_TYPE_NON_PCM (1 << 15)
243
955d2488 244/* Unsolicited response control */
797760ab
AP
245#define AC_UNSOL_TAG (0x3f<<0)
246#define AC_UNSOL_ENABLED (1<<7)
955d2488
TI
247#define AC_USRSP_EN AC_UNSOL_ENABLED
248
249/* Unsolicited responses */
250#define AC_UNSOL_RES_TAG (0x3f<<26)
251#define AC_UNSOL_RES_TAG_SHIFT 26
252#define AC_UNSOL_RES_SUBTAG (0x1f<<21)
253#define AC_UNSOL_RES_SUBTAG_SHIFT 21
254#define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
255#define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */
256#define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */
257#define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */
797760ab 258
1da177e4
LT
259/* Pin widget capabilies */
260#define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
261#define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */
262#define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */
263#define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */
264#define AC_PINCAP_OUT (1<<4) /* output capable */
265#define AC_PINCAP_IN (1<<5) /* input capable */
266#define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */
3982d17e
AP
267/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,
268 * but is marked reserved in the Intel HDA specification.
269 */
270#define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */
955d2488
TI
271/* Note: The same bit as LR_SWAP is newly defined as HDMI capability
272 * in HD-audio specification
273 */
274#define AC_PINCAP_HDMI (1<<7) /* HDMI pin */
728765b3
WF
275#define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can
276 * coexist with AC_PINCAP_HDMI
277 */
1a12de1e 278#define AC_PINCAP_VREF (0x37<<8)
1da177e4
LT
279#define AC_PINCAP_VREF_SHIFT 8
280#define AC_PINCAP_EAPD (1<<16) /* EAPD capable */
b923528e 281#define AC_PINCAP_HBR (1<<27) /* High Bit Rate */
1a12de1e
M
282/* Vref status (used in pin cap) */
283#define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
284#define AC_PINCAP_VREF_50 (1<<1) /* 50% */
285#define AC_PINCAP_VREF_GRD (1<<2) /* ground */
286#define AC_PINCAP_VREF_80 (1<<4) /* 80% */
287#define AC_PINCAP_VREF_100 (1<<5) /* 100% */
1da177e4
LT
288
289/* Amplifier capabilities */
290#define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */
291#define AC_AMPCAP_OFFSET_SHIFT 0
292#define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */
293#define AC_AMPCAP_NUM_STEPS_SHIFT 8
d01ce99f
TI
294#define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB
295 * in 0.25dB
296 */
1da177e4
LT
297#define AC_AMPCAP_STEP_SIZE_SHIFT 16
298#define AC_AMPCAP_MUTE (1<<31) /* mute capable */
299#define AC_AMPCAP_MUTE_SHIFT 31
300
3868137e
TI
301/* driver-specific amp-caps: using bits 24-30 */
302#define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */
303
1da177e4
LT
304/* Connection list */
305#define AC_CLIST_LENGTH (0x7f<<0)
306#define AC_CLIST_LONG (1<<7)
307
308/* Supported power status */
309#define AC_PWRST_D0SUP (1<<0)
310#define AC_PWRST_D1SUP (1<<1)
311#define AC_PWRST_D2SUP (1<<2)
312#define AC_PWRST_D3SUP (1<<3)
83d605fd
WF
313#define AC_PWRST_D3COLDSUP (1<<4)
314#define AC_PWRST_S3D3COLDSUP (1<<29)
315#define AC_PWRST_CLKSTOP (1<<30)
316#define AC_PWRST_EPSS (1U<<31)
1da177e4 317
54d17403 318/* Power state values */
797760ab
AP
319#define AC_PWRST_SETTING (0xf<<0)
320#define AC_PWRST_ACTUAL (0xf<<4)
321#define AC_PWRST_ACTUAL_SHIFT 4
54d17403
TI
322#define AC_PWRST_D0 0x00
323#define AC_PWRST_D1 0x01
324#define AC_PWRST_D2 0x02
325#define AC_PWRST_D3 0x03
ce63f3ba
WX
326#define AC_PWRST_ERROR (1<<8)
327#define AC_PWRST_CLK_STOP_OK (1<<9)
328#define AC_PWRST_SETTING_RESET (1<<10)
54d17403 329
1da177e4
LT
330/* Processing capabilies */
331#define AC_PCAP_BENIGN (1<<0)
332#define AC_PCAP_NUM_COEF (0xff<<8)
797760ab 333#define AC_PCAP_NUM_COEF_SHIFT 8
1da177e4
LT
334
335/* Volume knobs capabilities */
336#define AC_KNBCAP_NUM_STEPS (0x7f<<0)
38fcaf8e 337#define AC_KNBCAP_DELTA (1<<7)
1da177e4 338
955d2488
TI
339/* HDMI LPCM capabilities */
340#define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
341#define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
342#define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */
343#define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */
344#define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
345#define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
346#define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */
347#define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */
348#define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
349#define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
350#define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */
351#define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */
352#define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */
353#define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */
354
1da177e4
LT
355/*
356 * Control Parameters
357 */
358
359/* Amp gain/mute */
d427c77e 360#define AC_AMP_MUTE (1<<7)
1da177e4
LT
361#define AC_AMP_GAIN (0x7f)
362#define AC_AMP_GET_INDEX (0xf<<0)
363
364#define AC_AMP_GET_LEFT (1<<13)
365#define AC_AMP_GET_RIGHT (0<<13)
366#define AC_AMP_GET_OUTPUT (1<<15)
367#define AC_AMP_GET_INPUT (0<<15)
368
369#define AC_AMP_SET_INDEX (0xf<<8)
370#define AC_AMP_SET_INDEX_SHIFT 8
371#define AC_AMP_SET_RIGHT (1<<12)
372#define AC_AMP_SET_LEFT (1<<13)
373#define AC_AMP_SET_INPUT (1<<14)
374#define AC_AMP_SET_OUTPUT (1<<15)
375
376/* DIGITAL1 bits */
377#define AC_DIG1_ENABLE (1<<0)
378#define AC_DIG1_V (1<<1)
379#define AC_DIG1_VCFG (1<<2)
380#define AC_DIG1_EMPHASIS (1<<3)
381#define AC_DIG1_COPYRIGHT (1<<4)
382#define AC_DIG1_NONAUDIO (1<<5)
383#define AC_DIG1_PROFESSIONAL (1<<6)
384#define AC_DIG1_LEVEL (1<<7)
385
797760ab
AP
386/* DIGITAL2 bits */
387#define AC_DIG2_CC (0x7f<<0)
388
61525979
WX
389/* DIGITAL3 bits */
390#define AC_DIG3_ICT (0xf<<0)
391#define AC_DIG3_KAE (1<<7)
392
1da177e4 393/* Pin widget control - 8bit */
ea87d1c4
AH
394#define AC_PINCTL_EPT (0x3<<0)
395#define AC_PINCTL_EPT_NATIVE 0
396#define AC_PINCTL_EPT_HBR 3
1da177e4 397#define AC_PINCTL_VREFEN (0x7<<0)
98f759a6
TI
398#define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */
399#define AC_PINCTL_VREF_50 1 /* 50% */
400#define AC_PINCTL_VREF_GRD 2 /* ground */
401#define AC_PINCTL_VREF_80 4 /* 80% */
402#define AC_PINCTL_VREF_100 5 /* 100% */
1da177e4
LT
403#define AC_PINCTL_IN_EN (1<<5)
404#define AC_PINCTL_OUT_EN (1<<6)
405#define AC_PINCTL_HP_EN (1<<7)
406
797760ab
AP
407/* Pin sense - 32bit */
408#define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff)
409#define AC_PINSENSE_PRESENCE (1<<31)
955d2488 410#define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */
797760ab
AP
411
412/* EAPD/BTL enable - 32bit */
413#define AC_EAPDBTL_BALANCED (1<<0)
414#define AC_EAPDBTL_EAPD (1<<1)
415#define AC_EAPDBTL_LR_SWAP (1<<2)
416
955d2488
TI
417/* HDMI ELD data */
418#define AC_ELDD_ELD_VALID (1<<31)
419#define AC_ELDD_ELD_DATA 0xff
420
421/* HDMI DIP size */
422#define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */
423#define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */
424
425/* HDMI DIP index */
426#define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */
427#define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */
428
429/* HDMI DIP xmit (transmit) control */
430#define AC_DIPXMIT_MASK (0x3<<6)
431#define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */
432#define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */
433#define AC_DIPXMIT_BEST (0x3<<6) /* best effort */
434
435/* HDMI content protection (CP) control */
436#define AC_CPCTRL_CES (1<<9) /* current encryption state */
437#define AC_CPCTRL_READY (1<<8) /* ready bit */
438#define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */
439#define AC_CPCTRL_STATE (3<<0) /* current CP request state */
440
441/* Converter channel <-> HDMI slot mapping */
442#define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */
443#define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */
444
1da177e4
LT
445/* configuration default - 32bit */
446#define AC_DEFCFG_SEQUENCE (0xf<<0)
447#define AC_DEFCFG_DEF_ASSOC (0xf<<4)
d21b37ea 448#define AC_DEFCFG_ASSOC_SHIFT 4
1da177e4 449#define AC_DEFCFG_MISC (0xf<<8)
d21b37ea 450#define AC_DEFCFG_MISC_SHIFT 8
797760ab 451#define AC_DEFCFG_MISC_NO_PRESENCE (1<<0)
1da177e4
LT
452#define AC_DEFCFG_COLOR (0xf<<12)
453#define AC_DEFCFG_COLOR_SHIFT 12
454#define AC_DEFCFG_CONN_TYPE (0xf<<16)
455#define AC_DEFCFG_CONN_TYPE_SHIFT 16
456#define AC_DEFCFG_DEVICE (0xf<<20)
457#define AC_DEFCFG_DEVICE_SHIFT 20
458#define AC_DEFCFG_LOCATION (0x3f<<24)
459#define AC_DEFCFG_LOCATION_SHIFT 24
460#define AC_DEFCFG_PORT_CONN (0x3<<30)
461#define AC_DEFCFG_PORT_CONN_SHIFT 30
462
463/* device device types (0x0-0xf) */
464enum {
465 AC_JACK_LINE_OUT,
466 AC_JACK_SPEAKER,
467 AC_JACK_HP_OUT,
468 AC_JACK_CD,
469 AC_JACK_SPDIF_OUT,
470 AC_JACK_DIG_OTHER_OUT,
471 AC_JACK_MODEM_LINE_SIDE,
472 AC_JACK_MODEM_HAND_SIDE,
473 AC_JACK_LINE_IN,
474 AC_JACK_AUX,
475 AC_JACK_MIC_IN,
476 AC_JACK_TELEPHONY,
477 AC_JACK_SPDIF_IN,
478 AC_JACK_DIG_OTHER_IN,
479 AC_JACK_OTHER = 0xf,
480};
481
482/* jack connection types (0x0-0xf) */
483enum {
484 AC_JACK_CONN_UNKNOWN,
485 AC_JACK_CONN_1_8,
486 AC_JACK_CONN_1_4,
487 AC_JACK_CONN_ATAPI,
488 AC_JACK_CONN_RCA,
489 AC_JACK_CONN_OPTICAL,
490 AC_JACK_CONN_OTHER_DIGITAL,
491 AC_JACK_CONN_OTHER_ANALOG,
492 AC_JACK_CONN_DIN,
493 AC_JACK_CONN_XLR,
494 AC_JACK_CONN_RJ11,
495 AC_JACK_CONN_COMB,
496 AC_JACK_CONN_OTHER = 0xf,
497};
498
499/* jack colors (0x0-0xf) */
500enum {
501 AC_JACK_COLOR_UNKNOWN,
502 AC_JACK_COLOR_BLACK,
503 AC_JACK_COLOR_GREY,
504 AC_JACK_COLOR_BLUE,
505 AC_JACK_COLOR_GREEN,
506 AC_JACK_COLOR_RED,
507 AC_JACK_COLOR_ORANGE,
508 AC_JACK_COLOR_YELLOW,
509 AC_JACK_COLOR_PURPLE,
510 AC_JACK_COLOR_PINK,
511 AC_JACK_COLOR_WHITE = 0xe,
512 AC_JACK_COLOR_OTHER,
513};
514
515/* Jack location (0x0-0x3f) */
516/* common case */
517enum {
518 AC_JACK_LOC_NONE,
519 AC_JACK_LOC_REAR,
520 AC_JACK_LOC_FRONT,
521 AC_JACK_LOC_LEFT,
522 AC_JACK_LOC_RIGHT,
523 AC_JACK_LOC_TOP,
524 AC_JACK_LOC_BOTTOM,
525};
526/* bits 4-5 */
527enum {
528 AC_JACK_LOC_EXTERNAL = 0x00,
529 AC_JACK_LOC_INTERNAL = 0x10,
530 AC_JACK_LOC_SEPARATE = 0x20,
531 AC_JACK_LOC_OTHER = 0x30,
532};
533enum {
534 /* external on primary chasis */
535 AC_JACK_LOC_REAR_PANEL = 0x07,
536 AC_JACK_LOC_DRIVE_BAY,
537 /* internal */
538 AC_JACK_LOC_RISER = 0x17,
539 AC_JACK_LOC_HDMI,
540 AC_JACK_LOC_ATAPI,
541 /* others */
542 AC_JACK_LOC_MOBILE_IN = 0x37,
543 AC_JACK_LOC_MOBILE_OUT,
544};
545
546/* Port connectivity (0-3) */
547enum {
548 AC_JACK_PORT_COMPLEX,
549 AC_JACK_PORT_NONE,
550 AC_JACK_PORT_FIXED,
551 AC_JACK_PORT_BOTH,
552};
553
1da177e4
LT
554/* max. codec address */
555#define HDA_MAX_CODEC_ADDRESS 0x0f
556
b2e18597
TI
557/*
558 * generic arrays
559 */
560struct snd_array {
561 unsigned int used;
562 unsigned int alloced;
563 unsigned int elem_size;
564 unsigned int alloc_align;
565 void *list;
566};
567
568void *snd_array_new(struct snd_array *array);
569void snd_array_free(struct snd_array *array);
570static inline void snd_array_init(struct snd_array *array, unsigned int size,
571 unsigned int align)
572{
573 array->elem_size = size;
574 array->alloc_align = align;
575}
576
f43aa025
TI
577static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
578{
579 return array->list + idx * array->elem_size;
580}
581
582static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
583{
584 return (unsigned long)(ptr - array->list) / array->elem_size;
585}
586
1da177e4
LT
587/*
588 * Structures
589 */
590
591struct hda_bus;
1cd2224c 592struct hda_beep;
1da177e4
LT
593struct hda_codec;
594struct hda_pcm;
595struct hda_pcm_stream;
596struct hda_bus_unsolicited;
597
598/* NID type */
599typedef u16 hda_nid_t;
600
601/* bus operators */
602struct hda_bus_ops {
603 /* send a single command */
33fa35ed 604 int (*command)(struct hda_bus *bus, unsigned int cmd);
1da177e4 605 /* get a response from the last command */
deadff16 606 unsigned int (*get_response)(struct hda_bus *bus, unsigned int addr);
1da177e4
LT
607 /* free the private data */
608 void (*private_free)(struct hda_bus *);
176d5335 609 /* attach a PCM stream */
33fa35ed
TI
610 int (*attach_pcm)(struct hda_bus *bus, struct hda_codec *codec,
611 struct hda_pcm *pcm);
8dd78330
TI
612 /* reset bus for retry verb */
613 void (*bus_reset)(struct hda_bus *bus);
83012a7c 614#ifdef CONFIG_PM
561de31a 615 /* notify power-up/down from codec to controller */
68467f51 616 void (*pm_notify)(struct hda_bus *bus, bool power_up);
cb53c626 617#endif
1d1a4564
TI
618#ifdef CONFIG_SND_HDA_DSP_LOADER
619 /* prepare DSP transfer */
620 int (*load_dsp_prepare)(struct hda_bus *bus, unsigned int format,
621 unsigned int byte_size,
622 struct snd_dma_buffer *bufp);
623 /* start/stop DSP transfer */
624 void (*load_dsp_trigger)(struct hda_bus *bus, bool start);
625 /* clean up DSP transfer */
626 void (*load_dsp_cleanup)(struct hda_bus *bus,
627 struct snd_dma_buffer *dmab);
628#endif
1da177e4
LT
629};
630
631/* template to pass to the bus constructor */
632struct hda_bus_template {
633 void *private_data;
634 struct pci_dev *pci;
635 const char *modelname;
fee2fba3 636 int *power_save;
1da177e4
LT
637 struct hda_bus_ops ops;
638};
639
640/*
641 * codec bus
642 *
643 * each controller needs to creata a hda_bus to assign the accessor.
644 * A hda_bus contains several codecs in the list codec_list.
645 */
646struct hda_bus {
c8b6bf9b 647 struct snd_card *card;
1da177e4
LT
648
649 /* copied from template */
650 void *private_data;
651 struct pci_dev *pci;
652 const char *modelname;
fee2fba3 653 int *power_save;
1da177e4
LT
654 struct hda_bus_ops ops;
655
656 /* codec linked list */
657 struct list_head codec_list;
d01ce99f
TI
658 /* link caddr -> codec */
659 struct hda_codec *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
1da177e4 660
62932df8 661 struct mutex cmd_mutex;
3f50ac6a 662 struct mutex prepare_mutex;
1da177e4
LT
663
664 /* unsolicited event queue */
665 struct hda_bus_unsolicited *unsol;
e8c0ee5d 666 char workq_name[16];
6acaed38 667 struct workqueue_struct *workq; /* common workqueue for codecs */
1da177e4 668
529bd6c4
TI
669 /* assigned PCMs */
670 DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES);
671
52987656
TI
672 /* misc op flags */
673 unsigned int needs_damn_long_delay :1;
b20f3b83
TI
674 unsigned int allow_bus_reset:1; /* allow bus reset at fatal error */
675 unsigned int sync_write:1; /* sync after verb write */
676 /* status for codec/controller */
b94d3539 677 unsigned int shutdown :1; /* being unloaded */
b613291f 678 unsigned int rirb_error:1; /* error in codec communication */
8dd78330
TI
679 unsigned int response_reset:1; /* controller was reset */
680 unsigned int in_reset:1; /* during reset operation */
0287d970 681 unsigned int power_keep_link_on:1; /* don't power off HDA link */
ea9b43ad
TI
682
683 int primary_dig_out_type; /* primary digital out PCM type */
1da177e4
LT
684};
685
686/*
687 * codec preset
688 *
689 * Known codecs have the patch to build and set up the controls/PCMs
690 * better than the generic parser.
691 */
692struct hda_codec_preset {
693 unsigned int id;
694 unsigned int mask;
695 unsigned int subs;
696 unsigned int subs_mask;
697 unsigned int rev;
ca7cfae9 698 hda_nid_t afg, mfg;
1da177e4
LT
699 const char *name;
700 int (*patch)(struct hda_codec *codec);
701};
702
1289e9e8
TI
703struct hda_codec_preset_list {
704 const struct hda_codec_preset *preset;
705 struct module *owner;
706 struct list_head list;
707};
708
709/* initial hook */
710int snd_hda_add_codec_preset(struct hda_codec_preset_list *preset);
711int snd_hda_delete_codec_preset(struct hda_codec_preset_list *preset);
712
1da177e4
LT
713/* ops set by the preset patch */
714struct hda_codec_ops {
715 int (*build_controls)(struct hda_codec *codec);
716 int (*build_pcms)(struct hda_codec *codec);
717 int (*init)(struct hda_codec *codec);
718 void (*free)(struct hda_codec *codec);
719 void (*unsol_event)(struct hda_codec *codec, unsigned int res);
4d7fbdbc
TI
720 void (*set_power_state)(struct hda_codec *codec, hda_nid_t fg,
721 unsigned int power_state);
2a43952a 722#ifdef CONFIG_PM
68cb2b55 723 int (*suspend)(struct hda_codec *codec);
1da177e4 724 int (*resume)(struct hda_codec *codec);
cb53c626
TI
725 int (*check_power_status)(struct hda_codec *codec, hda_nid_t nid);
726#endif
fb8d1a34 727 void (*reboot_notify)(struct hda_codec *codec);
1da177e4
LT
728};
729
730/* record for amp information cache */
01751f54 731struct hda_cache_head {
c370dd6e
TI
732 u32 key:31; /* hash key */
733 u32 dirty:1;
01751f54 734 u16 val; /* assigned value */
c370dd6e 735 u16 next;
01751f54
TI
736};
737
738struct hda_amp_info {
739 struct hda_cache_head head;
1da177e4 740 u32 amp_caps; /* amp capabilities */
7f0e2f8b 741 u16 vol[2]; /* current volume & mute */
01751f54
TI
742};
743
744struct hda_cache_rec {
745 u16 hash[64]; /* hash table for index */
603c4019 746 struct snd_array buf; /* record entries */
1da177e4
LT
747};
748
749/* PCM callbacks */
750struct hda_pcm_ops {
751 int (*open)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 752 struct snd_pcm_substream *substream);
1da177e4 753 int (*close)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 754 struct snd_pcm_substream *substream);
1da177e4
LT
755 int (*prepare)(struct hda_pcm_stream *info, struct hda_codec *codec,
756 unsigned int stream_tag, unsigned int format,
c8b6bf9b 757 struct snd_pcm_substream *substream);
1da177e4 758 int (*cleanup)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 759 struct snd_pcm_substream *substream);
1da177e4
LT
760};
761
762/* PCM information for each substream */
763struct hda_pcm_stream {
d01ce99f 764 unsigned int substreams; /* number of substreams, 0 = not exist*/
1da177e4
LT
765 unsigned int channels_min; /* min. number of channels */
766 unsigned int channels_max; /* max. number of channels */
767 hda_nid_t nid; /* default NID to query rates/formats/bps, or set up */
768 u32 rates; /* supported rates */
769 u64 formats; /* supported formats (SNDRV_PCM_FMTBIT_) */
770 unsigned int maxbps; /* supported max. bit per sample */
ee81abb6 771 const struct snd_pcm_chmap_elem *chmap; /* chmap to override */
1da177e4
LT
772 struct hda_pcm_ops ops;
773};
774
7ba72ba1
TI
775/* PCM types */
776enum {
777 HDA_PCM_TYPE_AUDIO,
778 HDA_PCM_TYPE_SPDIF,
779 HDA_PCM_TYPE_HDMI,
780 HDA_PCM_TYPE_MODEM,
781 HDA_PCM_NTYPES
782};
783
1da177e4
LT
784/* for PCM creation */
785struct hda_pcm {
786 char *name;
787 struct hda_pcm_stream stream[2];
7ba72ba1 788 unsigned int pcm_type; /* HDA_PCM_TYPE_XXX */
176d5335
TI
789 int device; /* device number to assign */
790 struct snd_pcm *pcm; /* assigned PCM instance */
9c9a5175 791 bool own_chmap; /* codec driver provides own channel maps */
1da177e4
LT
792};
793
794/* codec information */
795struct hda_codec {
796 struct hda_bus *bus;
797 unsigned int addr; /* codec addr*/
798 struct list_head list; /* list point */
799
800 hda_nid_t afg; /* AFG node id */
673b683a 801 hda_nid_t mfg; /* MFG node id */
1da177e4
LT
802
803 /* ids */
79c944ad
JK
804 u8 afg_function_id;
805 u8 mfg_function_id;
806 u8 afg_unsol;
807 u8 mfg_unsol;
1da177e4
LT
808 u32 vendor_id;
809 u32 subsystem_id;
810 u32 revision_id;
811
812 /* detected preset */
813 const struct hda_codec_preset *preset;
1289e9e8 814 struct module *owner;
812a2cca
TI
815 const char *vendor_name; /* codec vendor name */
816 const char *chip_name; /* codec chip name */
f44ac837 817 const char *modelname; /* model name for preset */
1da177e4
LT
818
819 /* set by patch */
820 struct hda_codec_ops patch_ops;
821
1da177e4
LT
822 /* PCM to create, set by patch_ops.build_pcms callback */
823 unsigned int num_pcms;
824 struct hda_pcm *pcm_info;
825
826 /* codec specific info */
827 void *spec;
828
1cd2224c
MR
829 /* beep device */
830 struct hda_beep *beep;
2dca0bba 831 unsigned int beep_mode;
1cd2224c 832
54d17403
TI
833 /* widget capabilities cache */
834 unsigned int num_nodes;
835 hda_nid_t start_nid;
836 u32 *wcaps;
837
d13bd412 838 struct snd_array mixers; /* list of assigned mixer elements */
5b0cb1d8 839 struct snd_array nids; /* list of mapped mixer elements */
d13bd412 840
01751f54 841 struct hda_cache_rec amp_cache; /* cache for amp access */
b3ac5636 842 struct hda_cache_rec cmd_cache; /* cache for other commands */
1da177e4 843
ee8e765b 844 struct list_head conn_list; /* linked-list of connection-list */
a12d3e1e 845
62932df8 846 struct mutex spdif_mutex;
5a9e02e9 847 struct mutex control_mutex;
c3b6bcc2 848 struct mutex hash_mutex;
7c935976 849 struct snd_array spdif_out;
1da177e4 850 unsigned int spdif_in_enable; /* SPDIF input enable? */
dda14410 851 const hda_nid_t *slave_dig_outs; /* optional digital out slave widgets */
3be14149 852 struct snd_array init_pins; /* initial (BIOS) pin configurations */
346ff70f 853 struct snd_array driver_pins; /* pin configs set by codec parser */
eb541337 854 struct snd_array cvt_setups; /* audio convert setups */
2807314d 855
11aeff08 856#ifdef CONFIG_SND_HDA_HWDEP
09b70e85 857 struct mutex user_mutex;
2807314d 858 struct snd_hwdep *hwdep; /* assigned hwdep device */
11aeff08 859 struct snd_array init_verbs; /* additional init verbs */
1e1be432 860 struct snd_array hints; /* additional hints */
346ff70f 861 struct snd_array user_pins; /* default pin configs to override */
11aeff08 862#endif
cb53c626 863
963f803f
TI
864 /* misc flags */
865 unsigned int spdif_status_reset :1; /* needs to toggle SPDIF for each
866 * status change
867 * (e.g. Realtek codecs)
868 */
9421f954
TI
869 unsigned int pin_amp_workaround:1; /* pin out-amp takes index
870 * (e.g. Conexant codecs)
871 */
4f32456e
MK
872 unsigned int single_adc_amp:1; /* adc in-amp takes no index
873 * (e.g. CX20549 codec)
874 */
0e7adbe2 875 unsigned int no_sticky_stream:1; /* no sticky-PCM stream assignment */
ac0547dc 876 unsigned int pins_shutup:1; /* pins are shut up */
729d55ba 877 unsigned int no_trigger_sense:1; /* don't trigger at pin-sensing */
71b1e9e4 878 unsigned int no_jack_detect:1; /* Machine has no jack-detection */
ecac3ed1 879 unsigned int inv_eapd:1; /* broken h/w: inverted EAPD control */
9cc159c6 880 unsigned int inv_jack_detect:1; /* broken h/w: inverted detection bit */
ed360813 881 unsigned int pcm_format_first:1; /* PCM format must be set first */
983f6b93 882 unsigned int epss:1; /* supporting EPSS? */
c370dd6e 883 unsigned int cached_write:1; /* write only to caches */
83012a7c 884#ifdef CONFIG_PM
a221e287 885 unsigned int power_on :1; /* current (global) power-state */
4b927345 886 unsigned int d3_stop_clk:1; /* support D3 operation without BCLK */
08fa20ae 887 unsigned int pm_down_notified:1; /* PM notified to controller */
989c3187 888 unsigned int in_pm:1; /* suspend/resume being performed */
a2d96e77 889 int power_transition; /* power-state in transition */
cb53c626
TI
890 int power_count; /* current (global) power refcount */
891 struct delayed_work power_work; /* delayed task for powerdown */
a2f6309e
TI
892 unsigned long power_on_acct;
893 unsigned long power_off_acct;
894 unsigned long power_jiffies;
5536c6d6 895 spinlock_t power_lock;
cb53c626 896#endif
daead538 897
9419ab6b
TI
898 /* filter the requested power state per nid */
899 unsigned int (*power_filter)(struct hda_codec *codec, hda_nid_t nid,
900 unsigned int power_state);
901
daead538
TI
902 /* codec-specific additional proc output */
903 void (*proc_widget_hook)(struct snd_info_buffer *buffer,
904 struct hda_codec *codec, hda_nid_t nid);
cd372fb3 905
1835a0f9
TI
906 /* jack detection */
907 struct snd_array jacktbl;
26a6cb6c
DH
908 unsigned long jackpoll_interval; /* In jiffies. Zero means no poll, rely on unsol events */
909 struct delayed_work jackpoll_work;
1835a0f9 910
cd372fb3
TI
911#ifdef CONFIG_SND_HDA_INPUT_JACK
912 /* jack detection */
913 struct snd_array jacks;
914#endif
c9ce6b26
TI
915
916 /* fix-up list */
917 int fixup_id;
918 const struct hda_fixup *fixup_list;
919 const char *fixup_name;
920
921 /* additional init verbs */
922 struct snd_array verbs;
1da177e4
LT
923};
924
925/* direction */
926enum {
927 HDA_INPUT, HDA_OUTPUT
928};
929
930
931/*
932 * constructors
933 */
c8b6bf9b 934int snd_hda_bus_new(struct snd_card *card, const struct hda_bus_template *temp,
1da177e4
LT
935 struct hda_bus **busp);
936int snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr,
a1e21c90
TI
937 struct hda_codec **codecp);
938int snd_hda_codec_configure(struct hda_codec *codec);
a15d05db 939int snd_hda_codec_update_widgets(struct hda_codec *codec);
1da177e4
LT
940
941/*
942 * low level functions
943 */
d01ce99f
TI
944unsigned int snd_hda_codec_read(struct hda_codec *codec, hda_nid_t nid,
945 int direct,
1da177e4
LT
946 unsigned int verb, unsigned int parm);
947int snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int direct,
948 unsigned int verb, unsigned int parm);
d01ce99f
TI
949#define snd_hda_param_read(codec, nid, param) \
950 snd_hda_codec_read(codec, nid, 0, AC_VERB_PARAMETERS, param)
951int snd_hda_get_sub_nodes(struct hda_codec *codec, hda_nid_t nid,
952 hda_nid_t *start_id);
953int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid,
954 hda_nid_t *conn_list, int max_conns);
09cf03b8
TI
955static inline int
956snd_hda_get_num_conns(struct hda_codec *codec, hda_nid_t nid)
957{
958 return snd_hda_get_connections(codec, nid, NULL, 0);
959}
4eea3091 960int snd_hda_get_num_raw_conns(struct hda_codec *codec, hda_nid_t nid);
9e7717c9
TI
961int snd_hda_get_raw_connections(struct hda_codec *codec, hda_nid_t nid,
962 hda_nid_t *conn_list, int max_conns);
ee8e765b
TI
963int snd_hda_get_conn_list(struct hda_codec *codec, hda_nid_t nid,
964 const hda_nid_t **listp);
b2f934a0
TI
965int snd_hda_override_conn_list(struct hda_codec *codec, hda_nid_t nid, int nums,
966 const hda_nid_t *list);
8d087c76
TI
967int snd_hda_get_conn_index(struct hda_codec *codec, hda_nid_t mux,
968 hda_nid_t nid, int recursive);
384a48d7
SW
969int snd_hda_query_supported_pcm(struct hda_codec *codec, hda_nid_t nid,
970 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
1da177e4
LT
971
972struct hda_verb {
973 hda_nid_t nid;
974 u32 verb;
975 u32 param;
976};
977
d01ce99f
TI
978void snd_hda_sequence_write(struct hda_codec *codec,
979 const struct hda_verb *seq);
1da177e4
LT
980
981/* unsolicited event */
982int snd_hda_queue_unsol_event(struct hda_bus *bus, u32 res, u32 res_ex);
983
b3ac5636
TI
984/* cached write */
985int snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid,
986 int direct, unsigned int verb, unsigned int parm);
987void snd_hda_sequence_write_cache(struct hda_codec *codec,
988 const struct hda_verb *seq);
a68d5a54
TI
989int snd_hda_codec_update_cache(struct hda_codec *codec, hda_nid_t nid,
990 int direct, unsigned int verb, unsigned int parm);
b3ac5636 991void snd_hda_codec_resume_cache(struct hda_codec *codec);
dc870f38
TI
992/* both for cmd & amp caches */
993void snd_hda_codec_flush_cache(struct hda_codec *codec);
0c3d47b0 994
3be14149
TI
995/* the struct for codec->pin_configs */
996struct hda_pincfg {
997 hda_nid_t nid;
d7fdc00a
TI
998 unsigned char ctrl; /* original pin control value */
999 unsigned char target; /* target pin control value */
ac0547dc 1000 unsigned int cfg; /* default configuration */
3be14149
TI
1001};
1002
1003unsigned int snd_hda_codec_get_pincfg(struct hda_codec *codec, hda_nid_t nid);
1004int snd_hda_codec_set_pincfg(struct hda_codec *codec, hda_nid_t nid,
1005 unsigned int cfg);
1006int snd_hda_add_pincfg(struct hda_codec *codec, struct snd_array *list,
1007 hda_nid_t nid, unsigned int cfg); /* for hwdep */
92ee6162 1008void snd_hda_shutup_pins(struct hda_codec *codec);
3be14149 1009
7c935976
SW
1010/* SPDIF controls */
1011struct hda_spdif_out {
1012 hda_nid_t nid; /* Converter nid values relate to */
1013 unsigned int status; /* IEC958 status bits */
1014 unsigned short ctls; /* SPDIF control bits */
1015};
1016struct hda_spdif_out *snd_hda_spdif_out_of_nid(struct hda_codec *codec,
1017 hda_nid_t nid);
74b654c9
SW
1018void snd_hda_spdif_ctls_unassign(struct hda_codec *codec, int idx);
1019void snd_hda_spdif_ctls_assign(struct hda_codec *codec, int idx, hda_nid_t nid);
7c935976 1020
1da177e4
LT
1021/*
1022 * Mixer
1023 */
1024int snd_hda_build_controls(struct hda_bus *bus);
6c1f45ea 1025int snd_hda_codec_build_controls(struct hda_codec *codec);
1da177e4
LT
1026
1027/*
1028 * PCM
1029 */
1030int snd_hda_build_pcms(struct hda_bus *bus);
529bd6c4 1031int snd_hda_codec_build_pcms(struct hda_codec *codec);
eb541337
TI
1032
1033int snd_hda_codec_prepare(struct hda_codec *codec,
1034 struct hda_pcm_stream *hinfo,
1035 unsigned int stream,
1036 unsigned int format,
1037 struct snd_pcm_substream *substream);
1038void snd_hda_codec_cleanup(struct hda_codec *codec,
1039 struct hda_pcm_stream *hinfo,
1040 struct snd_pcm_substream *substream);
1041
d01ce99f
TI
1042void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid,
1043 u32 stream_tag,
1da177e4 1044 int channel_id, int format);
f0cea797
TI
1045void __snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid,
1046 int do_now);
1047#define snd_hda_codec_cleanup_stream(codec, nid) \
1048 __snd_hda_codec_cleanup_stream(codec, nid, 0)
d01ce99f
TI
1049unsigned int snd_hda_calc_stream_format(unsigned int rate,
1050 unsigned int channels,
1051 unsigned int format,
32c168c8
AH
1052 unsigned int maxbps,
1053 unsigned short spdif_ctls);
1da177e4
LT
1054int snd_hda_is_supported_format(struct hda_codec *codec, hda_nid_t nid,
1055 unsigned int format);
1056
ee81abb6
TI
1057extern const struct snd_pcm_chmap_elem snd_pcm_2_1_chmaps[];
1058
1da177e4
LT
1059/*
1060 * Misc
1061 */
1062void snd_hda_get_codec_name(struct hda_codec *codec, char *name, int namelen);
fb8d1a34 1063void snd_hda_bus_reboot_notify(struct hda_bus *bus);
4d7fbdbc 1064void snd_hda_codec_set_power_to_all(struct hda_codec *codec, hda_nid_t fg,
9419ab6b 1065 unsigned int power_state);
1da177e4 1066
d3d020bd
TI
1067int snd_hda_lock_devices(struct hda_bus *bus);
1068void snd_hda_unlock_devices(struct hda_bus *bus);
1069
1da177e4
LT
1070/*
1071 * power management
1072 */
1073#ifdef CONFIG_PM
8dd78330 1074int snd_hda_suspend(struct hda_bus *bus);
1da177e4
LT
1075int snd_hda_resume(struct hda_bus *bus);
1076#endif
1077
9e5341b9
TI
1078static inline
1079int hda_call_check_power_status(struct hda_codec *codec, hda_nid_t nid)
1080{
83012a7c 1081#ifdef CONFIG_PM
9e5341b9
TI
1082 if (codec->patch_ops.check_power_status)
1083 return codec->patch_ops.check_power_status(codec, nid);
ff2b7e2a 1084#endif
9e5341b9
TI
1085 return 0;
1086}
9e5341b9 1087
50a9f790
MR
1088/*
1089 * get widget information
1090 */
1091const char *snd_hda_get_jack_connectivity(u32 cfg);
1092const char *snd_hda_get_jack_type(u32 cfg);
1093const char *snd_hda_get_jack_location(u32 cfg);
1094
cb53c626
TI
1095/*
1096 * power saving
1097 */
83012a7c 1098#ifdef CONFIG_PM
c376e2c7 1099void snd_hda_power_save(struct hda_codec *codec, int delta, bool d3wait);
a2f6309e 1100void snd_hda_update_power_acct(struct hda_codec *codec);
cb53c626 1101#else
c376e2c7
TI
1102static inline void snd_hda_power_save(struct hda_codec *codec, int delta,
1103 bool d3wait) {}
cb53c626
TI
1104#endif
1105
c376e2c7
TI
1106/**
1107 * snd_hda_power_up - Power-up the codec
1108 * @codec: HD-audio codec
1109 *
1110 * Increment the power-up counter and power up the hardware really when
1111 * not turned on yet.
1112 */
1113static inline void snd_hda_power_up(struct hda_codec *codec)
1114{
1115 snd_hda_power_save(codec, 1, false);
1116}
1117
1118/**
1119 * snd_hda_power_up_d3wait - Power-up the codec after waiting for any pending
1120 * D3 transition to complete. This differs from snd_hda_power_up() when
1121 * power_transition == -1. snd_hda_power_up sees this case as a nop,
1122 * snd_hda_power_up_d3wait waits for the D3 transition to complete then powers
1123 * back up.
1124 * @codec: HD-audio codec
1125 *
1126 * Cancel any power down operation hapenning on the work queue, then power up.
1127 */
1128static inline void snd_hda_power_up_d3wait(struct hda_codec *codec)
1129{
1130 snd_hda_power_save(codec, 1, true);
1131}
1132
1133/**
1134 * snd_hda_power_down - Power-down the codec
1135 * @codec: HD-audio codec
1136 *
1137 * Decrement the power-up counter and schedules the power-off work if
1138 * the counter rearches to zero.
1139 */
1140static inline void snd_hda_power_down(struct hda_codec *codec)
1141{
1142 snd_hda_power_save(codec, -1, false);
1143}
1144
1145/**
1146 * snd_hda_power_sync - Synchronize the power-save status
1147 * @codec: HD-audio codec
1148 *
1149 * Synchronize the actual power state with the power account;
1150 * called when power_save parameter is changed
1151 */
1152static inline void snd_hda_power_sync(struct hda_codec *codec)
1153{
1154 snd_hda_power_save(codec, 0, false);
1155}
1156
4ea6fbc8
TI
1157#ifdef CONFIG_SND_HDA_PATCH_LOADER
1158/*
1159 * patch firmware
1160 */
4918cdab 1161int snd_hda_load_patch(struct hda_bus *bus, size_t size, const void *buf);
4ea6fbc8
TI
1162#endif
1163
1d1a4564
TI
1164#ifdef CONFIG_SND_HDA_DSP_LOADER
1165static inline int
1166snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
1167 unsigned int size,
1168 struct snd_dma_buffer *bufp)
1169{
1170 return codec->bus->ops.load_dsp_prepare(codec->bus, format, size, bufp);
1171}
1172static inline void
1173snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
1174{
1175 return codec->bus->ops.load_dsp_trigger(codec->bus, start);
1176}
1177static inline void
1178snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1179 struct snd_dma_buffer *dmab)
1180{
1181 return codec->bus->ops.load_dsp_cleanup(codec->bus, dmab);
1182}
1183#else
1184static inline int
1185snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
1186 unsigned int size,
1187 struct snd_dma_buffer *bufp)
1188{
a3af4807 1189 return -ENOSYS;
1d1a4564
TI
1190}
1191static inline void
1192snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) {}
1193static inline void
1194snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1195 struct snd_dma_buffer *dmab) {}
1196#endif
1197
ff7a3267
TI
1198/*
1199 * Codec modularization
1200 */
1201
1202/* Export symbols only for communication with codec drivers;
1203 * When built in kernel, all HD-audio drivers are supposed to be statically
1204 * linked to the kernel. Thus, the symbols don't have to (or shouldn't) be
1205 * exported unless it's built as a module.
1206 */
1207#ifdef MODULE
1208#define EXPORT_SYMBOL_HDA(sym) EXPORT_SYMBOL_GPL(sym)
1209#else
1210#define EXPORT_SYMBOL_HDA(sym)
1211#endif
1212
1da177e4 1213#endif /* __SOUND_HDA_CODEC_H */
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