ALSA: HDA: Make hda sound card usable for Loongson
[deliverable/linux.git] / sound / pci / hda / hda_codec.h
CommitLineData
1da177e4
LT
1/*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59
18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef __SOUND_HDA_CODEC_H
22#define __SOUND_HDA_CODEC_H
23
24#include <sound/info.h>
25#include <sound/control.h>
26#include <sound/pcm.h>
2807314d 27#include <sound/hwdep.h>
1da177e4
LT
28
29/*
30 * nodes
31 */
32#define AC_NODE_ROOT 0x00
33
34/*
35 * function group types
36 */
37enum {
38 AC_GRP_AUDIO_FUNCTION = 0x01,
39 AC_GRP_MODEM_FUNCTION = 0x02,
40};
41
42/*
43 * widget types
44 */
45enum {
46 AC_WID_AUD_OUT, /* Audio Out */
47 AC_WID_AUD_IN, /* Audio In */
48 AC_WID_AUD_MIX, /* Audio Mixer */
49 AC_WID_AUD_SEL, /* Audio Selector */
50 AC_WID_PIN, /* Pin Complex */
51 AC_WID_POWER, /* Power */
52 AC_WID_VOL_KNB, /* Volume Knob */
53 AC_WID_BEEP, /* Beep Generator */
54 AC_WID_VENDOR = 0x0f /* Vendor specific */
55};
56
57/*
58 * GET verbs
59 */
60#define AC_VERB_GET_STREAM_FORMAT 0x0a00
61#define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
62#define AC_VERB_GET_PROC_COEF 0x0c00
63#define AC_VERB_GET_COEF_INDEX 0x0d00
64#define AC_VERB_PARAMETERS 0x0f00
65#define AC_VERB_GET_CONNECT_SEL 0x0f01
66#define AC_VERB_GET_CONNECT_LIST 0x0f02
67#define AC_VERB_GET_PROC_STATE 0x0f03
68#define AC_VERB_GET_SDI_SELECT 0x0f04
69#define AC_VERB_GET_POWER_STATE 0x0f05
70#define AC_VERB_GET_CONV 0x0f06
71#define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07
72#define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08
73#define AC_VERB_GET_PIN_SENSE 0x0f09
74#define AC_VERB_GET_BEEP_CONTROL 0x0f0a
75#define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c
3982d17e 76#define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d
a1855d80 77#define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */
1da177e4
LT
78#define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f
79/* f10-f1a: GPIO */
16ded525
TI
80#define AC_VERB_GET_GPIO_DATA 0x0f15
81#define AC_VERB_GET_GPIO_MASK 0x0f16
82#define AC_VERB_GET_GPIO_DIRECTION 0x0f17
797760ab 83#define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18
3982d17e 84#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19
797760ab 85#define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a
1da177e4 86#define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c
86284e45
TI
87/* f20: AFG/MFG */
88#define AC_VERB_GET_SUBSYSTEM_ID 0x0f20
955d2488
TI
89#define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d
90#define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e
91#define AC_VERB_GET_HDMI_ELDD 0x0f2f
92#define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30
93#define AC_VERB_GET_HDMI_DIP_DATA 0x0f31
94#define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32
95#define AC_VERB_GET_HDMI_CP_CTRL 0x0f33
96#define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34
1da177e4
LT
97
98/*
99 * SET verbs
100 */
101#define AC_VERB_SET_STREAM_FORMAT 0x200
102#define AC_VERB_SET_AMP_GAIN_MUTE 0x300
103#define AC_VERB_SET_PROC_COEF 0x400
104#define AC_VERB_SET_COEF_INDEX 0x500
105#define AC_VERB_SET_CONNECT_SEL 0x701
106#define AC_VERB_SET_PROC_STATE 0x703
107#define AC_VERB_SET_SDI_SELECT 0x704
108#define AC_VERB_SET_POWER_STATE 0x705
109#define AC_VERB_SET_CHANNEL_STREAMID 0x706
110#define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707
111#define AC_VERB_SET_UNSOLICITED_ENABLE 0x708
112#define AC_VERB_SET_PIN_SENSE 0x709
113#define AC_VERB_SET_BEEP_CONTROL 0x70a
a2a20939 114#define AC_VERB_SET_EAPD_BTLENABLE 0x70c
1da177e4
LT
115#define AC_VERB_SET_DIGI_CONVERT_1 0x70d
116#define AC_VERB_SET_DIGI_CONVERT_2 0x70e
117#define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f
16ded525
TI
118#define AC_VERB_SET_GPIO_DATA 0x715
119#define AC_VERB_SET_GPIO_MASK 0x716
120#define AC_VERB_SET_GPIO_DIRECTION 0x717
797760ab 121#define AC_VERB_SET_GPIO_WAKE_MASK 0x718
3982d17e 122#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719
797760ab 123#define AC_VERB_SET_GPIO_STICKY_MASK 0x71a
1da177e4
LT
124#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c
125#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d
126#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e
127#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f
d0513fc6 128#define AC_VERB_SET_EAPD 0x788
1da177e4 129#define AC_VERB_SET_CODEC_RESET 0x7ff
955d2488
TI
130#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d
131#define AC_VERB_SET_HDMI_DIP_INDEX 0x730
132#define AC_VERB_SET_HDMI_DIP_DATA 0x731
133#define AC_VERB_SET_HDMI_DIP_XMIT 0x732
134#define AC_VERB_SET_HDMI_CP_CTRL 0x733
135#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734
1da177e4
LT
136
137/*
138 * Parameter IDs
139 */
140#define AC_PAR_VENDOR_ID 0x00
141#define AC_PAR_SUBSYSTEM_ID 0x01
142#define AC_PAR_REV_ID 0x02
143#define AC_PAR_NODE_COUNT 0x04
144#define AC_PAR_FUNCTION_TYPE 0x05
145#define AC_PAR_AUDIO_FG_CAP 0x08
146#define AC_PAR_AUDIO_WIDGET_CAP 0x09
147#define AC_PAR_PCM 0x0a
148#define AC_PAR_STREAM 0x0b
149#define AC_PAR_PIN_CAP 0x0c
150#define AC_PAR_AMP_IN_CAP 0x0d
151#define AC_PAR_CONNLIST_LEN 0x0e
152#define AC_PAR_POWER_STATE 0x0f
153#define AC_PAR_PROC_CAP 0x10
154#define AC_PAR_GPIO_CAP 0x11
155#define AC_PAR_AMP_OUT_CAP 0x12
e1716139 156#define AC_PAR_VOL_KNB_CAP 0x13
955d2488 157#define AC_PAR_HDMI_LPCM_CAP 0x20
1da177e4
LT
158
159/*
160 * AC_VERB_PARAMETERS results (32bit)
161 */
162
163/* Function Group Type */
164#define AC_FGT_TYPE (0xff<<0)
165#define AC_FGT_TYPE_SHIFT 0
166#define AC_FGT_UNSOL_CAP (1<<8)
167
168/* Audio Function Group Capabilities */
169#define AC_AFG_OUT_DELAY (0xf<<0)
170#define AC_AFG_IN_DELAY (0xf<<8)
171#define AC_AFG_BEEP_GEN (1<<16)
172
173/* Audio Widget Capabilities */
174#define AC_WCAP_STEREO (1<<0) /* stereo I/O */
175#define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
176#define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
177#define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
178#define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */
179#define AC_WCAP_STRIPE (1<<5) /* stripe */
180#define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */
181#define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */
182#define AC_WCAP_CONN_LIST (1<<8) /* connection list */
183#define AC_WCAP_DIGITAL (1<<9) /* digital I/O */
184#define AC_WCAP_POWER (1<<10) /* power control */
185#define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */
955d2488
TI
186#define AC_WCAP_CP_CAPS (1<<12) /* content protection */
187#define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */
1da177e4
LT
188#define AC_WCAP_DELAY (0xf<<16)
189#define AC_WCAP_DELAY_SHIFT 16
190#define AC_WCAP_TYPE (0xf<<20)
191#define AC_WCAP_TYPE_SHIFT 20
192
193/* supported PCM rates and bits */
194#define AC_SUPPCM_RATES (0xfff << 0)
195#define AC_SUPPCM_BITS_8 (1<<16)
196#define AC_SUPPCM_BITS_16 (1<<17)
197#define AC_SUPPCM_BITS_20 (1<<18)
198#define AC_SUPPCM_BITS_24 (1<<19)
199#define AC_SUPPCM_BITS_32 (1<<20)
200
201/* supported PCM stream format */
202#define AC_SUPFMT_PCM (1<<0)
203#define AC_SUPFMT_FLOAT32 (1<<1)
204#define AC_SUPFMT_AC3 (1<<2)
205
797760ab
AP
206/* GP I/O count */
207#define AC_GPIO_IO_COUNT (0xff<<0)
208#define AC_GPIO_O_COUNT (0xff<<8)
209#define AC_GPIO_O_COUNT_SHIFT 8
210#define AC_GPIO_I_COUNT (0xff<<16)
211#define AC_GPIO_I_COUNT_SHIFT 16
212#define AC_GPIO_UNSOLICITED (1<<30)
213#define AC_GPIO_WAKE (1<<31)
214
215/* Converter stream, channel */
216#define AC_CONV_CHANNEL (0xf<<0)
217#define AC_CONV_STREAM (0xf<<4)
218#define AC_CONV_STREAM_SHIFT 4
219
220/* Input converter SDI select */
221#define AC_SDI_SELECT (0xf<<0)
222
92f10b3f
TI
223/* stream format id */
224#define AC_FMT_CHAN_SHIFT 0
225#define AC_FMT_CHAN_MASK (0x0f << 0)
226#define AC_FMT_BITS_SHIFT 4
227#define AC_FMT_BITS_MASK (7 << 4)
228#define AC_FMT_BITS_8 (0 << 4)
229#define AC_FMT_BITS_16 (1 << 4)
230#define AC_FMT_BITS_20 (2 << 4)
231#define AC_FMT_BITS_24 (3 << 4)
232#define AC_FMT_BITS_32 (4 << 4)
233#define AC_FMT_DIV_SHIFT 8
234#define AC_FMT_DIV_MASK (7 << 8)
235#define AC_FMT_MULT_SHIFT 11
236#define AC_FMT_MULT_MASK (7 << 11)
237#define AC_FMT_BASE_SHIFT 14
238#define AC_FMT_BASE_48K (0 << 14)
239#define AC_FMT_BASE_44K (1 << 14)
240#define AC_FMT_TYPE_SHIFT 15
241#define AC_FMT_TYPE_PCM (0 << 15)
242#define AC_FMT_TYPE_NON_PCM (1 << 15)
243
955d2488 244/* Unsolicited response control */
797760ab
AP
245#define AC_UNSOL_TAG (0x3f<<0)
246#define AC_UNSOL_ENABLED (1<<7)
955d2488
TI
247#define AC_USRSP_EN AC_UNSOL_ENABLED
248
249/* Unsolicited responses */
250#define AC_UNSOL_RES_TAG (0x3f<<26)
251#define AC_UNSOL_RES_TAG_SHIFT 26
252#define AC_UNSOL_RES_SUBTAG (0x1f<<21)
253#define AC_UNSOL_RES_SUBTAG_SHIFT 21
254#define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
255#define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */
256#define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */
257#define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */
797760ab 258
1da177e4
LT
259/* Pin widget capabilies */
260#define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
261#define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */
262#define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */
263#define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */
264#define AC_PINCAP_OUT (1<<4) /* output capable */
265#define AC_PINCAP_IN (1<<5) /* input capable */
266#define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */
3982d17e
AP
267/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,
268 * but is marked reserved in the Intel HDA specification.
269 */
270#define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */
955d2488
TI
271/* Note: The same bit as LR_SWAP is newly defined as HDMI capability
272 * in HD-audio specification
273 */
274#define AC_PINCAP_HDMI (1<<7) /* HDMI pin */
728765b3
WF
275#define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can
276 * coexist with AC_PINCAP_HDMI
277 */
1a12de1e 278#define AC_PINCAP_VREF (0x37<<8)
1da177e4
LT
279#define AC_PINCAP_VREF_SHIFT 8
280#define AC_PINCAP_EAPD (1<<16) /* EAPD capable */
b923528e 281#define AC_PINCAP_HBR (1<<27) /* High Bit Rate */
1a12de1e
M
282/* Vref status (used in pin cap) */
283#define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
284#define AC_PINCAP_VREF_50 (1<<1) /* 50% */
285#define AC_PINCAP_VREF_GRD (1<<2) /* ground */
286#define AC_PINCAP_VREF_80 (1<<4) /* 80% */
287#define AC_PINCAP_VREF_100 (1<<5) /* 100% */
1da177e4
LT
288
289/* Amplifier capabilities */
290#define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */
291#define AC_AMPCAP_OFFSET_SHIFT 0
292#define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */
293#define AC_AMPCAP_NUM_STEPS_SHIFT 8
d01ce99f
TI
294#define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB
295 * in 0.25dB
296 */
1da177e4
LT
297#define AC_AMPCAP_STEP_SIZE_SHIFT 16
298#define AC_AMPCAP_MUTE (1<<31) /* mute capable */
299#define AC_AMPCAP_MUTE_SHIFT 31
300
3868137e
TI
301/* driver-specific amp-caps: using bits 24-30 */
302#define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */
303
1da177e4
LT
304/* Connection list */
305#define AC_CLIST_LENGTH (0x7f<<0)
306#define AC_CLIST_LONG (1<<7)
307
308/* Supported power status */
309#define AC_PWRST_D0SUP (1<<0)
310#define AC_PWRST_D1SUP (1<<1)
311#define AC_PWRST_D2SUP (1<<2)
312#define AC_PWRST_D3SUP (1<<3)
83d605fd
WF
313#define AC_PWRST_D3COLDSUP (1<<4)
314#define AC_PWRST_S3D3COLDSUP (1<<29)
315#define AC_PWRST_CLKSTOP (1<<30)
316#define AC_PWRST_EPSS (1U<<31)
1da177e4 317
54d17403 318/* Power state values */
797760ab
AP
319#define AC_PWRST_SETTING (0xf<<0)
320#define AC_PWRST_ACTUAL (0xf<<4)
321#define AC_PWRST_ACTUAL_SHIFT 4
54d17403
TI
322#define AC_PWRST_D0 0x00
323#define AC_PWRST_D1 0x01
324#define AC_PWRST_D2 0x02
325#define AC_PWRST_D3 0x03
ce63f3ba
WX
326#define AC_PWRST_ERROR (1<<8)
327#define AC_PWRST_CLK_STOP_OK (1<<9)
328#define AC_PWRST_SETTING_RESET (1<<10)
54d17403 329
1da177e4
LT
330/* Processing capabilies */
331#define AC_PCAP_BENIGN (1<<0)
332#define AC_PCAP_NUM_COEF (0xff<<8)
797760ab 333#define AC_PCAP_NUM_COEF_SHIFT 8
1da177e4
LT
334
335/* Volume knobs capabilities */
336#define AC_KNBCAP_NUM_STEPS (0x7f<<0)
38fcaf8e 337#define AC_KNBCAP_DELTA (1<<7)
1da177e4 338
955d2488
TI
339/* HDMI LPCM capabilities */
340#define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
341#define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
342#define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */
343#define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */
344#define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
345#define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
346#define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */
347#define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */
348#define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
349#define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
350#define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */
351#define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */
352#define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */
353#define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */
354
1da177e4
LT
355/*
356 * Control Parameters
357 */
358
359/* Amp gain/mute */
d427c77e 360#define AC_AMP_MUTE (1<<7)
1da177e4
LT
361#define AC_AMP_GAIN (0x7f)
362#define AC_AMP_GET_INDEX (0xf<<0)
363
364#define AC_AMP_GET_LEFT (1<<13)
365#define AC_AMP_GET_RIGHT (0<<13)
366#define AC_AMP_GET_OUTPUT (1<<15)
367#define AC_AMP_GET_INPUT (0<<15)
368
369#define AC_AMP_SET_INDEX (0xf<<8)
370#define AC_AMP_SET_INDEX_SHIFT 8
371#define AC_AMP_SET_RIGHT (1<<12)
372#define AC_AMP_SET_LEFT (1<<13)
373#define AC_AMP_SET_INPUT (1<<14)
374#define AC_AMP_SET_OUTPUT (1<<15)
375
376/* DIGITAL1 bits */
377#define AC_DIG1_ENABLE (1<<0)
378#define AC_DIG1_V (1<<1)
379#define AC_DIG1_VCFG (1<<2)
380#define AC_DIG1_EMPHASIS (1<<3)
381#define AC_DIG1_COPYRIGHT (1<<4)
382#define AC_DIG1_NONAUDIO (1<<5)
383#define AC_DIG1_PROFESSIONAL (1<<6)
384#define AC_DIG1_LEVEL (1<<7)
385
797760ab
AP
386/* DIGITAL2 bits */
387#define AC_DIG2_CC (0x7f<<0)
388
61525979
WX
389/* DIGITAL3 bits */
390#define AC_DIG3_ICT (0xf<<0)
391#define AC_DIG3_KAE (1<<7)
392
1da177e4 393/* Pin widget control - 8bit */
ea87d1c4
AH
394#define AC_PINCTL_EPT (0x3<<0)
395#define AC_PINCTL_EPT_NATIVE 0
396#define AC_PINCTL_EPT_HBR 3
1da177e4 397#define AC_PINCTL_VREFEN (0x7<<0)
98f759a6
TI
398#define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */
399#define AC_PINCTL_VREF_50 1 /* 50% */
400#define AC_PINCTL_VREF_GRD 2 /* ground */
401#define AC_PINCTL_VREF_80 4 /* 80% */
402#define AC_PINCTL_VREF_100 5 /* 100% */
1da177e4
LT
403#define AC_PINCTL_IN_EN (1<<5)
404#define AC_PINCTL_OUT_EN (1<<6)
405#define AC_PINCTL_HP_EN (1<<7)
406
797760ab
AP
407/* Pin sense - 32bit */
408#define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff)
409#define AC_PINSENSE_PRESENCE (1<<31)
955d2488 410#define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */
797760ab
AP
411
412/* EAPD/BTL enable - 32bit */
413#define AC_EAPDBTL_BALANCED (1<<0)
414#define AC_EAPDBTL_EAPD (1<<1)
415#define AC_EAPDBTL_LR_SWAP (1<<2)
416
955d2488
TI
417/* HDMI ELD data */
418#define AC_ELDD_ELD_VALID (1<<31)
419#define AC_ELDD_ELD_DATA 0xff
420
421/* HDMI DIP size */
422#define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */
423#define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */
424
425/* HDMI DIP index */
426#define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */
427#define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */
428
429/* HDMI DIP xmit (transmit) control */
430#define AC_DIPXMIT_MASK (0x3<<6)
431#define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */
432#define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */
433#define AC_DIPXMIT_BEST (0x3<<6) /* best effort */
434
435/* HDMI content protection (CP) control */
436#define AC_CPCTRL_CES (1<<9) /* current encryption state */
437#define AC_CPCTRL_READY (1<<8) /* ready bit */
438#define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */
439#define AC_CPCTRL_STATE (3<<0) /* current CP request state */
440
441/* Converter channel <-> HDMI slot mapping */
442#define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */
443#define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */
444
1da177e4
LT
445/* configuration default - 32bit */
446#define AC_DEFCFG_SEQUENCE (0xf<<0)
447#define AC_DEFCFG_DEF_ASSOC (0xf<<4)
d21b37ea 448#define AC_DEFCFG_ASSOC_SHIFT 4
1da177e4 449#define AC_DEFCFG_MISC (0xf<<8)
d21b37ea 450#define AC_DEFCFG_MISC_SHIFT 8
797760ab 451#define AC_DEFCFG_MISC_NO_PRESENCE (1<<0)
1da177e4
LT
452#define AC_DEFCFG_COLOR (0xf<<12)
453#define AC_DEFCFG_COLOR_SHIFT 12
454#define AC_DEFCFG_CONN_TYPE (0xf<<16)
455#define AC_DEFCFG_CONN_TYPE_SHIFT 16
456#define AC_DEFCFG_DEVICE (0xf<<20)
457#define AC_DEFCFG_DEVICE_SHIFT 20
458#define AC_DEFCFG_LOCATION (0x3f<<24)
459#define AC_DEFCFG_LOCATION_SHIFT 24
460#define AC_DEFCFG_PORT_CONN (0x3<<30)
461#define AC_DEFCFG_PORT_CONN_SHIFT 30
462
463/* device device types (0x0-0xf) */
464enum {
465 AC_JACK_LINE_OUT,
466 AC_JACK_SPEAKER,
467 AC_JACK_HP_OUT,
468 AC_JACK_CD,
469 AC_JACK_SPDIF_OUT,
470 AC_JACK_DIG_OTHER_OUT,
471 AC_JACK_MODEM_LINE_SIDE,
472 AC_JACK_MODEM_HAND_SIDE,
473 AC_JACK_LINE_IN,
474 AC_JACK_AUX,
475 AC_JACK_MIC_IN,
476 AC_JACK_TELEPHONY,
477 AC_JACK_SPDIF_IN,
478 AC_JACK_DIG_OTHER_IN,
479 AC_JACK_OTHER = 0xf,
480};
481
482/* jack connection types (0x0-0xf) */
483enum {
484 AC_JACK_CONN_UNKNOWN,
485 AC_JACK_CONN_1_8,
486 AC_JACK_CONN_1_4,
487 AC_JACK_CONN_ATAPI,
488 AC_JACK_CONN_RCA,
489 AC_JACK_CONN_OPTICAL,
490 AC_JACK_CONN_OTHER_DIGITAL,
491 AC_JACK_CONN_OTHER_ANALOG,
492 AC_JACK_CONN_DIN,
493 AC_JACK_CONN_XLR,
494 AC_JACK_CONN_RJ11,
495 AC_JACK_CONN_COMB,
496 AC_JACK_CONN_OTHER = 0xf,
497};
498
499/* jack colors (0x0-0xf) */
500enum {
501 AC_JACK_COLOR_UNKNOWN,
502 AC_JACK_COLOR_BLACK,
503 AC_JACK_COLOR_GREY,
504 AC_JACK_COLOR_BLUE,
505 AC_JACK_COLOR_GREEN,
506 AC_JACK_COLOR_RED,
507 AC_JACK_COLOR_ORANGE,
508 AC_JACK_COLOR_YELLOW,
509 AC_JACK_COLOR_PURPLE,
510 AC_JACK_COLOR_PINK,
511 AC_JACK_COLOR_WHITE = 0xe,
512 AC_JACK_COLOR_OTHER,
513};
514
515/* Jack location (0x0-0x3f) */
516/* common case */
517enum {
518 AC_JACK_LOC_NONE,
519 AC_JACK_LOC_REAR,
520 AC_JACK_LOC_FRONT,
521 AC_JACK_LOC_LEFT,
522 AC_JACK_LOC_RIGHT,
523 AC_JACK_LOC_TOP,
524 AC_JACK_LOC_BOTTOM,
525};
526/* bits 4-5 */
527enum {
528 AC_JACK_LOC_EXTERNAL = 0x00,
529 AC_JACK_LOC_INTERNAL = 0x10,
530 AC_JACK_LOC_SEPARATE = 0x20,
531 AC_JACK_LOC_OTHER = 0x30,
532};
533enum {
534 /* external on primary chasis */
535 AC_JACK_LOC_REAR_PANEL = 0x07,
536 AC_JACK_LOC_DRIVE_BAY,
537 /* internal */
538 AC_JACK_LOC_RISER = 0x17,
539 AC_JACK_LOC_HDMI,
540 AC_JACK_LOC_ATAPI,
541 /* others */
542 AC_JACK_LOC_MOBILE_IN = 0x37,
543 AC_JACK_LOC_MOBILE_OUT,
544};
545
546/* Port connectivity (0-3) */
547enum {
548 AC_JACK_PORT_COMPLEX,
549 AC_JACK_PORT_NONE,
550 AC_JACK_PORT_FIXED,
551 AC_JACK_PORT_BOTH,
552};
553
554/* max. connections to a widget */
54d17403 555#define HDA_MAX_CONNECTIONS 32
1da177e4
LT
556
557/* max. codec address */
558#define HDA_MAX_CODEC_ADDRESS 0x0f
559
b2e18597
TI
560/*
561 * generic arrays
562 */
563struct snd_array {
564 unsigned int used;
565 unsigned int alloced;
566 unsigned int elem_size;
567 unsigned int alloc_align;
568 void *list;
569};
570
571void *snd_array_new(struct snd_array *array);
572void snd_array_free(struct snd_array *array);
573static inline void snd_array_init(struct snd_array *array, unsigned int size,
574 unsigned int align)
575{
576 array->elem_size = size;
577 array->alloc_align = align;
578}
579
f43aa025
TI
580static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
581{
582 return array->list + idx * array->elem_size;
583}
584
585static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
586{
587 return (unsigned long)(ptr - array->list) / array->elem_size;
588}
589
1da177e4
LT
590/*
591 * Structures
592 */
593
594struct hda_bus;
1cd2224c 595struct hda_beep;
1da177e4
LT
596struct hda_codec;
597struct hda_pcm;
598struct hda_pcm_stream;
599struct hda_bus_unsolicited;
600
601/* NID type */
602typedef u16 hda_nid_t;
603
604/* bus operators */
605struct hda_bus_ops {
606 /* send a single command */
33fa35ed 607 int (*command)(struct hda_bus *bus, unsigned int cmd);
1da177e4 608 /* get a response from the last command */
deadff16 609 unsigned int (*get_response)(struct hda_bus *bus, unsigned int addr);
1da177e4
LT
610 /* free the private data */
611 void (*private_free)(struct hda_bus *);
176d5335 612 /* attach a PCM stream */
33fa35ed
TI
613 int (*attach_pcm)(struct hda_bus *bus, struct hda_codec *codec,
614 struct hda_pcm *pcm);
8dd78330
TI
615 /* reset bus for retry verb */
616 void (*bus_reset)(struct hda_bus *bus);
83012a7c 617#ifdef CONFIG_PM
561de31a 618 /* notify power-up/down from codec to controller */
68467f51 619 void (*pm_notify)(struct hda_bus *bus, bool power_up);
cb53c626 620#endif
1da177e4
LT
621};
622
623/* template to pass to the bus constructor */
624struct hda_bus_template {
625 void *private_data;
626 struct pci_dev *pci;
627 const char *modelname;
fee2fba3 628 int *power_save;
1da177e4
LT
629 struct hda_bus_ops ops;
630};
631
632/*
633 * codec bus
634 *
635 * each controller needs to creata a hda_bus to assign the accessor.
636 * A hda_bus contains several codecs in the list codec_list.
637 */
638struct hda_bus {
c8b6bf9b 639 struct snd_card *card;
1da177e4
LT
640
641 /* copied from template */
642 void *private_data;
643 struct pci_dev *pci;
644 const char *modelname;
fee2fba3 645 int *power_save;
1da177e4
LT
646 struct hda_bus_ops ops;
647
648 /* codec linked list */
649 struct list_head codec_list;
d01ce99f
TI
650 /* link caddr -> codec */
651 struct hda_codec *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
1da177e4 652
62932df8 653 struct mutex cmd_mutex;
3f50ac6a 654 struct mutex prepare_mutex;
1da177e4
LT
655
656 /* unsolicited event queue */
657 struct hda_bus_unsolicited *unsol;
e8c0ee5d 658 char workq_name[16];
6acaed38 659 struct workqueue_struct *workq; /* common workqueue for codecs */
1da177e4 660
529bd6c4
TI
661 /* assigned PCMs */
662 DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES);
663
52987656
TI
664 /* misc op flags */
665 unsigned int needs_damn_long_delay :1;
b20f3b83
TI
666 unsigned int allow_bus_reset:1; /* allow bus reset at fatal error */
667 unsigned int sync_write:1; /* sync after verb write */
668 /* status for codec/controller */
b94d3539 669 unsigned int shutdown :1; /* being unloaded */
b613291f 670 unsigned int rirb_error:1; /* error in codec communication */
8dd78330
TI
671 unsigned int response_reset:1; /* controller was reset */
672 unsigned int in_reset:1; /* during reset operation */
0287d970 673 unsigned int power_keep_link_on:1; /* don't power off HDA link */
1da177e4
LT
674};
675
676/*
677 * codec preset
678 *
679 * Known codecs have the patch to build and set up the controls/PCMs
680 * better than the generic parser.
681 */
682struct hda_codec_preset {
683 unsigned int id;
684 unsigned int mask;
685 unsigned int subs;
686 unsigned int subs_mask;
687 unsigned int rev;
ca7cfae9 688 hda_nid_t afg, mfg;
1da177e4
LT
689 const char *name;
690 int (*patch)(struct hda_codec *codec);
691};
692
1289e9e8
TI
693struct hda_codec_preset_list {
694 const struct hda_codec_preset *preset;
695 struct module *owner;
696 struct list_head list;
697};
698
699/* initial hook */
700int snd_hda_add_codec_preset(struct hda_codec_preset_list *preset);
701int snd_hda_delete_codec_preset(struct hda_codec_preset_list *preset);
702
1da177e4
LT
703/* ops set by the preset patch */
704struct hda_codec_ops {
705 int (*build_controls)(struct hda_codec *codec);
706 int (*build_pcms)(struct hda_codec *codec);
707 int (*init)(struct hda_codec *codec);
708 void (*free)(struct hda_codec *codec);
709 void (*unsol_event)(struct hda_codec *codec, unsigned int res);
4d7fbdbc
TI
710 void (*set_power_state)(struct hda_codec *codec, hda_nid_t fg,
711 unsigned int power_state);
2a43952a 712#ifdef CONFIG_PM
68cb2b55 713 int (*suspend)(struct hda_codec *codec);
1da177e4 714 int (*resume)(struct hda_codec *codec);
cb53c626
TI
715 int (*check_power_status)(struct hda_codec *codec, hda_nid_t nid);
716#endif
fb8d1a34 717 void (*reboot_notify)(struct hda_codec *codec);
1da177e4
LT
718};
719
720/* record for amp information cache */
01751f54 721struct hda_cache_head {
1da177e4 722 u32 key; /* hash key */
01751f54
TI
723 u16 val; /* assigned value */
724 u16 next; /* next link; -1 = terminal */
725};
726
727struct hda_amp_info {
728 struct hda_cache_head head;
1da177e4 729 u32 amp_caps; /* amp capabilities */
7f0e2f8b 730 u16 vol[2]; /* current volume & mute */
01751f54
TI
731};
732
733struct hda_cache_rec {
734 u16 hash[64]; /* hash table for index */
603c4019 735 struct snd_array buf; /* record entries */
1da177e4
LT
736};
737
738/* PCM callbacks */
739struct hda_pcm_ops {
740 int (*open)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 741 struct snd_pcm_substream *substream);
1da177e4 742 int (*close)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 743 struct snd_pcm_substream *substream);
1da177e4
LT
744 int (*prepare)(struct hda_pcm_stream *info, struct hda_codec *codec,
745 unsigned int stream_tag, unsigned int format,
c8b6bf9b 746 struct snd_pcm_substream *substream);
1da177e4 747 int (*cleanup)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 748 struct snd_pcm_substream *substream);
1da177e4
LT
749};
750
751/* PCM information for each substream */
752struct hda_pcm_stream {
d01ce99f 753 unsigned int substreams; /* number of substreams, 0 = not exist*/
1da177e4
LT
754 unsigned int channels_min; /* min. number of channels */
755 unsigned int channels_max; /* max. number of channels */
756 hda_nid_t nid; /* default NID to query rates/formats/bps, or set up */
757 u32 rates; /* supported rates */
758 u64 formats; /* supported formats (SNDRV_PCM_FMTBIT_) */
759 unsigned int maxbps; /* supported max. bit per sample */
760 struct hda_pcm_ops ops;
761};
762
7ba72ba1
TI
763/* PCM types */
764enum {
765 HDA_PCM_TYPE_AUDIO,
766 HDA_PCM_TYPE_SPDIF,
767 HDA_PCM_TYPE_HDMI,
768 HDA_PCM_TYPE_MODEM,
769 HDA_PCM_NTYPES
770};
771
1da177e4
LT
772/* for PCM creation */
773struct hda_pcm {
774 char *name;
775 struct hda_pcm_stream stream[2];
7ba72ba1 776 unsigned int pcm_type; /* HDA_PCM_TYPE_XXX */
176d5335
TI
777 int device; /* device number to assign */
778 struct snd_pcm *pcm; /* assigned PCM instance */
9c9a5175 779 bool own_chmap; /* codec driver provides own channel maps */
1da177e4
LT
780};
781
782/* codec information */
783struct hda_codec {
784 struct hda_bus *bus;
785 unsigned int addr; /* codec addr*/
786 struct list_head list; /* list point */
787
788 hda_nid_t afg; /* AFG node id */
673b683a 789 hda_nid_t mfg; /* MFG node id */
1da177e4
LT
790
791 /* ids */
79c944ad
JK
792 u8 afg_function_id;
793 u8 mfg_function_id;
794 u8 afg_unsol;
795 u8 mfg_unsol;
1da177e4
LT
796 u32 vendor_id;
797 u32 subsystem_id;
798 u32 revision_id;
799
800 /* detected preset */
801 const struct hda_codec_preset *preset;
1289e9e8 802 struct module *owner;
812a2cca
TI
803 const char *vendor_name; /* codec vendor name */
804 const char *chip_name; /* codec chip name */
f44ac837 805 const char *modelname; /* model name for preset */
1da177e4
LT
806
807 /* set by patch */
808 struct hda_codec_ops patch_ops;
809
1da177e4
LT
810 /* PCM to create, set by patch_ops.build_pcms callback */
811 unsigned int num_pcms;
812 struct hda_pcm *pcm_info;
813
814 /* codec specific info */
815 void *spec;
816
1cd2224c
MR
817 /* beep device */
818 struct hda_beep *beep;
2dca0bba 819 unsigned int beep_mode;
1cd2224c 820
54d17403
TI
821 /* widget capabilities cache */
822 unsigned int num_nodes;
823 hda_nid_t start_nid;
824 u32 *wcaps;
825
d13bd412 826 struct snd_array mixers; /* list of assigned mixer elements */
5b0cb1d8 827 struct snd_array nids; /* list of mapped mixer elements */
d13bd412 828
01751f54 829 struct hda_cache_rec amp_cache; /* cache for amp access */
b3ac5636 830 struct hda_cache_rec cmd_cache; /* cache for other commands */
1da177e4 831
a12d3e1e
TI
832 struct snd_array conn_lists; /* connection-list array */
833
62932df8 834 struct mutex spdif_mutex;
5a9e02e9 835 struct mutex control_mutex;
c3b6bcc2 836 struct mutex hash_mutex;
7c935976 837 struct snd_array spdif_out;
1da177e4 838 unsigned int spdif_in_enable; /* SPDIF input enable? */
dda14410 839 const hda_nid_t *slave_dig_outs; /* optional digital out slave widgets */
3be14149 840 struct snd_array init_pins; /* initial (BIOS) pin configurations */
346ff70f 841 struct snd_array driver_pins; /* pin configs set by codec parser */
eb541337 842 struct snd_array cvt_setups; /* audio convert setups */
2807314d 843
11aeff08 844#ifdef CONFIG_SND_HDA_HWDEP
2807314d 845 struct snd_hwdep *hwdep; /* assigned hwdep device */
11aeff08 846 struct snd_array init_verbs; /* additional init verbs */
1e1be432 847 struct snd_array hints; /* additional hints */
346ff70f 848 struct snd_array user_pins; /* default pin configs to override */
11aeff08 849#endif
cb53c626 850
963f803f
TI
851 /* misc flags */
852 unsigned int spdif_status_reset :1; /* needs to toggle SPDIF for each
853 * status change
854 * (e.g. Realtek codecs)
855 */
9421f954
TI
856 unsigned int pin_amp_workaround:1; /* pin out-amp takes index
857 * (e.g. Conexant codecs)
858 */
4f32456e
MK
859 unsigned int single_adc_amp:1; /* adc in-amp takes no index
860 * (e.g. CX20549 codec)
861 */
0e7adbe2 862 unsigned int no_sticky_stream:1; /* no sticky-PCM stream assignment */
ac0547dc 863 unsigned int pins_shutup:1; /* pins are shut up */
729d55ba 864 unsigned int no_trigger_sense:1; /* don't trigger at pin-sensing */
71b1e9e4 865 unsigned int no_jack_detect:1; /* Machine has no jack-detection */
ed360813 866 unsigned int pcm_format_first:1; /* PCM format must be set first */
983f6b93 867 unsigned int epss:1; /* supporting EPSS? */
83012a7c 868#ifdef CONFIG_PM
a221e287 869 unsigned int power_on :1; /* current (global) power-state */
4b927345 870 unsigned int d3_stop_clk:1; /* support D3 operation without BCLK */
08fa20ae 871 unsigned int pm_down_notified:1; /* PM notified to controller */
a2d96e77 872 int power_transition; /* power-state in transition */
cb53c626
TI
873 int power_count; /* current (global) power refcount */
874 struct delayed_work power_work; /* delayed task for powerdown */
a2f6309e
TI
875 unsigned long power_on_acct;
876 unsigned long power_off_acct;
877 unsigned long power_jiffies;
5536c6d6 878 spinlock_t power_lock;
cb53c626 879#endif
daead538
TI
880
881 /* codec-specific additional proc output */
882 void (*proc_widget_hook)(struct snd_info_buffer *buffer,
883 struct hda_codec *codec, hda_nid_t nid);
cd372fb3 884
1835a0f9
TI
885 /* jack detection */
886 struct snd_array jacktbl;
887
cd372fb3
TI
888#ifdef CONFIG_SND_HDA_INPUT_JACK
889 /* jack detection */
890 struct snd_array jacks;
891#endif
1da177e4
LT
892};
893
894/* direction */
895enum {
896 HDA_INPUT, HDA_OUTPUT
897};
898
899
900/*
901 * constructors
902 */
c8b6bf9b 903int snd_hda_bus_new(struct snd_card *card, const struct hda_bus_template *temp,
1da177e4
LT
904 struct hda_bus **busp);
905int snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr,
a1e21c90
TI
906 struct hda_codec **codecp);
907int snd_hda_codec_configure(struct hda_codec *codec);
1da177e4
LT
908
909/*
910 * low level functions
911 */
d01ce99f
TI
912unsigned int snd_hda_codec_read(struct hda_codec *codec, hda_nid_t nid,
913 int direct,
1da177e4
LT
914 unsigned int verb, unsigned int parm);
915int snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int direct,
916 unsigned int verb, unsigned int parm);
d01ce99f
TI
917#define snd_hda_param_read(codec, nid, param) \
918 snd_hda_codec_read(codec, nid, 0, AC_VERB_PARAMETERS, param)
919int snd_hda_get_sub_nodes(struct hda_codec *codec, hda_nid_t nid,
920 hda_nid_t *start_id);
921int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid,
922 hda_nid_t *conn_list, int max_conns);
09cf03b8
TI
923static inline int
924snd_hda_get_num_conns(struct hda_codec *codec, hda_nid_t nid)
925{
926 return snd_hda_get_connections(codec, nid, NULL, 0);
927}
9e7717c9
TI
928int snd_hda_get_raw_connections(struct hda_codec *codec, hda_nid_t nid,
929 hda_nid_t *conn_list, int max_conns);
b2f934a0
TI
930int snd_hda_override_conn_list(struct hda_codec *codec, hda_nid_t nid, int nums,
931 const hda_nid_t *list);
8d087c76
TI
932int snd_hda_get_conn_index(struct hda_codec *codec, hda_nid_t mux,
933 hda_nid_t nid, int recursive);
384a48d7
SW
934int snd_hda_query_supported_pcm(struct hda_codec *codec, hda_nid_t nid,
935 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
1da177e4
LT
936
937struct hda_verb {
938 hda_nid_t nid;
939 u32 verb;
940 u32 param;
941};
942
d01ce99f
TI
943void snd_hda_sequence_write(struct hda_codec *codec,
944 const struct hda_verb *seq);
1da177e4
LT
945
946/* unsolicited event */
947int snd_hda_queue_unsol_event(struct hda_bus *bus, u32 res, u32 res_ex);
948
b3ac5636 949/* cached write */
2a43952a 950#ifdef CONFIG_PM
b3ac5636
TI
951int snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid,
952 int direct, unsigned int verb, unsigned int parm);
953void snd_hda_sequence_write_cache(struct hda_codec *codec,
954 const struct hda_verb *seq);
a68d5a54
TI
955int snd_hda_codec_update_cache(struct hda_codec *codec, hda_nid_t nid,
956 int direct, unsigned int verb, unsigned int parm);
b3ac5636 957void snd_hda_codec_resume_cache(struct hda_codec *codec);
82beb8fd
TI
958#else
959#define snd_hda_codec_write_cache snd_hda_codec_write
a68d5a54 960#define snd_hda_codec_update_cache snd_hda_codec_write
82beb8fd
TI
961#define snd_hda_sequence_write_cache snd_hda_sequence_write
962#endif
b3ac5636 963
3be14149
TI
964/* the struct for codec->pin_configs */
965struct hda_pincfg {
966 hda_nid_t nid;
ac0547dc
TI
967 unsigned char ctrl; /* current pin control value */
968 unsigned char pad; /* reserved */
969 unsigned int cfg; /* default configuration */
3be14149
TI
970};
971
972unsigned int snd_hda_codec_get_pincfg(struct hda_codec *codec, hda_nid_t nid);
973int snd_hda_codec_set_pincfg(struct hda_codec *codec, hda_nid_t nid,
974 unsigned int cfg);
975int snd_hda_add_pincfg(struct hda_codec *codec, struct snd_array *list,
976 hda_nid_t nid, unsigned int cfg); /* for hwdep */
92ee6162 977void snd_hda_shutup_pins(struct hda_codec *codec);
3be14149 978
7c935976
SW
979/* SPDIF controls */
980struct hda_spdif_out {
981 hda_nid_t nid; /* Converter nid values relate to */
982 unsigned int status; /* IEC958 status bits */
983 unsigned short ctls; /* SPDIF control bits */
984};
985struct hda_spdif_out *snd_hda_spdif_out_of_nid(struct hda_codec *codec,
986 hda_nid_t nid);
74b654c9
SW
987void snd_hda_spdif_ctls_unassign(struct hda_codec *codec, int idx);
988void snd_hda_spdif_ctls_assign(struct hda_codec *codec, int idx, hda_nid_t nid);
7c935976 989
1da177e4
LT
990/*
991 * Mixer
992 */
993int snd_hda_build_controls(struct hda_bus *bus);
6c1f45ea 994int snd_hda_codec_build_controls(struct hda_codec *codec);
1da177e4
LT
995
996/*
997 * PCM
998 */
999int snd_hda_build_pcms(struct hda_bus *bus);
529bd6c4 1000int snd_hda_codec_build_pcms(struct hda_codec *codec);
eb541337
TI
1001
1002int snd_hda_codec_prepare(struct hda_codec *codec,
1003 struct hda_pcm_stream *hinfo,
1004 unsigned int stream,
1005 unsigned int format,
1006 struct snd_pcm_substream *substream);
1007void snd_hda_codec_cleanup(struct hda_codec *codec,
1008 struct hda_pcm_stream *hinfo,
1009 struct snd_pcm_substream *substream);
1010
d01ce99f
TI
1011void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid,
1012 u32 stream_tag,
1da177e4 1013 int channel_id, int format);
f0cea797
TI
1014void __snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid,
1015 int do_now);
1016#define snd_hda_codec_cleanup_stream(codec, nid) \
1017 __snd_hda_codec_cleanup_stream(codec, nid, 0)
d01ce99f
TI
1018unsigned int snd_hda_calc_stream_format(unsigned int rate,
1019 unsigned int channels,
1020 unsigned int format,
32c168c8
AH
1021 unsigned int maxbps,
1022 unsigned short spdif_ctls);
1da177e4
LT
1023int snd_hda_is_supported_format(struct hda_codec *codec, hda_nid_t nid,
1024 unsigned int format);
1025
1026/*
1027 * Misc
1028 */
1029void snd_hda_get_codec_name(struct hda_codec *codec, char *name, int namelen);
fb8d1a34 1030void snd_hda_bus_reboot_notify(struct hda_bus *bus);
4d7fbdbc
TI
1031void snd_hda_codec_set_power_to_all(struct hda_codec *codec, hda_nid_t fg,
1032 unsigned int power_state,
1033 bool eapd_workaround);
1da177e4 1034
d3d020bd
TI
1035int snd_hda_lock_devices(struct hda_bus *bus);
1036void snd_hda_unlock_devices(struct hda_bus *bus);
1037
1da177e4
LT
1038/*
1039 * power management
1040 */
1041#ifdef CONFIG_PM
8dd78330 1042int snd_hda_suspend(struct hda_bus *bus);
1da177e4
LT
1043int snd_hda_resume(struct hda_bus *bus);
1044#endif
1045
9e5341b9
TI
1046static inline
1047int hda_call_check_power_status(struct hda_codec *codec, hda_nid_t nid)
1048{
83012a7c 1049#ifdef CONFIG_PM
9e5341b9
TI
1050 if (codec->patch_ops.check_power_status)
1051 return codec->patch_ops.check_power_status(codec, nid);
ff2b7e2a 1052#endif
9e5341b9
TI
1053 return 0;
1054}
9e5341b9 1055
50a9f790
MR
1056/*
1057 * get widget information
1058 */
1059const char *snd_hda_get_jack_connectivity(u32 cfg);
1060const char *snd_hda_get_jack_type(u32 cfg);
1061const char *snd_hda_get_jack_location(u32 cfg);
1062
cb53c626
TI
1063/*
1064 * power saving
1065 */
83012a7c 1066#ifdef CONFIG_PM
c376e2c7 1067void snd_hda_power_save(struct hda_codec *codec, int delta, bool d3wait);
a2f6309e 1068void snd_hda_update_power_acct(struct hda_codec *codec);
cb53c626 1069#else
c376e2c7
TI
1070static inline void snd_hda_power_save(struct hda_codec *codec, int delta,
1071 bool d3wait) {}
cb53c626
TI
1072#endif
1073
c376e2c7
TI
1074/**
1075 * snd_hda_power_up - Power-up the codec
1076 * @codec: HD-audio codec
1077 *
1078 * Increment the power-up counter and power up the hardware really when
1079 * not turned on yet.
1080 */
1081static inline void snd_hda_power_up(struct hda_codec *codec)
1082{
1083 snd_hda_power_save(codec, 1, false);
1084}
1085
1086/**
1087 * snd_hda_power_up_d3wait - Power-up the codec after waiting for any pending
1088 * D3 transition to complete. This differs from snd_hda_power_up() when
1089 * power_transition == -1. snd_hda_power_up sees this case as a nop,
1090 * snd_hda_power_up_d3wait waits for the D3 transition to complete then powers
1091 * back up.
1092 * @codec: HD-audio codec
1093 *
1094 * Cancel any power down operation hapenning on the work queue, then power up.
1095 */
1096static inline void snd_hda_power_up_d3wait(struct hda_codec *codec)
1097{
1098 snd_hda_power_save(codec, 1, true);
1099}
1100
1101/**
1102 * snd_hda_power_down - Power-down the codec
1103 * @codec: HD-audio codec
1104 *
1105 * Decrement the power-up counter and schedules the power-off work if
1106 * the counter rearches to zero.
1107 */
1108static inline void snd_hda_power_down(struct hda_codec *codec)
1109{
1110 snd_hda_power_save(codec, -1, false);
1111}
1112
1113/**
1114 * snd_hda_power_sync - Synchronize the power-save status
1115 * @codec: HD-audio codec
1116 *
1117 * Synchronize the actual power state with the power account;
1118 * called when power_save parameter is changed
1119 */
1120static inline void snd_hda_power_sync(struct hda_codec *codec)
1121{
1122 snd_hda_power_save(codec, 0, false);
1123}
1124
4ea6fbc8
TI
1125#ifdef CONFIG_SND_HDA_PATCH_LOADER
1126/*
1127 * patch firmware
1128 */
4918cdab 1129int snd_hda_load_patch(struct hda_bus *bus, size_t size, const void *buf);
4ea6fbc8
TI
1130#endif
1131
ff7a3267
TI
1132/*
1133 * Codec modularization
1134 */
1135
1136/* Export symbols only for communication with codec drivers;
1137 * When built in kernel, all HD-audio drivers are supposed to be statically
1138 * linked to the kernel. Thus, the symbols don't have to (or shouldn't) be
1139 * exported unless it's built as a module.
1140 */
1141#ifdef MODULE
1142#define EXPORT_SYMBOL_HDA(sym) EXPORT_SYMBOL_GPL(sym)
1143#else
1144#define EXPORT_SYMBOL_HDA(sym)
1145#endif
1146
1da177e4 1147#endif /* __SOUND_HDA_CODEC_H */
This page took 0.583125 seconds and 5 git commands to generate.