ALSA: hda: corrected invalid mixer values
[deliverable/linux.git] / sound / pci / hda / hda_codec.h
CommitLineData
1da177e4
LT
1/*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59
18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef __SOUND_HDA_CODEC_H
22#define __SOUND_HDA_CODEC_H
23
24#include <sound/info.h>
25#include <sound/control.h>
26#include <sound/pcm.h>
2807314d 27#include <sound/hwdep.h>
1da177e4 28
cb53c626
TI
29#if defined(CONFIG_PM) || defined(CONFIG_SND_HDA_POWER_SAVE)
30#define SND_HDA_NEEDS_RESUME /* resume control code is required */
31#endif
32
1da177e4
LT
33/*
34 * nodes
35 */
36#define AC_NODE_ROOT 0x00
37
38/*
39 * function group types
40 */
41enum {
42 AC_GRP_AUDIO_FUNCTION = 0x01,
43 AC_GRP_MODEM_FUNCTION = 0x02,
44};
45
46/*
47 * widget types
48 */
49enum {
50 AC_WID_AUD_OUT, /* Audio Out */
51 AC_WID_AUD_IN, /* Audio In */
52 AC_WID_AUD_MIX, /* Audio Mixer */
53 AC_WID_AUD_SEL, /* Audio Selector */
54 AC_WID_PIN, /* Pin Complex */
55 AC_WID_POWER, /* Power */
56 AC_WID_VOL_KNB, /* Volume Knob */
57 AC_WID_BEEP, /* Beep Generator */
58 AC_WID_VENDOR = 0x0f /* Vendor specific */
59};
60
61/*
62 * GET verbs
63 */
64#define AC_VERB_GET_STREAM_FORMAT 0x0a00
65#define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
66#define AC_VERB_GET_PROC_COEF 0x0c00
67#define AC_VERB_GET_COEF_INDEX 0x0d00
68#define AC_VERB_PARAMETERS 0x0f00
69#define AC_VERB_GET_CONNECT_SEL 0x0f01
70#define AC_VERB_GET_CONNECT_LIST 0x0f02
71#define AC_VERB_GET_PROC_STATE 0x0f03
72#define AC_VERB_GET_SDI_SELECT 0x0f04
73#define AC_VERB_GET_POWER_STATE 0x0f05
74#define AC_VERB_GET_CONV 0x0f06
75#define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07
76#define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08
77#define AC_VERB_GET_PIN_SENSE 0x0f09
78#define AC_VERB_GET_BEEP_CONTROL 0x0f0a
79#define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c
3982d17e 80#define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d
a1855d80 81#define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */
1da177e4
LT
82#define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f
83/* f10-f1a: GPIO */
16ded525
TI
84#define AC_VERB_GET_GPIO_DATA 0x0f15
85#define AC_VERB_GET_GPIO_MASK 0x0f16
86#define AC_VERB_GET_GPIO_DIRECTION 0x0f17
797760ab 87#define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18
3982d17e 88#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19
797760ab 89#define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a
1da177e4 90#define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c
86284e45
TI
91/* f20: AFG/MFG */
92#define AC_VERB_GET_SUBSYSTEM_ID 0x0f20
955d2488
TI
93#define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d
94#define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e
95#define AC_VERB_GET_HDMI_ELDD 0x0f2f
96#define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30
97#define AC_VERB_GET_HDMI_DIP_DATA 0x0f31
98#define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32
99#define AC_VERB_GET_HDMI_CP_CTRL 0x0f33
100#define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34
1da177e4
LT
101
102/*
103 * SET verbs
104 */
105#define AC_VERB_SET_STREAM_FORMAT 0x200
106#define AC_VERB_SET_AMP_GAIN_MUTE 0x300
107#define AC_VERB_SET_PROC_COEF 0x400
108#define AC_VERB_SET_COEF_INDEX 0x500
109#define AC_VERB_SET_CONNECT_SEL 0x701
110#define AC_VERB_SET_PROC_STATE 0x703
111#define AC_VERB_SET_SDI_SELECT 0x704
112#define AC_VERB_SET_POWER_STATE 0x705
113#define AC_VERB_SET_CHANNEL_STREAMID 0x706
114#define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707
115#define AC_VERB_SET_UNSOLICITED_ENABLE 0x708
116#define AC_VERB_SET_PIN_SENSE 0x709
117#define AC_VERB_SET_BEEP_CONTROL 0x70a
a2a20939 118#define AC_VERB_SET_EAPD_BTLENABLE 0x70c
1da177e4
LT
119#define AC_VERB_SET_DIGI_CONVERT_1 0x70d
120#define AC_VERB_SET_DIGI_CONVERT_2 0x70e
121#define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f
16ded525
TI
122#define AC_VERB_SET_GPIO_DATA 0x715
123#define AC_VERB_SET_GPIO_MASK 0x716
124#define AC_VERB_SET_GPIO_DIRECTION 0x717
797760ab 125#define AC_VERB_SET_GPIO_WAKE_MASK 0x718
3982d17e 126#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719
797760ab 127#define AC_VERB_SET_GPIO_STICKY_MASK 0x71a
1da177e4
LT
128#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c
129#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d
130#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e
131#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f
d0513fc6 132#define AC_VERB_SET_EAPD 0x788
1da177e4 133#define AC_VERB_SET_CODEC_RESET 0x7ff
955d2488
TI
134#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d
135#define AC_VERB_SET_HDMI_DIP_INDEX 0x730
136#define AC_VERB_SET_HDMI_DIP_DATA 0x731
137#define AC_VERB_SET_HDMI_DIP_XMIT 0x732
138#define AC_VERB_SET_HDMI_CP_CTRL 0x733
139#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734
1da177e4
LT
140
141/*
142 * Parameter IDs
143 */
144#define AC_PAR_VENDOR_ID 0x00
145#define AC_PAR_SUBSYSTEM_ID 0x01
146#define AC_PAR_REV_ID 0x02
147#define AC_PAR_NODE_COUNT 0x04
148#define AC_PAR_FUNCTION_TYPE 0x05
149#define AC_PAR_AUDIO_FG_CAP 0x08
150#define AC_PAR_AUDIO_WIDGET_CAP 0x09
151#define AC_PAR_PCM 0x0a
152#define AC_PAR_STREAM 0x0b
153#define AC_PAR_PIN_CAP 0x0c
154#define AC_PAR_AMP_IN_CAP 0x0d
155#define AC_PAR_CONNLIST_LEN 0x0e
156#define AC_PAR_POWER_STATE 0x0f
157#define AC_PAR_PROC_CAP 0x10
158#define AC_PAR_GPIO_CAP 0x11
159#define AC_PAR_AMP_OUT_CAP 0x12
e1716139 160#define AC_PAR_VOL_KNB_CAP 0x13
955d2488 161#define AC_PAR_HDMI_LPCM_CAP 0x20
1da177e4
LT
162
163/*
164 * AC_VERB_PARAMETERS results (32bit)
165 */
166
167/* Function Group Type */
168#define AC_FGT_TYPE (0xff<<0)
169#define AC_FGT_TYPE_SHIFT 0
170#define AC_FGT_UNSOL_CAP (1<<8)
171
172/* Audio Function Group Capabilities */
173#define AC_AFG_OUT_DELAY (0xf<<0)
174#define AC_AFG_IN_DELAY (0xf<<8)
175#define AC_AFG_BEEP_GEN (1<<16)
176
177/* Audio Widget Capabilities */
178#define AC_WCAP_STEREO (1<<0) /* stereo I/O */
179#define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
180#define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
181#define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
182#define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */
183#define AC_WCAP_STRIPE (1<<5) /* stripe */
184#define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */
185#define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */
186#define AC_WCAP_CONN_LIST (1<<8) /* connection list */
187#define AC_WCAP_DIGITAL (1<<9) /* digital I/O */
188#define AC_WCAP_POWER (1<<10) /* power control */
189#define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */
955d2488
TI
190#define AC_WCAP_CP_CAPS (1<<12) /* content protection */
191#define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */
1da177e4
LT
192#define AC_WCAP_DELAY (0xf<<16)
193#define AC_WCAP_DELAY_SHIFT 16
194#define AC_WCAP_TYPE (0xf<<20)
195#define AC_WCAP_TYPE_SHIFT 20
196
197/* supported PCM rates and bits */
198#define AC_SUPPCM_RATES (0xfff << 0)
199#define AC_SUPPCM_BITS_8 (1<<16)
200#define AC_SUPPCM_BITS_16 (1<<17)
201#define AC_SUPPCM_BITS_20 (1<<18)
202#define AC_SUPPCM_BITS_24 (1<<19)
203#define AC_SUPPCM_BITS_32 (1<<20)
204
205/* supported PCM stream format */
206#define AC_SUPFMT_PCM (1<<0)
207#define AC_SUPFMT_FLOAT32 (1<<1)
208#define AC_SUPFMT_AC3 (1<<2)
209
797760ab
AP
210/* GP I/O count */
211#define AC_GPIO_IO_COUNT (0xff<<0)
212#define AC_GPIO_O_COUNT (0xff<<8)
213#define AC_GPIO_O_COUNT_SHIFT 8
214#define AC_GPIO_I_COUNT (0xff<<16)
215#define AC_GPIO_I_COUNT_SHIFT 16
216#define AC_GPIO_UNSOLICITED (1<<30)
217#define AC_GPIO_WAKE (1<<31)
218
219/* Converter stream, channel */
220#define AC_CONV_CHANNEL (0xf<<0)
221#define AC_CONV_STREAM (0xf<<4)
222#define AC_CONV_STREAM_SHIFT 4
223
224/* Input converter SDI select */
225#define AC_SDI_SELECT (0xf<<0)
226
955d2488 227/* Unsolicited response control */
797760ab
AP
228#define AC_UNSOL_TAG (0x3f<<0)
229#define AC_UNSOL_ENABLED (1<<7)
955d2488
TI
230#define AC_USRSP_EN AC_UNSOL_ENABLED
231
232/* Unsolicited responses */
233#define AC_UNSOL_RES_TAG (0x3f<<26)
234#define AC_UNSOL_RES_TAG_SHIFT 26
235#define AC_UNSOL_RES_SUBTAG (0x1f<<21)
236#define AC_UNSOL_RES_SUBTAG_SHIFT 21
237#define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
238#define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */
239#define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */
240#define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */
797760ab 241
1da177e4
LT
242/* Pin widget capabilies */
243#define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
244#define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */
245#define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */
246#define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */
247#define AC_PINCAP_OUT (1<<4) /* output capable */
248#define AC_PINCAP_IN (1<<5) /* input capable */
249#define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */
3982d17e
AP
250/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,
251 * but is marked reserved in the Intel HDA specification.
252 */
253#define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */
955d2488
TI
254/* Note: The same bit as LR_SWAP is newly defined as HDMI capability
255 * in HD-audio specification
256 */
257#define AC_PINCAP_HDMI (1<<7) /* HDMI pin */
1a12de1e 258#define AC_PINCAP_VREF (0x37<<8)
1da177e4
LT
259#define AC_PINCAP_VREF_SHIFT 8
260#define AC_PINCAP_EAPD (1<<16) /* EAPD capable */
1a12de1e
M
261/* Vref status (used in pin cap) */
262#define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
263#define AC_PINCAP_VREF_50 (1<<1) /* 50% */
264#define AC_PINCAP_VREF_GRD (1<<2) /* ground */
265#define AC_PINCAP_VREF_80 (1<<4) /* 80% */
266#define AC_PINCAP_VREF_100 (1<<5) /* 100% */
1da177e4
LT
267
268/* Amplifier capabilities */
269#define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */
270#define AC_AMPCAP_OFFSET_SHIFT 0
271#define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */
272#define AC_AMPCAP_NUM_STEPS_SHIFT 8
d01ce99f
TI
273#define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB
274 * in 0.25dB
275 */
1da177e4
LT
276#define AC_AMPCAP_STEP_SIZE_SHIFT 16
277#define AC_AMPCAP_MUTE (1<<31) /* mute capable */
278#define AC_AMPCAP_MUTE_SHIFT 31
279
280/* Connection list */
281#define AC_CLIST_LENGTH (0x7f<<0)
282#define AC_CLIST_LONG (1<<7)
283
284/* Supported power status */
285#define AC_PWRST_D0SUP (1<<0)
286#define AC_PWRST_D1SUP (1<<1)
287#define AC_PWRST_D2SUP (1<<2)
288#define AC_PWRST_D3SUP (1<<3)
289
54d17403 290/* Power state values */
797760ab
AP
291#define AC_PWRST_SETTING (0xf<<0)
292#define AC_PWRST_ACTUAL (0xf<<4)
293#define AC_PWRST_ACTUAL_SHIFT 4
54d17403
TI
294#define AC_PWRST_D0 0x00
295#define AC_PWRST_D1 0x01
296#define AC_PWRST_D2 0x02
297#define AC_PWRST_D3 0x03
298
1da177e4
LT
299/* Processing capabilies */
300#define AC_PCAP_BENIGN (1<<0)
301#define AC_PCAP_NUM_COEF (0xff<<8)
797760ab 302#define AC_PCAP_NUM_COEF_SHIFT 8
1da177e4
LT
303
304/* Volume knobs capabilities */
305#define AC_KNBCAP_NUM_STEPS (0x7f<<0)
38fcaf8e 306#define AC_KNBCAP_DELTA (1<<7)
1da177e4 307
955d2488
TI
308/* HDMI LPCM capabilities */
309#define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
310#define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
311#define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */
312#define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */
313#define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
314#define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
315#define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */
316#define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */
317#define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
318#define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
319#define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */
320#define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */
321#define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */
322#define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */
323
1da177e4
LT
324/*
325 * Control Parameters
326 */
327
328/* Amp gain/mute */
d427c77e 329#define AC_AMP_MUTE (1<<7)
1da177e4
LT
330#define AC_AMP_GAIN (0x7f)
331#define AC_AMP_GET_INDEX (0xf<<0)
332
333#define AC_AMP_GET_LEFT (1<<13)
334#define AC_AMP_GET_RIGHT (0<<13)
335#define AC_AMP_GET_OUTPUT (1<<15)
336#define AC_AMP_GET_INPUT (0<<15)
337
338#define AC_AMP_SET_INDEX (0xf<<8)
339#define AC_AMP_SET_INDEX_SHIFT 8
340#define AC_AMP_SET_RIGHT (1<<12)
341#define AC_AMP_SET_LEFT (1<<13)
342#define AC_AMP_SET_INPUT (1<<14)
343#define AC_AMP_SET_OUTPUT (1<<15)
344
345/* DIGITAL1 bits */
346#define AC_DIG1_ENABLE (1<<0)
347#define AC_DIG1_V (1<<1)
348#define AC_DIG1_VCFG (1<<2)
349#define AC_DIG1_EMPHASIS (1<<3)
350#define AC_DIG1_COPYRIGHT (1<<4)
351#define AC_DIG1_NONAUDIO (1<<5)
352#define AC_DIG1_PROFESSIONAL (1<<6)
353#define AC_DIG1_LEVEL (1<<7)
354
797760ab
AP
355/* DIGITAL2 bits */
356#define AC_DIG2_CC (0x7f<<0)
357
1da177e4
LT
358/* Pin widget control - 8bit */
359#define AC_PINCTL_VREFEN (0x7<<0)
98f759a6
TI
360#define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */
361#define AC_PINCTL_VREF_50 1 /* 50% */
362#define AC_PINCTL_VREF_GRD 2 /* ground */
363#define AC_PINCTL_VREF_80 4 /* 80% */
364#define AC_PINCTL_VREF_100 5 /* 100% */
1da177e4
LT
365#define AC_PINCTL_IN_EN (1<<5)
366#define AC_PINCTL_OUT_EN (1<<6)
367#define AC_PINCTL_HP_EN (1<<7)
368
797760ab
AP
369/* Pin sense - 32bit */
370#define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff)
371#define AC_PINSENSE_PRESENCE (1<<31)
955d2488 372#define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */
797760ab
AP
373
374/* EAPD/BTL enable - 32bit */
375#define AC_EAPDBTL_BALANCED (1<<0)
376#define AC_EAPDBTL_EAPD (1<<1)
377#define AC_EAPDBTL_LR_SWAP (1<<2)
378
955d2488
TI
379/* HDMI ELD data */
380#define AC_ELDD_ELD_VALID (1<<31)
381#define AC_ELDD_ELD_DATA 0xff
382
383/* HDMI DIP size */
384#define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */
385#define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */
386
387/* HDMI DIP index */
388#define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */
389#define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */
390
391/* HDMI DIP xmit (transmit) control */
392#define AC_DIPXMIT_MASK (0x3<<6)
393#define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */
394#define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */
395#define AC_DIPXMIT_BEST (0x3<<6) /* best effort */
396
397/* HDMI content protection (CP) control */
398#define AC_CPCTRL_CES (1<<9) /* current encryption state */
399#define AC_CPCTRL_READY (1<<8) /* ready bit */
400#define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */
401#define AC_CPCTRL_STATE (3<<0) /* current CP request state */
402
403/* Converter channel <-> HDMI slot mapping */
404#define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */
405#define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */
406
1da177e4
LT
407/* configuration default - 32bit */
408#define AC_DEFCFG_SEQUENCE (0xf<<0)
409#define AC_DEFCFG_DEF_ASSOC (0xf<<4)
d21b37ea 410#define AC_DEFCFG_ASSOC_SHIFT 4
1da177e4 411#define AC_DEFCFG_MISC (0xf<<8)
d21b37ea 412#define AC_DEFCFG_MISC_SHIFT 8
797760ab 413#define AC_DEFCFG_MISC_NO_PRESENCE (1<<0)
1da177e4
LT
414#define AC_DEFCFG_COLOR (0xf<<12)
415#define AC_DEFCFG_COLOR_SHIFT 12
416#define AC_DEFCFG_CONN_TYPE (0xf<<16)
417#define AC_DEFCFG_CONN_TYPE_SHIFT 16
418#define AC_DEFCFG_DEVICE (0xf<<20)
419#define AC_DEFCFG_DEVICE_SHIFT 20
420#define AC_DEFCFG_LOCATION (0x3f<<24)
421#define AC_DEFCFG_LOCATION_SHIFT 24
422#define AC_DEFCFG_PORT_CONN (0x3<<30)
423#define AC_DEFCFG_PORT_CONN_SHIFT 30
424
425/* device device types (0x0-0xf) */
426enum {
427 AC_JACK_LINE_OUT,
428 AC_JACK_SPEAKER,
429 AC_JACK_HP_OUT,
430 AC_JACK_CD,
431 AC_JACK_SPDIF_OUT,
432 AC_JACK_DIG_OTHER_OUT,
433 AC_JACK_MODEM_LINE_SIDE,
434 AC_JACK_MODEM_HAND_SIDE,
435 AC_JACK_LINE_IN,
436 AC_JACK_AUX,
437 AC_JACK_MIC_IN,
438 AC_JACK_TELEPHONY,
439 AC_JACK_SPDIF_IN,
440 AC_JACK_DIG_OTHER_IN,
441 AC_JACK_OTHER = 0xf,
442};
443
444/* jack connection types (0x0-0xf) */
445enum {
446 AC_JACK_CONN_UNKNOWN,
447 AC_JACK_CONN_1_8,
448 AC_JACK_CONN_1_4,
449 AC_JACK_CONN_ATAPI,
450 AC_JACK_CONN_RCA,
451 AC_JACK_CONN_OPTICAL,
452 AC_JACK_CONN_OTHER_DIGITAL,
453 AC_JACK_CONN_OTHER_ANALOG,
454 AC_JACK_CONN_DIN,
455 AC_JACK_CONN_XLR,
456 AC_JACK_CONN_RJ11,
457 AC_JACK_CONN_COMB,
458 AC_JACK_CONN_OTHER = 0xf,
459};
460
461/* jack colors (0x0-0xf) */
462enum {
463 AC_JACK_COLOR_UNKNOWN,
464 AC_JACK_COLOR_BLACK,
465 AC_JACK_COLOR_GREY,
466 AC_JACK_COLOR_BLUE,
467 AC_JACK_COLOR_GREEN,
468 AC_JACK_COLOR_RED,
469 AC_JACK_COLOR_ORANGE,
470 AC_JACK_COLOR_YELLOW,
471 AC_JACK_COLOR_PURPLE,
472 AC_JACK_COLOR_PINK,
473 AC_JACK_COLOR_WHITE = 0xe,
474 AC_JACK_COLOR_OTHER,
475};
476
477/* Jack location (0x0-0x3f) */
478/* common case */
479enum {
480 AC_JACK_LOC_NONE,
481 AC_JACK_LOC_REAR,
482 AC_JACK_LOC_FRONT,
483 AC_JACK_LOC_LEFT,
484 AC_JACK_LOC_RIGHT,
485 AC_JACK_LOC_TOP,
486 AC_JACK_LOC_BOTTOM,
487};
488/* bits 4-5 */
489enum {
490 AC_JACK_LOC_EXTERNAL = 0x00,
491 AC_JACK_LOC_INTERNAL = 0x10,
492 AC_JACK_LOC_SEPARATE = 0x20,
493 AC_JACK_LOC_OTHER = 0x30,
494};
495enum {
496 /* external on primary chasis */
497 AC_JACK_LOC_REAR_PANEL = 0x07,
498 AC_JACK_LOC_DRIVE_BAY,
499 /* internal */
500 AC_JACK_LOC_RISER = 0x17,
501 AC_JACK_LOC_HDMI,
502 AC_JACK_LOC_ATAPI,
503 /* others */
504 AC_JACK_LOC_MOBILE_IN = 0x37,
505 AC_JACK_LOC_MOBILE_OUT,
506};
507
508/* Port connectivity (0-3) */
509enum {
510 AC_JACK_PORT_COMPLEX,
511 AC_JACK_PORT_NONE,
512 AC_JACK_PORT_FIXED,
513 AC_JACK_PORT_BOTH,
514};
515
516/* max. connections to a widget */
54d17403 517#define HDA_MAX_CONNECTIONS 32
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518
519/* max. codec address */
520#define HDA_MAX_CODEC_ADDRESS 0x0f
521
522/*
523 * Structures
524 */
525
526struct hda_bus;
1cd2224c 527struct hda_beep;
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528struct hda_codec;
529struct hda_pcm;
530struct hda_pcm_stream;
531struct hda_bus_unsolicited;
532
533/* NID type */
534typedef u16 hda_nid_t;
535
536/* bus operators */
537struct hda_bus_ops {
538 /* send a single command */
539 int (*command)(struct hda_codec *codec, hda_nid_t nid, int direct,
540 unsigned int verb, unsigned int parm);
541 /* get a response from the last command */
542 unsigned int (*get_response)(struct hda_codec *codec);
543 /* free the private data */
544 void (*private_free)(struct hda_bus *);
cb53c626 545#ifdef CONFIG_SND_HDA_POWER_SAVE
561de31a 546 /* notify power-up/down from codec to controller */
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547 void (*pm_notify)(struct hda_codec *codec);
548#endif
1da177e4
LT
549};
550
551/* template to pass to the bus constructor */
552struct hda_bus_template {
553 void *private_data;
554 struct pci_dev *pci;
555 const char *modelname;
556 struct hda_bus_ops ops;
557};
558
559/*
560 * codec bus
561 *
562 * each controller needs to creata a hda_bus to assign the accessor.
563 * A hda_bus contains several codecs in the list codec_list.
564 */
565struct hda_bus {
c8b6bf9b 566 struct snd_card *card;
1da177e4
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567
568 /* copied from template */
569 void *private_data;
570 struct pci_dev *pci;
571 const char *modelname;
572 struct hda_bus_ops ops;
573
574 /* codec linked list */
575 struct list_head codec_list;
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576 /* link caddr -> codec */
577 struct hda_codec *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
1da177e4 578
62932df8 579 struct mutex cmd_mutex;
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LT
580
581 /* unsolicited event queue */
582 struct hda_bus_unsolicited *unsol;
583
c8b6bf9b 584 struct snd_info_entry *proc;
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585
586 /* misc op flags */
587 unsigned int needs_damn_long_delay :1;
1da177e4
LT
588};
589
590/*
591 * codec preset
592 *
593 * Known codecs have the patch to build and set up the controls/PCMs
594 * better than the generic parser.
595 */
596struct hda_codec_preset {
597 unsigned int id;
598 unsigned int mask;
599 unsigned int subs;
600 unsigned int subs_mask;
601 unsigned int rev;
ca7cfae9 602 hda_nid_t afg, mfg;
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LT
603 const char *name;
604 int (*patch)(struct hda_codec *codec);
605};
606
607/* ops set by the preset patch */
608struct hda_codec_ops {
609 int (*build_controls)(struct hda_codec *codec);
610 int (*build_pcms)(struct hda_codec *codec);
611 int (*init)(struct hda_codec *codec);
612 void (*free)(struct hda_codec *codec);
613 void (*unsol_event)(struct hda_codec *codec, unsigned int res);
cb53c626 614#ifdef SND_HDA_NEEDS_RESUME
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615 int (*suspend)(struct hda_codec *codec, pm_message_t state);
616 int (*resume)(struct hda_codec *codec);
617#endif
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618#ifdef CONFIG_SND_HDA_POWER_SAVE
619 int (*check_power_status)(struct hda_codec *codec, hda_nid_t nid);
620#endif
1da177e4
LT
621};
622
623/* record for amp information cache */
01751f54 624struct hda_cache_head {
1da177e4 625 u32 key; /* hash key */
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626 u16 val; /* assigned value */
627 u16 next; /* next link; -1 = terminal */
628};
629
630struct hda_amp_info {
631 struct hda_cache_head head;
1da177e4 632 u32 amp_caps; /* amp capabilities */
7f0e2f8b 633 u16 vol[2]; /* current volume & mute */
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634};
635
636struct hda_cache_rec {
637 u16 hash[64]; /* hash table for index */
638 unsigned int num_entries; /* number of assigned entries */
639 unsigned int size; /* allocated size */
640 unsigned int record_size; /* record size (including header) */
641 void *buffer; /* hash table entries */
1da177e4
LT
642};
643
644/* PCM callbacks */
645struct hda_pcm_ops {
646 int (*open)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 647 struct snd_pcm_substream *substream);
1da177e4 648 int (*close)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 649 struct snd_pcm_substream *substream);
1da177e4
LT
650 int (*prepare)(struct hda_pcm_stream *info, struct hda_codec *codec,
651 unsigned int stream_tag, unsigned int format,
c8b6bf9b 652 struct snd_pcm_substream *substream);
1da177e4 653 int (*cleanup)(struct hda_pcm_stream *info, struct hda_codec *codec,
c8b6bf9b 654 struct snd_pcm_substream *substream);
1da177e4
LT
655};
656
657/* PCM information for each substream */
658struct hda_pcm_stream {
d01ce99f 659 unsigned int substreams; /* number of substreams, 0 = not exist*/
1da177e4
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660 unsigned int channels_min; /* min. number of channels */
661 unsigned int channels_max; /* max. number of channels */
662 hda_nid_t nid; /* default NID to query rates/formats/bps, or set up */
663 u32 rates; /* supported rates */
664 u64 formats; /* supported formats (SNDRV_PCM_FMTBIT_) */
665 unsigned int maxbps; /* supported max. bit per sample */
666 struct hda_pcm_ops ops;
667};
668
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669/* PCM types */
670enum {
671 HDA_PCM_TYPE_AUDIO,
672 HDA_PCM_TYPE_SPDIF,
673 HDA_PCM_TYPE_HDMI,
674 HDA_PCM_TYPE_MODEM,
675 HDA_PCM_NTYPES
676};
677
1da177e4
LT
678/* for PCM creation */
679struct hda_pcm {
680 char *name;
681 struct hda_pcm_stream stream[2];
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682 unsigned int pcm_type; /* HDA_PCM_TYPE_XXX */
683 int device; /* assigned device number */
1da177e4
LT
684};
685
686/* codec information */
687struct hda_codec {
688 struct hda_bus *bus;
689 unsigned int addr; /* codec addr*/
690 struct list_head list; /* list point */
691
692 hda_nid_t afg; /* AFG node id */
673b683a 693 hda_nid_t mfg; /* MFG node id */
1da177e4
LT
694
695 /* ids */
696 u32 vendor_id;
697 u32 subsystem_id;
698 u32 revision_id;
699
700 /* detected preset */
701 const struct hda_codec_preset *preset;
702
703 /* set by patch */
704 struct hda_codec_ops patch_ops;
705
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706 /* PCM to create, set by patch_ops.build_pcms callback */
707 unsigned int num_pcms;
708 struct hda_pcm *pcm_info;
709
710 /* codec specific info */
711 void *spec;
712
1cd2224c
MR
713 /* beep device */
714 struct hda_beep *beep;
715
54d17403
TI
716 /* widget capabilities cache */
717 unsigned int num_nodes;
718 hda_nid_t start_nid;
719 u32 *wcaps;
720
01751f54 721 struct hda_cache_rec amp_cache; /* cache for amp access */
b3ac5636 722 struct hda_cache_rec cmd_cache; /* cache for other commands */
1da177e4 723
62932df8 724 struct mutex spdif_mutex;
1da177e4
LT
725 unsigned int spdif_status; /* IEC958 status bits */
726 unsigned short spdif_ctls; /* SPDIF control bits */
727 unsigned int spdif_in_enable; /* SPDIF input enable? */
de51ca12 728 hda_nid_t *slave_dig_outs; /* optional digital out slave widgets */
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729
730 struct snd_hwdep *hwdep; /* assigned hwdep device */
cb53c626 731
963f803f
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732 /* misc flags */
733 unsigned int spdif_status_reset :1; /* needs to toggle SPDIF for each
734 * status change
735 * (e.g. Realtek codecs)
736 */
cb53c626 737#ifdef CONFIG_SND_HDA_POWER_SAVE
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738 unsigned int power_on :1; /* current (global) power-state */
739 unsigned int power_transition :1; /* power-state in transition */
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740 int power_count; /* current (global) power refcount */
741 struct delayed_work power_work; /* delayed task for powerdown */
742#endif
1da177e4
LT
743};
744
745/* direction */
746enum {
747 HDA_INPUT, HDA_OUTPUT
748};
749
750
751/*
752 * constructors
753 */
c8b6bf9b 754int snd_hda_bus_new(struct snd_card *card, const struct hda_bus_template *temp,
1da177e4
LT
755 struct hda_bus **busp);
756int snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr,
757 struct hda_codec **codecp);
758
759/*
760 * low level functions
761 */
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762unsigned int snd_hda_codec_read(struct hda_codec *codec, hda_nid_t nid,
763 int direct,
1da177e4
LT
764 unsigned int verb, unsigned int parm);
765int snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int direct,
766 unsigned int verb, unsigned int parm);
d01ce99f
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767#define snd_hda_param_read(codec, nid, param) \
768 snd_hda_codec_read(codec, nid, 0, AC_VERB_PARAMETERS, param)
769int snd_hda_get_sub_nodes(struct hda_codec *codec, hda_nid_t nid,
770 hda_nid_t *start_id);
771int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid,
772 hda_nid_t *conn_list, int max_conns);
1da177e4
LT
773
774struct hda_verb {
775 hda_nid_t nid;
776 u32 verb;
777 u32 param;
778};
779
d01ce99f
TI
780void snd_hda_sequence_write(struct hda_codec *codec,
781 const struct hda_verb *seq);
1da177e4
LT
782
783/* unsolicited event */
784int snd_hda_queue_unsol_event(struct hda_bus *bus, u32 res, u32 res_ex);
785
b3ac5636 786/* cached write */
cb53c626 787#ifdef SND_HDA_NEEDS_RESUME
b3ac5636
TI
788int snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid,
789 int direct, unsigned int verb, unsigned int parm);
790void snd_hda_sequence_write_cache(struct hda_codec *codec,
791 const struct hda_verb *seq);
792void snd_hda_codec_resume_cache(struct hda_codec *codec);
82beb8fd
TI
793#else
794#define snd_hda_codec_write_cache snd_hda_codec_write
795#define snd_hda_sequence_write_cache snd_hda_sequence_write
796#endif
b3ac5636 797
1da177e4
LT
798/*
799 * Mixer
800 */
801int snd_hda_build_controls(struct hda_bus *bus);
802
803/*
804 * PCM
805 */
806int snd_hda_build_pcms(struct hda_bus *bus);
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TI
807void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid,
808 u32 stream_tag,
1da177e4 809 int channel_id, int format);
888afa15 810void snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid);
d01ce99f
TI
811unsigned int snd_hda_calc_stream_format(unsigned int rate,
812 unsigned int channels,
813 unsigned int format,
814 unsigned int maxbps);
1da177e4
LT
815int snd_hda_query_supported_pcm(struct hda_codec *codec, hda_nid_t nid,
816 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
817int snd_hda_is_supported_format(struct hda_codec *codec, hda_nid_t nid,
818 unsigned int format);
819
820/*
821 * Misc
822 */
823void snd_hda_get_codec_name(struct hda_codec *codec, char *name, int namelen);
824
825/*
826 * power management
827 */
828#ifdef CONFIG_PM
829int snd_hda_suspend(struct hda_bus *bus, pm_message_t state);
830int snd_hda_resume(struct hda_bus *bus);
831#endif
832
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TI
833/*
834 * power saving
835 */
836#ifdef CONFIG_SND_HDA_POWER_SAVE
837void snd_hda_power_up(struct hda_codec *codec);
838void snd_hda_power_down(struct hda_codec *codec);
d804ad92
ML
839#define snd_hda_codec_needs_resume(codec) codec->power_count
840int snd_hda_codecs_inuse(struct hda_bus *bus);
cb53c626
TI
841#else
842static inline void snd_hda_power_up(struct hda_codec *codec) {}
843static inline void snd_hda_power_down(struct hda_codec *codec) {}
d804ad92
ML
844#define snd_hda_codec_needs_resume(codec) 1
845#define snd_hda_codecs_inuse(bus) 1
cb53c626
TI
846#endif
847
1da177e4 848#endif /* __SOUND_HDA_CODEC_H */
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