Commit | Line | Data |
---|---|---|
05e84878 DR |
1 | /* |
2 | * | |
3 | * Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clocksource.h> | |
24 | #include <linux/delay.h> | |
f0b1df88 | 25 | #include <linux/interrupt.h> |
05e84878 DR |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
154867cf | 28 | #include <linux/pm_runtime.h> |
05e84878 DR |
29 | #include <linux/slab.h> |
30 | #include <sound/core.h> | |
31 | #include <sound/initval.h> | |
05e84878 DR |
32 | #include "hda_controller.h" |
33 | ||
43db4a59 TI |
34 | #define CREATE_TRACE_POINTS |
35 | #include "hda_intel_trace.h" | |
36 | ||
2b5fd6c2 | 37 | /* DSP lock helpers */ |
7833c3f8 TI |
38 | #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev)) |
39 | #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev)) | |
40 | #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev)) | |
2b5fd6c2 | 41 | |
05e84878 DR |
42 | /* assign a stream for the PCM */ |
43 | static inline struct azx_dev * | |
44 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
45 | { | |
7833c3f8 TI |
46 | struct hdac_stream *s; |
47 | ||
48 | s = snd_hdac_stream_assign(azx_bus(chip), substream); | |
49 | if (!s) | |
50 | return NULL; | |
51 | return stream_to_azx_dev(s); | |
05e84878 DR |
52 | } |
53 | ||
54 | /* release the assigned stream */ | |
55 | static inline void azx_release_device(struct azx_dev *azx_dev) | |
56 | { | |
7833c3f8 | 57 | snd_hdac_stream_release(azx_stream(azx_dev)); |
05e84878 DR |
58 | } |
59 | ||
820cc6cf TI |
60 | static inline struct hda_pcm_stream * |
61 | to_hda_pcm_stream(struct snd_pcm_substream *substream) | |
62 | { | |
63 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
64 | return &apcm->info->stream[substream->stream]; | |
65 | } | |
66 | ||
05e84878 DR |
67 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, |
68 | u64 nsec) | |
69 | { | |
70 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 71 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
72 | u64 codec_frames, codec_nsecs; |
73 | ||
74 | if (!hinfo->ops.get_delay) | |
75 | return nsec; | |
76 | ||
77 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | |
78 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
79 | substream->runtime->rate); | |
80 | ||
81 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
82 | return nsec + codec_nsecs; | |
83 | ||
84 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | |
85 | } | |
86 | ||
05e84878 DR |
87 | /* |
88 | * PCM ops | |
89 | */ | |
90 | ||
91 | static int azx_pcm_close(struct snd_pcm_substream *substream) | |
92 | { | |
93 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 94 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
95 | struct azx *chip = apcm->chip; |
96 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
05e84878 DR |
97 | |
98 | mutex_lock(&chip->open_mutex); | |
05e84878 | 99 | azx_release_device(azx_dev); |
61ca4107 TI |
100 | if (hinfo->ops.close) |
101 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
05e84878 DR |
102 | snd_hda_power_down(apcm->codec); |
103 | mutex_unlock(&chip->open_mutex); | |
9a6246ff | 104 | snd_hda_codec_pcm_put(apcm->info); |
05e84878 DR |
105 | return 0; |
106 | } | |
107 | ||
108 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, | |
109 | struct snd_pcm_hw_params *hw_params) | |
110 | { | |
111 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
112 | struct azx *chip = apcm->chip; | |
602518a2 | 113 | struct azx_dev *azx_dev = get_azx_dev(substream); |
05e84878 DR |
114 | int ret; |
115 | ||
602518a2 TI |
116 | dsp_lock(azx_dev); |
117 | if (dsp_is_locked(azx_dev)) { | |
05e84878 DR |
118 | ret = -EBUSY; |
119 | goto unlock; | |
120 | } | |
121 | ||
602518a2 TI |
122 | azx_dev->core.bufsize = 0; |
123 | azx_dev->core.period_bytes = 0; | |
124 | azx_dev->core.format_val = 0; | |
05e84878 DR |
125 | ret = chip->ops->substream_alloc_pages(chip, substream, |
126 | params_buffer_bytes(hw_params)); | |
127 | unlock: | |
602518a2 | 128 | dsp_unlock(azx_dev); |
05e84878 DR |
129 | return ret; |
130 | } | |
131 | ||
132 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | |
133 | { | |
134 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
135 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
136 | struct azx *chip = apcm->chip; | |
820cc6cf | 137 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
138 | int err; |
139 | ||
140 | /* reset BDL address */ | |
141 | dsp_lock(azx_dev); | |
ccc98865 TI |
142 | if (!dsp_is_locked(azx_dev)) |
143 | snd_hdac_stream_cleanup(azx_stream(azx_dev)); | |
05e84878 DR |
144 | |
145 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); | |
146 | ||
147 | err = chip->ops->substream_free_pages(chip, substream); | |
6d23c8f5 | 148 | azx_stream(azx_dev)->prepared = 0; |
05e84878 DR |
149 | dsp_unlock(azx_dev); |
150 | return err; | |
151 | } | |
152 | ||
153 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | |
154 | { | |
155 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
156 | struct azx *chip = apcm->chip; | |
157 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
820cc6cf | 158 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 | 159 | struct snd_pcm_runtime *runtime = substream->runtime; |
0dd76f36 | 160 | unsigned int format_val, stream_tag; |
05e84878 DR |
161 | int err; |
162 | struct hda_spdif_out *spdif = | |
163 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | |
164 | unsigned short ctls = spdif ? spdif->ctls : 0; | |
165 | ||
166 | dsp_lock(azx_dev); | |
167 | if (dsp_is_locked(azx_dev)) { | |
168 | err = -EBUSY; | |
169 | goto unlock; | |
170 | } | |
171 | ||
7833c3f8 | 172 | snd_hdac_stream_reset(azx_stream(azx_dev)); |
b7d023e1 | 173 | format_val = snd_hdac_calc_stream_format(runtime->rate, |
05e84878 DR |
174 | runtime->channels, |
175 | runtime->format, | |
176 | hinfo->maxbps, | |
177 | ctls); | |
178 | if (!format_val) { | |
179 | dev_err(chip->card->dev, | |
180 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
181 | runtime->rate, runtime->channels, runtime->format); | |
182 | err = -EINVAL; | |
183 | goto unlock; | |
184 | } | |
185 | ||
0dd76f36 TI |
186 | err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val); |
187 | if (err < 0) | |
188 | goto unlock; | |
05e84878 | 189 | |
ccc98865 | 190 | snd_hdac_stream_setup(azx_stream(azx_dev)); |
05e84878 | 191 | |
7833c3f8 | 192 | stream_tag = azx_dev->core.stream_tag; |
05e84878 DR |
193 | /* CA-IBG chips need the playback stream starting from 1 */ |
194 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && | |
195 | stream_tag > chip->capture_streams) | |
196 | stream_tag -= chip->capture_streams; | |
197 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, | |
7833c3f8 | 198 | azx_dev->core.format_val, substream); |
05e84878 DR |
199 | |
200 | unlock: | |
201 | if (!err) | |
6d23c8f5 | 202 | azx_stream(azx_dev)->prepared = 1; |
05e84878 DR |
203 | dsp_unlock(azx_dev); |
204 | return err; | |
205 | } | |
206 | ||
207 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | |
208 | { | |
209 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
210 | struct azx *chip = apcm->chip; | |
a41d1224 | 211 | struct hdac_bus *bus = azx_bus(chip); |
05e84878 DR |
212 | struct azx_dev *azx_dev; |
213 | struct snd_pcm_substream *s; | |
ccc98865 TI |
214 | struct hdac_stream *hstr; |
215 | bool start; | |
216 | int sbits = 0; | |
217 | int sync_reg; | |
05e84878 DR |
218 | |
219 | azx_dev = get_azx_dev(substream); | |
43db4a59 TI |
220 | trace_azx_pcm_trigger(chip, azx_dev, cmd); |
221 | ||
ccc98865 TI |
222 | hstr = azx_stream(azx_dev); |
223 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
224 | sync_reg = AZX_REG_OLD_SSYNC; | |
225 | else | |
226 | sync_reg = AZX_REG_SSYNC; | |
05e84878 | 227 | |
6d23c8f5 | 228 | if (dsp_is_locked(azx_dev) || !hstr->prepared) |
05e84878 DR |
229 | return -EPIPE; |
230 | ||
231 | switch (cmd) { | |
232 | case SNDRV_PCM_TRIGGER_START: | |
05e84878 DR |
233 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
234 | case SNDRV_PCM_TRIGGER_RESUME: | |
ccc98865 | 235 | start = true; |
05e84878 DR |
236 | break; |
237 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
238 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
239 | case SNDRV_PCM_TRIGGER_STOP: | |
ccc98865 | 240 | start = false; |
05e84878 DR |
241 | break; |
242 | default: | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | snd_pcm_group_for_each_entry(s, substream) { | |
247 | if (s->pcm->card != substream->pcm->card) | |
248 | continue; | |
249 | azx_dev = get_azx_dev(s); | |
7833c3f8 | 250 | sbits |= 1 << azx_dev->core.index; |
05e84878 DR |
251 | snd_pcm_trigger_done(s, substream); |
252 | } | |
253 | ||
a41d1224 | 254 | spin_lock(&bus->reg_lock); |
05e84878 DR |
255 | |
256 | /* first, set SYNC bits of corresponding streams */ | |
ccc98865 | 257 | snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg); |
05e84878 DR |
258 | |
259 | snd_pcm_group_for_each_entry(s, substream) { | |
260 | if (s->pcm->card != substream->pcm->card) | |
261 | continue; | |
262 | azx_dev = get_azx_dev(s); | |
263 | if (start) { | |
7833c3f8 TI |
264 | azx_dev->insufficient = 1; |
265 | snd_hdac_stream_start(azx_stream(azx_dev), true); | |
05e84878 | 266 | } else { |
7833c3f8 | 267 | snd_hdac_stream_stop(azx_stream(azx_dev)); |
05e84878 | 268 | } |
05e84878 | 269 | } |
a41d1224 | 270 | spin_unlock(&bus->reg_lock); |
ccc98865 TI |
271 | |
272 | snd_hdac_stream_sync(hstr, start, sbits); | |
273 | ||
a41d1224 | 274 | spin_lock(&bus->reg_lock); |
05e84878 | 275 | /* reset SYNC bits */ |
ccc98865 TI |
276 | snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg); |
277 | if (start) | |
278 | snd_hdac_stream_timecounter_init(hstr, sbits); | |
a41d1224 | 279 | spin_unlock(&bus->reg_lock); |
05e84878 DR |
280 | return 0; |
281 | } | |
282 | ||
b6050ef6 | 283 | unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 | 284 | { |
7833c3f8 | 285 | return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
b6050ef6 TI |
286 | } |
287 | EXPORT_SYMBOL_GPL(azx_get_pos_lpib); | |
05e84878 | 288 | |
b6050ef6 TI |
289 | unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) |
290 | { | |
7833c3f8 | 291 | return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev)); |
05e84878 | 292 | } |
b6050ef6 | 293 | EXPORT_SYMBOL_GPL(azx_get_pos_posbuf); |
05e84878 DR |
294 | |
295 | unsigned int azx_get_position(struct azx *chip, | |
b6050ef6 | 296 | struct azx_dev *azx_dev) |
05e84878 | 297 | { |
7833c3f8 | 298 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
05e84878 DR |
299 | unsigned int pos; |
300 | int stream = substream->stream; | |
05e84878 DR |
301 | int delay = 0; |
302 | ||
b6050ef6 TI |
303 | if (chip->get_position[stream]) |
304 | pos = chip->get_position[stream](chip, azx_dev); | |
305 | else /* use the position buffer as default */ | |
306 | pos = azx_get_pos_posbuf(chip, azx_dev); | |
05e84878 | 307 | |
7833c3f8 | 308 | if (pos >= azx_dev->core.bufsize) |
05e84878 DR |
309 | pos = 0; |
310 | ||
05e84878 | 311 | if (substream->runtime) { |
b6050ef6 | 312 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
820cc6cf | 313 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
b6050ef6 TI |
314 | |
315 | if (chip->get_delay[stream]) | |
316 | delay += chip->get_delay[stream](chip, azx_dev, pos); | |
05e84878 DR |
317 | if (hinfo->ops.get_delay) |
318 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | |
319 | substream); | |
320 | substream->runtime->delay = delay; | |
321 | } | |
322 | ||
43db4a59 | 323 | trace_azx_get_position(chip, azx_dev, pos, delay); |
05e84878 DR |
324 | return pos; |
325 | } | |
326 | EXPORT_SYMBOL_GPL(azx_get_position); | |
327 | ||
328 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
329 | { | |
330 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
331 | struct azx *chip = apcm->chip; | |
332 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
333 | return bytes_to_frames(substream->runtime, | |
b6050ef6 | 334 | azx_get_position(chip, azx_dev)); |
05e84878 DR |
335 | } |
336 | ||
9e94df3a PLB |
337 | static int azx_get_time_info(struct snd_pcm_substream *substream, |
338 | struct timespec *system_ts, struct timespec *audio_ts, | |
339 | struct snd_pcm_audio_tstamp_config *audio_tstamp_config, | |
340 | struct snd_pcm_audio_tstamp_report *audio_tstamp_report) | |
05e84878 DR |
341 | { |
342 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
343 | u64 nsec; | |
344 | ||
9e94df3a PLB |
345 | if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && |
346 | (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { | |
05e84878 | 347 | |
9e94df3a PLB |
348 | snd_pcm_gettime(substream->runtime, system_ts); |
349 | ||
7833c3f8 | 350 | nsec = timecounter_read(&azx_dev->core.tc); |
9e94df3a PLB |
351 | nsec = div_u64(nsec, 3); /* can be optimized */ |
352 | if (audio_tstamp_config->report_delay) | |
353 | nsec = azx_adjust_codec_delay(substream, nsec); | |
354 | ||
355 | *audio_ts = ns_to_timespec(nsec); | |
356 | ||
357 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; | |
358 | audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */ | |
359 | audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */ | |
360 | ||
361 | } else | |
362 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; | |
05e84878 DR |
363 | |
364 | return 0; | |
365 | } | |
366 | ||
367 | static struct snd_pcm_hardware azx_pcm_hw = { | |
368 | .info = (SNDRV_PCM_INFO_MMAP | | |
369 | SNDRV_PCM_INFO_INTERLEAVED | | |
370 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
371 | SNDRV_PCM_INFO_MMAP_VALID | | |
372 | /* No full-resume yet implemented */ | |
373 | /* SNDRV_PCM_INFO_RESUME |*/ | |
374 | SNDRV_PCM_INFO_PAUSE | | |
375 | SNDRV_PCM_INFO_SYNC_START | | |
9e94df3a PLB |
376 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ |
377 | SNDRV_PCM_INFO_HAS_LINK_ATIME | | |
05e84878 DR |
378 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), |
379 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
380 | .rates = SNDRV_PCM_RATE_48000, | |
381 | .rate_min = 48000, | |
382 | .rate_max = 48000, | |
383 | .channels_min = 2, | |
384 | .channels_max = 2, | |
385 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
386 | .period_bytes_min = 128, | |
387 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
388 | .periods_min = 2, | |
389 | .periods_max = AZX_MAX_FRAG, | |
390 | .fifo_size = 0, | |
391 | }; | |
392 | ||
393 | static int azx_pcm_open(struct snd_pcm_substream *substream) | |
394 | { | |
395 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 396 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
397 | struct azx *chip = apcm->chip; |
398 | struct azx_dev *azx_dev; | |
399 | struct snd_pcm_runtime *runtime = substream->runtime; | |
05e84878 DR |
400 | int err; |
401 | int buff_step; | |
402 | ||
9a6246ff | 403 | snd_hda_codec_pcm_get(apcm->info); |
05e84878 DR |
404 | mutex_lock(&chip->open_mutex); |
405 | azx_dev = azx_assign_device(chip, substream); | |
406 | if (azx_dev == NULL) { | |
61ca4107 TI |
407 | err = -EBUSY; |
408 | goto unlock; | |
05e84878 | 409 | } |
ccc98865 | 410 | runtime->private_data = azx_dev; |
05e84878 DR |
411 | runtime->hw = azx_pcm_hw; |
412 | runtime->hw.channels_min = hinfo->channels_min; | |
413 | runtime->hw.channels_max = hinfo->channels_max; | |
414 | runtime->hw.formats = hinfo->formats; | |
415 | runtime->hw.rates = hinfo->rates; | |
416 | snd_pcm_limit_hw_rates(runtime); | |
417 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
418 | ||
419 | /* avoid wrap-around with wall-clock */ | |
420 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
421 | 20, | |
422 | 178000000); | |
423 | ||
424 | if (chip->align_buffer_size) | |
425 | /* constrain buffer sizes to be multiple of 128 | |
426 | bytes. This is more efficient in terms of memory | |
427 | access but isn't required by the HDA spec and | |
428 | prevents users from specifying exact period/buffer | |
429 | sizes. For example for 44.1kHz, a period size set | |
430 | to 20ms will be rounded to 19.59ms. */ | |
431 | buff_step = 128; | |
432 | else | |
433 | /* Don't enforce steps on buffer sizes, still need to | |
434 | be multiple of 4 bytes (HDA spec). Tested on Intel | |
435 | HDA controllers, may not work on all devices where | |
436 | option needs to be disabled */ | |
437 | buff_step = 4; | |
438 | ||
439 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
440 | buff_step); | |
441 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
442 | buff_step); | |
cc72da7d | 443 | snd_hda_power_up(apcm->codec); |
61ca4107 TI |
444 | if (hinfo->ops.open) |
445 | err = hinfo->ops.open(hinfo, apcm->codec, substream); | |
446 | else | |
447 | err = -ENODEV; | |
05e84878 DR |
448 | if (err < 0) { |
449 | azx_release_device(azx_dev); | |
61ca4107 | 450 | goto powerdown; |
05e84878 DR |
451 | } |
452 | snd_pcm_limit_hw_rates(runtime); | |
453 | /* sanity check */ | |
454 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
455 | snd_BUG_ON(!runtime->hw.channels_max) || | |
456 | snd_BUG_ON(!runtime->hw.formats) || | |
457 | snd_BUG_ON(!runtime->hw.rates)) { | |
458 | azx_release_device(azx_dev); | |
61ca4107 TI |
459 | if (hinfo->ops.close) |
460 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
461 | err = -EINVAL; | |
462 | goto powerdown; | |
05e84878 DR |
463 | } |
464 | ||
9e94df3a | 465 | /* disable LINK_ATIME timestamps for capture streams |
05e84878 | 466 | until we figure out how to handle digital inputs */ |
9e94df3a PLB |
467 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
468 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ | |
469 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; | |
470 | } | |
05e84878 | 471 | |
05e84878 DR |
472 | snd_pcm_set_sync(substream); |
473 | mutex_unlock(&chip->open_mutex); | |
474 | return 0; | |
61ca4107 TI |
475 | |
476 | powerdown: | |
477 | snd_hda_power_down(apcm->codec); | |
478 | unlock: | |
479 | mutex_unlock(&chip->open_mutex); | |
9a6246ff | 480 | snd_hda_codec_pcm_put(apcm->info); |
61ca4107 | 481 | return err; |
05e84878 DR |
482 | } |
483 | ||
484 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | |
485 | struct vm_area_struct *area) | |
486 | { | |
487 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
488 | struct azx *chip = apcm->chip; | |
489 | if (chip->ops->pcm_mmap_prepare) | |
490 | chip->ops->pcm_mmap_prepare(substream, area); | |
491 | return snd_pcm_lib_default_mmap(substream, area); | |
492 | } | |
493 | ||
494 | static struct snd_pcm_ops azx_pcm_ops = { | |
495 | .open = azx_pcm_open, | |
496 | .close = azx_pcm_close, | |
497 | .ioctl = snd_pcm_lib_ioctl, | |
498 | .hw_params = azx_pcm_hw_params, | |
499 | .hw_free = azx_pcm_hw_free, | |
500 | .prepare = azx_pcm_prepare, | |
501 | .trigger = azx_pcm_trigger, | |
502 | .pointer = azx_pcm_pointer, | |
9e94df3a | 503 | .get_time_info = azx_get_time_info, |
05e84878 DR |
504 | .mmap = azx_pcm_mmap, |
505 | .page = snd_pcm_sgbuf_ops_page, | |
506 | }; | |
507 | ||
508 | static void azx_pcm_free(struct snd_pcm *pcm) | |
509 | { | |
510 | struct azx_pcm *apcm = pcm->private_data; | |
511 | if (apcm) { | |
512 | list_del(&apcm->list); | |
820cc6cf | 513 | apcm->info->pcm = NULL; |
05e84878 DR |
514 | kfree(apcm); |
515 | } | |
516 | } | |
517 | ||
518 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | |
519 | ||
0a50575b TI |
520 | int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, |
521 | struct hda_pcm *cpcm) | |
05e84878 | 522 | { |
a41d1224 TI |
523 | struct hdac_bus *bus = &_bus->core; |
524 | struct azx *chip = bus_to_azx(bus); | |
05e84878 DR |
525 | struct snd_pcm *pcm; |
526 | struct azx_pcm *apcm; | |
527 | int pcm_dev = cpcm->device; | |
528 | unsigned int size; | |
529 | int s, err; | |
530 | ||
531 | list_for_each_entry(apcm, &chip->pcm_list, list) { | |
532 | if (apcm->pcm->device == pcm_dev) { | |
533 | dev_err(chip->card->dev, "PCM %d already exists\n", | |
534 | pcm_dev); | |
535 | return -EBUSY; | |
536 | } | |
537 | } | |
538 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
539 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
540 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
541 | &pcm); | |
542 | if (err < 0) | |
543 | return err; | |
544 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); | |
545 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); | |
546 | if (apcm == NULL) | |
547 | return -ENOMEM; | |
548 | apcm->chip = chip; | |
549 | apcm->pcm = pcm; | |
550 | apcm->codec = codec; | |
820cc6cf | 551 | apcm->info = cpcm; |
05e84878 DR |
552 | pcm->private_data = apcm; |
553 | pcm->private_free = azx_pcm_free; | |
554 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) | |
555 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
556 | list_add_tail(&apcm->list, &chip->pcm_list); | |
557 | cpcm->pcm = pcm; | |
558 | for (s = 0; s < 2; s++) { | |
05e84878 DR |
559 | if (cpcm->stream[s].substreams) |
560 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
561 | } | |
562 | /* buffer pre-allocation */ | |
563 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | |
564 | if (size > MAX_PREALLOC_SIZE) | |
565 | size = MAX_PREALLOC_SIZE; | |
566 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, | |
567 | chip->card->dev, | |
568 | size, MAX_PREALLOC_SIZE); | |
05e84878 DR |
569 | return 0; |
570 | } | |
05e84878 | 571 | |
6e85dddc DR |
572 | static unsigned int azx_command_addr(u32 cmd) |
573 | { | |
574 | unsigned int addr = cmd >> 28; | |
575 | ||
576 | if (addr >= AZX_MAX_CODECS) { | |
577 | snd_BUG(); | |
578 | addr = 0; | |
579 | } | |
580 | ||
581 | return addr; | |
582 | } | |
583 | ||
6e85dddc | 584 | /* receive a response */ |
a41d1224 | 585 | static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 586 | unsigned int *res) |
6e85dddc | 587 | { |
a41d1224 TI |
588 | struct azx *chip = bus_to_azx(bus); |
589 | struct hda_bus *hbus = &chip->bus; | |
6e85dddc DR |
590 | unsigned long timeout; |
591 | unsigned long loopcounter; | |
592 | int do_poll = 0; | |
593 | ||
594 | again: | |
595 | timeout = jiffies + msecs_to_jiffies(1000); | |
596 | ||
597 | for (loopcounter = 0;; loopcounter++) { | |
a41d1224 TI |
598 | spin_lock_irq(&bus->reg_lock); |
599 | if (chip->polling_mode || do_poll) | |
600 | snd_hdac_bus_update_rirb(bus); | |
601 | if (!bus->rirb.cmds[addr]) { | |
6e85dddc DR |
602 | if (!do_poll) |
603 | chip->poll_count = 0; | |
cad372f1 | 604 | if (res) |
a41d1224 TI |
605 | *res = bus->rirb.res[addr]; /* the last value */ |
606 | spin_unlock_irq(&bus->reg_lock); | |
cad372f1 | 607 | return 0; |
6e85dddc | 608 | } |
a41d1224 | 609 | spin_unlock_irq(&bus->reg_lock); |
6e85dddc DR |
610 | if (time_after(jiffies, timeout)) |
611 | break; | |
a41d1224 | 612 | if (hbus->needs_damn_long_delay || loopcounter > 3000) |
6e85dddc DR |
613 | msleep(2); /* temporary workaround */ |
614 | else { | |
615 | udelay(10); | |
616 | cond_resched(); | |
617 | } | |
618 | } | |
619 | ||
a41d1224 | 620 | if (hbus->no_response_fallback) |
cad372f1 | 621 | return -EIO; |
6e85dddc DR |
622 | |
623 | if (!chip->polling_mode && chip->poll_count < 2) { | |
624 | dev_dbg(chip->card->dev, | |
625 | "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n", | |
a41d1224 | 626 | bus->last_cmd[addr]); |
6e85dddc DR |
627 | do_poll = 1; |
628 | chip->poll_count++; | |
629 | goto again; | |
630 | } | |
631 | ||
632 | ||
633 | if (!chip->polling_mode) { | |
634 | dev_warn(chip->card->dev, | |
635 | "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", | |
a41d1224 | 636 | bus->last_cmd[addr]); |
6e85dddc DR |
637 | chip->polling_mode = 1; |
638 | goto again; | |
639 | } | |
640 | ||
641 | if (chip->msi) { | |
642 | dev_warn(chip->card->dev, | |
643 | "No response from codec, disabling MSI: last cmd=0x%08x\n", | |
a41d1224 TI |
644 | bus->last_cmd[addr]); |
645 | if (chip->ops->disable_msi_reset_irq && | |
cad372f1 TI |
646 | chip->ops->disable_msi_reset_irq(chip) < 0) |
647 | return -EIO; | |
6e85dddc DR |
648 | goto again; |
649 | } | |
650 | ||
651 | if (chip->probing) { | |
652 | /* If this critical timeout happens during the codec probing | |
653 | * phase, this is likely an access to a non-existing codec | |
654 | * slot. Better to return an error and reset the system. | |
655 | */ | |
cad372f1 | 656 | return -EIO; |
6e85dddc DR |
657 | } |
658 | ||
659 | /* a fatal communication error; need either to reset or to fallback | |
660 | * to the single_cmd mode | |
661 | */ | |
a41d1224 TI |
662 | if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) { |
663 | hbus->response_reset = 1; | |
cad372f1 | 664 | return -EAGAIN; /* give a chance to retry */ |
6e85dddc DR |
665 | } |
666 | ||
667 | dev_err(chip->card->dev, | |
668 | "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", | |
a41d1224 | 669 | bus->last_cmd[addr]); |
6e85dddc | 670 | chip->single_cmd = 1; |
a41d1224 TI |
671 | hbus->response_reset = 0; |
672 | snd_hdac_bus_stop_cmd_io(bus); | |
cad372f1 | 673 | return -EIO; |
6e85dddc DR |
674 | } |
675 | ||
676 | /* | |
677 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
678 | * | |
679 | * Note: according to Intel, this is not preferred use. The command was | |
680 | * intended for the BIOS only, and may get confused with unsolicited | |
681 | * responses. So, we shouldn't use it for normal operation from the | |
682 | * driver. | |
683 | * I left the codes, however, for debugging/testing purposes. | |
684 | */ | |
685 | ||
686 | /* receive a response */ | |
687 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) | |
688 | { | |
689 | int timeout = 50; | |
690 | ||
691 | while (timeout--) { | |
692 | /* check IRV busy bit */ | |
fb1d8ac2 | 693 | if (azx_readw(chip, IRS) & AZX_IRS_VALID) { |
6e85dddc | 694 | /* reuse rirb.res as the response return value */ |
a41d1224 | 695 | azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR); |
6e85dddc DR |
696 | return 0; |
697 | } | |
698 | udelay(1); | |
699 | } | |
700 | if (printk_ratelimit()) | |
701 | dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", | |
702 | azx_readw(chip, IRS)); | |
a41d1224 | 703 | azx_bus(chip)->rirb.res[addr] = -1; |
6e85dddc DR |
704 | return -EIO; |
705 | } | |
706 | ||
707 | /* send a command */ | |
a41d1224 | 708 | static int azx_single_send_cmd(struct hdac_bus *bus, u32 val) |
6e85dddc | 709 | { |
a41d1224 | 710 | struct azx *chip = bus_to_azx(bus); |
6e85dddc DR |
711 | unsigned int addr = azx_command_addr(val); |
712 | int timeout = 50; | |
713 | ||
a41d1224 | 714 | bus->last_cmd[azx_command_addr(val)] = val; |
6e85dddc DR |
715 | while (timeout--) { |
716 | /* check ICB busy bit */ | |
fb1d8ac2 | 717 | if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { |
6e85dddc DR |
718 | /* Clear IRV valid bit */ |
719 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
fb1d8ac2 | 720 | AZX_IRS_VALID); |
6e85dddc DR |
721 | azx_writel(chip, IC, val); |
722 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
fb1d8ac2 | 723 | AZX_IRS_BUSY); |
6e85dddc DR |
724 | return azx_single_wait_for_response(chip, addr); |
725 | } | |
726 | udelay(1); | |
727 | } | |
728 | if (printk_ratelimit()) | |
729 | dev_dbg(chip->card->dev, | |
730 | "send_cmd timeout: IRS=0x%x, val=0x%x\n", | |
731 | azx_readw(chip, IRS), val); | |
732 | return -EIO; | |
733 | } | |
734 | ||
735 | /* receive a response */ | |
a41d1224 | 736 | static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 737 | unsigned int *res) |
6e85dddc | 738 | { |
cad372f1 | 739 | if (res) |
a41d1224 | 740 | *res = bus->rirb.res[addr]; |
cad372f1 | 741 | return 0; |
6e85dddc DR |
742 | } |
743 | ||
744 | /* | |
745 | * The below are the main callbacks from hda_codec. | |
746 | * | |
747 | * They are just the skeleton to call sub-callbacks according to the | |
748 | * current setting of chip->single_cmd. | |
749 | */ | |
750 | ||
751 | /* send a command */ | |
a41d1224 | 752 | static int azx_send_cmd(struct hdac_bus *bus, unsigned int val) |
6e85dddc | 753 | { |
a41d1224 | 754 | struct azx *chip = bus_to_azx(bus); |
6e85dddc DR |
755 | |
756 | if (chip->disabled) | |
757 | return 0; | |
6e85dddc DR |
758 | if (chip->single_cmd) |
759 | return azx_single_send_cmd(bus, val); | |
760 | else | |
a41d1224 | 761 | return snd_hdac_bus_send_cmd(bus, val); |
6e85dddc | 762 | } |
6e85dddc DR |
763 | |
764 | /* get a response */ | |
a41d1224 | 765 | static int azx_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 766 | unsigned int *res) |
6e85dddc | 767 | { |
a41d1224 TI |
768 | struct azx *chip = bus_to_azx(bus); |
769 | ||
6e85dddc DR |
770 | if (chip->disabled) |
771 | return 0; | |
772 | if (chip->single_cmd) | |
cad372f1 | 773 | return azx_single_get_response(bus, addr, res); |
6e85dddc | 774 | else |
cad372f1 | 775 | return azx_rirb_get_response(bus, addr, res); |
6e85dddc | 776 | } |
6e85dddc | 777 | |
17eccb27 ML |
778 | static int azx_link_power(struct hdac_bus *bus, bool enable) |
779 | { | |
780 | struct azx *chip = bus_to_azx(bus); | |
781 | ||
782 | if (chip->ops->link_power) | |
783 | return chip->ops->link_power(chip, enable); | |
784 | else | |
785 | return -EINVAL; | |
786 | } | |
787 | ||
7e8be1b3 TI |
788 | static const struct hdac_bus_ops bus_core_ops = { |
789 | .command = azx_send_cmd, | |
790 | .get_response = azx_get_response, | |
17eccb27 | 791 | .link_power = azx_link_power, |
7e8be1b3 TI |
792 | }; |
793 | ||
2b5fd6c2 DR |
794 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
795 | /* | |
796 | * DSP loading code (e.g. for CA0132) | |
797 | */ | |
798 | ||
799 | /* use the first stream for loading DSP */ | |
800 | static struct azx_dev * | |
801 | azx_get_dsp_loader_dev(struct azx *chip) | |
802 | { | |
7833c3f8 TI |
803 | struct hdac_bus *bus = azx_bus(chip); |
804 | struct hdac_stream *s; | |
805 | ||
806 | list_for_each_entry(s, &bus->stream_list, list) | |
807 | if (s->index == chip->playback_index_offset) | |
808 | return stream_to_azx_dev(s); | |
809 | ||
810 | return NULL; | |
2b5fd6c2 DR |
811 | } |
812 | ||
0a50575b TI |
813 | int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, |
814 | unsigned int byte_size, | |
815 | struct snd_dma_buffer *bufp) | |
2b5fd6c2 | 816 | { |
0a50575b | 817 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 818 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 | 819 | struct azx_dev *azx_dev; |
ccc98865 TI |
820 | struct hdac_stream *hstr; |
821 | bool saved = false; | |
2b5fd6c2 DR |
822 | int err; |
823 | ||
824 | azx_dev = azx_get_dsp_loader_dev(chip); | |
ccc98865 | 825 | hstr = azx_stream(azx_dev); |
a41d1224 | 826 | spin_lock_irq(&bus->reg_lock); |
ccc98865 TI |
827 | if (hstr->opened) { |
828 | chip->saved_azx_dev = *azx_dev; | |
829 | saved = true; | |
2b5fd6c2 | 830 | } |
a41d1224 | 831 | spin_unlock_irq(&bus->reg_lock); |
2b5fd6c2 | 832 | |
ccc98865 TI |
833 | err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp); |
834 | if (err < 0) { | |
a41d1224 | 835 | spin_lock_irq(&bus->reg_lock); |
ccc98865 TI |
836 | if (saved) |
837 | *azx_dev = chip->saved_azx_dev; | |
a41d1224 | 838 | spin_unlock_irq(&bus->reg_lock); |
ccc98865 TI |
839 | return err; |
840 | } | |
2b5fd6c2 | 841 | |
6d23c8f5 | 842 | hstr->prepared = 0; |
2b5fd6c2 DR |
843 | return err; |
844 | } | |
0a50575b | 845 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare); |
2b5fd6c2 | 846 | |
0a50575b | 847 | void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) |
2b5fd6c2 | 848 | { |
0a50575b | 849 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 850 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 DR |
851 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
852 | ||
ccc98865 | 853 | snd_hdac_dsp_trigger(azx_stream(azx_dev), start); |
2b5fd6c2 | 854 | } |
0a50575b | 855 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger); |
2b5fd6c2 | 856 | |
0a50575b TI |
857 | void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, |
858 | struct snd_dma_buffer *dmab) | |
2b5fd6c2 | 859 | { |
0a50575b | 860 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 861 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 | 862 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
ccc98865 | 863 | struct hdac_stream *hstr = azx_stream(azx_dev); |
2b5fd6c2 | 864 | |
0a50575b | 865 | if (!dmab->area || !hstr->locked) |
2b5fd6c2 DR |
866 | return; |
867 | ||
ccc98865 | 868 | snd_hdac_dsp_cleanup(hstr, dmab); |
a41d1224 | 869 | spin_lock_irq(&bus->reg_lock); |
ccc98865 | 870 | if (hstr->opened) |
2b5fd6c2 | 871 | *azx_dev = chip->saved_azx_dev; |
ccc98865 | 872 | hstr->locked = false; |
a41d1224 | 873 | spin_unlock_irq(&bus->reg_lock); |
2b5fd6c2 | 874 | } |
0a50575b | 875 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup); |
2b5fd6c2 DR |
876 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |
877 | ||
f43923ff DR |
878 | /* |
879 | * reset and start the controller registers | |
880 | */ | |
17c3ad03 | 881 | void azx_init_chip(struct azx *chip, bool full_reset) |
f43923ff | 882 | { |
a41d1224 TI |
883 | if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) { |
884 | /* correct RINTCNT for CXT */ | |
885 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | |
886 | azx_writew(chip, RINTCNT, 0xc0); | |
887 | } | |
f43923ff DR |
888 | } |
889 | EXPORT_SYMBOL_GPL(azx_init_chip); | |
890 | ||
7833c3f8 TI |
891 | void azx_stop_all_streams(struct azx *chip) |
892 | { | |
893 | struct hdac_bus *bus = azx_bus(chip); | |
894 | struct hdac_stream *s; | |
895 | ||
896 | list_for_each_entry(s, &bus->stream_list, list) | |
897 | snd_hdac_stream_stop(s); | |
898 | } | |
899 | EXPORT_SYMBOL_GPL(azx_stop_all_streams); | |
900 | ||
f43923ff DR |
901 | void azx_stop_chip(struct azx *chip) |
902 | { | |
a41d1224 | 903 | snd_hdac_bus_stop_chip(azx_bus(chip)); |
f43923ff | 904 | } |
154867cf | 905 | EXPORT_SYMBOL_GPL(azx_stop_chip); |
f43923ff | 906 | |
f0b1df88 DR |
907 | /* |
908 | * interrupt handler | |
909 | */ | |
7833c3f8 TI |
910 | static void stream_update(struct hdac_bus *bus, struct hdac_stream *s) |
911 | { | |
a41d1224 | 912 | struct azx *chip = bus_to_azx(bus); |
7833c3f8 TI |
913 | struct azx_dev *azx_dev = stream_to_azx_dev(s); |
914 | ||
915 | /* check whether this IRQ is really acceptable */ | |
916 | if (!chip->ops->position_check || | |
917 | chip->ops->position_check(chip, azx_dev)) { | |
a41d1224 TI |
918 | spin_unlock(&bus->reg_lock); |
919 | snd_pcm_period_elapsed(azx_stream(azx_dev)->substream); | |
920 | spin_lock(&bus->reg_lock); | |
7833c3f8 TI |
921 | } |
922 | } | |
923 | ||
f0b1df88 DR |
924 | irqreturn_t azx_interrupt(int irq, void *dev_id) |
925 | { | |
926 | struct azx *chip = dev_id; | |
7833c3f8 | 927 | struct hdac_bus *bus = azx_bus(chip); |
f0b1df88 | 928 | u32 status; |
f0b1df88 | 929 | |
641d334b | 930 | #ifdef CONFIG_PM |
364aa716 | 931 | if (azx_has_pm_runtime(chip)) |
7b0a48f3 | 932 | if (!pm_runtime_active(chip->card->dev)) |
f0b1df88 DR |
933 | return IRQ_NONE; |
934 | #endif | |
935 | ||
a41d1224 | 936 | spin_lock(&bus->reg_lock); |
f0b1df88 DR |
937 | |
938 | if (chip->disabled) { | |
a41d1224 | 939 | spin_unlock(&bus->reg_lock); |
f0b1df88 DR |
940 | return IRQ_NONE; |
941 | } | |
942 | ||
943 | status = azx_readl(chip, INTSTS); | |
944 | if (status == 0 || status == 0xffffffff) { | |
a41d1224 | 945 | spin_unlock(&bus->reg_lock); |
f0b1df88 DR |
946 | return IRQ_NONE; |
947 | } | |
948 | ||
7833c3f8 | 949 | snd_hdac_bus_handle_stream_irq(bus, status, stream_update); |
f0b1df88 DR |
950 | |
951 | /* clear rirb int */ | |
952 | status = azx_readb(chip, RIRBSTS); | |
953 | if (status & RIRB_INT_MASK) { | |
954 | if (status & RIRB_INT_RESPONSE) { | |
955 | if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) | |
956 | udelay(80); | |
a41d1224 | 957 | snd_hdac_bus_update_rirb(bus); |
f0b1df88 DR |
958 | } |
959 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
960 | } | |
961 | ||
a41d1224 | 962 | spin_unlock(&bus->reg_lock); |
f0b1df88 DR |
963 | |
964 | return IRQ_HANDLED; | |
965 | } | |
966 | EXPORT_SYMBOL_GPL(azx_interrupt); | |
967 | ||
154867cf DR |
968 | /* |
969 | * Codec initerface | |
970 | */ | |
971 | ||
972 | /* | |
973 | * Probe the given codec address | |
974 | */ | |
975 | static int probe_codec(struct azx *chip, int addr) | |
976 | { | |
977 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
978 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
7833c3f8 | 979 | struct hdac_bus *bus = azx_bus(chip); |
cad372f1 | 980 | int err; |
a41d1224 | 981 | unsigned int res = -1; |
154867cf | 982 | |
7e8be1b3 | 983 | mutex_lock(&bus->cmd_mutex); |
154867cf | 984 | chip->probing = 1; |
7e8be1b3 TI |
985 | azx_send_cmd(bus, cmd); |
986 | err = azx_get_response(bus, addr, &res); | |
154867cf | 987 | chip->probing = 0; |
7e8be1b3 | 988 | mutex_unlock(&bus->cmd_mutex); |
cad372f1 | 989 | if (err < 0 || res == -1) |
154867cf DR |
990 | return -EIO; |
991 | dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); | |
992 | return 0; | |
993 | } | |
994 | ||
0a50575b | 995 | void snd_hda_bus_reset(struct hda_bus *bus) |
154867cf | 996 | { |
a41d1224 | 997 | struct azx *chip = bus_to_azx(&bus->core); |
154867cf DR |
998 | |
999 | bus->in_reset = 1; | |
1000 | azx_stop_chip(chip); | |
17c3ad03 | 1001 | azx_init_chip(chip, true); |
a41d1224 | 1002 | if (bus->core.chip_init) |
0a50575b | 1003 | snd_hda_bus_reset_codecs(bus); |
154867cf DR |
1004 | bus->in_reset = 0; |
1005 | } | |
1006 | ||
154867cf DR |
1007 | static int get_jackpoll_interval(struct azx *chip) |
1008 | { | |
1009 | int i; | |
1010 | unsigned int j; | |
1011 | ||
1012 | if (!chip->jackpoll_ms) | |
1013 | return 0; | |
1014 | ||
1015 | i = chip->jackpoll_ms[chip->dev_index]; | |
1016 | if (i == 0) | |
1017 | return 0; | |
1018 | if (i < 50 || i > 60000) | |
1019 | j = 0; | |
1020 | else | |
1021 | j = msecs_to_jiffies(i); | |
1022 | if (j == 0) | |
1023 | dev_warn(chip->card->dev, | |
1024 | "jackpoll_ms value out of range: %d\n", i); | |
1025 | return j; | |
1026 | } | |
1027 | ||
96d2bd6e | 1028 | /* HD-audio bus initialization */ |
a41d1224 TI |
1029 | int azx_bus_init(struct azx *chip, const char *model, |
1030 | const struct hdac_io_ops *io_ops) | |
154867cf | 1031 | { |
a41d1224 | 1032 | struct hda_bus *bus = &chip->bus; |
96d2bd6e | 1033 | int err; |
154867cf | 1034 | |
a41d1224 TI |
1035 | err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops, |
1036 | io_ops); | |
154867cf DR |
1037 | if (err < 0) |
1038 | return err; | |
1039 | ||
a41d1224 TI |
1040 | bus->card = chip->card; |
1041 | mutex_init(&bus->prepare_mutex); | |
ef744978 TI |
1042 | bus->pci = chip->pci; |
1043 | bus->modelname = model; | |
ccc98865 TI |
1044 | bus->core.snoop = azx_snoop(chip); |
1045 | if (chip->get_position[0] != azx_get_pos_lpib || | |
1046 | chip->get_position[1] != azx_get_pos_lpib) | |
1047 | bus->core.use_posbuf = true; | |
1048 | if (chip->bdl_pos_adj) | |
1049 | bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index]; | |
a41d1224 TI |
1050 | if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR) |
1051 | bus->core.corbrp_self_clear = true; | |
ef744978 | 1052 | |
154867cf DR |
1053 | if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { |
1054 | dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); | |
ef744978 | 1055 | bus->needs_damn_long_delay = 1; |
154867cf DR |
1056 | } |
1057 | ||
96d2bd6e TI |
1058 | /* AMD chipsets often cause the communication stalls upon certain |
1059 | * sequence like the pin-detection. It seems that forcing the synced | |
1060 | * access works around the stall. Grrr... | |
1061 | */ | |
1062 | if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { | |
1063 | dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n"); | |
d068ebc2 | 1064 | bus->core.sync_write = 1; |
96d2bd6e TI |
1065 | bus->allow_bus_reset = 1; |
1066 | } | |
1067 | ||
1068 | return 0; | |
1069 | } | |
a41d1224 | 1070 | EXPORT_SYMBOL_GPL(azx_bus_init); |
96d2bd6e TI |
1071 | |
1072 | /* Probe codecs */ | |
1073 | int azx_probe_codecs(struct azx *chip, unsigned int max_slots) | |
1074 | { | |
a41d1224 | 1075 | struct hdac_bus *bus = azx_bus(chip); |
96d2bd6e TI |
1076 | int c, codecs, err; |
1077 | ||
154867cf DR |
1078 | codecs = 0; |
1079 | if (!max_slots) | |
1080 | max_slots = AZX_DEFAULT_CODECS; | |
1081 | ||
1082 | /* First try to probe all given codec slots */ | |
1083 | for (c = 0; c < max_slots; c++) { | |
a41d1224 | 1084 | if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
154867cf DR |
1085 | if (probe_codec(chip, c) < 0) { |
1086 | /* Some BIOSen give you wrong codec addresses | |
1087 | * that don't exist | |
1088 | */ | |
1089 | dev_warn(chip->card->dev, | |
1090 | "Codec #%d probe error; disabling it...\n", c); | |
a41d1224 | 1091 | bus->codec_mask &= ~(1 << c); |
154867cf DR |
1092 | /* More badly, accessing to a non-existing |
1093 | * codec often screws up the controller chip, | |
1094 | * and disturbs the further communications. | |
1095 | * Thus if an error occurs during probing, | |
1096 | * better to reset the controller chip to | |
1097 | * get back to the sanity state. | |
1098 | */ | |
1099 | azx_stop_chip(chip); | |
17c3ad03 | 1100 | azx_init_chip(chip, true); |
154867cf DR |
1101 | } |
1102 | } | |
1103 | } | |
1104 | ||
154867cf DR |
1105 | /* Then create codec instances */ |
1106 | for (c = 0; c < max_slots; c++) { | |
a41d1224 | 1107 | if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
154867cf | 1108 | struct hda_codec *codec; |
a41d1224 | 1109 | err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec); |
154867cf DR |
1110 | if (err < 0) |
1111 | continue; | |
1112 | codec->jackpoll_interval = get_jackpoll_interval(chip); | |
1113 | codec->beep_mode = chip->beep_mode; | |
1114 | codecs++; | |
1115 | } | |
1116 | } | |
1117 | if (!codecs) { | |
1118 | dev_err(chip->card->dev, "no codecs initialized\n"); | |
1119 | return -ENXIO; | |
1120 | } | |
1121 | return 0; | |
1122 | } | |
96d2bd6e | 1123 | EXPORT_SYMBOL_GPL(azx_probe_codecs); |
154867cf DR |
1124 | |
1125 | /* configure each codec instance */ | |
1126 | int azx_codec_configure(struct azx *chip) | |
1127 | { | |
1128 | struct hda_codec *codec; | |
a41d1224 | 1129 | list_for_each_codec(codec, &chip->bus) { |
154867cf DR |
1130 | snd_hda_codec_configure(codec); |
1131 | } | |
1132 | return 0; | |
1133 | } | |
1134 | EXPORT_SYMBOL_GPL(azx_codec_configure); | |
1135 | ||
7833c3f8 | 1136 | static int stream_direction(struct azx *chip, unsigned char index) |
93e3423e | 1137 | { |
7833c3f8 TI |
1138 | if (index >= chip->capture_index_offset && |
1139 | index < chip->capture_index_offset + chip->capture_streams) | |
1140 | return SNDRV_PCM_STREAM_CAPTURE; | |
1141 | return SNDRV_PCM_STREAM_PLAYBACK; | |
93e3423e RR |
1142 | } |
1143 | ||
154867cf | 1144 | /* initialize SD streams */ |
a41d1224 | 1145 | int azx_init_streams(struct azx *chip) |
154867cf DR |
1146 | { |
1147 | int i; | |
7833c3f8 | 1148 | int stream_tags[2] = { 0, 0 }; |
154867cf DR |
1149 | |
1150 | /* initialize each stream (aka device) | |
1151 | * assign the starting bdl address to each stream (device) | |
1152 | * and initialize | |
1153 | */ | |
1154 | for (i = 0; i < chip->num_streams; i++) { | |
7833c3f8 TI |
1155 | struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL); |
1156 | int dir, tag; | |
1157 | ||
1158 | if (!azx_dev) | |
1159 | return -ENOMEM; | |
93e3423e | 1160 | |
7833c3f8 | 1161 | dir = stream_direction(chip, i); |
93e3423e RR |
1162 | /* stream tag must be unique throughout |
1163 | * the stream direction group, | |
1164 | * valid values 1...15 | |
1165 | * use separate stream tag if the flag | |
1166 | * AZX_DCAPS_SEPARATE_STREAM_TAG is used | |
1167 | */ | |
1168 | if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) | |
7833c3f8 | 1169 | tag = ++stream_tags[dir]; |
93e3423e | 1170 | else |
7833c3f8 TI |
1171 | tag = i + 1; |
1172 | snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev), | |
1173 | i, dir, tag); | |
154867cf DR |
1174 | } |
1175 | ||
1176 | return 0; | |
1177 | } | |
a41d1224 TI |
1178 | EXPORT_SYMBOL_GPL(azx_init_streams); |
1179 | ||
1180 | void azx_free_streams(struct azx *chip) | |
1181 | { | |
1182 | struct hdac_bus *bus = azx_bus(chip); | |
1183 | struct hdac_stream *s; | |
1184 | ||
1185 | while (!list_empty(&bus->stream_list)) { | |
1186 | s = list_first_entry(&bus->stream_list, struct hdac_stream, list); | |
1187 | list_del(&s->list); | |
1188 | kfree(stream_to_azx_dev(s)); | |
1189 | } | |
1190 | } | |
1191 | EXPORT_SYMBOL_GPL(azx_free_streams); |