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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
05e84878 66#include "hda_controller.h"
2538a4f5 67#include "hda_priv.h"
1da177e4
LT		 68
69
5aba4f8e
TI		 70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 73static char *model[SNDRV_CARDS];
1dac6695 74static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 75static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 76static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 77static int probe_only[SNDRV_CARDS];
26a6cb6c 78static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 79static bool single_cmd;
71623855 80static int enable_msi = -1;
4ea6fbc8
TI		 81#ifdef CONFIG_SND_HDA_PATCH_LOADER
82static char *patch[SNDRV_CARDS];
83#endif
2dca0bba 84#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 85static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87#endif
1da177e4 88
5aba4f8e 89module_param_array(index, int, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 91module_param_array(id, charp, NULL, 0444);
1da177e4 92MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 93module_param_array(enable, bool, NULL, 0444);
94MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95module_param_array(model, charp, NULL, 0444);
1da177e4 96MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 97module_param_array(position_fix, int, NULL, 0444);
4cb36310 98MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 100module_param_array(bdl_pos_adj, int, NULL, 0644);
101MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 102module_param_array(probe_mask, int, NULL, 0444);
606ad75f 103MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 104module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 105MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 106module_param_array(jackpoll_ms, int, NULL, 0444);
107MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 108module_param(single_cmd, bool, 0444);
d01ce99f
TI		 109MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
ac9ef6cf 111module_param(enable_msi, bint, 0444);
134a11f0 112MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 113#ifdef CONFIG_SND_HDA_PATCH_LOADER
114module_param_array(patch, charp, NULL, 0444);
115MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116#endif
2dca0bba 117#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 118module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 119MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 120 "(0=off, 1=on) (default=1).");
2dca0bba 121#endif
606ad75f 122
83012a7c 123#ifdef CONFIG_PM
65fcd41d
TI		 124static int param_set_xint(const char *val, const struct kernel_param *kp);
125static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128};
129#define param_check_xint param_check_int
130
fee2fba3 131static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 132static int *power_save_addr = &power_save;
65fcd41d 133module_param(power_save, xint, 0644);
fee2fba3
TI		 134MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
1da177e4 136
dee1b66c
TI		 137/* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
8fc24426
TI		 141static bool power_save_controller = 1;
142module_param(power_save_controller, bool, 0644);
dee1b66c 143MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 144#else
145static int *power_save_addr;
83012a7c 146#endif /* CONFIG_PM */
dee1b66c 147
7bfe059e
TI		 148static int align_buffer_size = -1;
149module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 150MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
27fe48d9
TI		 153#ifdef CONFIG_X86
154static bool hda_snoop = true;
155module_param_named(snoop, hda_snoop, bool, 0444);
156MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 157#else
158#define hda_snoop true
27fe48d9
TI		 159#endif
160
161
1da177e4
LT		 162MODULE_LICENSE("GPL");
163MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
2f1b3818 165 "{Intel, ICH7},"
f5d40b30 166 "{Intel, ESB2},"
d2981393 167 "{Intel, ICH8},"
f9cc8a8b 168 "{Intel, ICH9},"
c34f5a04 169 "{Intel, ICH10},"
b29c2360 170 "{Intel, PCH},"
d2f2fcd2 171 "{Intel, CPT},"
d2edeb7c 172 "{Intel, PPT},"
8bc039a1 173 "{Intel, LPT},"
144dad99 174 "{Intel, LPT_LP},"
4eeca499 175 "{Intel, WPT_LP},"
e926f2c8 176 "{Intel, HPT},"
cea310e8 177 "{Intel, PBG},"
4979bca9 178 "{Intel, SCH},"
fc20a562 179 "{ATI, SB450},"
89be83f8 180 "{ATI, SB600},"
778b6e1b 181 "{ATI, RS600},"
5b15c95f 182 "{ATI, RS690},"
e6db1119
WL		 183 "{ATI, RS780},"
184 "{ATI, R600},"
2797f724
HRK		 185 "{ATI, RV630},"
186 "{ATI, RV610},"
27da1834
WL		 187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
fc20a562 191 "{VIA, VT8251},"
47672310 192 "{VIA, VT8237A},"
07e4ca50
TI		 193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
1da177e4
LT		 195MODULE_DESCRIPTION("Intel HDA driver");
196
a82d51ed 197#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 198#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 199#define SUPPORT_VGA_SWITCHEROO
200#endif
201#endif
202
203
1da177e4 204/*
1da177e4 205 */
1da177e4 206
07e4ca50
TI		 207/* driver types */
208enum {
209 AZX_DRIVER_ICH,
32679f95 210 AZX_DRIVER_PCH,
4979bca9 211 AZX_DRIVER_SCH,
fab1285a 212 AZX_DRIVER_HDMI,
07e4ca50 213 AZX_DRIVER_ATI,
778b6e1b 214 AZX_DRIVER_ATIHDMI,
1815b34a 215 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
da3fca21 219 AZX_DRIVER_NVIDIA,
f269002e 220 AZX_DRIVER_TERA,
14d34f16 221 AZX_DRIVER_CTX,
5ae763b1 222 AZX_DRIVER_CTHDA,
c4da29ca 223 AZX_DRIVER_GENERIC,
2f5983f2 224 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 225};
226
2ea3c6a2 227/* quirks for Intel PCH */
d7dab4db 228#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232#define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 234
33499a15
TI		 235#define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
9477c58e
TI		 240/* quirks for ATI SB / AMD Hudson */
241#define AZX_DCAPS_PRESET_ATI_SB \
242 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
243 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
244
245/* quirks for ATI/AMD HDMI */
246#define AZX_DCAPS_PRESET_ATI_HDMI \
247 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
248
249/* quirks for Nvidia */
250#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 251 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
6ba736dd
TI		 252 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
253 AZX_DCAPS_CORBRP_SELF_CLEAR)
9477c58e 254
5ae763b1
TI		 255#define AZX_DCAPS_PRESET_CTHDA \
256 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
257
a82d51ed
TI		 258/*
259 * VGA-switcher support
260 */
261#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 262#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
263#else
264#define use_vga_switcheroo(chip) 0
265#endif
266
48c8b0eb 267static char *driver_short_names[] = {
07e4ca50 268 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 269 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 270 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 271 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 272 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 273 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 274 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 275 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
276 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 277 [AZX_DRIVER_ULI] = "HDA ULI M5461",
278 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 279 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 280 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 281 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 282 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 283};
284
27fe48d9 285#ifdef CONFIG_X86
9ddf1aeb 286static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 287{
9ddf1aeb
TI		 288 int pages;
289
27fe48d9
TI		 290 if (azx_snoop(chip))
291 return;
9ddf1aeb
TI		 292 if (!dmab || !dmab->area || !dmab->bytes)
293 return;
294
295#ifdef CONFIG_SND_DMA_SGBUF
296 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
297 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 298 if (on)
9ddf1aeb 299 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 300 else
9ddf1aeb
TI		 301 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
302 return;
27fe48d9 303 }
9ddf1aeb
TI		 304#endif
305
306 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
307 if (on)
308 set_memory_wc((unsigned long)dmab->area, pages);
309 else
310 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 311}
312
313static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
314 bool on)
315{
9ddf1aeb 316 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 317}
318static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 319 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 320{
321 if (azx_dev->wc_marked != on) {
9ddf1aeb 322 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 323 azx_dev->wc_marked = on;
324 }
325}
326#else
327/* NOP for other archs */
328static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
329 bool on)
330{
331}
332static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 333 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 334{
335}
336#endif
337
68e7fffc 338static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 339
cb53c626
TI		 340/*
341 * initialize the PCI registers
342 */
343/* update bits in a PCI register byte */
344static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
345 unsigned char mask, unsigned char val)
346{
347 unsigned char data;
348
349 pci_read_config_byte(pci, reg, &data);
350 data &= ~mask;
351 data |= (val & mask);
352 pci_write_config_byte(pci, reg, data);
353}
354
355static void azx_init_pci(struct azx *chip)
356{
357 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
358 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
359 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 360 * codecs.
361 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 362 */
46f2cc80 363 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 364 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 365 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 366 }
cb53c626 367
9477c58e
TI		 368 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
369 * we need to enable snoop.
370 */
371 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 372 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
373 azx_snoop(chip));
cb53c626 374 update_pci_byte(chip->pci,
27fe48d9
TI		 375 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
376 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 377 }
378
379 /* For NVIDIA HDA, enable snoop */
380 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 381 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
382 azx_snoop(chip));
cb53c626
TI		 383 update_pci_byte(chip->pci,
384 NVIDIA_HDA_TRANSREG_ADDR,
385 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 386 update_pci_byte(chip->pci,
387 NVIDIA_HDA_ISTRM_COH,
388 0x01, NVIDIA_HDA_ENABLE_COHBIT);
389 update_pci_byte(chip->pci,
390 NVIDIA_HDA_OSTRM_COH,
391 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 392 }
393
394 /* Enable SCH/PCH snoop if needed */
395 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 396 unsigned short snoop;
90a5ad52 397 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 398 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
399 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
400 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
401 if (!azx_snoop(chip))
402 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
403 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 404 pci_read_config_word(chip->pci,
405 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 406 }
4e76a883
TI		 407 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
408 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
409 "Disabled" : "Enabled");
da3fca21 410 }
1da177e4
LT		 411}
412
9ad593f6
TI		 413static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
414
7ca954a8
DR		 415/* called from IRQ */
416static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
417{
418 int ok;
419
420 ok = azx_position_ok(chip, azx_dev);
421 if (ok == 1) {
422 azx_dev->irq_pending = 0;
423 return ok;
424 } else if (ok == 0 && chip->bus && chip->bus->workq) {
425 /* bogus IRQ, process it later */
426 azx_dev->irq_pending = 1;
427 queue_work(chip->bus->workq, &chip->irq_pending_work);
428 }
429 return 0;
430}
431
9ad593f6
TI		 432/*
433 * Check whether the current DMA position is acceptable for updating
434 * periods. Returns non-zero if it's OK.
435 *
436 * Many HD-audio controllers appear pretty inaccurate about
437 * the update-IRQ timing. The IRQ is issued before actually the
438 * data is processed. So, we need to process it afterwords in a
439 * workqueue.
440 */
441static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
442{
e5463720 443 u32 wallclk;
9ad593f6
TI		 444 unsigned int pos;
445
f48f606d
JK		 446 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
447 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 448 return -1; /* bogus (too early) interrupt */
fa00e046 449
798cb7e8 450 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 451
d6d8bf54
TI		 452 if (WARN_ONCE(!azx_dev->period_bytes,
453 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 454 return -1; /* this shouldn't happen! */
edb39935 455 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 456 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
457 /* NG - it's below the first next period boundary */
9cdc0115 458 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 459 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 460 return 1; /* OK, it's fine */
461}
462
463/*
464 * The work for pending PCM period updates.
465 */
466static void azx_irq_pending_work(struct work_struct *work)
467{
468 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 469 int i, pending, ok;
9ad593f6 470
a6a950a8 471 if (!chip->irq_pending_warned) {
4e76a883
TI		 472 dev_info(chip->card->dev,
473 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
474 chip->card->number);
a6a950a8
TI		 475 chip->irq_pending_warned = 1;
476 }
477
9ad593f6
TI		 478 for (;;) {
479 pending = 0;
480 spin_lock_irq(&chip->reg_lock);
481 for (i = 0; i < chip->num_streams; i++) {
482 struct azx_dev *azx_dev = &chip->azx_dev[i];
483 if (!azx_dev->irq_pending ||
484 !azx_dev->substream ||
485 !azx_dev->running)
486 continue;
e5463720
JK		 487 ok = azx_position_ok(chip, azx_dev);
488 if (ok > 0) {
9ad593f6
TI		 489 azx_dev->irq_pending = 0;
490 spin_unlock(&chip->reg_lock);
491 snd_pcm_period_elapsed(azx_dev->substream);
492 spin_lock(&chip->reg_lock);
e5463720
JK		 493 } else if (ok < 0) {
494 pending = 0; /* too early */
9ad593f6
TI		 495 } else
496 pending++;
497 }
498 spin_unlock_irq(&chip->reg_lock);
499 if (!pending)
500 return;
08af495f 501 msleep(1);
9ad593f6
TI		 502 }
503}
504
505/* clear irq_pending flags and assure no on-going workq */
506static void azx_clear_irq_pending(struct azx *chip)
507{
508 int i;
509
510 spin_lock_irq(&chip->reg_lock);
511 for (i = 0; i < chip->num_streams; i++)
512 chip->azx_dev[i].irq_pending = 0;
513 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 514}
515
68e7fffc
TI		 516static int azx_acquire_irq(struct azx *chip, int do_disconnect)
517{
437a5a46
TI		 518 if (request_irq(chip->pci->irq, azx_interrupt,
519 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 520 KBUILD_MODNAME, chip)) {
4e76a883
TI		 521 dev_err(chip->card->dev,
522 "unable to grab IRQ %d, disabling device\n",
523 chip->pci->irq);
68e7fffc
TI		 524 if (do_disconnect)
525 snd_card_disconnect(chip->card);
526 return -1;
527 }
528 chip->irq = chip->pci->irq;
69e13418 529 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 530 return 0;
531}
532
83012a7c 533#ifdef CONFIG_PM
65fcd41d
TI		 534static DEFINE_MUTEX(card_list_lock);
535static LIST_HEAD(card_list);
536
537static void azx_add_card_list(struct azx *chip)
538{
539 mutex_lock(&card_list_lock);
540 list_add(&chip->list, &card_list);
541 mutex_unlock(&card_list_lock);
542}
543
544static void azx_del_card_list(struct azx *chip)
545{
546 mutex_lock(&card_list_lock);
547 list_del_init(&chip->list);
548 mutex_unlock(&card_list_lock);
549}
550
551/* trigger power-save check at writing parameter */
552static int param_set_xint(const char *val, const struct kernel_param *kp)
553{
554 struct azx *chip;
555 struct hda_codec *c;
556 int prev = power_save;
557 int ret = param_set_int(val, kp);
558
559 if (ret || prev == power_save)
560 return ret;
561
562 mutex_lock(&card_list_lock);
563 list_for_each_entry(chip, &card_list, list) {
564 if (!chip->bus || chip->disabled)
565 continue;
566 list_for_each_entry(c, &chip->bus->codec_list, list)
567 snd_hda_power_sync(c);
568 }
569 mutex_unlock(&card_list_lock);
570 return 0;
571}
572#else
573#define azx_add_card_list(chip) /* NOP */
574#define azx_del_card_list(chip) /* NOP */
83012a7c 575#endif /* CONFIG_PM */
5c0b9bec 576
7ccbde57 577#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 578/*
579 * power management
580 */
68cb2b55 581static int azx_suspend(struct device *dev)
1da177e4 582{
68cb2b55
TI		 583 struct pci_dev *pci = to_pci_dev(dev);
584 struct snd_card *card = dev_get_drvdata(dev);
421a1252 585 struct azx *chip = card->private_data;
01b65bfb 586 struct azx_pcm *p;
1da177e4 587
c5c21523
TI		 588 if (chip->disabled)
589 return 0;
590
421a1252 591 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 592 azx_clear_irq_pending(chip);
01b65bfb
TI		 593 list_for_each_entry(p, &chip->pcm_list, list)
594 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 595 if (chip->initialized)
8dd78330 596 snd_hda_suspend(chip->bus);
cb53c626 597 azx_stop_chip(chip);
7295b264 598 azx_enter_link_reset(chip);
30b35399 599 if (chip->irq >= 0) {
43001c95 600 free_irq(chip->irq, chip);
30b35399
TI		 601 chip->irq = -1;
602 }
68e7fffc 603 if (chip->msi)
43001c95 604 pci_disable_msi(chip->pci);
421a1252
TI		 605 pci_disable_device(pci);
606 pci_save_state(pci);
68cb2b55 607 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 608 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
609 hda_display_power(false);
1da177e4
LT		 610 return 0;
611}
612
68cb2b55 613static int azx_resume(struct device *dev)
1da177e4 614{
68cb2b55
TI		 615 struct pci_dev *pci = to_pci_dev(dev);
616 struct snd_card *card = dev_get_drvdata(dev);
421a1252 617 struct azx *chip = card->private_data;
1da177e4 618
c5c21523
TI		 619 if (chip->disabled)
620 return 0;
621
99a2008d
WX		 622 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
623 hda_display_power(true);
d14a7e0b
TI		 624 pci_set_power_state(pci, PCI_D0);
625 pci_restore_state(pci);
30b35399 626 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 627 dev_err(chip->card->dev,
628 "pci_enable_device failed, disabling device\n");
30b35399
TI		 629 snd_card_disconnect(card);
630 return -EIO;
631 }
632 pci_set_master(pci);
68e7fffc
TI		 633 if (chip->msi)
634 if (pci_enable_msi(pci) < 0)
635 chip->msi = 0;
636 if (azx_acquire_irq(chip, 1) < 0)
30b35399 637 return -EIO;
cb53c626 638 azx_init_pci(chip);
d804ad92 639
17c3ad03 640 azx_init_chip(chip, true);
d804ad92 641
1da177e4 642 snd_hda_resume(chip->bus);
421a1252 643 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 644 return 0;
645}
b8dfc462
ML		 646#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
647
648#ifdef CONFIG_PM_RUNTIME
649static int azx_runtime_suspend(struct device *dev)
650{
651 struct snd_card *card = dev_get_drvdata(dev);
652 struct azx *chip = card->private_data;
653
246efa4a
DA		 654 if (chip->disabled)
655 return 0;
656
657 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
658 return 0;
659
7d4f606c
WX		 660 /* enable controller wake up event */
661 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
662 STATESTS_INT_MASK);
663
b8dfc462 664 azx_stop_chip(chip);
873ce8ad 665 azx_enter_link_reset(chip);
b8dfc462 666 azx_clear_irq_pending(chip);
99a2008d
WX		 667 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
668 hda_display_power(false);
b8dfc462
ML		 669 return 0;
670}
671
672static int azx_runtime_resume(struct device *dev)
673{
674 struct snd_card *card = dev_get_drvdata(dev);
675 struct azx *chip = card->private_data;
7d4f606c
WX		 676 struct hda_bus *bus;
677 struct hda_codec *codec;
678 int status;
b8dfc462 679
246efa4a
DA		 680 if (chip->disabled)
681 return 0;
682
683 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
684 return 0;
685
99a2008d
WX		 686 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
687 hda_display_power(true);
7d4f606c
WX		 688
689 /* Read STATESTS before controller reset */
690 status = azx_readw(chip, STATESTS);
691
b8dfc462 692 azx_init_pci(chip);
17c3ad03 693 azx_init_chip(chip, true);
7d4f606c
WX		 694
695 bus = chip->bus;
696 if (status && bus) {
697 list_for_each_entry(codec, &bus->codec_list, list)
698 if (status & (1 << codec->addr))
699 queue_delayed_work(codec->bus->workq,
700 &codec->jackpoll_work, codec->jackpoll_interval);
701 }
702
703 /* disable controller Wake Up event*/
704 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
705 ~STATESTS_INT_MASK);
706
b8dfc462
ML		 707 return 0;
708}
6eb827d2
TI		 709
710static int azx_runtime_idle(struct device *dev)
711{
712 struct snd_card *card = dev_get_drvdata(dev);
713 struct azx *chip = card->private_data;
714
246efa4a
DA		 715 if (chip->disabled)
716 return 0;
717
6eb827d2
TI		 718 if (!power_save_controller ||
719 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
720 return -EBUSY;
721
722 return 0;
723}
724
b8dfc462
ML		 725#endif /* CONFIG_PM_RUNTIME */
726
727#ifdef CONFIG_PM
728static const struct dev_pm_ops azx_pm = {
729 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 730 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 731};
732
68cb2b55
TI		 733#define AZX_PM_OPS &azx_pm
734#else
68cb2b55 735#define AZX_PM_OPS NULL
b8dfc462 736#endif /* CONFIG_PM */
1da177e4
LT		 737
738
0cbf0098
TI		 739/*
740 * reboot notifier for hang-up problem at power-down
741 */
742static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
743{
744 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 745 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 746 azx_stop_chip(chip);
747 return NOTIFY_OK;
748}
749
750static void azx_notifier_register(struct azx *chip)
751{
752 chip->reboot_notifier.notifier_call = azx_halt;
753 register_reboot_notifier(&chip->reboot_notifier);
754}
755
756static void azx_notifier_unregister(struct azx *chip)
757{
758 if (chip->reboot_notifier.notifier_call)
759 unregister_reboot_notifier(&chip->reboot_notifier);
760}
761
48c8b0eb 762static int azx_probe_continue(struct azx *chip);
a82d51ed 763
8393ec4a 764#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 765static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 766
a82d51ed
TI		 767static void azx_vs_set_state(struct pci_dev *pci,
768 enum vga_switcheroo_state state)
769{
770 struct snd_card *card = pci_get_drvdata(pci);
771 struct azx *chip = card->private_data;
772 bool disabled;
773
f4c482a4 774 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 775 if (chip->init_failed)
776 return;
777
778 disabled = (state == VGA_SWITCHEROO_OFF);
779 if (chip->disabled == disabled)
780 return;
781
782 if (!chip->bus) {
783 chip->disabled = disabled;
784 if (!disabled) {
4e76a883
TI		 785 dev_info(chip->card->dev,
786 "Start delayed initialization\n");
5c90680e 787 if (azx_probe_continue(chip) < 0) {
4e76a883 788 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 789 chip->init_failed = true;
790 }
791 }
792 } else {
4e76a883
TI		 793 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
794 disabled ? "Disabling" : "Enabling");
a82d51ed 795 if (disabled) {
8928756d
DR		 796 pm_runtime_put_sync_suspend(card->dev);
797 azx_suspend(card->dev);
246efa4a
DA		 798 /* when we get suspended by vga switcheroo we end up in D3cold,
799 * however we have no ACPI handle, so pci/acpi can't put us there,
800 * put ourselves there */
801 pci->current_state = PCI_D3cold;
a82d51ed 802 chip->disabled = true;
128960a9 803 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 804 dev_warn(chip->card->dev,
805 "Cannot lock devices!\n");
a82d51ed
TI		 806 } else {
807 snd_hda_unlock_devices(chip->bus);
8928756d 808 pm_runtime_get_noresume(card->dev);
a82d51ed 809 chip->disabled = false;
8928756d 810 azx_resume(card->dev);
a82d51ed
TI		 811 }
812 }
813}
814
815static bool azx_vs_can_switch(struct pci_dev *pci)
816{
817 struct snd_card *card = pci_get_drvdata(pci);
818 struct azx *chip = card->private_data;
819
f4c482a4 820 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 821 if (chip->init_failed)
822 return false;
823 if (chip->disabled || !chip->bus)
824 return true;
825 if (snd_hda_lock_devices(chip->bus))
826 return false;
827 snd_hda_unlock_devices(chip->bus);
828 return true;
829}
830
e23e7a14 831static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 832{
833 struct pci_dev *p = get_bound_vga(chip->pci);
834 if (p) {
4e76a883
TI		 835 dev_info(chip->card->dev,
836 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 837 chip->use_vga_switcheroo = 1;
838 pci_dev_put(p);
839 }
840}
841
842static const struct vga_switcheroo_client_ops azx_vs_ops = {
843 .set_gpu_state = azx_vs_set_state,
844 .can_switch = azx_vs_can_switch,
845};
846
e23e7a14 847static int register_vga_switcheroo(struct azx *chip)
a82d51ed 848{
128960a9
TI		 849 int err;
850
a82d51ed
TI		 851 if (!chip->use_vga_switcheroo)
852 return 0;
853 /* FIXME: currently only handling DIS controller
854 * is there any machine with two switchable HDMI audio controllers?
855 */
128960a9 856 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 857 VGA_SWITCHEROO_DIS,
858 chip->bus != NULL);
128960a9
TI		 859 if (err < 0)
860 return err;
861 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 862
863 /* register as an optimus hdmi audio power domain */
8928756d
DR		 864 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
865 &chip->hdmi_pm_domain);
128960a9 866 return 0;
a82d51ed
TI		 867}
868#else
869#define init_vga_switcheroo(chip) /* NOP */
870#define register_vga_switcheroo(chip) 0
8393ec4a 871#define check_hdmi_disabled(pci) false
a82d51ed
TI		 872#endif /* SUPPORT_VGA_SWITCHER */
873
1da177e4
LT		 874/*
875 * destructor
876 */
a98f90fd 877static int azx_free(struct azx *chip)
1da177e4 878{
c67e2228 879 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 880 int i;
881
c67e2228
WX		 882 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
883 && chip->running)
884 pm_runtime_get_noresume(&pci->dev);
885
65fcd41d
TI		 886 azx_del_card_list(chip);
887
0cbf0098
TI		 888 azx_notifier_unregister(chip);
889
f4c482a4 890 chip->init_failed = 1; /* to be sure */
44728e97 891 complete_all(&chip->probe_wait);
f4c482a4 892
a82d51ed
TI		 893 if (use_vga_switcheroo(chip)) {
894 if (chip->disabled && chip->bus)
895 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 896 if (chip->vga_switcheroo_registered)
897 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 898 }
899
ce43fbae 900 if (chip->initialized) {
9ad593f6 901 azx_clear_irq_pending(chip);
07e4ca50 902 for (i = 0; i < chip->num_streams; i++)
1da177e4 903 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 904 azx_stop_chip(chip);
1da177e4
LT		 905 }
906
f000fd80 907 if (chip->irq >= 0)
1da177e4 908 free_irq(chip->irq, (void*)chip);
68e7fffc 909 if (chip->msi)
30b35399 910 pci_disable_msi(chip->pci);
f079c25a
TI		 911 if (chip->remap_addr)
912 iounmap(chip->remap_addr);
1da177e4 913
67908994 914 azx_free_stream_pages(chip);
a82d51ed
TI		 915 if (chip->region_requested)
916 pci_release_regions(chip->pci);
1da177e4 917 pci_disable_device(chip->pci);
07e4ca50 918 kfree(chip->azx_dev);
4918cdab
TI		 919#ifdef CONFIG_SND_HDA_PATCH_LOADER
920 if (chip->fw)
921 release_firmware(chip->fw);
922#endif
99a2008d
WX		 923 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
924 hda_display_power(false);
925 hda_i915_exit();
926 }
1da177e4
LT		 927 kfree(chip);
928
929 return 0;
930}
931
a98f90fd 932static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 933{
934 return azx_free(device->device_data);
935}
936
8393ec4a 937#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 938/*
939 * Check of disabled HDMI controller by vga-switcheroo
940 */
e23e7a14 941static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 942{
943 struct pci_dev *p;
944
945 /* check only discrete GPU */
946 switch (pci->vendor) {
947 case PCI_VENDOR_ID_ATI:
948 case PCI_VENDOR_ID_AMD:
949 case PCI_VENDOR_ID_NVIDIA:
950 if (pci->devfn == 1) {
951 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
952 pci->bus->number, 0);
953 if (p) {
954 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
955 return p;
956 pci_dev_put(p);
957 }
958 }
959 break;
960 }
961 return NULL;
962}
963
e23e7a14 964static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 965{
966 bool vga_inactive = false;
967 struct pci_dev *p = get_bound_vga(pci);
968
969 if (p) {
12b78a7f 970 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 971 vga_inactive = true;
972 pci_dev_put(p);
973 }
974 return vga_inactive;
975}
8393ec4a 976#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 977
3372a153
TI		 978/*
979 * white/black-listing for position_fix
980 */
e23e7a14 981static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 982 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
983 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 984 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 985 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 986 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 987 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 988 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 989 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 990 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 991 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 992 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 993 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 994 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 995 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 996 {}
997};
998
e23e7a14 999static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1000{
1001 const struct snd_pci_quirk *q;
1002
c673ba1c 1003 switch (fix) {
1dac6695 1004 case POS_FIX_AUTO:
c673ba1c
TI		 1005 case POS_FIX_LPIB:
1006 case POS_FIX_POSBUF:
4cb36310 1007 case POS_FIX_VIACOMBO:
a6f2fd55 1008 case POS_FIX_COMBO:
c673ba1c
TI		 1009 return fix;
1010 }
1011
c673ba1c
TI		 1012 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1013 if (q) {
4e76a883
TI		 1014 dev_info(chip->card->dev,
1015 "position_fix set to %d for device %04x:%04x\n",
1016 q->value, q->subvendor, q->subdevice);
c673ba1c 1017 return q->value;
3372a153 1018 }
bdd9ef24
DH		 1019
1020 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1021 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1022 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1023 return POS_FIX_VIACOMBO;
9477c58e
TI		 1024 }
1025 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1026 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1027 return POS_FIX_LPIB;
bdd9ef24 1028 }
c673ba1c 1029 return POS_FIX_AUTO;
3372a153
TI		 1030}
1031
669ba27a
TI		 1032/*
1033 * black-lists for probe_mask
1034 */
e23e7a14 1035static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1036 /* Thinkpad often breaks the controller communication when accessing
1037 * to the non-working (or non-existing) modem codec slot.
1038 */
1039 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1040 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1041 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1042 /* broken BIOS */
1043 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1044 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1045 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1046 /* forced codec slots */
93574844 1047 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1048 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1049 /* WinFast VP200 H (Teradici) user reported broken communication */
1050 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1051 {}
1052};
1053
f1eaaeec
TI		 1054#define AZX_FORCE_CODEC_MASK 0x100
1055
e23e7a14 1056static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1057{
1058 const struct snd_pci_quirk *q;
1059
f1eaaeec
TI		 1060 chip->codec_probe_mask = probe_mask[dev];
1061 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1062 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1063 if (q) {
4e76a883
TI		 1064 dev_info(chip->card->dev,
1065 "probe_mask set to 0x%x for device %04x:%04x\n",
1066 q->value, q->subvendor, q->subdevice);
f1eaaeec 1067 chip->codec_probe_mask = q->value;
669ba27a
TI		 1068 }
1069 }
f1eaaeec
TI		 1070
1071 /* check forced option */
1072 if (chip->codec_probe_mask != -1 &&
1073 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1074 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1075 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1076 chip->codec_mask);
f1eaaeec 1077 }
669ba27a
TI		 1078}
1079
4d8e22e0 1080/*
71623855 1081 * white/black-list for enable_msi
4d8e22e0 1082 */
e23e7a14 1083static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1084 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1085 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1086 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1087 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1088 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1089 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1090 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1091 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1092 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1093 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1094 {}
1095};
1096
e23e7a14 1097static void check_msi(struct azx *chip)
4d8e22e0
TI		 1098{
1099 const struct snd_pci_quirk *q;
1100
71623855
TI		 1101 if (enable_msi >= 0) {
1102 chip->msi = !!enable_msi;
4d8e22e0 1103 return;
71623855
TI		 1104 }
1105 chip->msi = 1; /* enable MSI as default */
1106 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1107 if (q) {
4e76a883
TI		 1108 dev_info(chip->card->dev,
1109 "msi for device %04x:%04x set to %d\n",
1110 q->subvendor, q->subdevice, q->value);
4d8e22e0 1111 chip->msi = q->value;
80c43ed7
TI		 1112 return;
1113 }
1114
1115 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1116 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1117 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1118 chip->msi = 0;
4d8e22e0
TI		 1119 }
1120}
1121
a1585d76 1122/* check the snoop mode availability */
e23e7a14 1123static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1124{
1125 bool snoop = chip->snoop;
1126
1127 switch (chip->driver_type) {
1128 case AZX_DRIVER_VIA:
1129 /* force to non-snoop mode for a new VIA controller
1130 * when BIOS is set
1131 */
1132 if (snoop) {
1133 u8 val;
1134 pci_read_config_byte(chip->pci, 0x42, &val);
1135 if (!(val & 0x80) && chip->pci->revision == 0x30)
1136 snoop = false;
1137 }
1138 break;
1139 case AZX_DRIVER_ATIHDMI_NS:
1140 /* new ATI HDMI requires non-snoop */
1141 snoop = false;
1142 break;
c1279f87
TI		 1143 case AZX_DRIVER_CTHDA:
1144 snoop = false;
1145 break;
a1585d76
TI		 1146 }
1147
1148 if (snoop != chip->snoop) {
4e76a883
TI		 1149 dev_info(chip->card->dev, "Force to %s mode\n",
1150 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1151 chip->snoop = snoop;
1152 }
1153}
669ba27a 1154
99a2008d
WX		 1155static void azx_probe_work(struct work_struct *work)
1156{
1157 azx_probe_continue(container_of(work, struct azx, probe_work));
1158}
99a2008d 1159
1da177e4
LT		 1160/*
1161 * constructor
1162 */
e23e7a14
BP		 1163static int azx_create(struct snd_card *card, struct pci_dev *pci,
1164 int dev, unsigned int driver_caps,
40830813 1165 const struct hda_controller_ops *hda_ops,
e23e7a14 1166 struct azx **rchip)
1da177e4 1167{
a98f90fd 1168 static struct snd_device_ops ops = {
1da177e4
LT		 1169 .dev_free = azx_dev_free,
1170 };
a82d51ed
TI		 1171 struct azx *chip;
1172 int err;
1da177e4
LT		 1173
1174 *rchip = NULL;
bcd72003 1175
927fc866
PM		 1176 err = pci_enable_device(pci);
1177 if (err < 0)
1da177e4
LT		 1178 return err;
1179
e560d8d8 1180 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1181 if (!chip) {
4e76a883 1182 dev_err(card->dev, "Cannot allocate chip\n");
1da177e4
LT		 1183 pci_disable_device(pci);
1184 return -ENOMEM;
1185 }
1186
1187 spin_lock_init(&chip->reg_lock);
62932df8 1188 mutex_init(&chip->open_mutex);
1da177e4
LT		 1189 chip->card = card;
1190 chip->pci = pci;
40830813 1191 chip->ops = hda_ops;
1da177e4 1192 chip->irq = -1;
9477c58e
TI		 1193 chip->driver_caps = driver_caps;
1194 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1195 check_msi(chip);
555e219f 1196 chip->dev_index = dev;
749ee287 1197 chip->jackpoll_ms = jackpoll_ms;
9ad593f6 1198 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 1199 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 1200 INIT_LIST_HEAD(&chip->list);
a82d51ed 1201 init_vga_switcheroo(chip);
f4c482a4 1202 init_completion(&chip->probe_wait);
1da177e4 1203
beaffc39
SG		 1204 chip->position_fix[0] = chip->position_fix[1] =
1205 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 1206 /* combo mode uses LPIB for playback */
1207 if (chip->position_fix[0] == POS_FIX_COMBO) {
1208 chip->position_fix[0] = POS_FIX_LPIB;
1209 chip->position_fix[1] = POS_FIX_AUTO;
1210 }
1211
5aba4f8e 1212 check_probe_mask(chip, dev);
3372a153 1213
27346166 1214 chip->single_cmd = single_cmd;
27fe48d9 1215 chip->snoop = hda_snoop;
a1585d76 1216 azx_check_snoop_available(chip);
c74db86b 1217
5c0d7bc1
TI		 1218 if (bdl_pos_adj[dev] < 0) {
1219 switch (chip->driver_type) {
0c6341ac 1220 case AZX_DRIVER_ICH:
32679f95 1221 case AZX_DRIVER_PCH:
0c6341ac 1222 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1223 break;
1224 default:
0c6341ac 1225 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1226 break;
1227 }
1228 }
9cdc0115 1229 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1230
a82d51ed
TI		 1231 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1232 if (err < 0) {
4e76a883 1233 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1234 azx_free(chip);
1235 return err;
1236 }
1237
99a2008d
WX		 1238 /* continue probing in work context as may trigger request module */
1239 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 1240
a82d51ed 1241 *rchip = chip;
99a2008d 1242
a82d51ed
TI		 1243 return 0;
1244}
1245
48c8b0eb 1246static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1247{
1248 int dev = chip->dev_index;
1249 struct pci_dev *pci = chip->pci;
1250 struct snd_card *card = chip->card;
67908994 1251 int err;
a82d51ed
TI		 1252 unsigned short gcap;
1253
07e4ca50
TI		 1254#if BITS_PER_LONG != 64
1255 /* Fix up base address on ULI M5461 */
1256 if (chip->driver_type == AZX_DRIVER_ULI) {
1257 u16 tmp3;
1258 pci_read_config_word(pci, 0x40, &tmp3);
1259 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1260 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1261 }
1262#endif
1263
927fc866 1264 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1265 if (err < 0)
1da177e4 1266 return err;
a82d51ed 1267 chip->region_requested = 1;
1da177e4 1268
927fc866 1269 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1270 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1271 if (chip->remap_addr == NULL) {
4e76a883 1272 dev_err(card->dev, "ioremap error\n");
a82d51ed 1273 return -ENXIO;
1da177e4
LT		 1274 }
1275
68e7fffc
TI		 1276 if (chip->msi)
1277 if (pci_enable_msi(pci) < 0)
1278 chip->msi = 0;
7376d013 1279
a82d51ed
TI		 1280 if (azx_acquire_irq(chip, 0) < 0)
1281 return -EBUSY;
1da177e4
LT		 1282
1283 pci_set_master(pci);
1284 synchronize_irq(chip->irq);
1285
bcd72003 1286 gcap = azx_readw(chip, GCAP);
4e76a883 1287 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1288
dc4c2e6b 1289 /* disable SB600 64bit support for safety */
9477c58e 1290 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1291 struct pci_dev *p_smbus;
1292 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1293 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1294 NULL);
1295 if (p_smbus) {
1296 if (p_smbus->revision < 0x30)
1297 gcap &= ~ICH6_GCAP_64OK;
1298 pci_dev_put(p_smbus);
1299 }
1300 }
09240cf4 1301
9477c58e
TI		 1302 /* disable 64bit DMA address on some devices */
1303 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1304 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1305 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1306 }
396087ea 1307
2ae66c26 1308 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1309 if (align_buffer_size >= 0)
1310 chip->align_buffer_size = !!align_buffer_size;
1311 else {
1312 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1313 chip->align_buffer_size = 0;
1314 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1315 chip->align_buffer_size = 1;
1316 else
1317 chip->align_buffer_size = 1;
1318 }
2ae66c26 1319
cf7aaca8 1320 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1321 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1322 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1323 else {
e930438c
YH		 1324 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1325 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1326 }
cf7aaca8 1327
8b6ed8e7
TI		 1328 /* read number of streams from GCAP register instead of using
1329 * hardcoded value
1330 */
1331 chip->capture_streams = (gcap >> 8) & 0x0f;
1332 chip->playback_streams = (gcap >> 12) & 0x0f;
1333 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1334 /* gcap didn't give any info, switching to old method */
1335
1336 switch (chip->driver_type) {
1337 case AZX_DRIVER_ULI:
1338 chip->playback_streams = ULI_NUM_PLAYBACK;
1339 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1340 break;
1341 case AZX_DRIVER_ATIHDMI:
1815b34a 1342 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1343 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1344 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1345 break;
c4da29ca 1346 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1347 default:
1348 chip->playback_streams = ICH6_NUM_PLAYBACK;
1349 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1350 break;
1351 }
07e4ca50 1352 }
8b6ed8e7
TI		 1353 chip->capture_index_offset = 0;
1354 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1355 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1356 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1357 GFP_KERNEL);
927fc866 1358 if (!chip->azx_dev) {
4e76a883 1359 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1360 return -ENOMEM;
07e4ca50
TI		 1361 }
1362
67908994 1363 err = azx_alloc_stream_pages(chip);
81740861 1364 if (err < 0)
a82d51ed 1365 return err;
1da177e4
LT		 1366
1367 /* initialize streams */
1368 azx_init_stream(chip);
1369
1370 /* initialize chip */
cb53c626 1371 azx_init_pci(chip);
10e77dda 1372 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1373
1374 /* codec detection */
927fc866 1375 if (!chip->codec_mask) {
4e76a883 1376 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1377 return -ENODEV;
1da177e4
LT		 1378 }
1379
07e4ca50 1380 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1381 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1382 sizeof(card->shortname));
1383 snprintf(card->longname, sizeof(card->longname),
1384 "%s at 0x%lx irq %i",
1385 card->shortname, chip->addr, chip->irq);
07e4ca50 1386
1da177e4 1387 return 0;
1da177e4
LT		 1388}
1389
cb53c626
TI		 1390static void power_down_all_codecs(struct azx *chip)
1391{
83012a7c 1392#ifdef CONFIG_PM
cb53c626
TI		 1393 /* The codecs were powered up in snd_hda_codec_new().
1394 * Now all initialization done, so turn them down if possible
1395 */
1396 struct hda_codec *codec;
1397 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1398 snd_hda_power_down(codec);
1399 }
1400#endif
1401}
1402
97c6a3d1 1403#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1404/* callback from request_firmware_nowait() */
1405static void azx_firmware_cb(const struct firmware *fw, void *context)
1406{
1407 struct snd_card *card = context;
1408 struct azx *chip = card->private_data;
1409 struct pci_dev *pci = chip->pci;
1410
1411 if (!fw) {
4e76a883 1412 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1413 goto error;
1414 }
1415
1416 chip->fw = fw;
1417 if (!chip->disabled) {
1418 /* continue probing */
1419 if (azx_probe_continue(chip))
1420 goto error;
1421 }
1422 return; /* OK */
1423
1424 error:
1425 snd_card_free(card);
1426 pci_set_drvdata(pci, NULL);
1427}
97c6a3d1 1428#endif
5cb543db 1429
40830813
DR		 1430/*
1431 * HDA controller ops.
1432 */
1433
1434/* PCI register access. */
db291e36 1435static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1436{
1437 writel(value, addr);
1438}
1439
db291e36 1440static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1441{
1442 return readl(addr);
1443}
1444
db291e36 1445static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1446{
1447 writew(value, addr);
1448}
1449
db291e36 1450static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1451{
1452 return readw(addr);
1453}
1454
db291e36 1455static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1456{
1457 writeb(value, addr);
1458}
1459
db291e36 1460static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1461{
1462 return readb(addr);
1463}
1464
f46ea609
DR		 1465static int disable_msi_reset_irq(struct azx *chip)
1466{
1467 int err;
1468
1469 free_irq(chip->irq, chip);
1470 chip->irq = -1;
1471 pci_disable_msi(chip->pci);
1472 chip->msi = 0;
1473 err = azx_acquire_irq(chip, 1);
1474 if (err < 0)
1475 return err;
1476
1477 return 0;
1478}
1479
b419b35b
DR		 1480/* DMA page allocation helpers. */
1481static int dma_alloc_pages(struct azx *chip,
1482 int type,
1483 size_t size,
1484 struct snd_dma_buffer *buf)
1485{
1486 int err;
1487
1488 err = snd_dma_alloc_pages(type,
1489 chip->card->dev,
1490 size, buf);
1491 if (err < 0)
1492 return err;
1493 mark_pages_wc(chip, buf, true);
1494 return 0;
1495}
1496
1497static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1498{
1499 mark_pages_wc(chip, buf, false);
1500 snd_dma_free_pages(buf);
1501}
1502
1503static int substream_alloc_pages(struct azx *chip,
1504 struct snd_pcm_substream *substream,
1505 size_t size)
1506{
1507 struct azx_dev *azx_dev = get_azx_dev(substream);
1508 int ret;
1509
1510 mark_runtime_wc(chip, azx_dev, substream, false);
1511 azx_dev->bufsize = 0;
1512 azx_dev->period_bytes = 0;
1513 azx_dev->format_val = 0;
1514 ret = snd_pcm_lib_malloc_pages(substream, size);
1515 if (ret < 0)
1516 return ret;
1517 mark_runtime_wc(chip, azx_dev, substream, true);
1518 return 0;
1519}
1520
1521static int substream_free_pages(struct azx *chip,
1522 struct snd_pcm_substream *substream)
1523{
1524 struct azx_dev *azx_dev = get_azx_dev(substream);
1525 mark_runtime_wc(chip, azx_dev, substream, false);
1526 return snd_pcm_lib_free_pages(substream);
1527}
1528
8769b278
DR		 1529static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1530 struct vm_area_struct *area)
1531{
1532#ifdef CONFIG_X86
1533 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1534 struct azx *chip = apcm->chip;
1535 if (!azx_snoop(chip))
1536 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1537#endif
1538}
1539
40830813 1540static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1541 .reg_writel = pci_azx_writel,
1542 .reg_readl = pci_azx_readl,
1543 .reg_writew = pci_azx_writew,
1544 .reg_readw = pci_azx_readw,
1545 .reg_writeb = pci_azx_writeb,
1546 .reg_readb = pci_azx_readb,
f46ea609 1547 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1548 .dma_alloc_pages = dma_alloc_pages,
1549 .dma_free_pages = dma_free_pages,
1550 .substream_alloc_pages = substream_alloc_pages,
1551 .substream_free_pages = substream_free_pages,
8769b278 1552 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1553 .position_check = azx_position_check,
40830813
DR		 1554};
1555
e23e7a14
BP		 1556static int azx_probe(struct pci_dev *pci,
1557 const struct pci_device_id *pci_id)
1da177e4 1558{
5aba4f8e 1559 static int dev;
a98f90fd
TI		 1560 struct snd_card *card;
1561 struct azx *chip;
aad730d0 1562 bool schedule_probe;
927fc866 1563 int err;
1da177e4 1564
5aba4f8e
TI		 1565 if (dev >= SNDRV_CARDS)
1566 return -ENODEV;
1567 if (!enable[dev]) {
1568 dev++;
1569 return -ENOENT;
1570 }
1571
60c5772b
TI		 1572 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1573 0, &card);
e58de7ba 1574 if (err < 0) {
4e76a883 1575 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1576 return err;
1da177e4
LT		 1577 }
1578
40830813
DR		 1579 err = azx_create(card, pci, dev, pci_id->driver_data,
1580 &pci_hda_ops, &chip);
41dda0fd
WF		 1581 if (err < 0)
1582 goto out_free;
421a1252 1583 card->private_data = chip;
f4c482a4
TI		 1584
1585 pci_set_drvdata(pci, card);
1586
1587 err = register_vga_switcheroo(chip);
1588 if (err < 0) {
4e76a883 1589 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1590 goto out_free;
1591 }
1592
1593 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1594 dev_info(card->dev, "VGA controller is disabled\n");
1595 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1596 chip->disabled = true;
1597 }
1598
aad730d0 1599 schedule_probe = !chip->disabled;
1da177e4 1600
4918cdab
TI		 1601#ifdef CONFIG_SND_HDA_PATCH_LOADER
1602 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1603 dev_info(card->dev, "Applying patch firmware '%s'\n",
1604 patch[dev]);
5cb543db
TI		 1605 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1606 &pci->dev, GFP_KERNEL, card,
1607 azx_firmware_cb);
4918cdab
TI		 1608 if (err < 0)
1609 goto out_free;
aad730d0 1610 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1611 }
1612#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1613
aad730d0
TI		 1614#ifndef CONFIG_SND_HDA_I915
1615 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1616 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1617#endif
99a2008d 1618
aad730d0
TI		 1619 if (schedule_probe)
1620 schedule_work(&chip->probe_work);
a82d51ed 1621
a82d51ed 1622 dev++;
88d071fc
TI		 1623 if (chip->disabled)
1624 complete_all(&chip->probe_wait);
a82d51ed
TI		 1625 return 0;
1626
1627out_free:
1628 snd_card_free(card);
1629 return err;
1630}
1631
e62a42ae
DR		 1632/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1633static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1634 [AZX_DRIVER_NVIDIA] = 8,
1635 [AZX_DRIVER_TERA] = 1,
1636};
1637
48c8b0eb 1638static int azx_probe_continue(struct azx *chip)
a82d51ed 1639{
c67e2228 1640 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1641 int dev = chip->dev_index;
1642 int err;
1643
99a2008d
WX		 1644 /* Request power well for Haswell HDA controller and codec */
1645 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1646#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1647 err = hda_i915_init();
1648 if (err < 0) {
4e76a883
TI		 1649 dev_err(chip->card->dev,
1650 "Error request power-well from i915\n");
99a2008d
WX		 1651 goto out_free;
1652 }
c841ad2a 1653#endif
99a2008d
WX		 1654 hda_display_power(true);
1655 }
1656
5c90680e
TI		 1657 err = azx_first_init(chip);
1658 if (err < 0)
1659 goto out_free;
1660
2dca0bba
JK		 1661#ifdef CONFIG_SND_HDA_INPUT_BEEP
1662 chip->beep_mode = beep_mode[dev];
1663#endif
1664
1da177e4 1665 /* create codec instances */
e62a42ae
DR		 1666 err = azx_codec_create(chip, model[dev],
1667 azx_max_codecs[chip->driver_type],
1668 power_save_addr);
1669
41dda0fd
WF		 1670 if (err < 0)
1671 goto out_free;
4ea6fbc8 1672#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1673 if (chip->fw) {
1674 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1675 chip->fw->data);
4ea6fbc8
TI		 1676 if (err < 0)
1677 goto out_free;
e39ae856 1678#ifndef CONFIG_PM
4918cdab
TI		 1679 release_firmware(chip->fw); /* no longer needed */
1680 chip->fw = NULL;
e39ae856 1681#endif
4ea6fbc8
TI		 1682 }
1683#endif
10e77dda 1684 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1685 err = azx_codec_configure(chip);
1686 if (err < 0)
1687 goto out_free;
1688 }
1da177e4
LT		 1689
1690 /* create PCM streams */
176d5335 1691 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1692 if (err < 0)
1693 goto out_free;
1da177e4
LT		 1694
1695 /* create mixer controls */
d01ce99f 1696 err = azx_mixer_create(chip);
41dda0fd
WF		 1697 if (err < 0)
1698 goto out_free;
1da177e4 1699
a82d51ed 1700 err = snd_card_register(chip->card);
41dda0fd
WF		 1701 if (err < 0)
1702 goto out_free;
1da177e4 1703
cb53c626
TI		 1704 chip->running = 1;
1705 power_down_all_codecs(chip);
0cbf0098 1706 azx_notifier_register(chip);
65fcd41d 1707 azx_add_card_list(chip);
246efa4a 1708 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 1709 pm_runtime_put_noidle(&pci->dev);
1da177e4 1710
41dda0fd 1711out_free:
88d071fc
TI		 1712 if (err < 0)
1713 chip->init_failed = 1;
1714 complete_all(&chip->probe_wait);
41dda0fd 1715 return err;
1da177e4
LT		 1716}
1717
e23e7a14 1718static void azx_remove(struct pci_dev *pci)
1da177e4 1719{
9121947d 1720 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1721
9121947d
TI		 1722 if (card)
1723 snd_card_free(card);
1da177e4
LT		 1724}
1725
1726/* PCI IDs */
cebe41d4 1727static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 1728 /* CPT */
9477c58e 1729 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1730 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1731 /* PBG */
9477c58e 1732 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1733 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1734 /* Panther Point */
9477c58e 1735 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1736 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1737 /* Lynx Point */
1738 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1739 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1740 /* Wellsburg */
1741 { PCI_DEVICE(0x8086, 0x8d20),
1742 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1743 { PCI_DEVICE(0x8086, 0x8d21),
1744 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1745 /* Lynx Point-LP */
1746 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1747 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1748 /* Lynx Point-LP */
1749 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1750 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1751 /* Wildcat Point-LP */
1752 { PCI_DEVICE(0x8086, 0x9ca0),
1753 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 1754 /* Haswell */
4a7c516b 1755 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 1756 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 1757 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 1758 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 1759 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 1760 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 1761 /* Broadwell */
1762 { PCI_DEVICE(0x8086, 0x160c),
1763 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 1764 /* 5 Series/3400 */
1765 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 1766 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 1767 /* Poulsbo */
9477c58e 1768 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 1769 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1770 /* Oaktrail */
09904b95 1771 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 1772 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 1773 /* BayTrail */
1774 { PCI_DEVICE(0x8086, 0x0f04),
1775 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 1776 /* ICH */
8b0bd226 1777 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 1778 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1779 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 1780 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 1781 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1782 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 1783 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 1784 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1785 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 1786 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 1787 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1788 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 1789 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 1790 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1791 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1792 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 1793 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1794 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1795 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 1796 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1797 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 1798 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 1799 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1800 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 1801 /* Generic Intel */
1802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
1803 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1804 .class_mask = 0xffffff,
2ae66c26 1805 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 1806 /* ATI SB 450/600/700/800/900 */
1807 { PCI_DEVICE(0x1002, 0x437b),
1808 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1809 { PCI_DEVICE(0x1002, 0x4383),
1810 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1811 /* AMD Hudson */
1812 { PCI_DEVICE(0x1022, 0x780d),
1813 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 1814 /* ATI HDMI */
9477c58e
TI		 1815 { PCI_DEVICE(0x1002, 0x793b),
1816 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1817 { PCI_DEVICE(0x1002, 0x7919),
1818 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1819 { PCI_DEVICE(0x1002, 0x960f),
1820 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1821 { PCI_DEVICE(0x1002, 0x970f),
1822 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1823 { PCI_DEVICE(0x1002, 0xaa00),
1824 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1825 { PCI_DEVICE(0x1002, 0xaa08),
1826 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1827 { PCI_DEVICE(0x1002, 0xaa10),
1828 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1829 { PCI_DEVICE(0x1002, 0xaa18),
1830 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1831 { PCI_DEVICE(0x1002, 0xaa20),
1832 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1833 { PCI_DEVICE(0x1002, 0xaa28),
1834 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1835 { PCI_DEVICE(0x1002, 0xaa30),
1836 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1837 { PCI_DEVICE(0x1002, 0xaa38),
1838 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1839 { PCI_DEVICE(0x1002, 0xaa40),
1840 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1841 { PCI_DEVICE(0x1002, 0xaa48),
1842 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 1843 { PCI_DEVICE(0x1002, 0xaa50),
1844 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1845 { PCI_DEVICE(0x1002, 0xaa58),
1846 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1847 { PCI_DEVICE(0x1002, 0xaa60),
1848 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1849 { PCI_DEVICE(0x1002, 0xaa68),
1850 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1851 { PCI_DEVICE(0x1002, 0xaa80),
1852 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1853 { PCI_DEVICE(0x1002, 0xaa88),
1854 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1855 { PCI_DEVICE(0x1002, 0xaa90),
1856 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1857 { PCI_DEVICE(0x1002, 0xaa98),
1858 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 1859 { PCI_DEVICE(0x1002, 0x9902),
1860 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1861 { PCI_DEVICE(0x1002, 0xaaa0),
1862 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1863 { PCI_DEVICE(0x1002, 0xaaa8),
1864 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1865 { PCI_DEVICE(0x1002, 0xaab0),
1866 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 1867 /* VIA VT8251/VT8237A */
9477c58e
TI		 1868 { PCI_DEVICE(0x1106, 0x3288),
1869 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 1870 /* VIA GFX VT7122/VX900 */
1871 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
1872 /* VIA GFX VT6122/VX11 */
1873 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 1874 /* SIS966 */
1875 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
1876 /* ULI M5461 */
1877 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
1878 /* NVIDIA MCP */
0c2fd1bf
TI		 1879 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1880 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1881 .class_mask = 0xffffff,
9477c58e 1882 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 1883 /* Teradici */
9477c58e
TI		 1884 { PCI_DEVICE(0x6549, 0x1200),
1885 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 1886 { PCI_DEVICE(0x6549, 0x2200),
1887 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 1888 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 1889 /* CTHDA chips */
1890 { PCI_DEVICE(0x1102, 0x0010),
1891 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
1892 { PCI_DEVICE(0x1102, 0x0012),
1893 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 1894#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 1895 /* the following entry conflicts with snd-ctxfi driver,
1896 * as ctxfi driver mutates from HD-audio to native mode with
1897 * a special command sequence.
1898 */
4e01f54b
TI		 1899 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
1900 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1901 .class_mask = 0xffffff,
9477c58e 1902 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1903 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 1904#else
1905 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 1906 { PCI_DEVICE(0x1102, 0x0009),
1907 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1908 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 1909#endif
e35d4b11
OS		 1910 /* Vortex86MX */
1911 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 1912 /* VMware HDAudio */
1913 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 1914 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 1915 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
1916 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1917 .class_mask = 0xffffff,
9477c58e 1918 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 1919 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
1920 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1921 .class_mask = 0xffffff,
9477c58e 1922 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 1923 { 0, }
1924};
1925MODULE_DEVICE_TABLE(pci, azx_ids);
1926
1927/* pci_driver definition */
e9f66d9b 1928static struct pci_driver azx_driver = {
3733e424 1929 .name = KBUILD_MODNAME,
1da177e4
LT		 1930 .id_table = azx_ids,
1931 .probe = azx_probe,
e23e7a14 1932 .remove = azx_remove,
68cb2b55
TI		 1933 .driver = {
1934 .pm = AZX_PM_OPS,
1935 },
1da177e4
LT		 1936};
1937
e9f66d9b 1938module_pci_driver(azx_driver);
Linux kernel - Deliverables
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