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ALSA: hda - Support VGA-switcheroo
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9
TI		 48#include <linux/io.h>
49#ifdef CONFIG_X86
50/* for snoop control */
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
1da177e4
LT		 54#include <sound/core.h>
55#include <sound/initval.h>
9121947d 56#include <linux/vgaarb.h>
a82d51ed 57#include <linux/vga_switcheroo.h>
1da177e4
LT		 58#include "hda_codec.h"
59
60
5aba4f8e
TI		 61static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 63static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e
TI		 64static char *model[SNDRV_CARDS];
65static int position_fix[SNDRV_CARDS];
5c0d7bc1 66static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 67static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 68static int probe_only[SNDRV_CARDS];
a67ff6a5 69static bool single_cmd;
71623855 70static int enable_msi = -1;
4ea6fbc8
TI		 71#ifdef CONFIG_SND_HDA_PATCH_LOADER
72static char *patch[SNDRV_CARDS];
73#endif
2dca0bba
JK		 74#ifdef CONFIG_SND_HDA_INPUT_BEEP
75static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
76 CONFIG_SND_HDA_INPUT_BEEP_MODE};
77#endif
1da177e4 78
5aba4f8e 79module_param_array(index, int, NULL, 0444);
1da177e4 80MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 81module_param_array(id, charp, NULL, 0444);
1da177e4 82MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 83module_param_array(enable, bool, NULL, 0444);
84MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
85module_param_array(model, charp, NULL, 0444);
1da177e4 86MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 87module_param_array(position_fix, int, NULL, 0444);
4cb36310 88MODULE_PARM_DESC(position_fix, "DMA pointer read method."
a6f2fd55 89 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 90module_param_array(bdl_pos_adj, int, NULL, 0644);
91MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 92module_param_array(probe_mask, int, NULL, 0444);
606ad75f 93MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 94module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 95MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 96module_param(single_cmd, bool, 0444);
d01ce99f
TI		 97MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
98 "(for debugging only).");
ac9ef6cf 99module_param(enable_msi, bint, 0444);
134a11f0 100MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 101#ifdef CONFIG_SND_HDA_PATCH_LOADER
102module_param_array(patch, charp, NULL, 0444);
103MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
104#endif
2dca0bba
JK		 105#ifdef CONFIG_SND_HDA_INPUT_BEEP
106module_param_array(beep_mode, int, NULL, 0444);
107MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
108 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
109#endif
606ad75f 110
dee1b66c 111#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 112static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
113module_param(power_save, int, 0644);
114MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
115 "(in second, 0 = disable).");
1da177e4 116
dee1b66c
TI		 117/* reset the HD-audio controller in power save mode.
118 * this may give more power-saving, but will take longer time to
119 * wake up.
120 */
a67ff6a5 121static bool power_save_controller = 1;
dee1b66c
TI		 122module_param(power_save_controller, bool, 0644);
123MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
124#endif
125
7bfe059e
TI		 126static int align_buffer_size = -1;
127module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 128MODULE_PARM_DESC(align_buffer_size,
129 "Force buffer and period sizes to be multiple of 128 bytes.");
130
27fe48d9
TI		 131#ifdef CONFIG_X86
132static bool hda_snoop = true;
133module_param_named(snoop, hda_snoop, bool, 0444);
134MODULE_PARM_DESC(snoop, "Enable/disable snooping");
135#define azx_snoop(chip) (chip)->snoop
136#else
137#define hda_snoop true
138#define azx_snoop(chip) true
139#endif
140
141
1da177e4
LT		 142MODULE_LICENSE("GPL");
143MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
144 "{Intel, ICH6M},"
2f1b3818 145 "{Intel, ICH7},"
f5d40b30 146 "{Intel, ESB2},"
d2981393 147 "{Intel, ICH8},"
f9cc8a8b 148 "{Intel, ICH9},"
c34f5a04 149 "{Intel, ICH10},"
b29c2360 150 "{Intel, PCH},"
d2f2fcd2 151 "{Intel, CPT},"
d2edeb7c 152 "{Intel, PPT},"
8bc039a1 153 "{Intel, LPT},"
cea310e8 154 "{Intel, PBG},"
4979bca9 155 "{Intel, SCH},"
fc20a562 156 "{ATI, SB450},"
89be83f8 157 "{ATI, SB600},"
778b6e1b 158 "{ATI, RS600},"
5b15c95f 159 "{ATI, RS690},"
e6db1119
WL		 160 "{ATI, RS780},"
161 "{ATI, R600},"
2797f724
HRK		 162 "{ATI, RV630},"
163 "{ATI, RV610},"
27da1834
WL		 164 "{ATI, RV670},"
165 "{ATI, RV635},"
166 "{ATI, RV620},"
167 "{ATI, RV770},"
fc20a562 168 "{VIA, VT8251},"
47672310 169 "{VIA, VT8237A},"
07e4ca50
TI		 170 "{SiS, SIS966},"
171 "{ULI, M5461}}");
1da177e4
LT		 172MODULE_DESCRIPTION("Intel HDA driver");
173
4abc1cc2
TI		 174#ifdef CONFIG_SND_VERBOSE_PRINTK
175#define SFX /* nop */
176#else
1da177e4 177#define SFX "hda-intel: "
4abc1cc2 178#endif
cb53c626 179
a82d51ed
TI		 180#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
181#ifdef CONFIG_SND_HDA_CODEC_HDMI
182#define SUPPORT_VGA_SWITCHEROO
183#endif
184#endif
185
186
1da177e4
LT		 187/*
188 * registers
189 */
190#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 191#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
192#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
193#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
194#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
195#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 196#define ICH6_REG_VMIN 0x02
197#define ICH6_REG_VMAJ 0x03
198#define ICH6_REG_OUTPAY 0x04
199#define ICH6_REG_INPAY 0x06
200#define ICH6_REG_GCTL 0x08
8a933ece 201#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 202#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
203#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 204#define ICH6_REG_WAKEEN 0x0c
205#define ICH6_REG_STATESTS 0x0e
206#define ICH6_REG_GSTS 0x10
b21fadb9 207#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 208#define ICH6_REG_INTCTL 0x20
209#define ICH6_REG_INTSTS 0x24
e5463720 210#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 211#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
212#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 213#define ICH6_REG_CORBLBASE 0x40
214#define ICH6_REG_CORBUBASE 0x44
215#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 216#define ICH6_REG_CORBRP 0x4a
217#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 218#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 219#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
220#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 221#define ICH6_REG_CORBSTS 0x4d
b21fadb9 222#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 223#define ICH6_REG_CORBSIZE 0x4e
224
225#define ICH6_REG_RIRBLBASE 0x50
226#define ICH6_REG_RIRBUBASE 0x54
227#define ICH6_REG_RIRBWP 0x58
b21fadb9 228#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 229#define ICH6_REG_RINTCNT 0x5a
230#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 231#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
232#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
233#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 234#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 235#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
236#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 237#define ICH6_REG_RIRBSIZE 0x5e
238
239#define ICH6_REG_IC 0x60
240#define ICH6_REG_IR 0x64
241#define ICH6_REG_IRS 0x68
242#define ICH6_IRS_VALID (1<<1)
243#define ICH6_IRS_BUSY (1<<0)
244
245#define ICH6_REG_DPLBASE 0x70
246#define ICH6_REG_DPUBASE 0x74
247#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
248
249/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
250enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
251
252/* stream register offsets from stream base */
253#define ICH6_REG_SD_CTL 0x00
254#define ICH6_REG_SD_STS 0x03
255#define ICH6_REG_SD_LPIB 0x04
256#define ICH6_REG_SD_CBL 0x08
257#define ICH6_REG_SD_LVI 0x0c
258#define ICH6_REG_SD_FIFOW 0x0e
259#define ICH6_REG_SD_FIFOSIZE 0x10
260#define ICH6_REG_SD_FORMAT 0x12
261#define ICH6_REG_SD_BDLPL 0x18
262#define ICH6_REG_SD_BDLPU 0x1c
263
264/* PCI space */
265#define ICH6_PCIREG_TCSEL 0x44
266
267/*
268 * other constants
269 */
270
271/* max number of SDs */
07e4ca50 272/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 273#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 274#define ICH6_NUM_PLAYBACK 4
275
276/* ULI has 6 playback and 5 capture */
07e4ca50 277#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 278#define ULI_NUM_PLAYBACK 6
279
778b6e1b 280/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 281#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 282#define ATIHDMI_NUM_PLAYBACK 1
283
f269002e
KY		 284/* TERA has 4 playback and 3 capture */
285#define TERA_NUM_CAPTURE 3
286#define TERA_NUM_PLAYBACK 4
287
07e4ca50
TI		 288/* this number is statically defined for simplicity */
289#define MAX_AZX_DEV 16
290
1da177e4 291/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 292#define BDL_SIZE 4096
293#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
294#define AZX_MAX_FRAG 32
1da177e4
LT		 295/* max buffer size - no h/w limit, you can increase as you like */
296#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 297
298/* RIRB int mask: overrun[2], response[0] */
299#define RIRB_INT_RESPONSE 0x01
300#define RIRB_INT_OVERRUN 0x04
301#define RIRB_INT_MASK 0x05
302
2f5983f2 303/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 304#define AZX_MAX_CODECS 8
305#define AZX_DEFAULT_CODECS 4
deadff16 306#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 307
308/* SD_CTL bits */
309#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
310#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 311#define SD_CTL_STRIPE (3 << 16) /* stripe control */
312#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
313#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 314#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
315#define SD_CTL_STREAM_TAG_SHIFT 20
316
317/* SD_CTL and SD_STS */
318#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
319#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
320#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 321#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
322 SD_INT_COMPLETE)
1da177e4
LT		 323
324/* SD_STS */
325#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
326
327/* INTCTL and INTSTS */
d01ce99f
TI		 328#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
329#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
330#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 331
1da177e4
LT		 332/* below are so far hardcoded - should read registers in future */
333#define ICH6_MAX_CORB_ENTRIES 256
334#define ICH6_MAX_RIRB_ENTRIES 256
335
c74db86b
TI		 336/* position fix mode */
337enum {
0be3b5d3 338 POS_FIX_AUTO,
d2e1c973 339 POS_FIX_LPIB,
0be3b5d3 340 POS_FIX_POSBUF,
4cb36310 341 POS_FIX_VIACOMBO,
a6f2fd55 342 POS_FIX_COMBO,
c74db86b 343};
1da177e4 344
f5d40b30 345/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 346#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
347#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
348
da3fca21
V		 349/* Defines for Nvidia HDA support */
350#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
351#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 352#define NVIDIA_HDA_ISTRM_COH 0x4d
353#define NVIDIA_HDA_OSTRM_COH 0x4c
354#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 355
90a5ad52
TI		 356/* Defines for Intel SCH HDA snoop control */
357#define INTEL_SCH_HDA_DEVC 0x78
358#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
359
0e153474
JC		 360/* Define IN stream 0 FIFO size offset in VIA controller */
361#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
362/* Define VIA HD Audio Device ID*/
363#define VIA_HDAC_DEVICE_ID 0x3288
364
c4da29ca
YL		 365/* HD Audio class code */
366#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 367
1da177e4
LT		 368/*
369 */
370
a98f90fd 371struct azx_dev {
4ce107b9 372 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 373 u32 *posbuf; /* position buffer pointer */
1da177e4 374
d01ce99f 375 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 376 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 377 unsigned int frags; /* number for period in the play buffer */
378 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 379 unsigned long start_wallclk; /* start + minimum wallclk */
380 unsigned long period_wallclk; /* wallclk for period */
1da177e4 381
d01ce99f 382 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 383
d01ce99f 384 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 385
386 /* pcm support */
d01ce99f
TI		 387 struct snd_pcm_substream *substream; /* assigned substream,
388 * set in PCM open
389 */
390 unsigned int format_val; /* format value to be set in the
391 * controller and the codec
392 */
1da177e4
LT		 393 unsigned char stream_tag; /* assigned stream */
394 unsigned char index; /* stream index */
d5cf9911 395 int assigned_key; /* last device# key assigned to */
1da177e4 396
927fc866
PM		 397 unsigned int opened :1;
398 unsigned int running :1;
675f25d4 399 unsigned int irq_pending :1;
0e153474
JC		 400 /*
401 * For VIA:
402 * A flag to ensure DMA position is 0
403 * when link position is not greater than FIFO size
404 */
405 unsigned int insufficient :1;
27fe48d9 406 unsigned int wc_marked:1;
1da177e4
LT		 407};
408
409/* CORB/RIRB */
a98f90fd 410struct azx_rb {
1da177e4
LT		 411 u32 *buf; /* CORB/RIRB buffer
412 * Each CORB entry is 4byte, RIRB is 8byte
413 */
414 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
415 /* for RIRB */
416 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 417 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
418 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 419};
420
01b65bfb
TI		 421struct azx_pcm {
422 struct azx *chip;
423 struct snd_pcm *pcm;
424 struct hda_codec *codec;
425 struct hda_pcm_stream *hinfo[2];
426 struct list_head list;
427};
428
a98f90fd
TI		 429struct azx {
430 struct snd_card *card;
1da177e4 431 struct pci_dev *pci;
555e219f 432 int dev_index;
1da177e4 433
07e4ca50
TI		 434 /* chip type specific */
435 int driver_type;
9477c58e 436 unsigned int driver_caps;
07e4ca50
TI		 437 int playback_streams;
438 int playback_index_offset;
439 int capture_streams;
440 int capture_index_offset;
441 int num_streams;
442
1da177e4
LT		 443 /* pci resources */
444 unsigned long addr;
445 void __iomem *remap_addr;
446 int irq;
447
448 /* locks */
449 spinlock_t reg_lock;
62932df8 450 struct mutex open_mutex;
1da177e4 451
07e4ca50 452 /* streams (x num_streams) */
a98f90fd 453 struct azx_dev *azx_dev;
1da177e4
LT		 454
455 /* PCM */
01b65bfb 456 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 457
458 /* HD codec */
459 unsigned short codec_mask;
f1eaaeec 460 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 461 struct hda_bus *bus;
2dca0bba 462 unsigned int beep_mode;
1da177e4
LT		 463
464 /* CORB/RIRB */
a98f90fd
TI		 465 struct azx_rb corb;
466 struct azx_rb rirb;
1da177e4 467
4ce107b9 468 /* CORB/RIRB and position buffers */
1da177e4
LT		 469 struct snd_dma_buffer rb;
470 struct snd_dma_buffer posbuf;
c74db86b
TI		 471
472 /* flags */
beaffc39 473 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 474 int poll_count;
cb53c626 475 unsigned int running :1;
927fc866
PM		 476 unsigned int initialized :1;
477 unsigned int single_cmd :1;
478 unsigned int polling_mode :1;
68e7fffc 479 unsigned int msi :1;
a6a950a8 480 unsigned int irq_pending_warned :1;
6ce4a3bc 481 unsigned int probing :1; /* codec probing phase */
27fe48d9 482 unsigned int snoop:1;
52409aa6 483 unsigned int align_buffer_size:1;
a82d51ed
TI		 484 unsigned int region_requested:1;
485
486 /* VGA-switcheroo setup */
487 unsigned int use_vga_switcheroo:1;
488 unsigned int init_failed:1; /* delayed init failed */
489 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 490
491 /* for debugging */
feb27340 492 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 493
494 /* for pending irqs */
495 struct work_struct irq_pending_work;
0cbf0098
TI		 496
497 /* reboot notifier (for mysterious hangup problem at power-down) */
498 struct notifier_block reboot_notifier;
1da177e4
LT		 499};
500
07e4ca50
TI		 501/* driver types */
502enum {
503 AZX_DRIVER_ICH,
32679f95 504 AZX_DRIVER_PCH,
4979bca9 505 AZX_DRIVER_SCH,
07e4ca50 506 AZX_DRIVER_ATI,
778b6e1b 507 AZX_DRIVER_ATIHDMI,
1815b34a 508 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 509 AZX_DRIVER_VIA,
510 AZX_DRIVER_SIS,
511 AZX_DRIVER_ULI,
da3fca21 512 AZX_DRIVER_NVIDIA,
f269002e 513 AZX_DRIVER_TERA,
14d34f16 514 AZX_DRIVER_CTX,
5ae763b1 515 AZX_DRIVER_CTHDA,
c4da29ca 516 AZX_DRIVER_GENERIC,
2f5983f2 517 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 518};
519
9477c58e
TI		 520/* driver quirks (capabilities) */
521/* bits 0-7 are used for indicating driver type */
522#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
523#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
524#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
525#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
526#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
527#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
528#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
529#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
530#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
531#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
532#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
533#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 534#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 535#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 536#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 537#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
9477c58e
TI		 538
539/* quirks for ATI SB / AMD Hudson */
540#define AZX_DCAPS_PRESET_ATI_SB \
541 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
542 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
543
544/* quirks for ATI/AMD HDMI */
545#define AZX_DCAPS_PRESET_ATI_HDMI \
546 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
547
548/* quirks for Nvidia */
549#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 550 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
551 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 552
5ae763b1
TI		 553#define AZX_DCAPS_PRESET_CTHDA \
554 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
555
a82d51ed
TI		 556/*
557 * VGA-switcher support
558 */
559#ifdef SUPPORT_VGA_SWITCHEROO
560#define DELAYED_INIT_MARK
561#define DELAYED_INITDATA_MARK
562#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
563#else
564#define DELAYED_INIT_MARK __devinit
565#define DELAYED_INITDATA_MARK __devinitdata
566#define use_vga_switcheroo(chip) 0
567#endif
568
569static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 570 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 571 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 572 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 573 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 574 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 575 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 576 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
577 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 578 [AZX_DRIVER_ULI] = "HDA ULI M5461",
579 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 580 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 581 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 582 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 583 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 584};
585
1da177e4
LT		 586/*
587 * macros for easy use
588 */
589#define azx_writel(chip,reg,value) \
590 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
591#define azx_readl(chip,reg) \
592 readl((chip)->remap_addr + ICH6_REG_##reg)
593#define azx_writew(chip,reg,value) \
594 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
595#define azx_readw(chip,reg) \
596 readw((chip)->remap_addr + ICH6_REG_##reg)
597#define azx_writeb(chip,reg,value) \
598 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
599#define azx_readb(chip,reg) \
600 readb((chip)->remap_addr + ICH6_REG_##reg)
601
602#define azx_sd_writel(dev,reg,value) \
603 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
604#define azx_sd_readl(dev,reg) \
605 readl((dev)->sd_addr + ICH6_REG_##reg)
606#define azx_sd_writew(dev,reg,value) \
607 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
608#define azx_sd_readw(dev,reg) \
609 readw((dev)->sd_addr + ICH6_REG_##reg)
610#define azx_sd_writeb(dev,reg,value) \
611 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
612#define azx_sd_readb(dev,reg) \
613 readb((dev)->sd_addr + ICH6_REG_##reg)
614
615/* for pcm support */
a98f90fd 616#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 617
27fe48d9
TI		 618#ifdef CONFIG_X86
619static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
620{
621 if (azx_snoop(chip))
622 return;
623 if (addr && size) {
624 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
625 if (on)
626 set_memory_wc((unsigned long)addr, pages);
627 else
628 set_memory_wb((unsigned long)addr, pages);
629 }
630}
631
632static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
633 bool on)
634{
635 __mark_pages_wc(chip, buf->area, buf->bytes, on);
636}
637static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
638 struct snd_pcm_runtime *runtime, bool on)
639{
640 if (azx_dev->wc_marked != on) {
641 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
642 azx_dev->wc_marked = on;
643 }
644}
645#else
646/* NOP for other archs */
647static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
648 bool on)
649{
650}
651static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
652 struct snd_pcm_runtime *runtime, bool on)
653{
654}
655#endif
656
68e7fffc 657static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 658static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 659/*
660 * Interface for HD codec
661 */
662
1da177e4
LT		 663/*
664 * CORB / RIRB interface
665 */
a98f90fd 666static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 667{
668 int err;
669
670 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 671 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
672 snd_dma_pci_data(chip->pci),
1da177e4
LT		 673 PAGE_SIZE, &chip->rb);
674 if (err < 0) {
675 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
676 return err;
677 }
27fe48d9 678 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 679 return 0;
680}
681
a98f90fd 682static void azx_init_cmd_io(struct azx *chip)
1da177e4 683{
cdb1fbf2 684 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 685 /* CORB set up */
686 chip->corb.addr = chip->rb.addr;
687 chip->corb.buf = (u32 *)chip->rb.area;
688 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 689 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 690
07e4ca50
TI		 691 /* set the corb size to 256 entries (ULI requires explicitly) */
692 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 693 /* set the corb write pointer to 0 */
694 azx_writew(chip, CORBWP, 0);
695 /* reset the corb hw read pointer */
b21fadb9 696 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 697 /* enable corb dma */
b21fadb9 698 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 699
700 /* RIRB set up */
701 chip->rirb.addr = chip->rb.addr + 2048;
702 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 703 chip->rirb.wp = chip->rirb.rp = 0;
704 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 705 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 706 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 707
07e4ca50
TI		 708 /* set the rirb size to 256 entries (ULI requires explicitly) */
709 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 710 /* reset the rirb hw write pointer */
b21fadb9 711 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 712 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 713 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 714 azx_writew(chip, RINTCNT, 0xc0);
715 else
716 azx_writew(chip, RINTCNT, 1);
1da177e4 717 /* enable rirb dma and response irq */
1da177e4 718 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 719 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 720}
721
a98f90fd 722static void azx_free_cmd_io(struct azx *chip)
1da177e4 723{
cdb1fbf2 724 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 725 /* disable ringbuffer DMAs */
726 azx_writeb(chip, RIRBCTL, 0);
727 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 728 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 729}
730
deadff16
WF		 731static unsigned int azx_command_addr(u32 cmd)
732{
733 unsigned int addr = cmd >> 28;
734
735 if (addr >= AZX_MAX_CODECS) {
736 snd_BUG();
737 addr = 0;
738 }
739
740 return addr;
741}
742
743static unsigned int azx_response_addr(u32 res)
744{
745 unsigned int addr = res & 0xf;
746
747 if (addr >= AZX_MAX_CODECS) {
748 snd_BUG();
749 addr = 0;
750 }
751
752 return addr;
1da177e4
LT		 753}
754
755/* send a command */
33fa35ed 756static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 757{
33fa35ed 758 struct azx *chip = bus->private_data;
deadff16 759 unsigned int addr = azx_command_addr(val);
1da177e4 760 unsigned int wp;
1da177e4 761
c32649fe
WF		 762 spin_lock_irq(&chip->reg_lock);
763
1da177e4
LT		 764 /* add command to corb */
765 wp = azx_readb(chip, CORBWP);
766 wp++;
767 wp %= ICH6_MAX_CORB_ENTRIES;
768
deadff16 769 chip->rirb.cmds[addr]++;
1da177e4
LT		 770 chip->corb.buf[wp] = cpu_to_le32(val);
771 azx_writel(chip, CORBWP, wp);
c32649fe 772
1da177e4
LT		 773 spin_unlock_irq(&chip->reg_lock);
774
775 return 0;
776}
777
778#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
779
780/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 781static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 782{
783 unsigned int rp, wp;
deadff16 784 unsigned int addr;
1da177e4
LT		 785 u32 res, res_ex;
786
787 wp = azx_readb(chip, RIRBWP);
788 if (wp == chip->rirb.wp)
789 return;
790 chip->rirb.wp = wp;
deadff16 791
1da177e4
LT		 792 while (chip->rirb.rp != wp) {
793 chip->rirb.rp++;
794 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
795
796 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
797 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
798 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 799 addr = azx_response_addr(res_ex);
1da177e4
LT		 800 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
801 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 802 else if (chip->rirb.cmds[addr]) {
803 chip->rirb.res[addr] = res;
2add9b92 804 smp_wmb();
deadff16 805 chip->rirb.cmds[addr]--;
e310bb06
WF		 806 } else
807 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
808 "last cmd=%#08x\n",
809 res, res_ex,
810 chip->last_cmd[addr]);
1da177e4
LT		 811 }
812}
813
814/* receive a response */
deadff16
WF		 815static unsigned int azx_rirb_get_response(struct hda_bus *bus,
816 unsigned int addr)
1da177e4 817{
33fa35ed 818 struct azx *chip = bus->private_data;
5c79b1f8 819 unsigned long timeout;
1eb6dc7d 820 int do_poll = 0;
1da177e4 821
5c79b1f8
TI		 822 again:
823 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 824 for (;;) {
1eb6dc7d 825 if (chip->polling_mode || do_poll) {
e96224ae
TI		 826 spin_lock_irq(&chip->reg_lock);
827 azx_update_rirb(chip);
828 spin_unlock_irq(&chip->reg_lock);
829 }
deadff16 830 if (!chip->rirb.cmds[addr]) {
2add9b92 831 smp_rmb();
b613291f 832 bus->rirb_error = 0;
1eb6dc7d
ML		 833
834 if (!do_poll)
835 chip->poll_count = 0;
deadff16 836 return chip->rirb.res[addr]; /* the last value */
2add9b92 837 }
28a0d9df
TI		 838 if (time_after(jiffies, timeout))
839 break;
33fa35ed 840 if (bus->needs_damn_long_delay)
52987656
TI		 841 msleep(2); /* temporary workaround */
842 else {
843 udelay(10);
844 cond_resched();
845 }
28a0d9df 846 }
5c79b1f8 847
1eb6dc7d
ML		 848 if (!chip->polling_mode && chip->poll_count < 2) {
849 snd_printdd(SFX "azx_get_response timeout, "
850 "polling the codec once: last cmd=0x%08x\n",
851 chip->last_cmd[addr]);
852 do_poll = 1;
853 chip->poll_count++;
854 goto again;
855 }
856
857
23c4a881
TI		 858 if (!chip->polling_mode) {
859 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
860 "switching to polling mode: last cmd=0x%08x\n",
861 chip->last_cmd[addr]);
862 chip->polling_mode = 1;
863 goto again;
864 }
865
68e7fffc 866 if (chip->msi) {
4abc1cc2 867 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 868 "disabling MSI: last cmd=0x%08x\n",
869 chip->last_cmd[addr]);
68e7fffc
TI		 870 free_irq(chip->irq, chip);
871 chip->irq = -1;
872 pci_disable_msi(chip->pci);
873 chip->msi = 0;
b613291f
TI		 874 if (azx_acquire_irq(chip, 1) < 0) {
875 bus->rirb_error = 1;
68e7fffc 876 return -1;
b613291f 877 }
68e7fffc
TI		 878 goto again;
879 }
880
6ce4a3bc
TI		 881 if (chip->probing) {
882 /* If this critical timeout happens during the codec probing
883 * phase, this is likely an access to a non-existing codec
884 * slot. Better to return an error and reset the system.
885 */
886 return -1;
887 }
888
8dd78330
TI		 889 /* a fatal communication error; need either to reset or to fallback
890 * to the single_cmd mode
891 */
b613291f 892 bus->rirb_error = 1;
b20f3b83 893 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 894 bus->response_reset = 1;
895 return -1; /* give a chance to retry */
896 }
897
898 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
899 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 900 chip->last_cmd[addr]);
8dd78330
TI		 901 chip->single_cmd = 1;
902 bus->response_reset = 0;
1a696978 903 /* release CORB/RIRB */
4fcd3920 904 azx_free_cmd_io(chip);
1a696978
TI		 905 /* disable unsolicited responses */
906 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 907 return -1;
1da177e4
LT		 908}
909
1da177e4
LT		 910/*
911 * Use the single immediate command instead of CORB/RIRB for simplicity
912 *
913 * Note: according to Intel, this is not preferred use. The command was
914 * intended for the BIOS only, and may get confused with unsolicited
915 * responses. So, we shouldn't use it for normal operation from the
916 * driver.
917 * I left the codes, however, for debugging/testing purposes.
918 */
919
b05a7d4f 920/* receive a response */
deadff16 921static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 922{
923 int timeout = 50;
924
925 while (timeout--) {
926 /* check IRV busy bit */
927 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
928 /* reuse rirb.res as the response return value */
deadff16 929 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 930 return 0;
931 }
932 udelay(1);
933 }
934 if (printk_ratelimit())
935 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
936 azx_readw(chip, IRS));
deadff16 937 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 938 return -EIO;
939}
940
1da177e4 941/* send a command */
33fa35ed 942static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 943{
33fa35ed 944 struct azx *chip = bus->private_data;
deadff16 945 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 946 int timeout = 50;
947
8dd78330 948 bus->rirb_error = 0;
1da177e4
LT		 949 while (timeout--) {
950 /* check ICB busy bit */
d01ce99f 951 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 952 /* Clear IRV valid bit */
d01ce99f
TI		 953 azx_writew(chip, IRS, azx_readw(chip, IRS) |
954 ICH6_IRS_VALID);
1da177e4 955 azx_writel(chip, IC, val);
d01ce99f
TI		 956 azx_writew(chip, IRS, azx_readw(chip, IRS) |
957 ICH6_IRS_BUSY);
deadff16 958 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 959 }
960 udelay(1);
961 }
1cfd52bc
MB		 962 if (printk_ratelimit())
963 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
964 azx_readw(chip, IRS), val);
1da177e4
LT		 965 return -EIO;
966}
967
968/* receive a response */
deadff16
WF		 969static unsigned int azx_single_get_response(struct hda_bus *bus,
970 unsigned int addr)
1da177e4 971{
33fa35ed 972 struct azx *chip = bus->private_data;
deadff16 973 return chip->rirb.res[addr];
1da177e4
LT		 974}
975
111d3af5
TI		 976/*
977 * The below are the main callbacks from hda_codec.
978 *
979 * They are just the skeleton to call sub-callbacks according to the
980 * current setting of chip->single_cmd.
981 */
982
983/* send a command */
33fa35ed 984static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 985{
33fa35ed 986 struct azx *chip = bus->private_data;
43bbb6cc 987
a82d51ed
TI		 988 if (chip->disabled)
989 return 0;
feb27340 990 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 991 if (chip->single_cmd)
33fa35ed 992 return azx_single_send_cmd(bus, val);
111d3af5 993 else
33fa35ed 994 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 995}
996
997/* get a response */
deadff16
WF		 998static unsigned int azx_get_response(struct hda_bus *bus,
999 unsigned int addr)
111d3af5 1000{
33fa35ed 1001 struct azx *chip = bus->private_data;
a82d51ed
TI		 1002 if (chip->disabled)
1003 return 0;
111d3af5 1004 if (chip->single_cmd)
deadff16 1005 return azx_single_get_response(bus, addr);
111d3af5 1006 else
deadff16 1007 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1008}
1009
cb53c626 1010#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 1011static void azx_power_notify(struct hda_bus *bus);
cb53c626 1012#endif
111d3af5 1013
1da177e4 1014/* reset codec link */
cd508fe5 1015static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1016{
1017 int count;
1018
cd508fe5
JK		 1019 if (!full_reset)
1020 goto __skip;
1021
e8a7f136
DT		 1022 /* clear STATESTS */
1023 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1024
1da177e4
LT		 1025 /* reset controller */
1026 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1027
1028 count = 50;
1029 while (azx_readb(chip, GCTL) && --count)
1030 msleep(1);
1031
1032 /* delay for >= 100us for codec PLL to settle per spec
1033 * Rev 0.9 section 5.5.1
1034 */
1035 msleep(1);
1036
1037 /* Bring controller out of reset */
1038 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1039
1040 count = 50;
927fc866 1041 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1042 msleep(1);
1043
927fc866 1044 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1045 msleep(1);
1046
cd508fe5 1047 __skip:
1da177e4 1048 /* check to see if controller is ready */
927fc866 1049 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1050 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1051 return -EBUSY;
1052 }
1053
41e2fce4 1054 /* Accept unsolicited responses */
1a696978
TI		 1055 if (!chip->single_cmd)
1056 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1057 ICH6_GCTL_UNSOL);
41e2fce4 1058
1da177e4 1059 /* detect codecs */
927fc866 1060 if (!chip->codec_mask) {
1da177e4 1061 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1062 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1063 }
1064
1065 return 0;
1066}
1067
1068
1069/*
1070 * Lowlevel interface
1071 */
1072
1073/* enable interrupts */
a98f90fd 1074static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1075{
1076 /* enable controller CIE and GIE */
1077 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1078 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1079}
1080
1081/* disable interrupts */
a98f90fd 1082static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1083{
1084 int i;
1085
1086 /* disable interrupts in stream descriptor */
07e4ca50 1087 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1088 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1089 azx_sd_writeb(azx_dev, SD_CTL,
1090 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1091 }
1092
1093 /* disable SIE for all streams */
1094 azx_writeb(chip, INTCTL, 0);
1095
1096 /* disable controller CIE and GIE */
1097 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1098 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1099}
1100
1101/* clear interrupts */
a98f90fd 1102static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1103{
1104 int i;
1105
1106 /* clear stream status */
07e4ca50 1107 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1108 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1109 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1110 }
1111
1112 /* clear STATESTS */
1113 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1114
1115 /* clear rirb status */
1116 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1117
1118 /* clear int status */
1119 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1120}
1121
1122/* start a stream */
a98f90fd 1123static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1124{
0e153474
JC		 1125 /*
1126 * Before stream start, initialize parameter
1127 */
1128 azx_dev->insufficient = 1;
1129
1da177e4 1130 /* enable SIE */
ccc5df05
WN		 1131 azx_writel(chip, INTCTL,
1132 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1133 /* set DMA start and interrupt mask */
1134 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1135 SD_CTL_DMA_START | SD_INT_MASK);
1136}
1137
1dddab40
TI		 1138/* stop DMA */
1139static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1140{
1da177e4
LT		 1141 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1142 ~(SD_CTL_DMA_START | SD_INT_MASK));
1143 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1144}
1145
1146/* stop a stream */
1147static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1148{
1149 azx_stream_clear(chip, azx_dev);
1da177e4 1150 /* disable SIE */
ccc5df05
WN		 1151 azx_writel(chip, INTCTL,
1152 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1153}
1154
1155
1156/*
cb53c626 1157 * reset and start the controller registers
1da177e4 1158 */
cd508fe5 1159static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1160{
cb53c626
TI		 1161 if (chip->initialized)
1162 return;
1da177e4
LT		 1163
1164 /* reset controller */
cd508fe5 1165 azx_reset(chip, full_reset);
1da177e4
LT		 1166
1167 /* initialize interrupts */
1168 azx_int_clear(chip);
1169 azx_int_enable(chip);
1170
1171 /* initialize the codec command I/O */
1a696978
TI		 1172 if (!chip->single_cmd)
1173 azx_init_cmd_io(chip);
1da177e4 1174
0be3b5d3
TI		 1175 /* program the position buffer */
1176 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1177 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1178
cb53c626
TI		 1179 chip->initialized = 1;
1180}
1181
1182/*
1183 * initialize the PCI registers
1184 */
1185/* update bits in a PCI register byte */
1186static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1187 unsigned char mask, unsigned char val)
1188{
1189 unsigned char data;
1190
1191 pci_read_config_byte(pci, reg, &data);
1192 data &= ~mask;
1193 data |= (val & mask);
1194 pci_write_config_byte(pci, reg, data);
1195}
1196
1197static void azx_init_pci(struct azx *chip)
1198{
1199 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1200 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1201 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1202 * codecs.
1203 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1204 */
46f2cc80 1205 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1206 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1207 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1208 }
cb53c626 1209
9477c58e
TI		 1210 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1211 * we need to enable snoop.
1212 */
1213 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1214 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1215 update_pci_byte(chip->pci,
27fe48d9
TI		 1216 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1217 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1218 }
1219
1220 /* For NVIDIA HDA, enable snoop */
1221 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1222 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1223 update_pci_byte(chip->pci,
1224 NVIDIA_HDA_TRANSREG_ADDR,
1225 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1226 update_pci_byte(chip->pci,
1227 NVIDIA_HDA_ISTRM_COH,
1228 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1229 update_pci_byte(chip->pci,
1230 NVIDIA_HDA_OSTRM_COH,
1231 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1232 }
1233
1234 /* Enable SCH/PCH snoop if needed */
1235 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1236 unsigned short snoop;
90a5ad52 1237 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1238 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1239 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1240 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1241 if (!azx_snoop(chip))
1242 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1243 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1244 pci_read_config_word(chip->pci,
1245 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1246 }
27fe48d9
TI		 1247 snd_printdd(SFX "SCH snoop: %s\n",
1248 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1249 ? "Disabled" : "Enabled");
da3fca21 1250 }
1da177e4
LT		 1251}
1252
1253
9ad593f6
TI		 1254static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1255
1da177e4
LT		 1256/*
1257 * interrupt handler
1258 */
7d12e780 1259static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1260{
a98f90fd
TI		 1261 struct azx *chip = dev_id;
1262 struct azx_dev *azx_dev;
1da177e4 1263 u32 status;
9ef04066 1264 u8 sd_status;
fa00e046 1265 int i, ok;
1da177e4
LT		 1266
1267 spin_lock(&chip->reg_lock);
1268
a82d51ed
TI		 1269 if (chip->disabled)
1270 return IRQ_NONE;
1271
1da177e4
LT		 1272 status = azx_readl(chip, INTSTS);
1273 if (status == 0) {
1274 spin_unlock(&chip->reg_lock);
1275 return IRQ_NONE;
1276 }
1277
07e4ca50 1278 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1279 azx_dev = &chip->azx_dev[i];
1280 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1281 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1282 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1283 if (!azx_dev->substream || !azx_dev->running ||
1284 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1285 continue;
1286 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1287 ok = azx_position_ok(chip, azx_dev);
1288 if (ok == 1) {
9ad593f6 1289 azx_dev->irq_pending = 0;
1da177e4
LT		 1290 spin_unlock(&chip->reg_lock);
1291 snd_pcm_period_elapsed(azx_dev->substream);
1292 spin_lock(&chip->reg_lock);
fa00e046 1293 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1294 /* bogus IRQ, process it later */
1295 azx_dev->irq_pending = 1;
6acaed38
TI		 1296 queue_work(chip->bus->workq,
1297 &chip->irq_pending_work);
1da177e4
LT		 1298 }
1299 }
1300 }
1301
1302 /* clear rirb int */
1303 status = azx_readb(chip, RIRBSTS);
1304 if (status & RIRB_INT_MASK) {
14d34f16 1305 if (status & RIRB_INT_RESPONSE) {
9477c58e 1306 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1307 udelay(80);
1da177e4 1308 azx_update_rirb(chip);
14d34f16 1309 }
1da177e4
LT		 1310 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1311 }
1312
1313#if 0
1314 /* clear state status int */
1315 if (azx_readb(chip, STATESTS) & 0x04)
1316 azx_writeb(chip, STATESTS, 0x04);
1317#endif
1318 spin_unlock(&chip->reg_lock);
1319
1320 return IRQ_HANDLED;
1321}
1322
1323
675f25d4
TI		 1324/*
1325 * set up a BDL entry
1326 */
5ae763b1
TI		 1327static int setup_bdle(struct azx *chip,
1328 struct snd_pcm_substream *substream,
675f25d4
TI		 1329 struct azx_dev *azx_dev, u32 **bdlp,
1330 int ofs, int size, int with_ioc)
1331{
675f25d4
TI		 1332 u32 *bdl = *bdlp;
1333
1334 while (size > 0) {
1335 dma_addr_t addr;
1336 int chunk;
1337
1338 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1339 return -EINVAL;
1340
77a23f26 1341 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1342 /* program the address field of the BDL entry */
1343 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1344 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1345 /* program the size field of the BDL entry */
fc4abee8 1346 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1347 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1348 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1349 u32 remain = 0x1000 - (ofs & 0xfff);
1350 if (chunk > remain)
1351 chunk = remain;
1352 }
675f25d4
TI		 1353 bdl[2] = cpu_to_le32(chunk);
1354 /* program the IOC to enable interrupt
1355 * only when the whole fragment is processed
1356 */
1357 size -= chunk;
1358 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1359 bdl += 4;
1360 azx_dev->frags++;
1361 ofs += chunk;
1362 }
1363 *bdlp = bdl;
1364 return ofs;
1365}
1366
1da177e4
LT		 1367/*
1368 * set up BDL entries
1369 */
555e219f
TI		 1370static int azx_setup_periods(struct azx *chip,
1371 struct snd_pcm_substream *substream,
4ce107b9 1372 struct azx_dev *azx_dev)
1da177e4 1373{
4ce107b9
TI		 1374 u32 *bdl;
1375 int i, ofs, periods, period_bytes;
555e219f 1376 int pos_adj;
1da177e4
LT		 1377
1378 /* reset BDL address */
1379 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1380 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1381
97b71c94 1382 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1383 periods = azx_dev->bufsize / period_bytes;
1384
1da177e4 1385 /* program the initial BDL entries */
4ce107b9
TI		 1386 bdl = (u32 *)azx_dev->bdl.area;
1387 ofs = 0;
1388 azx_dev->frags = 0;
555e219f
TI		 1389 pos_adj = bdl_pos_adj[chip->dev_index];
1390 if (pos_adj > 0) {
675f25d4 1391 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1392 int pos_align = pos_adj;
555e219f 1393 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1394 if (!pos_adj)
e785d3d8
TI		 1395 pos_adj = pos_align;
1396 else
1397 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1398 pos_align;
675f25d4
TI		 1399 pos_adj = frames_to_bytes(runtime, pos_adj);
1400 if (pos_adj >= period_bytes) {
4abc1cc2 1401 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1402 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1403 pos_adj = 0;
1404 } else {
5ae763b1 1405 ofs = setup_bdle(chip, substream, azx_dev,
7bb8fb70
CL		 1406 &bdl, ofs, pos_adj,
1407 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1408 if (ofs < 0)
1409 goto error;
4ce107b9 1410 }
555e219f
TI		 1411 } else
1412 pos_adj = 0;
675f25d4
TI		 1413 for (i = 0; i < periods; i++) {
1414 if (i == periods - 1 && pos_adj)
5ae763b1 1415 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1416 period_bytes - pos_adj, 0);
1417 else
5ae763b1 1418 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1419 period_bytes,
1420 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1421 if (ofs < 0)
1422 goto error;
1da177e4 1423 }
4ce107b9 1424 return 0;
675f25d4
TI		 1425
1426 error:
4abc1cc2 1427 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1428 azx_dev->bufsize, period_bytes);
675f25d4 1429 return -EINVAL;
1da177e4
LT		 1430}
1431
1dddab40
TI		 1432/* reset stream */
1433static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1434{
1435 unsigned char val;
1436 int timeout;
1437
1dddab40
TI		 1438 azx_stream_clear(chip, azx_dev);
1439
d01ce99f
TI		 1440 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1441 SD_CTL_STREAM_RESET);
1da177e4
LT		 1442 udelay(3);
1443 timeout = 300;
1444 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1445 --timeout)
1446 ;
1447 val &= ~SD_CTL_STREAM_RESET;
1448 azx_sd_writeb(azx_dev, SD_CTL, val);
1449 udelay(3);
1450
1451 timeout = 300;
1452 /* waiting for hardware to report that the stream is out of reset */
1453 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1454 --timeout)
1455 ;
fa00e046
JK		 1456
1457 /* reset first position - may not be synced with hw at this time */
1458 *azx_dev->posbuf = 0;
1dddab40 1459}
1da177e4 1460
1dddab40
TI		 1461/*
1462 * set up the SD for streaming
1463 */
1464static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1465{
27fe48d9 1466 unsigned int val;
1dddab40
TI		 1467 /* make sure the run bit is zero for SD */
1468 azx_stream_clear(chip, azx_dev);
1da177e4 1469 /* program the stream_tag */
27fe48d9
TI		 1470 val = azx_sd_readl(azx_dev, SD_CTL);
1471 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1472 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1473 if (!azx_snoop(chip))
1474 val |= SD_CTL_TRAFFIC_PRIO;
1475 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1476
1477 /* program the length of samples in cyclic buffer */
1478 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1479
1480 /* program the stream format */
1481 /* this value needs to be the same as the one programmed */
1482 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1483
1484 /* program the stream LVI (last valid index) of the BDL */
1485 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1486
1487 /* program the BDL address */
1488 /* lower BDL address */
4ce107b9 1489 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1490 /* upper BDL address */
766979e0 1491 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1492
0be3b5d3 1493 /* enable the position buffer */
4cb36310
DH		 1494 if (chip->position_fix[0] != POS_FIX_LPIB ||
1495 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1496 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1497 azx_writel(chip, DPLBASE,
1498 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1499 }
c74db86b 1500
1da177e4 1501 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1502 azx_sd_writel(azx_dev, SD_CTL,
1503 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1504
1505 return 0;
1506}
1507
6ce4a3bc
TI		 1508/*
1509 * Probe the given codec address
1510 */
1511static int probe_codec(struct azx *chip, int addr)
1512{
1513 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1514 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1515 unsigned int res;
1516
a678cdee 1517 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1518 chip->probing = 1;
1519 azx_send_cmd(chip->bus, cmd);
deadff16 1520 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1521 chip->probing = 0;
a678cdee 1522 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1523 if (res == -1)
1524 return -EIO;
4abc1cc2 1525 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1526 return 0;
1527}
1528
33fa35ed
TI		 1529static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1530 struct hda_pcm *cpcm);
6ce4a3bc 1531static void azx_stop_chip(struct azx *chip);
1da177e4 1532
8dd78330
TI		 1533static void azx_bus_reset(struct hda_bus *bus)
1534{
1535 struct azx *chip = bus->private_data;
8dd78330
TI		 1536
1537 bus->in_reset = 1;
1538 azx_stop_chip(chip);
cd508fe5 1539 azx_init_chip(chip, 1);
65f75983 1540#ifdef CONFIG_PM
8dd78330 1541 if (chip->initialized) {
01b65bfb
TI		 1542 struct azx_pcm *p;
1543 list_for_each_entry(p, &chip->pcm_list, list)
1544 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1545 snd_hda_suspend(chip->bus);
1546 snd_hda_resume(chip->bus);
1547 }
65f75983 1548#endif
8dd78330
TI		 1549 bus->in_reset = 0;
1550}
1551
1da177e4
LT		 1552/*
1553 * Codec initialization
1554 */
1555
2f5983f2 1556/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1557static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1558 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1559 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1560};
1561
a82d51ed 1562static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1563{
1564 struct hda_bus_template bus_temp;
34c25350
TI		 1565 int c, codecs, err;
1566 int max_slots;
1da177e4
LT		 1567
1568 memset(&bus_temp, 0, sizeof(bus_temp));
1569 bus_temp.private_data = chip;
1570 bus_temp.modelname = model;
1571 bus_temp.pci = chip->pci;
111d3af5
TI		 1572 bus_temp.ops.command = azx_send_cmd;
1573 bus_temp.ops.get_response = azx_get_response;
176d5335 1574 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1575 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1576#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1577 bus_temp.power_save = &power_save;
cb53c626
TI		 1578 bus_temp.ops.pm_notify = azx_power_notify;
1579#endif
1da177e4 1580
d01ce99f
TI		 1581 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1582 if (err < 0)
1da177e4
LT		 1583 return err;
1584
9477c58e
TI		 1585 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1586 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1587 chip->bus->needs_damn_long_delay = 1;
9477c58e 1588 }
dc9c8e21 1589
34c25350 1590 codecs = 0;
2f5983f2
TI		 1591 max_slots = azx_max_codecs[chip->driver_type];
1592 if (!max_slots)
7445dfc1 1593 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1594
1595 /* First try to probe all given codec slots */
1596 for (c = 0; c < max_slots; c++) {
f1eaaeec 1597 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1598 if (probe_codec(chip, c) < 0) {
1599 /* Some BIOSen give you wrong codec addresses
1600 * that don't exist
1601 */
4abc1cc2
TI		 1602 snd_printk(KERN_WARNING SFX
1603 "Codec #%d probe error; "
6ce4a3bc
TI		 1604 "disabling it...\n", c);
1605 chip->codec_mask &= ~(1 << c);
1606 /* More badly, accessing to a non-existing
1607 * codec often screws up the controller chip,
2448158e 1608 * and disturbs the further communications.
6ce4a3bc
TI		 1609 * Thus if an error occurs during probing,
1610 * better to reset the controller chip to
1611 * get back to the sanity state.
1612 */
1613 azx_stop_chip(chip);
cd508fe5 1614 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1615 }
1616 }
1617 }
1618
d507cd66
TI		 1619 /* AMD chipsets often cause the communication stalls upon certain
1620 * sequence like the pin-detection. It seems that forcing the synced
1621 * access works around the stall. Grrr...
1622 */
9477c58e
TI		 1623 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1624 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1625 chip->bus->sync_write = 1;
1626 chip->bus->allow_bus_reset = 1;
1627 }
1628
6ce4a3bc 1629 /* Then create codec instances */
34c25350 1630 for (c = 0; c < max_slots; c++) {
f1eaaeec 1631 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1632 struct hda_codec *codec;
a1e21c90 1633 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1634 if (err < 0)
1635 continue;
2dca0bba 1636 codec->beep_mode = chip->beep_mode;
1da177e4 1637 codecs++;
19a982b6
TI		 1638 }
1639 }
1640 if (!codecs) {
1da177e4
LT		 1641 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1642 return -ENXIO;
1643 }
a1e21c90
TI		 1644 return 0;
1645}
1da177e4 1646
a1e21c90
TI		 1647/* configure each codec instance */
1648static int __devinit azx_codec_configure(struct azx *chip)
1649{
1650 struct hda_codec *codec;
1651 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1652 snd_hda_codec_configure(codec);
1653 }
1da177e4
LT		 1654 return 0;
1655}
1656
1657
1658/*
1659 * PCM support
1660 */
1661
1662/* assign a stream for the PCM */
ef18bede
WF		 1663static inline struct azx_dev *
1664azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1665{
07e4ca50 1666 int dev, i, nums;
ef18bede 1667 struct azx_dev *res = NULL;
d5cf9911
TI		 1668 /* make a non-zero unique key for the substream */
1669 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1670 (substream->stream + 1);
ef18bede
WF		 1671
1672 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1673 dev = chip->playback_index_offset;
1674 nums = chip->playback_streams;
1675 } else {
1676 dev = chip->capture_index_offset;
1677 nums = chip->capture_streams;
1678 }
1679 for (i = 0; i < nums; i++, dev++)
d01ce99f 1680 if (!chip->azx_dev[dev].opened) {
ef18bede 1681 res = &chip->azx_dev[dev];
d5cf9911 1682 if (res->assigned_key == key)
ef18bede 1683 break;
1da177e4 1684 }
ef18bede
WF		 1685 if (res) {
1686 res->opened = 1;
d5cf9911 1687 res->assigned_key = key;
ef18bede
WF		 1688 }
1689 return res;
1da177e4
LT		 1690}
1691
1692/* release the assigned stream */
a98f90fd 1693static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1694{
1695 azx_dev->opened = 0;
1696}
1697
a98f90fd 1698static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1699 .info = (SNDRV_PCM_INFO_MMAP |
1700 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1701 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1702 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1703 /* No full-resume yet implemented */
1704 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1705 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1706 SNDRV_PCM_INFO_SYNC_START |
1707 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1708 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1709 .rates = SNDRV_PCM_RATE_48000,
1710 .rate_min = 48000,
1711 .rate_max = 48000,
1712 .channels_min = 2,
1713 .channels_max = 2,
1714 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1715 .period_bytes_min = 128,
1716 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1717 .periods_min = 2,
1718 .periods_max = AZX_MAX_FRAG,
1719 .fifo_size = 0,
1720};
1721
a98f90fd 1722static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1723{
1724 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1725 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1726 struct azx *chip = apcm->chip;
1727 struct azx_dev *azx_dev;
1728 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1729 unsigned long flags;
1730 int err;
2ae66c26 1731 int buff_step;
1da177e4 1732
62932df8 1733 mutex_lock(&chip->open_mutex);
ef18bede 1734 azx_dev = azx_assign_device(chip, substream);
1da177e4 1735 if (azx_dev == NULL) {
62932df8 1736 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1737 return -EBUSY;
1738 }
1739 runtime->hw = azx_pcm_hw;
1740 runtime->hw.channels_min = hinfo->channels_min;
1741 runtime->hw.channels_max = hinfo->channels_max;
1742 runtime->hw.formats = hinfo->formats;
1743 runtime->hw.rates = hinfo->rates;
1744 snd_pcm_limit_hw_rates(runtime);
1745 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1746 if (chip->align_buffer_size)
2ae66c26
PLB		 1747 /* constrain buffer sizes to be multiple of 128
1748 bytes. This is more efficient in terms of memory
1749 access but isn't required by the HDA spec and
1750 prevents users from specifying exact period/buffer
1751 sizes. For example for 44.1kHz, a period size set
1752 to 20ms will be rounded to 19.59ms. */
1753 buff_step = 128;
1754 else
1755 /* Don't enforce steps on buffer sizes, still need to
1756 be multiple of 4 bytes (HDA spec). Tested on Intel
1757 HDA controllers, may not work on all devices where
1758 option needs to be disabled */
1759 buff_step = 4;
1760
5f1545bc 1761 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1762 buff_step);
5f1545bc 1763 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1764 buff_step);
cb53c626 1765 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1766 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1767 if (err < 0) {
1da177e4 1768 azx_release_device(azx_dev);
cb53c626 1769 snd_hda_power_down(apcm->codec);
62932df8 1770 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1771 return err;
1772 }
70d321e6 1773 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1774 /* sanity check */
1775 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1776 snd_BUG_ON(!runtime->hw.channels_max) ||
1777 snd_BUG_ON(!runtime->hw.formats) ||
1778 snd_BUG_ON(!runtime->hw.rates)) {
1779 azx_release_device(azx_dev);
1780 hinfo->ops.close(hinfo, apcm->codec, substream);
1781 snd_hda_power_down(apcm->codec);
1782 mutex_unlock(&chip->open_mutex);
1783 return -EINVAL;
1784 }
1da177e4
LT		 1785 spin_lock_irqsave(&chip->reg_lock, flags);
1786 azx_dev->substream = substream;
1787 azx_dev->running = 0;
1788 spin_unlock_irqrestore(&chip->reg_lock, flags);
1789
1790 runtime->private_data = azx_dev;
850f0e52 1791 snd_pcm_set_sync(substream);
62932df8 1792 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1793 return 0;
1794}
1795
a98f90fd 1796static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1797{
1798 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1799 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1800 struct azx *chip = apcm->chip;
1801 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1802 unsigned long flags;
1803
62932df8 1804 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1805 spin_lock_irqsave(&chip->reg_lock, flags);
1806 azx_dev->substream = NULL;
1807 azx_dev->running = 0;
1808 spin_unlock_irqrestore(&chip->reg_lock, flags);
1809 azx_release_device(azx_dev);
1810 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1811 snd_hda_power_down(apcm->codec);
62932df8 1812 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1813 return 0;
1814}
1815
d01ce99f
TI		 1816static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1817 struct snd_pcm_hw_params *hw_params)
1da177e4 1818{
27fe48d9
TI		 1819 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1820 struct azx *chip = apcm->chip;
1821 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1822 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1823 int ret;
97b71c94 1824
27fe48d9 1825 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1826 azx_dev->bufsize = 0;
1827 azx_dev->period_bytes = 0;
1828 azx_dev->format_val = 0;
27fe48d9 1829 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1830 params_buffer_bytes(hw_params));
27fe48d9
TI		 1831 if (ret < 0)
1832 return ret;
1833 mark_runtime_wc(chip, azx_dev, runtime, true);
1834 return ret;
1da177e4
LT		 1835}
1836
a98f90fd 1837static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1838{
1839 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1840 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1841 struct azx *chip = apcm->chip;
1842 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1843 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1844
1845 /* reset BDL address */
1846 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1847 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1848 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1849 azx_dev->bufsize = 0;
1850 azx_dev->period_bytes = 0;
1851 azx_dev->format_val = 0;
1da177e4 1852
eb541337 1853 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1854
27fe48d9 1855 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1856 return snd_pcm_lib_free_pages(substream);
1857}
1858
a98f90fd 1859static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1860{
1861 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1862 struct azx *chip = apcm->chip;
1863 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1864 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1865 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1866 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1867 int err;
7c935976
SW		 1868 struct hda_spdif_out *spdif =
1869 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1870 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1871
fa00e046 1872 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1873 format_val = snd_hda_calc_stream_format(runtime->rate,
1874 runtime->channels,
1875 runtime->format,
32c168c8 1876 hinfo->maxbps,
7c935976 1877 ctls);
97b71c94 1878 if (!format_val) {
d01ce99f
TI		 1879 snd_printk(KERN_ERR SFX
1880 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1881 runtime->rate, runtime->channels, runtime->format);
1882 return -EINVAL;
1883 }
1884
97b71c94
TI		 1885 bufsize = snd_pcm_lib_buffer_bytes(substream);
1886 period_bytes = snd_pcm_lib_period_bytes(substream);
1887
4abc1cc2 1888 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1889 bufsize, format_val);
1890
1891 if (bufsize != azx_dev->bufsize ||
1892 period_bytes != azx_dev->period_bytes ||
1893 format_val != azx_dev->format_val) {
1894 azx_dev->bufsize = bufsize;
1895 azx_dev->period_bytes = period_bytes;
1896 azx_dev->format_val = format_val;
1897 err = azx_setup_periods(chip, substream, azx_dev);
1898 if (err < 0)
1899 return err;
1900 }
1901
e5463720
JK		 1902 /* wallclk has 24Mhz clock source */
1903 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1904 runtime->rate) * 1000);
1da177e4
LT		 1905 azx_setup_controller(chip, azx_dev);
1906 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1907 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1908 else
1909 azx_dev->fifo_size = 0;
1910
62b7e5e0
TI		 1911 stream_tag = azx_dev->stream_tag;
1912 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1913 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1914 stream_tag > chip->capture_streams)
1915 stream_tag -= chip->capture_streams;
1916 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1917 azx_dev->format_val, substream);
1da177e4
LT		 1918}
1919
a98f90fd 1920static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1921{
1922 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1923 struct azx *chip = apcm->chip;
850f0e52
TI		 1924 struct azx_dev *azx_dev;
1925 struct snd_pcm_substream *s;
fa00e046 1926 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1927 int nwait, timeout;
1da177e4 1928
1da177e4 1929 switch (cmd) {
fa00e046
JK		 1930 case SNDRV_PCM_TRIGGER_START:
1931 rstart = 1;
1da177e4
LT		 1932 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1933 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1934 start = 1;
1da177e4
LT		 1935 break;
1936 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1937 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1938 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1939 start = 0;
1da177e4
LT		 1940 break;
1941 default:
850f0e52
TI		 1942 return -EINVAL;
1943 }
1944
1945 snd_pcm_group_for_each_entry(s, substream) {
1946 if (s->pcm->card != substream->pcm->card)
1947 continue;
1948 azx_dev = get_azx_dev(s);
1949 sbits |= 1 << azx_dev->index;
1950 nsync++;
1951 snd_pcm_trigger_done(s, substream);
1952 }
1953
1954 spin_lock(&chip->reg_lock);
1955 if (nsync > 1) {
1956 /* first, set SYNC bits of corresponding streams */
8b0bd226
TI		 1957 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1958 azx_writel(chip, OLD_SSYNC,
1959 azx_readl(chip, OLD_SSYNC) | sbits);
1960 else
1961 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
850f0e52
TI		 1962 }
1963 snd_pcm_group_for_each_entry(s, substream) {
1964 if (s->pcm->card != substream->pcm->card)
1965 continue;
1966 azx_dev = get_azx_dev(s);
e5463720
JK		 1967 if (start) {
1968 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1969 if (!rstart)
1970 azx_dev->start_wallclk -=
1971 azx_dev->period_wallclk;
850f0e52 1972 azx_stream_start(chip, azx_dev);
e5463720 1973 } else {
850f0e52 1974 azx_stream_stop(chip, azx_dev);
e5463720 1975 }
850f0e52 1976 azx_dev->running = start;
1da177e4
LT		 1977 }
1978 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1979 if (start) {
1980 if (nsync == 1)
1981 return 0;
1982 /* wait until all FIFOs get ready */
1983 for (timeout = 5000; timeout; timeout--) {
1984 nwait = 0;
1985 snd_pcm_group_for_each_entry(s, substream) {
1986 if (s->pcm->card != substream->pcm->card)
1987 continue;
1988 azx_dev = get_azx_dev(s);
1989 if (!(azx_sd_readb(azx_dev, SD_STS) &
1990 SD_STS_FIFO_READY))
1991 nwait++;
1992 }
1993 if (!nwait)
1994 break;
1995 cpu_relax();
1996 }
1997 } else {
1998 /* wait until all RUN bits are cleared */
1999 for (timeout = 5000; timeout; timeout--) {
2000 nwait = 0;
2001 snd_pcm_group_for_each_entry(s, substream) {
2002 if (s->pcm->card != substream->pcm->card)
2003 continue;
2004 azx_dev = get_azx_dev(s);
2005 if (azx_sd_readb(azx_dev, SD_CTL) &
2006 SD_CTL_DMA_START)
2007 nwait++;
2008 }
2009 if (!nwait)
2010 break;
2011 cpu_relax();
2012 }
1da177e4 2013 }
850f0e52
TI		 2014 if (nsync > 1) {
2015 spin_lock(&chip->reg_lock);
2016 /* reset SYNC bits */
8b0bd226
TI		 2017 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2018 azx_writel(chip, OLD_SSYNC,
2019 azx_readl(chip, OLD_SSYNC) & ~sbits);
2020 else
2021 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
850f0e52
TI		 2022 spin_unlock(&chip->reg_lock);
2023 }
2024 return 0;
1da177e4
LT		 2025}
2026
0e153474
JC		 2027/* get the current DMA position with correction on VIA chips */
2028static unsigned int azx_via_get_position(struct azx *chip,
2029 struct azx_dev *azx_dev)
2030{
2031 unsigned int link_pos, mini_pos, bound_pos;
2032 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2033 unsigned int fifo_size;
2034
2035 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2036 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2037 /* Playback, no problem using link position */
2038 return link_pos;
2039 }
2040
2041 /* Capture */
2042 /* For new chipset,
2043 * use mod to get the DMA position just like old chipset
2044 */
2045 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2046 mod_dma_pos %= azx_dev->period_bytes;
2047
2048 /* azx_dev->fifo_size can't get FIFO size of in stream.
2049 * Get from base address + offset.
2050 */
2051 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2052
2053 if (azx_dev->insufficient) {
2054 /* Link position never gather than FIFO size */
2055 if (link_pos <= fifo_size)
2056 return 0;
2057
2058 azx_dev->insufficient = 0;
2059 }
2060
2061 if (link_pos <= fifo_size)
2062 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2063 else
2064 mini_pos = link_pos - fifo_size;
2065
2066 /* Find nearest previous boudary */
2067 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2068 mod_link_pos = link_pos % azx_dev->period_bytes;
2069 if (mod_link_pos >= fifo_size)
2070 bound_pos = link_pos - mod_link_pos;
2071 else if (mod_dma_pos >= mod_mini_pos)
2072 bound_pos = mini_pos - mod_mini_pos;
2073 else {
2074 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2075 if (bound_pos >= azx_dev->bufsize)
2076 bound_pos = 0;
2077 }
2078
2079 /* Calculate real DMA position we want */
2080 return bound_pos + mod_dma_pos;
2081}
2082
9ad593f6 2083static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2084 struct azx_dev *azx_dev,
2085 bool with_check)
1da177e4 2086{
1da177e4 2087 unsigned int pos;
4cb36310 2088 int stream = azx_dev->substream->stream;
1da177e4 2089
4cb36310
DH		 2090 switch (chip->position_fix[stream]) {
2091 case POS_FIX_LPIB:
2092 /* read LPIB */
2093 pos = azx_sd_readl(azx_dev, SD_LPIB);
2094 break;
2095 case POS_FIX_VIACOMBO:
0e153474 2096 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2097 break;
2098 default:
2099 /* use the position buffer */
2100 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2101 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2102 if (!pos || pos == (u32)-1) {
2103 printk(KERN_WARNING
2104 "hda-intel: Invalid position buffer, "
2105 "using LPIB read method instead.\n");
2106 chip->position_fix[stream] = POS_FIX_LPIB;
2107 pos = azx_sd_readl(azx_dev, SD_LPIB);
2108 } else
2109 chip->position_fix[stream] = POS_FIX_POSBUF;
2110 }
2111 break;
c74db86b 2112 }
4cb36310 2113
1da177e4
LT		 2114 if (pos >= azx_dev->bufsize)
2115 pos = 0;
9ad593f6
TI		 2116 return pos;
2117}
2118
2119static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2120{
2121 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2122 struct azx *chip = apcm->chip;
2123 struct azx_dev *azx_dev = get_azx_dev(substream);
2124 return bytes_to_frames(substream->runtime,
798cb7e8 2125 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2126}
2127
2128/*
2129 * Check whether the current DMA position is acceptable for updating
2130 * periods. Returns non-zero if it's OK.
2131 *
2132 * Many HD-audio controllers appear pretty inaccurate about
2133 * the update-IRQ timing. The IRQ is issued before actually the
2134 * data is processed. So, we need to process it afterwords in a
2135 * workqueue.
2136 */
2137static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2138{
e5463720 2139 u32 wallclk;
9ad593f6 2140 unsigned int pos;
beaffc39 2141 int stream;
9ad593f6 2142
f48f606d
JK		 2143 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2144 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2145 return -1; /* bogus (too early) interrupt */
fa00e046 2146
beaffc39 2147 stream = azx_dev->substream->stream;
798cb7e8 2148 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2149
d6d8bf54
TI		 2150 if (WARN_ONCE(!azx_dev->period_bytes,
2151 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2152 return -1; /* this shouldn't happen! */
edb39935 2153 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2154 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2155 /* NG - it's below the first next period boundary */
2156 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2157 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2158 return 1; /* OK, it's fine */
2159}
2160
2161/*
2162 * The work for pending PCM period updates.
2163 */
2164static void azx_irq_pending_work(struct work_struct *work)
2165{
2166 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2167 int i, pending, ok;
9ad593f6 2168
a6a950a8
TI		 2169 if (!chip->irq_pending_warned) {
2170 printk(KERN_WARNING
2171 "hda-intel: IRQ timing workaround is activated "
2172 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2173 chip->card->number);
2174 chip->irq_pending_warned = 1;
2175 }
2176
9ad593f6
TI		 2177 for (;;) {
2178 pending = 0;
2179 spin_lock_irq(&chip->reg_lock);
2180 for (i = 0; i < chip->num_streams; i++) {
2181 struct azx_dev *azx_dev = &chip->azx_dev[i];
2182 if (!azx_dev->irq_pending ||
2183 !azx_dev->substream ||
2184 !azx_dev->running)
2185 continue;
e5463720
JK		 2186 ok = azx_position_ok(chip, azx_dev);
2187 if (ok > 0) {
9ad593f6
TI		 2188 azx_dev->irq_pending = 0;
2189 spin_unlock(&chip->reg_lock);
2190 snd_pcm_period_elapsed(azx_dev->substream);
2191 spin_lock(&chip->reg_lock);
e5463720
JK		 2192 } else if (ok < 0) {
2193 pending = 0; /* too early */
9ad593f6
TI		 2194 } else
2195 pending++;
2196 }
2197 spin_unlock_irq(&chip->reg_lock);
2198 if (!pending)
2199 return;
08af495f 2200 msleep(1);
9ad593f6
TI		 2201 }
2202}
2203
2204/* clear irq_pending flags and assure no on-going workq */
2205static void azx_clear_irq_pending(struct azx *chip)
2206{
2207 int i;
2208
2209 spin_lock_irq(&chip->reg_lock);
2210 for (i = 0; i < chip->num_streams; i++)
2211 chip->azx_dev[i].irq_pending = 0;
2212 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2213}
2214
27fe48d9
TI		 2215#ifdef CONFIG_X86
2216static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2217 struct vm_area_struct *area)
2218{
2219 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2220 struct azx *chip = apcm->chip;
2221 if (!azx_snoop(chip))
2222 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2223 return snd_pcm_lib_default_mmap(substream, area);
2224}
2225#else
2226#define azx_pcm_mmap NULL
2227#endif
2228
a98f90fd 2229static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2230 .open = azx_pcm_open,
2231 .close = azx_pcm_close,
2232 .ioctl = snd_pcm_lib_ioctl,
2233 .hw_params = azx_pcm_hw_params,
2234 .hw_free = azx_pcm_hw_free,
2235 .prepare = azx_pcm_prepare,
2236 .trigger = azx_pcm_trigger,
2237 .pointer = azx_pcm_pointer,
27fe48d9 2238 .mmap = azx_pcm_mmap,
4ce107b9 2239 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2240};
2241
a98f90fd 2242static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2243{
176d5335
TI		 2244 struct azx_pcm *apcm = pcm->private_data;
2245 if (apcm) {
01b65bfb 2246 list_del(&apcm->list);
176d5335
TI		 2247 kfree(apcm);
2248 }
1da177e4
LT		 2249}
2250
acfa634f
TI		 2251#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2252
176d5335 2253static int
33fa35ed
TI		 2254azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2255 struct hda_pcm *cpcm)
1da177e4 2256{
33fa35ed 2257 struct azx *chip = bus->private_data;
a98f90fd 2258 struct snd_pcm *pcm;
1da177e4 2259 struct azx_pcm *apcm;
176d5335 2260 int pcm_dev = cpcm->device;
acfa634f 2261 unsigned int size;
176d5335 2262 int s, err;
1da177e4 2263
01b65bfb
TI		 2264 list_for_each_entry(apcm, &chip->pcm_list, list) {
2265 if (apcm->pcm->device == pcm_dev) {
2266 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2267 return -EBUSY;
2268 }
176d5335
TI		 2269 }
2270 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2271 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2272 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2273 &pcm);
2274 if (err < 0)
2275 return err;
18cb7109 2276 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2277 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2278 if (apcm == NULL)
2279 return -ENOMEM;
2280 apcm->chip = chip;
01b65bfb 2281 apcm->pcm = pcm;
1da177e4 2282 apcm->codec = codec;
1da177e4
LT		 2283 pcm->private_data = apcm;
2284 pcm->private_free = azx_pcm_free;
176d5335
TI		 2285 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2286 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2287 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2288 cpcm->pcm = pcm;
2289 for (s = 0; s < 2; s++) {
2290 apcm->hinfo[s] = &cpcm->stream[s];
2291 if (cpcm->stream[s].substreams)
2292 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2293 }
2294 /* buffer pre-allocation */
acfa634f
TI		 2295 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2296 if (size > MAX_PREALLOC_SIZE)
2297 size = MAX_PREALLOC_SIZE;
4ce107b9 2298 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2299 snd_dma_pci_data(chip->pci),
acfa634f 2300 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2301 return 0;
2302}
2303
2304/*
2305 * mixer creation - all stuff is implemented in hda module
2306 */
a98f90fd 2307static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2308{
2309 return snd_hda_build_controls(chip->bus);
2310}
2311
2312
2313/*
2314 * initialize SD streams
2315 */
a98f90fd 2316static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2317{
2318 int i;
2319
2320 /* initialize each stream (aka device)
d01ce99f
TI		 2321 * assign the starting bdl address to each stream (device)
2322 * and initialize
1da177e4 2323 */
07e4ca50 2324 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2325 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2326 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2327 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2328 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2329 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2330 azx_dev->sd_int_sta_mask = 1 << i;
2331 /* stream tag: must be non-zero and unique */
2332 azx_dev->index = i;
2333 azx_dev->stream_tag = i + 1;
2334 }
2335
2336 return 0;
2337}
2338
68e7fffc
TI		 2339static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2340{
437a5a46
TI		 2341 if (request_irq(chip->pci->irq, azx_interrupt,
2342 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2343 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2344 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2345 "disabling device\n", chip->pci->irq);
2346 if (do_disconnect)
2347 snd_card_disconnect(chip->card);
2348 return -1;
2349 }
2350 chip->irq = chip->pci->irq;
69e13418 2351 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2352 return 0;
2353}
2354
1da177e4 2355
cb53c626
TI		 2356static void azx_stop_chip(struct azx *chip)
2357{
95e99fda 2358 if (!chip->initialized)
cb53c626
TI		 2359 return;
2360
2361 /* disable interrupts */
2362 azx_int_disable(chip);
2363 azx_int_clear(chip);
2364
2365 /* disable CORB/RIRB */
2366 azx_free_cmd_io(chip);
2367
2368 /* disable position buffer */
2369 azx_writel(chip, DPLBASE, 0);
2370 azx_writel(chip, DPUBASE, 0);
2371
2372 chip->initialized = 0;
2373}
2374
2375#ifdef CONFIG_SND_HDA_POWER_SAVE
2376/* power-up/down the controller */
33fa35ed 2377static void azx_power_notify(struct hda_bus *bus)
cb53c626 2378{
33fa35ed 2379 struct azx *chip = bus->private_data;
cb53c626
TI		 2380 struct hda_codec *c;
2381 int power_on = 0;
2382
33fa35ed 2383 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2384 if (c->power_on) {
2385 power_on = 1;
2386 break;
2387 }
2388 }
2389 if (power_on)
cd508fe5 2390 azx_init_chip(chip, 1);
0287d970
WF		 2391 else if (chip->running && power_save_controller &&
2392 !bus->power_keep_link_on)
cb53c626 2393 azx_stop_chip(chip);
cb53c626 2394}
5c0b9bec
TI		 2395#endif /* CONFIG_SND_HDA_POWER_SAVE */
2396
2397#ifdef CONFIG_PM
2398/*
2399 * power management
2400 */
986862bd 2401
421a1252 2402static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2403{
421a1252
TI		 2404 struct snd_card *card = pci_get_drvdata(pci);
2405 struct azx *chip = card->private_data;
01b65bfb 2406 struct azx_pcm *p;
1da177e4 2407
421a1252 2408 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2409 azx_clear_irq_pending(chip);
01b65bfb
TI		 2410 list_for_each_entry(p, &chip->pcm_list, list)
2411 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2412 if (chip->initialized)
8dd78330 2413 snd_hda_suspend(chip->bus);
cb53c626 2414 azx_stop_chip(chip);
30b35399 2415 if (chip->irq >= 0) {
43001c95 2416 free_irq(chip->irq, chip);
30b35399
TI		 2417 chip->irq = -1;
2418 }
68e7fffc 2419 if (chip->msi)
43001c95 2420 pci_disable_msi(chip->pci);
421a1252
TI		 2421 pci_disable_device(pci);
2422 pci_save_state(pci);
30b35399 2423 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2424 return 0;
2425}
2426
421a1252 2427static int azx_resume(struct pci_dev *pci)
1da177e4 2428{
421a1252
TI		 2429 struct snd_card *card = pci_get_drvdata(pci);
2430 struct azx *chip = card->private_data;
1da177e4 2431
d14a7e0b
TI		 2432 pci_set_power_state(pci, PCI_D0);
2433 pci_restore_state(pci);
30b35399
TI		 2434 if (pci_enable_device(pci) < 0) {
2435 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2436 "disabling device\n");
2437 snd_card_disconnect(card);
2438 return -EIO;
2439 }
2440 pci_set_master(pci);
68e7fffc
TI		 2441 if (chip->msi)
2442 if (pci_enable_msi(pci) < 0)
2443 chip->msi = 0;
2444 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2445 return -EIO;
cb53c626 2446 azx_init_pci(chip);
d804ad92 2447
7f30830b 2448 azx_init_chip(chip, 1);
d804ad92 2449
1da177e4 2450 snd_hda_resume(chip->bus);
421a1252 2451 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2452 return 0;
2453}
2454#endif /* CONFIG_PM */
2455
2456
0cbf0098
TI		 2457/*
2458 * reboot notifier for hang-up problem at power-down
2459 */
2460static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2461{
2462 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2463 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2464 azx_stop_chip(chip);
2465 return NOTIFY_OK;
2466}
2467
2468static void azx_notifier_register(struct azx *chip)
2469{
2470 chip->reboot_notifier.notifier_call = azx_halt;
2471 register_reboot_notifier(&chip->reboot_notifier);
2472}
2473
2474static void azx_notifier_unregister(struct azx *chip)
2475{
2476 if (chip->reboot_notifier.notifier_call)
2477 unregister_reboot_notifier(&chip->reboot_notifier);
2478}
2479
a82d51ed
TI		 2480static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2481static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2482
2483static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2484
2485#ifdef SUPPORT_VGA_SWITCHEROO
2486static void azx_vs_set_state(struct pci_dev *pci,
2487 enum vga_switcheroo_state state)
2488{
2489 struct snd_card *card = pci_get_drvdata(pci);
2490 struct azx *chip = card->private_data;
2491 bool disabled;
2492
2493 if (chip->init_failed)
2494 return;
2495
2496 disabled = (state == VGA_SWITCHEROO_OFF);
2497 if (chip->disabled == disabled)
2498 return;
2499
2500 if (!chip->bus) {
2501 chip->disabled = disabled;
2502 if (!disabled) {
2503 snd_printk(KERN_INFO SFX
2504 "%s: Start delayed initialization\n",
2505 pci_name(chip->pci));
2506 if (azx_first_init(chip) < 0 ||
2507 azx_probe_continue(chip) < 0) {
2508 snd_printk(KERN_ERR SFX
2509 "%s: initialization error\n",
2510 pci_name(chip->pci));
2511 chip->init_failed = true;
2512 }
2513 }
2514 } else {
2515 snd_printk(KERN_INFO SFX
2516 "%s %s via VGA-switcheroo\n",
2517 disabled ? "Disabling" : "Enabling",
2518 pci_name(chip->pci));
2519 if (disabled) {
2520 azx_suspend(pci, PMSG_FREEZE);
2521 chip->disabled = true;
2522 snd_hda_lock_devices(chip->bus);
2523 } else {
2524 snd_hda_unlock_devices(chip->bus);
2525 chip->disabled = false;
2526 azx_resume(pci);
2527 }
2528 }
2529}
2530
2531static bool azx_vs_can_switch(struct pci_dev *pci)
2532{
2533 struct snd_card *card = pci_get_drvdata(pci);
2534 struct azx *chip = card->private_data;
2535
2536 if (chip->init_failed)
2537 return false;
2538 if (chip->disabled || !chip->bus)
2539 return true;
2540 if (snd_hda_lock_devices(chip->bus))
2541 return false;
2542 snd_hda_unlock_devices(chip->bus);
2543 return true;
2544}
2545
2546static void __devinit init_vga_switcheroo(struct azx *chip)
2547{
2548 struct pci_dev *p = get_bound_vga(chip->pci);
2549 if (p) {
2550 snd_printk(KERN_INFO SFX
2551 "%s: Handle VGA-switcheroo audio client\n",
2552 pci_name(chip->pci));
2553 chip->use_vga_switcheroo = 1;
2554 pci_dev_put(p);
2555 }
2556}
2557
2558static const struct vga_switcheroo_client_ops azx_vs_ops = {
2559 .set_gpu_state = azx_vs_set_state,
2560 .can_switch = azx_vs_can_switch,
2561};
2562
2563static int __devinit register_vga_switcheroo(struct azx *chip)
2564{
2565 if (!chip->use_vga_switcheroo)
2566 return 0;
2567 /* FIXME: currently only handling DIS controller
2568 * is there any machine with two switchable HDMI audio controllers?
2569 */
2570 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2571 VGA_SWITCHEROO_DIS,
2572 chip->bus != NULL);
2573}
2574#else
2575#define init_vga_switcheroo(chip) /* NOP */
2576#define register_vga_switcheroo(chip) 0
2577#endif /* SUPPORT_VGA_SWITCHER */
2578
1da177e4
LT		 2579/*
2580 * destructor
2581 */
a98f90fd 2582static int azx_free(struct azx *chip)
1da177e4 2583{
4ce107b9
TI		 2584 int i;
2585
0cbf0098
TI		 2586 azx_notifier_unregister(chip);
2587
a82d51ed
TI		 2588 if (use_vga_switcheroo(chip)) {
2589 if (chip->disabled && chip->bus)
2590 snd_hda_unlock_devices(chip->bus);
2591 vga_switcheroo_unregister_client(chip->pci);
2592 }
2593
ce43fbae 2594 if (chip->initialized) {
9ad593f6 2595 azx_clear_irq_pending(chip);
07e4ca50 2596 for (i = 0; i < chip->num_streams; i++)
1da177e4 2597 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2598 azx_stop_chip(chip);
1da177e4
LT		 2599 }
2600
f000fd80 2601 if (chip->irq >= 0)
1da177e4 2602 free_irq(chip->irq, (void*)chip);
68e7fffc 2603 if (chip->msi)
30b35399 2604 pci_disable_msi(chip->pci);
f079c25a
TI		 2605 if (chip->remap_addr)
2606 iounmap(chip->remap_addr);
1da177e4 2607
4ce107b9
TI		 2608 if (chip->azx_dev) {
2609 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2610 if (chip->azx_dev[i].bdl.area) {
2611 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2612 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2613 }
4ce107b9 2614 }
27fe48d9
TI		 2615 if (chip->rb.area) {
2616 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2617 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2618 }
2619 if (chip->posbuf.area) {
2620 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2621 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2622 }
a82d51ed
TI		 2623 if (chip->region_requested)
2624 pci_release_regions(chip->pci);
1da177e4 2625 pci_disable_device(chip->pci);
07e4ca50 2626 kfree(chip->azx_dev);
1da177e4
LT		 2627 kfree(chip);
2628
2629 return 0;
2630}
2631
a98f90fd 2632static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2633{
2634 return azx_free(device->device_data);
2635}
2636
9121947d
TI		 2637/*
2638 * Check of disabled HDMI controller by vga-switcheroo
2639 */
2640static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2641{
2642 struct pci_dev *p;
2643
2644 /* check only discrete GPU */
2645 switch (pci->vendor) {
2646 case PCI_VENDOR_ID_ATI:
2647 case PCI_VENDOR_ID_AMD:
2648 case PCI_VENDOR_ID_NVIDIA:
2649 if (pci->devfn == 1) {
2650 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2651 pci->bus->number, 0);
2652 if (p) {
2653 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2654 return p;
2655 pci_dev_put(p);
2656 }
2657 }
2658 break;
2659 }
2660 return NULL;
2661}
2662
2663static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2664{
2665 bool vga_inactive = false;
2666 struct pci_dev *p = get_bound_vga(pci);
2667
2668 if (p) {
2669 if (vga_default_device() && p != vga_default_device())
2670 vga_inactive = true;
2671 pci_dev_put(p);
2672 }
2673 return vga_inactive;
2674}
2675
3372a153
TI		 2676/*
2677 * white/black-listing for position_fix
2678 */
623ec047 2679static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2680 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2681 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2682 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2683 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2684 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2685 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2686 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2687 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2688 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2689 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2690 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2691 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2692 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2693 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2694 {}
2695};
2696
2697static int __devinit check_position_fix(struct azx *chip, int fix)
2698{
2699 const struct snd_pci_quirk *q;
2700
c673ba1c
TI		 2701 switch (fix) {
2702 case POS_FIX_LPIB:
2703 case POS_FIX_POSBUF:
4cb36310 2704 case POS_FIX_VIACOMBO:
a6f2fd55 2705 case POS_FIX_COMBO:
c673ba1c
TI		 2706 return fix;
2707 }
2708
c673ba1c
TI		 2709 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2710 if (q) {
2711 printk(KERN_INFO
2712 "hda_intel: position_fix set to %d "
2713 "for device %04x:%04x\n",
2714 q->value, q->subvendor, q->subdevice);
2715 return q->value;
3372a153 2716 }
bdd9ef24
DH		 2717
2718 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2719 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2720 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2721 return POS_FIX_VIACOMBO;
9477c58e
TI		 2722 }
2723 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2724 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2725 return POS_FIX_LPIB;
bdd9ef24 2726 }
c673ba1c 2727 return POS_FIX_AUTO;
3372a153
TI		 2728}
2729
669ba27a
TI		 2730/*
2731 * black-lists for probe_mask
2732 */
2733static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2734 /* Thinkpad often breaks the controller communication when accessing
2735 * to the non-working (or non-existing) modem codec slot.
2736 */
2737 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2738 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2739 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2740 /* broken BIOS */
2741 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2742 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2743 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2744 /* forced codec slots */
93574844 2745 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2746 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2747 {}
2748};
2749
f1eaaeec
TI		 2750#define AZX_FORCE_CODEC_MASK 0x100
2751
5aba4f8e 2752static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2753{
2754 const struct snd_pci_quirk *q;
2755
f1eaaeec
TI		 2756 chip->codec_probe_mask = probe_mask[dev];
2757 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2758 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2759 if (q) {
2760 printk(KERN_INFO
2761 "hda_intel: probe_mask set to 0x%x "
2762 "for device %04x:%04x\n",
2763 q->value, q->subvendor, q->subdevice);
f1eaaeec 2764 chip->codec_probe_mask = q->value;
669ba27a
TI		 2765 }
2766 }
f1eaaeec
TI		 2767
2768 /* check forced option */
2769 if (chip->codec_probe_mask != -1 &&
2770 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2771 chip->codec_mask = chip->codec_probe_mask & 0xff;
2772 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2773 chip->codec_mask);
2774 }
669ba27a
TI		 2775}
2776
4d8e22e0 2777/*
71623855 2778 * white/black-list for enable_msi
4d8e22e0 2779 */
71623855 2780static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2781 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2782 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2783 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2784 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2785 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2786 {}
2787};
2788
2789static void __devinit check_msi(struct azx *chip)
2790{
2791 const struct snd_pci_quirk *q;
2792
71623855
TI		 2793 if (enable_msi >= 0) {
2794 chip->msi = !!enable_msi;
4d8e22e0 2795 return;
71623855
TI		 2796 }
2797 chip->msi = 1; /* enable MSI as default */
2798 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2799 if (q) {
2800 printk(KERN_INFO
2801 "hda_intel: msi for device %04x:%04x set to %d\n",
2802 q->subvendor, q->subdevice, q->value);
2803 chip->msi = q->value;
80c43ed7
TI		 2804 return;
2805 }
2806
2807 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2808 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2809 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2810 chip->msi = 0;
4d8e22e0
TI		 2811 }
2812}
2813
a1585d76
TI		 2814/* check the snoop mode availability */
2815static void __devinit azx_check_snoop_available(struct azx *chip)
2816{
2817 bool snoop = chip->snoop;
2818
2819 switch (chip->driver_type) {
2820 case AZX_DRIVER_VIA:
2821 /* force to non-snoop mode for a new VIA controller
2822 * when BIOS is set
2823 */
2824 if (snoop) {
2825 u8 val;
2826 pci_read_config_byte(chip->pci, 0x42, &val);
2827 if (!(val & 0x80) && chip->pci->revision == 0x30)
2828 snoop = false;
2829 }
2830 break;
2831 case AZX_DRIVER_ATIHDMI_NS:
2832 /* new ATI HDMI requires non-snoop */
2833 snoop = false;
2834 break;
2835 }
2836
2837 if (snoop != chip->snoop) {
2838 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2839 snoop ? "snoop" : "non-snoop");
2840 chip->snoop = snoop;
2841 }
2842}
669ba27a 2843
1da177e4
LT		 2844/*
2845 * constructor
2846 */
a98f90fd 2847static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2848 int dev, unsigned int driver_caps,
a98f90fd 2849 struct azx **rchip)
1da177e4 2850{
a98f90fd 2851 static struct snd_device_ops ops = {
1da177e4
LT		 2852 .dev_free = azx_dev_free,
2853 };
a82d51ed
TI		 2854 struct azx *chip;
2855 int err;
1da177e4
LT		 2856
2857 *rchip = NULL;
bcd72003 2858
927fc866
PM		 2859 err = pci_enable_device(pci);
2860 if (err < 0)
1da177e4
LT		 2861 return err;
2862
e560d8d8 2863 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2864 if (!chip) {
1da177e4
LT		 2865 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2866 pci_disable_device(pci);
2867 return -ENOMEM;
2868 }
2869
2870 spin_lock_init(&chip->reg_lock);
62932df8 2871 mutex_init(&chip->open_mutex);
1da177e4
LT		 2872 chip->card = card;
2873 chip->pci = pci;
2874 chip->irq = -1;
9477c58e
TI		 2875 chip->driver_caps = driver_caps;
2876 chip->driver_type = driver_caps & 0xff;
4d8e22e0 2877 check_msi(chip);
555e219f 2878 chip->dev_index = dev;
9ad593f6 2879 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 2880 INIT_LIST_HEAD(&chip->pcm_list);
a82d51ed 2881 init_vga_switcheroo(chip);
1da177e4 2882
beaffc39
SG		 2883 chip->position_fix[0] = chip->position_fix[1] =
2884 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 2885 /* combo mode uses LPIB for playback */
2886 if (chip->position_fix[0] == POS_FIX_COMBO) {
2887 chip->position_fix[0] = POS_FIX_LPIB;
2888 chip->position_fix[1] = POS_FIX_AUTO;
2889 }
2890
5aba4f8e 2891 check_probe_mask(chip, dev);
3372a153 2892
27346166 2893 chip->single_cmd = single_cmd;
27fe48d9 2894 chip->snoop = hda_snoop;
a1585d76 2895 azx_check_snoop_available(chip);
c74db86b 2896
5c0d7bc1
TI		 2897 if (bdl_pos_adj[dev] < 0) {
2898 switch (chip->driver_type) {
0c6341ac 2899 case AZX_DRIVER_ICH:
32679f95 2900 case AZX_DRIVER_PCH:
0c6341ac 2901 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2902 break;
2903 default:
0c6341ac 2904 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2905 break;
2906 }
2907 }
2908
a82d51ed
TI		 2909 if (check_hdmi_disabled(pci)) {
2910 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2911 pci_name(pci));
2912 if (use_vga_switcheroo(chip)) {
2913 snd_printk(KERN_INFO SFX "Delaying initialization\n");
2914 chip->disabled = true;
2915 goto ok;
2916 }
2917 kfree(chip);
2918 pci_disable_device(pci);
2919 return -ENXIO;
2920 }
2921
2922 err = azx_first_init(chip);
2923 if (err < 0) {
2924 azx_free(chip);
2925 return err;
2926 }
2927
2928 ok:
2929 err = register_vga_switcheroo(chip);
2930 if (err < 0) {
2931 snd_printk(KERN_ERR SFX
2932 "Error registering VGA-switcheroo client\n");
2933 azx_free(chip);
2934 return err;
2935 }
2936
2937 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2938 if (err < 0) {
2939 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2940 azx_free(chip);
2941 return err;
2942 }
2943
2944 *rchip = chip;
2945 return 0;
2946}
2947
2948static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
2949{
2950 int dev = chip->dev_index;
2951 struct pci_dev *pci = chip->pci;
2952 struct snd_card *card = chip->card;
2953 int i, err;
2954 unsigned short gcap;
2955
07e4ca50
TI		 2956#if BITS_PER_LONG != 64
2957 /* Fix up base address on ULI M5461 */
2958 if (chip->driver_type == AZX_DRIVER_ULI) {
2959 u16 tmp3;
2960 pci_read_config_word(pci, 0x40, &tmp3);
2961 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2962 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2963 }
2964#endif
2965
927fc866 2966 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 2967 if (err < 0)
1da177e4 2968 return err;
a82d51ed 2969 chip->region_requested = 1;
1da177e4 2970
927fc866 2971 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2972 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2973 if (chip->remap_addr == NULL) {
2974 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 2975 return -ENXIO;
1da177e4
LT		 2976 }
2977
68e7fffc
TI		 2978 if (chip->msi)
2979 if (pci_enable_msi(pci) < 0)
2980 chip->msi = 0;
7376d013 2981
a82d51ed
TI		 2982 if (azx_acquire_irq(chip, 0) < 0)
2983 return -EBUSY;
1da177e4
LT		 2984
2985 pci_set_master(pci);
2986 synchronize_irq(chip->irq);
2987
bcd72003 2988 gcap = azx_readw(chip, GCAP);
4abc1cc2 2989 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2990
dc4c2e6b 2991 /* disable SB600 64bit support for safety */
9477c58e 2992 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 2993 struct pci_dev *p_smbus;
2994 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2995 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2996 NULL);
2997 if (p_smbus) {
2998 if (p_smbus->revision < 0x30)
2999 gcap &= ~ICH6_GCAP_64OK;
3000 pci_dev_put(p_smbus);
3001 }
3002 }
09240cf4 3003
9477c58e
TI		 3004 /* disable 64bit DMA address on some devices */
3005 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3006 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3007 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3008 }
396087ea 3009
2ae66c26 3010 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3011 if (align_buffer_size >= 0)
3012 chip->align_buffer_size = !!align_buffer_size;
3013 else {
3014 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3015 chip->align_buffer_size = 0;
3016 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3017 chip->align_buffer_size = 1;
3018 else
3019 chip->align_buffer_size = 1;
3020 }
2ae66c26 3021
cf7aaca8 3022 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3023 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3024 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3025 else {
e930438c
YH		 3026 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3027 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3028 }
cf7aaca8 3029
8b6ed8e7
TI		 3030 /* read number of streams from GCAP register instead of using
3031 * hardcoded value
3032 */
3033 chip->capture_streams = (gcap >> 8) & 0x0f;
3034 chip->playback_streams = (gcap >> 12) & 0x0f;
3035 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3036 /* gcap didn't give any info, switching to old method */
3037
3038 switch (chip->driver_type) {
3039 case AZX_DRIVER_ULI:
3040 chip->playback_streams = ULI_NUM_PLAYBACK;
3041 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3042 break;
3043 case AZX_DRIVER_ATIHDMI:
1815b34a 3044 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3045 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3046 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3047 break;
c4da29ca 3048 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3049 default:
3050 chip->playback_streams = ICH6_NUM_PLAYBACK;
3051 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3052 break;
3053 }
07e4ca50 3054 }
8b6ed8e7
TI		 3055 chip->capture_index_offset = 0;
3056 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3057 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3058 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3059 GFP_KERNEL);
927fc866 3060 if (!chip->azx_dev) {
4abc1cc2 3061 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3062 return -ENOMEM;
07e4ca50
TI		 3063 }
3064
4ce107b9
TI		 3065 for (i = 0; i < chip->num_streams; i++) {
3066 /* allocate memory for the BDL for each stream */
3067 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3068 snd_dma_pci_data(chip->pci),
3069 BDL_SIZE, &chip->azx_dev[i].bdl);
3070 if (err < 0) {
3071 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3072 return -ENOMEM;
4ce107b9 3073 }
27fe48d9 3074 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3075 }
0be3b5d3 3076 /* allocate memory for the position buffer */
d01ce99f
TI		 3077 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3078 snd_dma_pci_data(chip->pci),
3079 chip->num_streams * 8, &chip->posbuf);
3080 if (err < 0) {
0be3b5d3 3081 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3082 return -ENOMEM;
1da177e4 3083 }
27fe48d9 3084 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3085 /* allocate CORB/RIRB */
81740861
TI		 3086 err = azx_alloc_cmd_io(chip);
3087 if (err < 0)
a82d51ed 3088 return err;
1da177e4
LT		 3089
3090 /* initialize streams */
3091 azx_init_stream(chip);
3092
3093 /* initialize chip */
cb53c626 3094 azx_init_pci(chip);
10e77dda 3095 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3096
3097 /* codec detection */
927fc866 3098 if (!chip->codec_mask) {
1da177e4 3099 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3100 return -ENODEV;
1da177e4
LT		 3101 }
3102
07e4ca50 3103 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3104 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3105 sizeof(card->shortname));
3106 snprintf(card->longname, sizeof(card->longname),
3107 "%s at 0x%lx irq %i",
3108 card->shortname, chip->addr, chip->irq);
07e4ca50 3109
1da177e4 3110 return 0;
1da177e4
LT		 3111}
3112
cb53c626
TI		 3113static void power_down_all_codecs(struct azx *chip)
3114{
3115#ifdef CONFIG_SND_HDA_POWER_SAVE
3116 /* The codecs were powered up in snd_hda_codec_new().
3117 * Now all initialization done, so turn them down if possible
3118 */
3119 struct hda_codec *codec;
3120 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3121 snd_hda_power_down(codec);
3122 }
3123#endif
3124}
3125
d01ce99f
TI		 3126static int __devinit azx_probe(struct pci_dev *pci,
3127 const struct pci_device_id *pci_id)
1da177e4 3128{
5aba4f8e 3129 static int dev;
a98f90fd
TI		 3130 struct snd_card *card;
3131 struct azx *chip;
927fc866 3132 int err;
1da177e4 3133
5aba4f8e
TI		 3134 if (dev >= SNDRV_CARDS)
3135 return -ENODEV;
3136 if (!enable[dev]) {
3137 dev++;
3138 return -ENOENT;
3139 }
3140
e58de7ba
TI		 3141 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3142 if (err < 0) {
1da177e4 3143 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3144 return err;
1da177e4
LT		 3145 }
3146
4ea6fbc8
TI		 3147 /* set this here since it's referred in snd_hda_load_patch() */
3148 snd_card_set_dev(card, &pci->dev);
3149
5aba4f8e 3150 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3151 if (err < 0)
3152 goto out_free;
421a1252 3153 card->private_data = chip;
1da177e4 3154
a82d51ed
TI		 3155 if (!chip->disabled) {
3156 err = azx_probe_continue(chip);
3157 if (err < 0)
3158 goto out_free;
3159 }
3160
3161 pci_set_drvdata(pci, card);
3162
3163 dev++;
3164 return 0;
3165
3166out_free:
3167 snd_card_free(card);
3168 return err;
3169}
3170
3171static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3172{
3173 int dev = chip->dev_index;
3174 int err;
3175
2dca0bba
JK		 3176#ifdef CONFIG_SND_HDA_INPUT_BEEP
3177 chip->beep_mode = beep_mode[dev];
3178#endif
3179
1da177e4 3180 /* create codec instances */
a1e21c90 3181 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3182 if (err < 0)
3183 goto out_free;
4ea6fbc8 3184#ifdef CONFIG_SND_HDA_PATCH_LOADER
41a63f18 3185 if (patch[dev] && *patch[dev]) {
4ea6fbc8
TI		 3186 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3187 patch[dev]);
3188 err = snd_hda_load_patch(chip->bus, patch[dev]);
3189 if (err < 0)
3190 goto out_free;
3191 }
3192#endif
10e77dda 3193 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3194 err = azx_codec_configure(chip);
3195 if (err < 0)
3196 goto out_free;
3197 }
1da177e4
LT		 3198
3199 /* create PCM streams */
176d5335 3200 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3201 if (err < 0)
3202 goto out_free;
1da177e4
LT		 3203
3204 /* create mixer controls */
d01ce99f 3205 err = azx_mixer_create(chip);
41dda0fd
WF		 3206 if (err < 0)
3207 goto out_free;
1da177e4 3208
a82d51ed 3209 err = snd_card_register(chip->card);
41dda0fd
WF		 3210 if (err < 0)
3211 goto out_free;
1da177e4 3212
cb53c626
TI		 3213 chip->running = 1;
3214 power_down_all_codecs(chip);
0cbf0098 3215 azx_notifier_register(chip);
1da177e4 3216
9121947d
TI		 3217 return 0;
3218
41dda0fd 3219out_free:
a82d51ed 3220 chip->init_failed = 1;
41dda0fd 3221 return err;
1da177e4
LT		 3222}
3223
3224static void __devexit azx_remove(struct pci_dev *pci)
3225{
9121947d
TI		 3226 struct snd_card *card = pci_get_drvdata(pci);
3227 if (card)
3228 snd_card_free(card);
1da177e4
LT		 3229 pci_set_drvdata(pci, NULL);
3230}
3231
3232/* PCI IDs */
cebe41d4 3233static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3234 /* CPT */
9477c58e 3235 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26
PLB		 3236 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3237 AZX_DCAPS_BUFSIZE },
cea310e8 3238 /* PBG */
9477c58e 3239 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3240 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3241 AZX_DCAPS_BUFSIZE},
d2edeb7c 3242 /* Panther Point */
9477c58e 3243 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3244 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
8bc039a1
SH		 3245 AZX_DCAPS_BUFSIZE},
3246 /* Lynx Point */
3247 { PCI_DEVICE(0x8086, 0x8c20),
3248 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2ae66c26 3249 AZX_DCAPS_BUFSIZE},
87218e9c 3250 /* SCH */
9477c58e 3251 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3252 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3253 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3254 { PCI_DEVICE(0x8086, 0x080a),
3255 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3256 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3257 /* ICH */
8b0bd226 3258 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3259 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3260 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3261 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3262 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3263 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3264 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3265 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3266 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3267 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3268 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3269 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3270 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3271 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3272 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3273 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3274 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3275 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3276 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3277 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3278 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3279 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3280 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3281 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3282 /* Generic Intel */
3283 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3284 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3285 .class_mask = 0xffffff,
2ae66c26 3286 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3287 /* ATI SB 450/600/700/800/900 */
3288 { PCI_DEVICE(0x1002, 0x437b),
3289 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3290 { PCI_DEVICE(0x1002, 0x4383),
3291 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3292 /* AMD Hudson */
3293 { PCI_DEVICE(0x1022, 0x780d),
3294 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3295 /* ATI HDMI */
9477c58e
TI		 3296 { PCI_DEVICE(0x1002, 0x793b),
3297 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3298 { PCI_DEVICE(0x1002, 0x7919),
3299 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3300 { PCI_DEVICE(0x1002, 0x960f),
3301 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3302 { PCI_DEVICE(0x1002, 0x970f),
3303 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3304 { PCI_DEVICE(0x1002, 0xaa00),
3305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3306 { PCI_DEVICE(0x1002, 0xaa08),
3307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3308 { PCI_DEVICE(0x1002, 0xaa10),
3309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3310 { PCI_DEVICE(0x1002, 0xaa18),
3311 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3312 { PCI_DEVICE(0x1002, 0xaa20),
3313 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3314 { PCI_DEVICE(0x1002, 0xaa28),
3315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3316 { PCI_DEVICE(0x1002, 0xaa30),
3317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3318 { PCI_DEVICE(0x1002, 0xaa38),
3319 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3320 { PCI_DEVICE(0x1002, 0xaa40),
3321 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3322 { PCI_DEVICE(0x1002, 0xaa48),
3323 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3324 { PCI_DEVICE(0x1002, 0x9902),
3325 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3326 { PCI_DEVICE(0x1002, 0xaaa0),
3327 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3328 { PCI_DEVICE(0x1002, 0xaaa8),
3329 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3330 { PCI_DEVICE(0x1002, 0xaab0),
3331 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3332 /* VIA VT8251/VT8237A */
9477c58e
TI		 3333 { PCI_DEVICE(0x1106, 0x3288),
3334 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
87218e9c
TI		 3335 /* SIS966 */
3336 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3337 /* ULI M5461 */
3338 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3339 /* NVIDIA MCP */
0c2fd1bf
TI		 3340 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3341 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3342 .class_mask = 0xffffff,
9477c58e 3343 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3344 /* Teradici */
9477c58e
TI		 3345 { PCI_DEVICE(0x6549, 0x1200),
3346 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3347 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 3348#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3349 /* the following entry conflicts with snd-ctxfi driver,
3350 * as ctxfi driver mutates from HD-audio to native mode with
3351 * a special command sequence.
3352 */
4e01f54b
TI		 3353 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3354 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3355 .class_mask = 0xffffff,
9477c58e 3356 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3357 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3358#else
3359 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3360 { PCI_DEVICE(0x1102, 0x0009),
3361 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3362 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3363#endif
5ae763b1
TI		 3364 /* CTHDA chips */
3365 { PCI_DEVICE(0x1102, 0x0010),
3366 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3367 { PCI_DEVICE(0x1102, 0x0012),
3368 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
e35d4b11
OS		 3369 /* Vortex86MX */
3370 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3371 /* VMware HDAudio */
3372 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3373 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3374 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3375 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3376 .class_mask = 0xffffff,
9477c58e 3377 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3378 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3379 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3380 .class_mask = 0xffffff,
9477c58e 3381 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3382 { 0, }
3383};
3384MODULE_DEVICE_TABLE(pci, azx_ids);
3385
3386/* pci_driver definition */
3387static struct pci_driver driver = {
3733e424 3388 .name = KBUILD_MODNAME,
1da177e4
LT		 3389 .id_table = azx_ids,
3390 .probe = azx_probe,
3391 .remove = __devexit_p(azx_remove),
421a1252
TI		 3392#ifdef CONFIG_PM
3393 .suspend = azx_suspend,
3394 .resume = azx_resume,
3395#endif
1da177e4
LT		 3396};
3397
3398static int __init alsa_card_azx_init(void)
3399{
01d25d46 3400 return pci_register_driver(&driver);
1da177e4
LT		 3401}
3402
3403static void __exit alsa_card_azx_exit(void)
3404{
3405 pci_unregister_driver(&driver);
3406}
3407
3408module_init(alsa_card_azx_init)
3409module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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