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Merge remote-tracking branch 'regulator/topic/max8973' into regulator-next
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
27fe48d9
TI		 50#ifdef CONFIG_X86
51/* for snoop control */
52#include <asm/pgtable.h>
53#include <asm/cacheflush.h>
54#endif
1da177e4
LT		 55#include <sound/core.h>
56#include <sound/initval.h>
9121947d 57#include <linux/vgaarb.h>
a82d51ed 58#include <linux/vga_switcheroo.h>
4918cdab 59#include <linux/firmware.h>
1da177e4
LT		 60#include "hda_codec.h"
61
62
5aba4f8e
TI		 63static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 65static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 66static char *model[SNDRV_CARDS];
1dac6695 67static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 68static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 69static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 70static int probe_only[SNDRV_CARDS];
a67ff6a5 71static bool single_cmd;
71623855 72static int enable_msi = -1;
4ea6fbc8
TI		 73#ifdef CONFIG_SND_HDA_PATCH_LOADER
74static char *patch[SNDRV_CARDS];
75#endif
2dca0bba 76#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 77static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 78 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79#endif
1da177e4 80
5aba4f8e 81module_param_array(index, int, NULL, 0444);
1da177e4 82MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 83module_param_array(id, charp, NULL, 0444);
1da177e4 84MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 85module_param_array(enable, bool, NULL, 0444);
86MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87module_param_array(model, charp, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 89module_param_array(position_fix, int, NULL, 0444);
4cb36310 90MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 91 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 92module_param_array(bdl_pos_adj, int, NULL, 0644);
93MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 94module_param_array(probe_mask, int, NULL, 0444);
606ad75f 95MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 96module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 97MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 98module_param(single_cmd, bool, 0444);
d01ce99f
TI		 99MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100 "(for debugging only).");
ac9ef6cf 101module_param(enable_msi, bint, 0444);
134a11f0 102MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 103#ifdef CONFIG_SND_HDA_PATCH_LOADER
104module_param_array(patch, charp, NULL, 0444);
105MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106#endif
2dca0bba 107#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 108module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 109MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 110 "(0=off, 1=on) (default=1).");
2dca0bba 111#endif
606ad75f 112
83012a7c 113#ifdef CONFIG_PM
65fcd41d
TI		 114static int param_set_xint(const char *val, const struct kernel_param *kp);
115static struct kernel_param_ops param_ops_xint = {
116 .set = param_set_xint,
117 .get = param_get_int,
118};
119#define param_check_xint param_check_int
120
fee2fba3 121static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 122module_param(power_save, xint, 0644);
fee2fba3
TI		 123MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124 "(in second, 0 = disable).");
1da177e4 125
dee1b66c
TI		 126/* reset the HD-audio controller in power save mode.
127 * this may give more power-saving, but will take longer time to
128 * wake up.
129 */
a67ff6a5 130static bool power_save_controller = 1;
dee1b66c
TI		 131module_param(power_save_controller, bool, 0644);
132MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 133#endif /* CONFIG_PM */
dee1b66c 134
7bfe059e
TI		 135static int align_buffer_size = -1;
136module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 137MODULE_PARM_DESC(align_buffer_size,
138 "Force buffer and period sizes to be multiple of 128 bytes.");
139
27fe48d9
TI		 140#ifdef CONFIG_X86
141static bool hda_snoop = true;
142module_param_named(snoop, hda_snoop, bool, 0444);
143MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144#define azx_snoop(chip) (chip)->snoop
145#else
146#define hda_snoop true
147#define azx_snoop(chip) true
148#endif
149
150
1da177e4
LT		 151MODULE_LICENSE("GPL");
152MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
153 "{Intel, ICH6M},"
2f1b3818 154 "{Intel, ICH7},"
f5d40b30 155 "{Intel, ESB2},"
d2981393 156 "{Intel, ICH8},"
f9cc8a8b 157 "{Intel, ICH9},"
c34f5a04 158 "{Intel, ICH10},"
b29c2360 159 "{Intel, PCH},"
d2f2fcd2 160 "{Intel, CPT},"
d2edeb7c 161 "{Intel, PPT},"
8bc039a1 162 "{Intel, LPT},"
144dad99 163 "{Intel, LPT_LP},"
e926f2c8 164 "{Intel, HPT},"
cea310e8 165 "{Intel, PBG},"
4979bca9 166 "{Intel, SCH},"
fc20a562 167 "{ATI, SB450},"
89be83f8 168 "{ATI, SB600},"
778b6e1b 169 "{ATI, RS600},"
5b15c95f 170 "{ATI, RS690},"
e6db1119
WL		 171 "{ATI, RS780},"
172 "{ATI, R600},"
2797f724
HRK		 173 "{ATI, RV630},"
174 "{ATI, RV610},"
27da1834
WL		 175 "{ATI, RV670},"
176 "{ATI, RV635},"
177 "{ATI, RV620},"
178 "{ATI, RV770},"
fc20a562 179 "{VIA, VT8251},"
47672310 180 "{VIA, VT8237A},"
07e4ca50
TI		 181 "{SiS, SIS966},"
182 "{ULI, M5461}}");
1da177e4
LT		 183MODULE_DESCRIPTION("Intel HDA driver");
184
4abc1cc2
TI		 185#ifdef CONFIG_SND_VERBOSE_PRINTK
186#define SFX /* nop */
187#else
1da177e4 188#define SFX "hda-intel: "
4abc1cc2 189#endif
cb53c626 190
a82d51ed
TI		 191#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192#ifdef CONFIG_SND_HDA_CODEC_HDMI
193#define SUPPORT_VGA_SWITCHEROO
194#endif
195#endif
196
197
1da177e4
LT		 198/*
199 * registers
200 */
201#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 202#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
203#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
204#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
205#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
206#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 207#define ICH6_REG_VMIN 0x02
208#define ICH6_REG_VMAJ 0x03
209#define ICH6_REG_OUTPAY 0x04
210#define ICH6_REG_INPAY 0x06
211#define ICH6_REG_GCTL 0x08
8a933ece 212#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 213#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
214#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 215#define ICH6_REG_WAKEEN 0x0c
216#define ICH6_REG_STATESTS 0x0e
217#define ICH6_REG_GSTS 0x10
b21fadb9 218#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 219#define ICH6_REG_INTCTL 0x20
220#define ICH6_REG_INTSTS 0x24
e5463720 221#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 222#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
223#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 224#define ICH6_REG_CORBLBASE 0x40
225#define ICH6_REG_CORBUBASE 0x44
226#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 227#define ICH6_REG_CORBRP 0x4a
228#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 229#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 230#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
231#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 232#define ICH6_REG_CORBSTS 0x4d
b21fadb9 233#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 234#define ICH6_REG_CORBSIZE 0x4e
235
236#define ICH6_REG_RIRBLBASE 0x50
237#define ICH6_REG_RIRBUBASE 0x54
238#define ICH6_REG_RIRBWP 0x58
b21fadb9 239#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 240#define ICH6_REG_RINTCNT 0x5a
241#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 242#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
243#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
244#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 245#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 246#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
247#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 248#define ICH6_REG_RIRBSIZE 0x5e
249
250#define ICH6_REG_IC 0x60
251#define ICH6_REG_IR 0x64
252#define ICH6_REG_IRS 0x68
253#define ICH6_IRS_VALID (1<<1)
254#define ICH6_IRS_BUSY (1<<0)
255
256#define ICH6_REG_DPLBASE 0x70
257#define ICH6_REG_DPUBASE 0x74
258#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
259
260/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
262
263/* stream register offsets from stream base */
264#define ICH6_REG_SD_CTL 0x00
265#define ICH6_REG_SD_STS 0x03
266#define ICH6_REG_SD_LPIB 0x04
267#define ICH6_REG_SD_CBL 0x08
268#define ICH6_REG_SD_LVI 0x0c
269#define ICH6_REG_SD_FIFOW 0x0e
270#define ICH6_REG_SD_FIFOSIZE 0x10
271#define ICH6_REG_SD_FORMAT 0x12
272#define ICH6_REG_SD_BDLPL 0x18
273#define ICH6_REG_SD_BDLPU 0x1c
274
275/* PCI space */
276#define ICH6_PCIREG_TCSEL 0x44
277
278/*
279 * other constants
280 */
281
282/* max number of SDs */
07e4ca50 283/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 284#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 285#define ICH6_NUM_PLAYBACK 4
286
287/* ULI has 6 playback and 5 capture */
07e4ca50 288#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 289#define ULI_NUM_PLAYBACK 6
290
778b6e1b 291/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 292#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 293#define ATIHDMI_NUM_PLAYBACK 1
294
f269002e
KY		 295/* TERA has 4 playback and 3 capture */
296#define TERA_NUM_CAPTURE 3
297#define TERA_NUM_PLAYBACK 4
298
07e4ca50
TI		 299/* this number is statically defined for simplicity */
300#define MAX_AZX_DEV 16
301
1da177e4 302/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 303#define BDL_SIZE 4096
304#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
305#define AZX_MAX_FRAG 32
1da177e4
LT		 306/* max buffer size - no h/w limit, you can increase as you like */
307#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 308
309/* RIRB int mask: overrun[2], response[0] */
310#define RIRB_INT_RESPONSE 0x01
311#define RIRB_INT_OVERRUN 0x04
312#define RIRB_INT_MASK 0x05
313
2f5983f2 314/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 315#define AZX_MAX_CODECS 8
316#define AZX_DEFAULT_CODECS 4
deadff16 317#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 318
319/* SD_CTL bits */
320#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
321#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 322#define SD_CTL_STRIPE (3 << 16) /* stripe control */
323#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
324#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 325#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
326#define SD_CTL_STREAM_TAG_SHIFT 20
327
328/* SD_CTL and SD_STS */
329#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
330#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
331#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 332#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
333 SD_INT_COMPLETE)
1da177e4
LT		 334
335/* SD_STS */
336#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
337
338/* INTCTL and INTSTS */
d01ce99f
TI		 339#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
340#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
341#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 342
1da177e4
LT		 343/* below are so far hardcoded - should read registers in future */
344#define ICH6_MAX_CORB_ENTRIES 256
345#define ICH6_MAX_RIRB_ENTRIES 256
346
c74db86b
TI		 347/* position fix mode */
348enum {
0be3b5d3 349 POS_FIX_AUTO,
d2e1c973 350 POS_FIX_LPIB,
0be3b5d3 351 POS_FIX_POSBUF,
4cb36310 352 POS_FIX_VIACOMBO,
a6f2fd55 353 POS_FIX_COMBO,
c74db86b 354};
1da177e4 355
f5d40b30 356/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 357#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
358#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
359
da3fca21
V		 360/* Defines for Nvidia HDA support */
361#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
362#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 363#define NVIDIA_HDA_ISTRM_COH 0x4d
364#define NVIDIA_HDA_OSTRM_COH 0x4c
365#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 366
90a5ad52
TI		 367/* Defines for Intel SCH HDA snoop control */
368#define INTEL_SCH_HDA_DEVC 0x78
369#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
370
0e153474
JC		 371/* Define IN stream 0 FIFO size offset in VIA controller */
372#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373/* Define VIA HD Audio Device ID*/
374#define VIA_HDAC_DEVICE_ID 0x3288
375
c4da29ca
YL		 376/* HD Audio class code */
377#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 378
1da177e4
LT		 379/*
380 */
381
a98f90fd 382struct azx_dev {
4ce107b9 383 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 384 u32 *posbuf; /* position buffer pointer */
1da177e4 385
d01ce99f 386 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 387 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 388 unsigned int frags; /* number for period in the play buffer */
389 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 390 unsigned long start_wallclk; /* start + minimum wallclk */
391 unsigned long period_wallclk; /* wallclk for period */
1da177e4 392
d01ce99f 393 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 394
d01ce99f 395 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 396
397 /* pcm support */
d01ce99f
TI		 398 struct snd_pcm_substream *substream; /* assigned substream,
399 * set in PCM open
400 */
401 unsigned int format_val; /* format value to be set in the
402 * controller and the codec
403 */
1da177e4
LT		 404 unsigned char stream_tag; /* assigned stream */
405 unsigned char index; /* stream index */
d5cf9911 406 int assigned_key; /* last device# key assigned to */
1da177e4 407
927fc866
PM		 408 unsigned int opened :1;
409 unsigned int running :1;
675f25d4 410 unsigned int irq_pending :1;
0e153474
JC		 411 /*
412 * For VIA:
413 * A flag to ensure DMA position is 0
414 * when link position is not greater than FIFO size
415 */
416 unsigned int insufficient :1;
27fe48d9 417 unsigned int wc_marked:1;
915bf29e 418 unsigned int no_period_wakeup:1;
1da177e4
LT		 419};
420
421/* CORB/RIRB */
a98f90fd 422struct azx_rb {
1da177e4
LT		 423 u32 *buf; /* CORB/RIRB buffer
424 * Each CORB entry is 4byte, RIRB is 8byte
425 */
426 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
427 /* for RIRB */
428 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 429 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
430 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 431};
432
01b65bfb
TI		 433struct azx_pcm {
434 struct azx *chip;
435 struct snd_pcm *pcm;
436 struct hda_codec *codec;
437 struct hda_pcm_stream *hinfo[2];
438 struct list_head list;
439};
440
a98f90fd
TI		 441struct azx {
442 struct snd_card *card;
1da177e4 443 struct pci_dev *pci;
555e219f 444 int dev_index;
1da177e4 445
07e4ca50
TI		 446 /* chip type specific */
447 int driver_type;
9477c58e 448 unsigned int driver_caps;
07e4ca50
TI		 449 int playback_streams;
450 int playback_index_offset;
451 int capture_streams;
452 int capture_index_offset;
453 int num_streams;
454
1da177e4
LT		 455 /* pci resources */
456 unsigned long addr;
457 void __iomem *remap_addr;
458 int irq;
459
460 /* locks */
461 spinlock_t reg_lock;
62932df8 462 struct mutex open_mutex;
1da177e4 463
07e4ca50 464 /* streams (x num_streams) */
a98f90fd 465 struct azx_dev *azx_dev;
1da177e4
LT		 466
467 /* PCM */
01b65bfb 468 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 469
470 /* HD codec */
471 unsigned short codec_mask;
f1eaaeec 472 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 473 struct hda_bus *bus;
2dca0bba 474 unsigned int beep_mode;
1da177e4
LT		 475
476 /* CORB/RIRB */
a98f90fd
TI		 477 struct azx_rb corb;
478 struct azx_rb rirb;
1da177e4 479
4ce107b9 480 /* CORB/RIRB and position buffers */
1da177e4
LT		 481 struct snd_dma_buffer rb;
482 struct snd_dma_buffer posbuf;
c74db86b 483
4918cdab
TI		 484#ifdef CONFIG_SND_HDA_PATCH_LOADER
485 const struct firmware *fw;
486#endif
487
c74db86b 488 /* flags */
beaffc39 489 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 490 int poll_count;
cb53c626 491 unsigned int running :1;
927fc866
PM		 492 unsigned int initialized :1;
493 unsigned int single_cmd :1;
494 unsigned int polling_mode :1;
68e7fffc 495 unsigned int msi :1;
a6a950a8 496 unsigned int irq_pending_warned :1;
6ce4a3bc 497 unsigned int probing :1; /* codec probing phase */
27fe48d9 498 unsigned int snoop:1;
52409aa6 499 unsigned int align_buffer_size:1;
a82d51ed
TI		 500 unsigned int region_requested:1;
501
502 /* VGA-switcheroo setup */
503 unsigned int use_vga_switcheroo:1;
128960a9 504 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 505 unsigned int init_failed:1; /* delayed init failed */
506 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 507
508 /* for debugging */
feb27340 509 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 510
511 /* for pending irqs */
512 struct work_struct irq_pending_work;
0cbf0098
TI		 513
514 /* reboot notifier (for mysterious hangup problem at power-down) */
515 struct notifier_block reboot_notifier;
65fcd41d
TI		 516
517 /* card list (for power_save trigger) */
518 struct list_head list;
1da177e4
LT		 519};
520
07e4ca50
TI		 521/* driver types */
522enum {
523 AZX_DRIVER_ICH,
32679f95 524 AZX_DRIVER_PCH,
4979bca9 525 AZX_DRIVER_SCH,
07e4ca50 526 AZX_DRIVER_ATI,
778b6e1b 527 AZX_DRIVER_ATIHDMI,
1815b34a 528 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 529 AZX_DRIVER_VIA,
530 AZX_DRIVER_SIS,
531 AZX_DRIVER_ULI,
da3fca21 532 AZX_DRIVER_NVIDIA,
f269002e 533 AZX_DRIVER_TERA,
14d34f16 534 AZX_DRIVER_CTX,
5ae763b1 535 AZX_DRIVER_CTHDA,
c4da29ca 536 AZX_DRIVER_GENERIC,
2f5983f2 537 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 538};
539
9477c58e
TI		 540/* driver quirks (capabilities) */
541/* bits 0-7 are used for indicating driver type */
542#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
543#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
544#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
545#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
546#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
547#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
548#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
549#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
550#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
551#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
552#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
553#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 554#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 555#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 556#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 557#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 558#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2
TI		 559#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
560
561/* quirks for Intel PCH */
562#define AZX_DCAPS_INTEL_PCH \
563 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
564 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 565
566/* quirks for ATI SB / AMD Hudson */
567#define AZX_DCAPS_PRESET_ATI_SB \
568 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
569 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
570
571/* quirks for ATI/AMD HDMI */
572#define AZX_DCAPS_PRESET_ATI_HDMI \
573 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
574
575/* quirks for Nvidia */
576#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 577 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
578 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 579
5ae763b1
TI		 580#define AZX_DCAPS_PRESET_CTHDA \
581 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
582
a82d51ed
TI		 583/*
584 * VGA-switcher support
585 */
586#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 587#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
588#else
589#define use_vga_switcheroo(chip) 0
590#endif
591
592#if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
a82d51ed
TI		 593#define DELAYED_INIT_MARK
594#define DELAYED_INITDATA_MARK
a82d51ed
TI		 595#else
596#define DELAYED_INIT_MARK __devinit
597#define DELAYED_INITDATA_MARK __devinitdata
a82d51ed
TI		 598#endif
599
600static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 601 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 602 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 603 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 604 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 605 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 606 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 607 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
608 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 609 [AZX_DRIVER_ULI] = "HDA ULI M5461",
610 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 611 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 612 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 613 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 614 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 615};
616
1da177e4
LT		 617/*
618 * macros for easy use
619 */
620#define azx_writel(chip,reg,value) \
621 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
622#define azx_readl(chip,reg) \
623 readl((chip)->remap_addr + ICH6_REG_##reg)
624#define azx_writew(chip,reg,value) \
625 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
626#define azx_readw(chip,reg) \
627 readw((chip)->remap_addr + ICH6_REG_##reg)
628#define azx_writeb(chip,reg,value) \
629 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
630#define azx_readb(chip,reg) \
631 readb((chip)->remap_addr + ICH6_REG_##reg)
632
633#define azx_sd_writel(dev,reg,value) \
634 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
635#define azx_sd_readl(dev,reg) \
636 readl((dev)->sd_addr + ICH6_REG_##reg)
637#define azx_sd_writew(dev,reg,value) \
638 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
639#define azx_sd_readw(dev,reg) \
640 readw((dev)->sd_addr + ICH6_REG_##reg)
641#define azx_sd_writeb(dev,reg,value) \
642 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
643#define azx_sd_readb(dev,reg) \
644 readb((dev)->sd_addr + ICH6_REG_##reg)
645
646/* for pcm support */
a98f90fd 647#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 648
27fe48d9
TI		 649#ifdef CONFIG_X86
650static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
651{
652 if (azx_snoop(chip))
653 return;
654 if (addr && size) {
655 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
656 if (on)
657 set_memory_wc((unsigned long)addr, pages);
658 else
659 set_memory_wb((unsigned long)addr, pages);
660 }
661}
662
663static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
664 bool on)
665{
666 __mark_pages_wc(chip, buf->area, buf->bytes, on);
667}
668static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
669 struct snd_pcm_runtime *runtime, bool on)
670{
671 if (azx_dev->wc_marked != on) {
672 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
673 azx_dev->wc_marked = on;
674 }
675}
676#else
677/* NOP for other archs */
678static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
679 bool on)
680{
681}
682static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
683 struct snd_pcm_runtime *runtime, bool on)
684{
685}
686#endif
687
68e7fffc 688static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 689static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 690/*
691 * Interface for HD codec
692 */
693
1da177e4
LT		 694/*
695 * CORB / RIRB interface
696 */
a98f90fd 697static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 698{
699 int err;
700
701 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 702 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
703 snd_dma_pci_data(chip->pci),
1da177e4
LT		 704 PAGE_SIZE, &chip->rb);
705 if (err < 0) {
706 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
707 return err;
708 }
27fe48d9 709 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 710 return 0;
711}
712
a98f90fd 713static void azx_init_cmd_io(struct azx *chip)
1da177e4 714{
cdb1fbf2 715 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 716 /* CORB set up */
717 chip->corb.addr = chip->rb.addr;
718 chip->corb.buf = (u32 *)chip->rb.area;
719 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 720 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 721
07e4ca50
TI		 722 /* set the corb size to 256 entries (ULI requires explicitly) */
723 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 724 /* set the corb write pointer to 0 */
725 azx_writew(chip, CORBWP, 0);
726 /* reset the corb hw read pointer */
b21fadb9 727 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 728 /* enable corb dma */
b21fadb9 729 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 730
731 /* RIRB set up */
732 chip->rirb.addr = chip->rb.addr + 2048;
733 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 734 chip->rirb.wp = chip->rirb.rp = 0;
735 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 736 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 737 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 738
07e4ca50
TI		 739 /* set the rirb size to 256 entries (ULI requires explicitly) */
740 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 741 /* reset the rirb hw write pointer */
b21fadb9 742 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 743 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 744 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 745 azx_writew(chip, RINTCNT, 0xc0);
746 else
747 azx_writew(chip, RINTCNT, 1);
1da177e4 748 /* enable rirb dma and response irq */
1da177e4 749 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 750 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 751}
752
a98f90fd 753static void azx_free_cmd_io(struct azx *chip)
1da177e4 754{
cdb1fbf2 755 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 756 /* disable ringbuffer DMAs */
757 azx_writeb(chip, RIRBCTL, 0);
758 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 759 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 760}
761
deadff16
WF		 762static unsigned int azx_command_addr(u32 cmd)
763{
764 unsigned int addr = cmd >> 28;
765
766 if (addr >= AZX_MAX_CODECS) {
767 snd_BUG();
768 addr = 0;
769 }
770
771 return addr;
772}
773
774static unsigned int azx_response_addr(u32 res)
775{
776 unsigned int addr = res & 0xf;
777
778 if (addr >= AZX_MAX_CODECS) {
779 snd_BUG();
780 addr = 0;
781 }
782
783 return addr;
1da177e4
LT		 784}
785
786/* send a command */
33fa35ed 787static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 788{
33fa35ed 789 struct azx *chip = bus->private_data;
deadff16 790 unsigned int addr = azx_command_addr(val);
1da177e4 791 unsigned int wp;
1da177e4 792
c32649fe
WF		 793 spin_lock_irq(&chip->reg_lock);
794
1da177e4
LT		 795 /* add command to corb */
796 wp = azx_readb(chip, CORBWP);
797 wp++;
798 wp %= ICH6_MAX_CORB_ENTRIES;
799
deadff16 800 chip->rirb.cmds[addr]++;
1da177e4
LT		 801 chip->corb.buf[wp] = cpu_to_le32(val);
802 azx_writel(chip, CORBWP, wp);
c32649fe 803
1da177e4
LT		 804 spin_unlock_irq(&chip->reg_lock);
805
806 return 0;
807}
808
809#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
810
811/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 812static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 813{
814 unsigned int rp, wp;
deadff16 815 unsigned int addr;
1da177e4
LT		 816 u32 res, res_ex;
817
818 wp = azx_readb(chip, RIRBWP);
819 if (wp == chip->rirb.wp)
820 return;
821 chip->rirb.wp = wp;
deadff16 822
1da177e4
LT		 823 while (chip->rirb.rp != wp) {
824 chip->rirb.rp++;
825 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
826
827 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
828 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
829 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 830 addr = azx_response_addr(res_ex);
1da177e4
LT		 831 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
832 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 833 else if (chip->rirb.cmds[addr]) {
834 chip->rirb.res[addr] = res;
2add9b92 835 smp_wmb();
deadff16 836 chip->rirb.cmds[addr]--;
e310bb06
WF		 837 } else
838 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
839 "last cmd=%#08x\n",
840 res, res_ex,
841 chip->last_cmd[addr]);
1da177e4
LT		 842 }
843}
844
845/* receive a response */
deadff16
WF		 846static unsigned int azx_rirb_get_response(struct hda_bus *bus,
847 unsigned int addr)
1da177e4 848{
33fa35ed 849 struct azx *chip = bus->private_data;
5c79b1f8 850 unsigned long timeout;
32cf4023 851 unsigned long loopcounter;
1eb6dc7d 852 int do_poll = 0;
1da177e4 853
5c79b1f8
TI		 854 again:
855 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 856
857 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 858 if (chip->polling_mode || do_poll) {
e96224ae
TI		 859 spin_lock_irq(&chip->reg_lock);
860 azx_update_rirb(chip);
861 spin_unlock_irq(&chip->reg_lock);
862 }
deadff16 863 if (!chip->rirb.cmds[addr]) {
2add9b92 864 smp_rmb();
b613291f 865 bus->rirb_error = 0;
1eb6dc7d
ML		 866
867 if (!do_poll)
868 chip->poll_count = 0;
deadff16 869 return chip->rirb.res[addr]; /* the last value */
2add9b92 870 }
28a0d9df
TI		 871 if (time_after(jiffies, timeout))
872 break;
32cf4023 873 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 874 msleep(2); /* temporary workaround */
875 else {
876 udelay(10);
877 cond_resched();
878 }
28a0d9df 879 }
5c79b1f8 880
1eb6dc7d
ML		 881 if (!chip->polling_mode && chip->poll_count < 2) {
882 snd_printdd(SFX "azx_get_response timeout, "
883 "polling the codec once: last cmd=0x%08x\n",
884 chip->last_cmd[addr]);
885 do_poll = 1;
886 chip->poll_count++;
887 goto again;
888 }
889
890
23c4a881
TI		 891 if (!chip->polling_mode) {
892 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
893 "switching to polling mode: last cmd=0x%08x\n",
894 chip->last_cmd[addr]);
895 chip->polling_mode = 1;
896 goto again;
897 }
898
68e7fffc 899 if (chip->msi) {
4abc1cc2 900 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 901 "disabling MSI: last cmd=0x%08x\n",
902 chip->last_cmd[addr]);
68e7fffc
TI		 903 free_irq(chip->irq, chip);
904 chip->irq = -1;
905 pci_disable_msi(chip->pci);
906 chip->msi = 0;
b613291f
TI		 907 if (azx_acquire_irq(chip, 1) < 0) {
908 bus->rirb_error = 1;
68e7fffc 909 return -1;
b613291f 910 }
68e7fffc
TI		 911 goto again;
912 }
913
6ce4a3bc
TI		 914 if (chip->probing) {
915 /* If this critical timeout happens during the codec probing
916 * phase, this is likely an access to a non-existing codec
917 * slot. Better to return an error and reset the system.
918 */
919 return -1;
920 }
921
8dd78330
TI		 922 /* a fatal communication error; need either to reset or to fallback
923 * to the single_cmd mode
924 */
b613291f 925 bus->rirb_error = 1;
b20f3b83 926 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 927 bus->response_reset = 1;
928 return -1; /* give a chance to retry */
929 }
930
931 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
932 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 933 chip->last_cmd[addr]);
8dd78330
TI		 934 chip->single_cmd = 1;
935 bus->response_reset = 0;
1a696978 936 /* release CORB/RIRB */
4fcd3920 937 azx_free_cmd_io(chip);
1a696978
TI		 938 /* disable unsolicited responses */
939 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 940 return -1;
1da177e4
LT		 941}
942
1da177e4
LT		 943/*
944 * Use the single immediate command instead of CORB/RIRB for simplicity
945 *
946 * Note: according to Intel, this is not preferred use. The command was
947 * intended for the BIOS only, and may get confused with unsolicited
948 * responses. So, we shouldn't use it for normal operation from the
949 * driver.
950 * I left the codes, however, for debugging/testing purposes.
951 */
952
b05a7d4f 953/* receive a response */
deadff16 954static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 955{
956 int timeout = 50;
957
958 while (timeout--) {
959 /* check IRV busy bit */
960 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
961 /* reuse rirb.res as the response return value */
deadff16 962 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 963 return 0;
964 }
965 udelay(1);
966 }
967 if (printk_ratelimit())
968 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
969 azx_readw(chip, IRS));
deadff16 970 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 971 return -EIO;
972}
973
1da177e4 974/* send a command */
33fa35ed 975static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 976{
33fa35ed 977 struct azx *chip = bus->private_data;
deadff16 978 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 979 int timeout = 50;
980
8dd78330 981 bus->rirb_error = 0;
1da177e4
LT		 982 while (timeout--) {
983 /* check ICB busy bit */
d01ce99f 984 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 985 /* Clear IRV valid bit */
d01ce99f
TI		 986 azx_writew(chip, IRS, azx_readw(chip, IRS) |
987 ICH6_IRS_VALID);
1da177e4 988 azx_writel(chip, IC, val);
d01ce99f
TI		 989 azx_writew(chip, IRS, azx_readw(chip, IRS) |
990 ICH6_IRS_BUSY);
deadff16 991 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 992 }
993 udelay(1);
994 }
1cfd52bc
MB		 995 if (printk_ratelimit())
996 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
997 azx_readw(chip, IRS), val);
1da177e4
LT		 998 return -EIO;
999}
1000
1001/* receive a response */
deadff16
WF		 1002static unsigned int azx_single_get_response(struct hda_bus *bus,
1003 unsigned int addr)
1da177e4 1004{
33fa35ed 1005 struct azx *chip = bus->private_data;
deadff16 1006 return chip->rirb.res[addr];
1da177e4
LT		 1007}
1008
111d3af5
TI		 1009/*
1010 * The below are the main callbacks from hda_codec.
1011 *
1012 * They are just the skeleton to call sub-callbacks according to the
1013 * current setting of chip->single_cmd.
1014 */
1015
1016/* send a command */
33fa35ed 1017static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1018{
33fa35ed 1019 struct azx *chip = bus->private_data;
43bbb6cc 1020
a82d51ed
TI		 1021 if (chip->disabled)
1022 return 0;
feb27340 1023 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1024 if (chip->single_cmd)
33fa35ed 1025 return azx_single_send_cmd(bus, val);
111d3af5 1026 else
33fa35ed 1027 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1028}
1029
1030/* get a response */
deadff16
WF		 1031static unsigned int azx_get_response(struct hda_bus *bus,
1032 unsigned int addr)
111d3af5 1033{
33fa35ed 1034 struct azx *chip = bus->private_data;
a82d51ed
TI		 1035 if (chip->disabled)
1036 return 0;
111d3af5 1037 if (chip->single_cmd)
deadff16 1038 return azx_single_get_response(bus, addr);
111d3af5 1039 else
deadff16 1040 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1041}
1042
83012a7c 1043#ifdef CONFIG_PM
68467f51 1044static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1045#endif
111d3af5 1046
1da177e4 1047/* reset codec link */
cd508fe5 1048static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1049{
1050 int count;
1051
cd508fe5
JK		 1052 if (!full_reset)
1053 goto __skip;
1054
e8a7f136
DT		 1055 /* clear STATESTS */
1056 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1057
1da177e4
LT		 1058 /* reset controller */
1059 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1060
1061 count = 50;
1062 while (azx_readb(chip, GCTL) && --count)
1063 msleep(1);
1064
1065 /* delay for >= 100us for codec PLL to settle per spec
1066 * Rev 0.9 section 5.5.1
1067 */
1068 msleep(1);
1069
1070 /* Bring controller out of reset */
1071 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1072
1073 count = 50;
927fc866 1074 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1075 msleep(1);
1076
927fc866 1077 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1078 msleep(1);
1079
cd508fe5 1080 __skip:
1da177e4 1081 /* check to see if controller is ready */
927fc866 1082 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1083 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1084 return -EBUSY;
1085 }
1086
41e2fce4 1087 /* Accept unsolicited responses */
1a696978
TI		 1088 if (!chip->single_cmd)
1089 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1090 ICH6_GCTL_UNSOL);
41e2fce4 1091
1da177e4 1092 /* detect codecs */
927fc866 1093 if (!chip->codec_mask) {
1da177e4 1094 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1095 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1096 }
1097
1098 return 0;
1099}
1100
1101
1102/*
1103 * Lowlevel interface
1104 */
1105
1106/* enable interrupts */
a98f90fd 1107static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1108{
1109 /* enable controller CIE and GIE */
1110 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1111 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1112}
1113
1114/* disable interrupts */
a98f90fd 1115static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1116{
1117 int i;
1118
1119 /* disable interrupts in stream descriptor */
07e4ca50 1120 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1121 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1122 azx_sd_writeb(azx_dev, SD_CTL,
1123 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1124 }
1125
1126 /* disable SIE for all streams */
1127 azx_writeb(chip, INTCTL, 0);
1128
1129 /* disable controller CIE and GIE */
1130 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1131 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1132}
1133
1134/* clear interrupts */
a98f90fd 1135static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1136{
1137 int i;
1138
1139 /* clear stream status */
07e4ca50 1140 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1141 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1142 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1143 }
1144
1145 /* clear STATESTS */
1146 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1147
1148 /* clear rirb status */
1149 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1150
1151 /* clear int status */
1152 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1153}
1154
1155/* start a stream */
a98f90fd 1156static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1157{
0e153474
JC		 1158 /*
1159 * Before stream start, initialize parameter
1160 */
1161 azx_dev->insufficient = 1;
1162
1da177e4 1163 /* enable SIE */
ccc5df05
WN		 1164 azx_writel(chip, INTCTL,
1165 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1166 /* set DMA start and interrupt mask */
1167 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1168 SD_CTL_DMA_START | SD_INT_MASK);
1169}
1170
1dddab40
TI		 1171/* stop DMA */
1172static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1173{
1da177e4
LT		 1174 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1175 ~(SD_CTL_DMA_START | SD_INT_MASK));
1176 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1177}
1178
1179/* stop a stream */
1180static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1181{
1182 azx_stream_clear(chip, azx_dev);
1da177e4 1183 /* disable SIE */
ccc5df05
WN		 1184 azx_writel(chip, INTCTL,
1185 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1186}
1187
1188
1189/*
cb53c626 1190 * reset and start the controller registers
1da177e4 1191 */
cd508fe5 1192static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1193{
cb53c626
TI		 1194 if (chip->initialized)
1195 return;
1da177e4
LT		 1196
1197 /* reset controller */
cd508fe5 1198 azx_reset(chip, full_reset);
1da177e4
LT		 1199
1200 /* initialize interrupts */
1201 azx_int_clear(chip);
1202 azx_int_enable(chip);
1203
1204 /* initialize the codec command I/O */
1a696978
TI		 1205 if (!chip->single_cmd)
1206 azx_init_cmd_io(chip);
1da177e4 1207
0be3b5d3
TI		 1208 /* program the position buffer */
1209 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1210 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1211
cb53c626
TI		 1212 chip->initialized = 1;
1213}
1214
1215/*
1216 * initialize the PCI registers
1217 */
1218/* update bits in a PCI register byte */
1219static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1220 unsigned char mask, unsigned char val)
1221{
1222 unsigned char data;
1223
1224 pci_read_config_byte(pci, reg, &data);
1225 data &= ~mask;
1226 data |= (val & mask);
1227 pci_write_config_byte(pci, reg, data);
1228}
1229
1230static void azx_init_pci(struct azx *chip)
1231{
1232 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1233 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1234 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1235 * codecs.
1236 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1237 */
46f2cc80 1238 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1239 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1240 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1241 }
cb53c626 1242
9477c58e
TI		 1243 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1244 * we need to enable snoop.
1245 */
1246 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1247 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1248 update_pci_byte(chip->pci,
27fe48d9
TI		 1249 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1250 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1251 }
1252
1253 /* For NVIDIA HDA, enable snoop */
1254 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1255 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1256 update_pci_byte(chip->pci,
1257 NVIDIA_HDA_TRANSREG_ADDR,
1258 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1259 update_pci_byte(chip->pci,
1260 NVIDIA_HDA_ISTRM_COH,
1261 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1262 update_pci_byte(chip->pci,
1263 NVIDIA_HDA_OSTRM_COH,
1264 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1265 }
1266
1267 /* Enable SCH/PCH snoop if needed */
1268 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1269 unsigned short snoop;
90a5ad52 1270 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1271 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1272 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1273 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1274 if (!azx_snoop(chip))
1275 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1276 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1277 pci_read_config_word(chip->pci,
1278 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1279 }
27fe48d9
TI		 1280 snd_printdd(SFX "SCH snoop: %s\n",
1281 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1282 ? "Disabled" : "Enabled");
da3fca21 1283 }
1da177e4
LT		 1284}
1285
1286
9ad593f6
TI		 1287static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1288
1da177e4
LT		 1289/*
1290 * interrupt handler
1291 */
7d12e780 1292static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1293{
a98f90fd
TI		 1294 struct azx *chip = dev_id;
1295 struct azx_dev *azx_dev;
1da177e4 1296 u32 status;
9ef04066 1297 u8 sd_status;
fa00e046 1298 int i, ok;
1da177e4 1299
b8dfc462
ML		 1300#ifdef CONFIG_PM_RUNTIME
1301 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1302 return IRQ_NONE;
1303#endif
1304
1da177e4
LT		 1305 spin_lock(&chip->reg_lock);
1306
60911062
DC		 1307 if (chip->disabled) {
1308 spin_unlock(&chip->reg_lock);
a82d51ed 1309 return IRQ_NONE;
60911062 1310 }
a82d51ed 1311
1da177e4
LT		 1312 status = azx_readl(chip, INTSTS);
1313 if (status == 0) {
1314 spin_unlock(&chip->reg_lock);
1315 return IRQ_NONE;
1316 }
1317
07e4ca50 1318 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1319 azx_dev = &chip->azx_dev[i];
1320 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1321 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1322 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1323 if (!azx_dev->substream || !azx_dev->running ||
1324 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1325 continue;
1326 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1327 ok = azx_position_ok(chip, azx_dev);
1328 if (ok == 1) {
9ad593f6 1329 azx_dev->irq_pending = 0;
1da177e4
LT		 1330 spin_unlock(&chip->reg_lock);
1331 snd_pcm_period_elapsed(azx_dev->substream);
1332 spin_lock(&chip->reg_lock);
fa00e046 1333 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1334 /* bogus IRQ, process it later */
1335 azx_dev->irq_pending = 1;
6acaed38
TI		 1336 queue_work(chip->bus->workq,
1337 &chip->irq_pending_work);
1da177e4
LT		 1338 }
1339 }
1340 }
1341
1342 /* clear rirb int */
1343 status = azx_readb(chip, RIRBSTS);
1344 if (status & RIRB_INT_MASK) {
14d34f16 1345 if (status & RIRB_INT_RESPONSE) {
9477c58e 1346 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1347 udelay(80);
1da177e4 1348 azx_update_rirb(chip);
14d34f16 1349 }
1da177e4
LT		 1350 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1351 }
1352
1353#if 0
1354 /* clear state status int */
1355 if (azx_readb(chip, STATESTS) & 0x04)
1356 azx_writeb(chip, STATESTS, 0x04);
1357#endif
1358 spin_unlock(&chip->reg_lock);
1359
1360 return IRQ_HANDLED;
1361}
1362
1363
675f25d4
TI		 1364/*
1365 * set up a BDL entry
1366 */
5ae763b1
TI		 1367static int setup_bdle(struct azx *chip,
1368 struct snd_pcm_substream *substream,
675f25d4
TI		 1369 struct azx_dev *azx_dev, u32 **bdlp,
1370 int ofs, int size, int with_ioc)
1371{
675f25d4
TI		 1372 u32 *bdl = *bdlp;
1373
1374 while (size > 0) {
1375 dma_addr_t addr;
1376 int chunk;
1377
1378 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1379 return -EINVAL;
1380
77a23f26 1381 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1382 /* program the address field of the BDL entry */
1383 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1384 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1385 /* program the size field of the BDL entry */
fc4abee8 1386 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1387 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1388 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1389 u32 remain = 0x1000 - (ofs & 0xfff);
1390 if (chunk > remain)
1391 chunk = remain;
1392 }
675f25d4
TI		 1393 bdl[2] = cpu_to_le32(chunk);
1394 /* program the IOC to enable interrupt
1395 * only when the whole fragment is processed
1396 */
1397 size -= chunk;
1398 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1399 bdl += 4;
1400 azx_dev->frags++;
1401 ofs += chunk;
1402 }
1403 *bdlp = bdl;
1404 return ofs;
1405}
1406
1da177e4
LT		 1407/*
1408 * set up BDL entries
1409 */
555e219f
TI		 1410static int azx_setup_periods(struct azx *chip,
1411 struct snd_pcm_substream *substream,
4ce107b9 1412 struct azx_dev *azx_dev)
1da177e4 1413{
4ce107b9
TI		 1414 u32 *bdl;
1415 int i, ofs, periods, period_bytes;
555e219f 1416 int pos_adj;
1da177e4
LT		 1417
1418 /* reset BDL address */
1419 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1420 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1421
97b71c94 1422 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1423 periods = azx_dev->bufsize / period_bytes;
1424
1da177e4 1425 /* program the initial BDL entries */
4ce107b9
TI		 1426 bdl = (u32 *)azx_dev->bdl.area;
1427 ofs = 0;
1428 azx_dev->frags = 0;
555e219f 1429 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1430 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1431 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1432 int pos_align = pos_adj;
555e219f 1433 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1434 if (!pos_adj)
e785d3d8
TI		 1435 pos_adj = pos_align;
1436 else
1437 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1438 pos_align;
675f25d4
TI		 1439 pos_adj = frames_to_bytes(runtime, pos_adj);
1440 if (pos_adj >= period_bytes) {
4abc1cc2 1441 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1442 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1443 pos_adj = 0;
1444 } else {
5ae763b1 1445 ofs = setup_bdle(chip, substream, azx_dev,
915bf29e 1446 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1447 if (ofs < 0)
1448 goto error;
4ce107b9 1449 }
555e219f
TI		 1450 } else
1451 pos_adj = 0;
675f25d4
TI		 1452 for (i = 0; i < periods; i++) {
1453 if (i == periods - 1 && pos_adj)
5ae763b1 1454 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1455 period_bytes - pos_adj, 0);
1456 else
5ae763b1 1457 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70 1458 period_bytes,
915bf29e 1459 !azx_dev->no_period_wakeup);
675f25d4
TI		 1460 if (ofs < 0)
1461 goto error;
1da177e4 1462 }
4ce107b9 1463 return 0;
675f25d4
TI		 1464
1465 error:
4abc1cc2 1466 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1467 azx_dev->bufsize, period_bytes);
675f25d4 1468 return -EINVAL;
1da177e4
LT		 1469}
1470
1dddab40
TI		 1471/* reset stream */
1472static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1473{
1474 unsigned char val;
1475 int timeout;
1476
1dddab40
TI		 1477 azx_stream_clear(chip, azx_dev);
1478
d01ce99f
TI		 1479 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1480 SD_CTL_STREAM_RESET);
1da177e4
LT		 1481 udelay(3);
1482 timeout = 300;
1483 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1484 --timeout)
1485 ;
1486 val &= ~SD_CTL_STREAM_RESET;
1487 azx_sd_writeb(azx_dev, SD_CTL, val);
1488 udelay(3);
1489
1490 timeout = 300;
1491 /* waiting for hardware to report that the stream is out of reset */
1492 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1493 --timeout)
1494 ;
fa00e046
JK		 1495
1496 /* reset first position - may not be synced with hw at this time */
1497 *azx_dev->posbuf = 0;
1dddab40 1498}
1da177e4 1499
1dddab40
TI		 1500/*
1501 * set up the SD for streaming
1502 */
1503static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1504{
27fe48d9 1505 unsigned int val;
1dddab40
TI		 1506 /* make sure the run bit is zero for SD */
1507 azx_stream_clear(chip, azx_dev);
1da177e4 1508 /* program the stream_tag */
27fe48d9
TI		 1509 val = azx_sd_readl(azx_dev, SD_CTL);
1510 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1511 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1512 if (!azx_snoop(chip))
1513 val |= SD_CTL_TRAFFIC_PRIO;
1514 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1515
1516 /* program the length of samples in cyclic buffer */
1517 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1518
1519 /* program the stream format */
1520 /* this value needs to be the same as the one programmed */
1521 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1522
1523 /* program the stream LVI (last valid index) of the BDL */
1524 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1525
1526 /* program the BDL address */
1527 /* lower BDL address */
4ce107b9 1528 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1529 /* upper BDL address */
766979e0 1530 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1531
0be3b5d3 1532 /* enable the position buffer */
4cb36310
DH		 1533 if (chip->position_fix[0] != POS_FIX_LPIB ||
1534 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1535 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1536 azx_writel(chip, DPLBASE,
1537 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1538 }
c74db86b 1539
1da177e4 1540 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1541 azx_sd_writel(azx_dev, SD_CTL,
1542 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1543
1544 return 0;
1545}
1546
6ce4a3bc
TI		 1547/*
1548 * Probe the given codec address
1549 */
1550static int probe_codec(struct azx *chip, int addr)
1551{
1552 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1553 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1554 unsigned int res;
1555
a678cdee 1556 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1557 chip->probing = 1;
1558 azx_send_cmd(chip->bus, cmd);
deadff16 1559 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1560 chip->probing = 0;
a678cdee 1561 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1562 if (res == -1)
1563 return -EIO;
4abc1cc2 1564 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1565 return 0;
1566}
1567
33fa35ed
TI		 1568static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1569 struct hda_pcm *cpcm);
6ce4a3bc 1570static void azx_stop_chip(struct azx *chip);
1da177e4 1571
8dd78330
TI		 1572static void azx_bus_reset(struct hda_bus *bus)
1573{
1574 struct azx *chip = bus->private_data;
8dd78330
TI		 1575
1576 bus->in_reset = 1;
1577 azx_stop_chip(chip);
cd508fe5 1578 azx_init_chip(chip, 1);
65f75983 1579#ifdef CONFIG_PM
8dd78330 1580 if (chip->initialized) {
01b65bfb
TI		 1581 struct azx_pcm *p;
1582 list_for_each_entry(p, &chip->pcm_list, list)
1583 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1584 snd_hda_suspend(chip->bus);
1585 snd_hda_resume(chip->bus);
1586 }
65f75983 1587#endif
8dd78330
TI		 1588 bus->in_reset = 0;
1589}
1590
1da177e4
LT		 1591/*
1592 * Codec initialization
1593 */
1594
2f5983f2 1595/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1596static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1597 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1598 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1599};
1600
a82d51ed 1601static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1602{
1603 struct hda_bus_template bus_temp;
34c25350
TI		 1604 int c, codecs, err;
1605 int max_slots;
1da177e4
LT		 1606
1607 memset(&bus_temp, 0, sizeof(bus_temp));
1608 bus_temp.private_data = chip;
1609 bus_temp.modelname = model;
1610 bus_temp.pci = chip->pci;
111d3af5
TI		 1611 bus_temp.ops.command = azx_send_cmd;
1612 bus_temp.ops.get_response = azx_get_response;
176d5335 1613 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1614 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1615#ifdef CONFIG_PM
11cd41b8 1616 bus_temp.power_save = &power_save;
cb53c626
TI		 1617 bus_temp.ops.pm_notify = azx_power_notify;
1618#endif
1da177e4 1619
d01ce99f
TI		 1620 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1621 if (err < 0)
1da177e4
LT		 1622 return err;
1623
9477c58e
TI		 1624 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1625 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1626 chip->bus->needs_damn_long_delay = 1;
9477c58e 1627 }
dc9c8e21 1628
34c25350 1629 codecs = 0;
2f5983f2
TI		 1630 max_slots = azx_max_codecs[chip->driver_type];
1631 if (!max_slots)
7445dfc1 1632 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1633
1634 /* First try to probe all given codec slots */
1635 for (c = 0; c < max_slots; c++) {
f1eaaeec 1636 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1637 if (probe_codec(chip, c) < 0) {
1638 /* Some BIOSen give you wrong codec addresses
1639 * that don't exist
1640 */
4abc1cc2
TI		 1641 snd_printk(KERN_WARNING SFX
1642 "Codec #%d probe error; "
6ce4a3bc
TI		 1643 "disabling it...\n", c);
1644 chip->codec_mask &= ~(1 << c);
1645 /* More badly, accessing to a non-existing
1646 * codec often screws up the controller chip,
2448158e 1647 * and disturbs the further communications.
6ce4a3bc
TI		 1648 * Thus if an error occurs during probing,
1649 * better to reset the controller chip to
1650 * get back to the sanity state.
1651 */
1652 azx_stop_chip(chip);
cd508fe5 1653 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1654 }
1655 }
1656 }
1657
d507cd66
TI		 1658 /* AMD chipsets often cause the communication stalls upon certain
1659 * sequence like the pin-detection. It seems that forcing the synced
1660 * access works around the stall. Grrr...
1661 */
9477c58e
TI		 1662 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1663 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1664 chip->bus->sync_write = 1;
1665 chip->bus->allow_bus_reset = 1;
1666 }
1667
6ce4a3bc 1668 /* Then create codec instances */
34c25350 1669 for (c = 0; c < max_slots; c++) {
f1eaaeec 1670 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1671 struct hda_codec *codec;
a1e21c90 1672 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1673 if (err < 0)
1674 continue;
2dca0bba 1675 codec->beep_mode = chip->beep_mode;
1da177e4 1676 codecs++;
19a982b6
TI		 1677 }
1678 }
1679 if (!codecs) {
1da177e4
LT		 1680 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1681 return -ENXIO;
1682 }
a1e21c90
TI		 1683 return 0;
1684}
1da177e4 1685
a1e21c90
TI		 1686/* configure each codec instance */
1687static int __devinit azx_codec_configure(struct azx *chip)
1688{
1689 struct hda_codec *codec;
1690 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1691 snd_hda_codec_configure(codec);
1692 }
1da177e4
LT		 1693 return 0;
1694}
1695
1696
1697/*
1698 * PCM support
1699 */
1700
1701/* assign a stream for the PCM */
ef18bede
WF		 1702static inline struct azx_dev *
1703azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1704{
07e4ca50 1705 int dev, i, nums;
ef18bede 1706 struct azx_dev *res = NULL;
d5cf9911
TI		 1707 /* make a non-zero unique key for the substream */
1708 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1709 (substream->stream + 1);
ef18bede
WF		 1710
1711 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1712 dev = chip->playback_index_offset;
1713 nums = chip->playback_streams;
1714 } else {
1715 dev = chip->capture_index_offset;
1716 nums = chip->capture_streams;
1717 }
1718 for (i = 0; i < nums; i++, dev++)
d01ce99f 1719 if (!chip->azx_dev[dev].opened) {
ef18bede 1720 res = &chip->azx_dev[dev];
d5cf9911 1721 if (res->assigned_key == key)
ef18bede 1722 break;
1da177e4 1723 }
ef18bede
WF		 1724 if (res) {
1725 res->opened = 1;
d5cf9911 1726 res->assigned_key = key;
ef18bede
WF		 1727 }
1728 return res;
1da177e4
LT		 1729}
1730
1731/* release the assigned stream */
a98f90fd 1732static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1733{
1734 azx_dev->opened = 0;
1735}
1736
a98f90fd 1737static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1738 .info = (SNDRV_PCM_INFO_MMAP |
1739 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1740 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1741 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1742 /* No full-resume yet implemented */
1743 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1744 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1745 SNDRV_PCM_INFO_SYNC_START |
1746 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1747 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1748 .rates = SNDRV_PCM_RATE_48000,
1749 .rate_min = 48000,
1750 .rate_max = 48000,
1751 .channels_min = 2,
1752 .channels_max = 2,
1753 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1754 .period_bytes_min = 128,
1755 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1756 .periods_min = 2,
1757 .periods_max = AZX_MAX_FRAG,
1758 .fifo_size = 0,
1759};
1760
a98f90fd 1761static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1762{
1763 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1764 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1765 struct azx *chip = apcm->chip;
1766 struct azx_dev *azx_dev;
1767 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1768 unsigned long flags;
1769 int err;
2ae66c26 1770 int buff_step;
1da177e4 1771
62932df8 1772 mutex_lock(&chip->open_mutex);
ef18bede 1773 azx_dev = azx_assign_device(chip, substream);
1da177e4 1774 if (azx_dev == NULL) {
62932df8 1775 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1776 return -EBUSY;
1777 }
1778 runtime->hw = azx_pcm_hw;
1779 runtime->hw.channels_min = hinfo->channels_min;
1780 runtime->hw.channels_max = hinfo->channels_max;
1781 runtime->hw.formats = hinfo->formats;
1782 runtime->hw.rates = hinfo->rates;
1783 snd_pcm_limit_hw_rates(runtime);
1784 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1785 if (chip->align_buffer_size)
2ae66c26
PLB		 1786 /* constrain buffer sizes to be multiple of 128
1787 bytes. This is more efficient in terms of memory
1788 access but isn't required by the HDA spec and
1789 prevents users from specifying exact period/buffer
1790 sizes. For example for 44.1kHz, a period size set
1791 to 20ms will be rounded to 19.59ms. */
1792 buff_step = 128;
1793 else
1794 /* Don't enforce steps on buffer sizes, still need to
1795 be multiple of 4 bytes (HDA spec). Tested on Intel
1796 HDA controllers, may not work on all devices where
1797 option needs to be disabled */
1798 buff_step = 4;
1799
5f1545bc 1800 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1801 buff_step);
5f1545bc 1802 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1803 buff_step);
b4a91cf0 1804 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1805 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1806 if (err < 0) {
1da177e4 1807 azx_release_device(azx_dev);
cb53c626 1808 snd_hda_power_down(apcm->codec);
62932df8 1809 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1810 return err;
1811 }
70d321e6 1812 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1813 /* sanity check */
1814 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1815 snd_BUG_ON(!runtime->hw.channels_max) ||
1816 snd_BUG_ON(!runtime->hw.formats) ||
1817 snd_BUG_ON(!runtime->hw.rates)) {
1818 azx_release_device(azx_dev);
1819 hinfo->ops.close(hinfo, apcm->codec, substream);
1820 snd_hda_power_down(apcm->codec);
1821 mutex_unlock(&chip->open_mutex);
1822 return -EINVAL;
1823 }
1da177e4
LT		 1824 spin_lock_irqsave(&chip->reg_lock, flags);
1825 azx_dev->substream = substream;
1826 azx_dev->running = 0;
1827 spin_unlock_irqrestore(&chip->reg_lock, flags);
1828
1829 runtime->private_data = azx_dev;
850f0e52 1830 snd_pcm_set_sync(substream);
62932df8 1831 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1832 return 0;
1833}
1834
a98f90fd 1835static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1836{
1837 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1838 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1839 struct azx *chip = apcm->chip;
1840 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1841 unsigned long flags;
1842
62932df8 1843 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1844 spin_lock_irqsave(&chip->reg_lock, flags);
1845 azx_dev->substream = NULL;
1846 azx_dev->running = 0;
1847 spin_unlock_irqrestore(&chip->reg_lock, flags);
1848 azx_release_device(azx_dev);
1849 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1850 snd_hda_power_down(apcm->codec);
62932df8 1851 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1852 return 0;
1853}
1854
d01ce99f
TI		 1855static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1856 struct snd_pcm_hw_params *hw_params)
1da177e4 1857{
27fe48d9
TI		 1858 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1859 struct azx *chip = apcm->chip;
1860 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1861 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1862 int ret;
97b71c94 1863
27fe48d9 1864 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1865 azx_dev->bufsize = 0;
1866 azx_dev->period_bytes = 0;
1867 azx_dev->format_val = 0;
27fe48d9 1868 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1869 params_buffer_bytes(hw_params));
27fe48d9
TI		 1870 if (ret < 0)
1871 return ret;
1872 mark_runtime_wc(chip, azx_dev, runtime, true);
1873 return ret;
1da177e4
LT		 1874}
1875
a98f90fd 1876static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1877{
1878 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1879 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1880 struct azx *chip = apcm->chip;
1881 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1882 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1883
1884 /* reset BDL address */
1885 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1886 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1887 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1888 azx_dev->bufsize = 0;
1889 azx_dev->period_bytes = 0;
1890 azx_dev->format_val = 0;
1da177e4 1891
eb541337 1892 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1893
27fe48d9 1894 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1895 return snd_pcm_lib_free_pages(substream);
1896}
1897
a98f90fd 1898static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1899{
1900 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1901 struct azx *chip = apcm->chip;
1902 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1903 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1904 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1905 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1906 int err;
7c935976
SW		 1907 struct hda_spdif_out *spdif =
1908 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1909 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1910
fa00e046 1911 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1912 format_val = snd_hda_calc_stream_format(runtime->rate,
1913 runtime->channels,
1914 runtime->format,
32c168c8 1915 hinfo->maxbps,
7c935976 1916 ctls);
97b71c94 1917 if (!format_val) {
d01ce99f
TI		 1918 snd_printk(KERN_ERR SFX
1919 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1920 runtime->rate, runtime->channels, runtime->format);
1921 return -EINVAL;
1922 }
1923
97b71c94
TI		 1924 bufsize = snd_pcm_lib_buffer_bytes(substream);
1925 period_bytes = snd_pcm_lib_period_bytes(substream);
1926
4abc1cc2 1927 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1928 bufsize, format_val);
1929
1930 if (bufsize != azx_dev->bufsize ||
1931 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 1932 format_val != azx_dev->format_val ||
1933 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 1934 azx_dev->bufsize = bufsize;
1935 azx_dev->period_bytes = period_bytes;
1936 azx_dev->format_val = format_val;
915bf29e 1937 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 1938 err = azx_setup_periods(chip, substream, azx_dev);
1939 if (err < 0)
1940 return err;
1941 }
1942
e5463720
JK		 1943 /* wallclk has 24Mhz clock source */
1944 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1945 runtime->rate) * 1000);
1da177e4
LT		 1946 azx_setup_controller(chip, azx_dev);
1947 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1948 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1949 else
1950 azx_dev->fifo_size = 0;
1951
62b7e5e0
TI		 1952 stream_tag = azx_dev->stream_tag;
1953 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1954 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1955 stream_tag > chip->capture_streams)
1956 stream_tag -= chip->capture_streams;
1957 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1958 azx_dev->format_val, substream);
1da177e4
LT		 1959}
1960
a98f90fd 1961static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1962{
1963 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1964 struct azx *chip = apcm->chip;
850f0e52
TI		 1965 struct azx_dev *azx_dev;
1966 struct snd_pcm_substream *s;
fa00e046 1967 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1968 int nwait, timeout;
1da177e4 1969
1da177e4 1970 switch (cmd) {
fa00e046
JK		 1971 case SNDRV_PCM_TRIGGER_START:
1972 rstart = 1;
1da177e4
LT		 1973 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1974 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1975 start = 1;
1da177e4
LT		 1976 break;
1977 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1978 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1979 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1980 start = 0;
1da177e4
LT		 1981 break;
1982 default:
850f0e52
TI		 1983 return -EINVAL;
1984 }
1985
1986 snd_pcm_group_for_each_entry(s, substream) {
1987 if (s->pcm->card != substream->pcm->card)
1988 continue;
1989 azx_dev = get_azx_dev(s);
1990 sbits |= 1 << azx_dev->index;
1991 nsync++;
1992 snd_pcm_trigger_done(s, substream);
1993 }
1994
1995 spin_lock(&chip->reg_lock);
172d3b20
PLB		 1996
1997 /* first, set SYNC bits of corresponding streams */
1998 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1999 azx_writel(chip, OLD_SSYNC,
2000 azx_readl(chip, OLD_SSYNC) | sbits);
2001 else
2002 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2003
850f0e52
TI		 2004 snd_pcm_group_for_each_entry(s, substream) {
2005 if (s->pcm->card != substream->pcm->card)
2006 continue;
2007 azx_dev = get_azx_dev(s);
e5463720
JK		 2008 if (start) {
2009 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2010 if (!rstart)
2011 azx_dev->start_wallclk -=
2012 azx_dev->period_wallclk;
850f0e52 2013 azx_stream_start(chip, azx_dev);
e5463720 2014 } else {
850f0e52 2015 azx_stream_stop(chip, azx_dev);
e5463720 2016 }
850f0e52 2017 azx_dev->running = start;
1da177e4
LT		 2018 }
2019 spin_unlock(&chip->reg_lock);
850f0e52 2020 if (start) {
850f0e52
TI		 2021 /* wait until all FIFOs get ready */
2022 for (timeout = 5000; timeout; timeout--) {
2023 nwait = 0;
2024 snd_pcm_group_for_each_entry(s, substream) {
2025 if (s->pcm->card != substream->pcm->card)
2026 continue;
2027 azx_dev = get_azx_dev(s);
2028 if (!(azx_sd_readb(azx_dev, SD_STS) &
2029 SD_STS_FIFO_READY))
2030 nwait++;
2031 }
2032 if (!nwait)
2033 break;
2034 cpu_relax();
2035 }
2036 } else {
2037 /* wait until all RUN bits are cleared */
2038 for (timeout = 5000; timeout; timeout--) {
2039 nwait = 0;
2040 snd_pcm_group_for_each_entry(s, substream) {
2041 if (s->pcm->card != substream->pcm->card)
2042 continue;
2043 azx_dev = get_azx_dev(s);
2044 if (azx_sd_readb(azx_dev, SD_CTL) &
2045 SD_CTL_DMA_START)
2046 nwait++;
2047 }
2048 if (!nwait)
2049 break;
2050 cpu_relax();
2051 }
1da177e4 2052 }
172d3b20
PLB		 2053 spin_lock(&chip->reg_lock);
2054 /* reset SYNC bits */
2055 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2056 azx_writel(chip, OLD_SSYNC,
2057 azx_readl(chip, OLD_SSYNC) & ~sbits);
2058 else
2059 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2060 spin_unlock(&chip->reg_lock);
850f0e52 2061 return 0;
1da177e4
LT		 2062}
2063
0e153474
JC		 2064/* get the current DMA position with correction on VIA chips */
2065static unsigned int azx_via_get_position(struct azx *chip,
2066 struct azx_dev *azx_dev)
2067{
2068 unsigned int link_pos, mini_pos, bound_pos;
2069 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2070 unsigned int fifo_size;
2071
2072 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2073 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2074 /* Playback, no problem using link position */
2075 return link_pos;
2076 }
2077
2078 /* Capture */
2079 /* For new chipset,
2080 * use mod to get the DMA position just like old chipset
2081 */
2082 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2083 mod_dma_pos %= azx_dev->period_bytes;
2084
2085 /* azx_dev->fifo_size can't get FIFO size of in stream.
2086 * Get from base address + offset.
2087 */
2088 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2089
2090 if (azx_dev->insufficient) {
2091 /* Link position never gather than FIFO size */
2092 if (link_pos <= fifo_size)
2093 return 0;
2094
2095 azx_dev->insufficient = 0;
2096 }
2097
2098 if (link_pos <= fifo_size)
2099 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2100 else
2101 mini_pos = link_pos - fifo_size;
2102
2103 /* Find nearest previous boudary */
2104 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2105 mod_link_pos = link_pos % azx_dev->period_bytes;
2106 if (mod_link_pos >= fifo_size)
2107 bound_pos = link_pos - mod_link_pos;
2108 else if (mod_dma_pos >= mod_mini_pos)
2109 bound_pos = mini_pos - mod_mini_pos;
2110 else {
2111 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2112 if (bound_pos >= azx_dev->bufsize)
2113 bound_pos = 0;
2114 }
2115
2116 /* Calculate real DMA position we want */
2117 return bound_pos + mod_dma_pos;
2118}
2119
9ad593f6 2120static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2121 struct azx_dev *azx_dev,
2122 bool with_check)
1da177e4 2123{
1da177e4 2124 unsigned int pos;
4cb36310 2125 int stream = azx_dev->substream->stream;
1da177e4 2126
4cb36310
DH		 2127 switch (chip->position_fix[stream]) {
2128 case POS_FIX_LPIB:
2129 /* read LPIB */
2130 pos = azx_sd_readl(azx_dev, SD_LPIB);
2131 break;
2132 case POS_FIX_VIACOMBO:
0e153474 2133 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2134 break;
2135 default:
2136 /* use the position buffer */
2137 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2138 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2139 if (!pos || pos == (u32)-1) {
2140 printk(KERN_WARNING
2141 "hda-intel: Invalid position buffer, "
2142 "using LPIB read method instead.\n");
2143 chip->position_fix[stream] = POS_FIX_LPIB;
2144 pos = azx_sd_readl(azx_dev, SD_LPIB);
2145 } else
2146 chip->position_fix[stream] = POS_FIX_POSBUF;
2147 }
2148 break;
c74db86b 2149 }
4cb36310 2150
1da177e4
LT		 2151 if (pos >= azx_dev->bufsize)
2152 pos = 0;
90accc58
PLB		 2153
2154 /* calculate runtime delay from LPIB */
2155 if (azx_dev->substream->runtime &&
2156 chip->position_fix[stream] == POS_FIX_POSBUF &&
2157 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2158 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2159 int delay;
2160 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2161 delay = pos - lpib_pos;
2162 else
2163 delay = lpib_pos - pos;
2164 if (delay < 0)
2165 delay += azx_dev->bufsize;
2166 if (delay >= azx_dev->period_bytes) {
1f04661f
TI		 2167 snd_printk(KERN_WARNING SFX
2168 "Unstable LPIB (%d >= %d); "
2169 "disabling LPIB delay counting\n",
2170 delay, azx_dev->period_bytes);
2171 delay = 0;
2172 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58
PLB		 2173 }
2174 azx_dev->substream->runtime->delay =
2175 bytes_to_frames(azx_dev->substream->runtime, delay);
2176 }
9ad593f6
TI		 2177 return pos;
2178}
2179
2180static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2181{
2182 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2183 struct azx *chip = apcm->chip;
2184 struct azx_dev *azx_dev = get_azx_dev(substream);
2185 return bytes_to_frames(substream->runtime,
798cb7e8 2186 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2187}
2188
2189/*
2190 * Check whether the current DMA position is acceptable for updating
2191 * periods. Returns non-zero if it's OK.
2192 *
2193 * Many HD-audio controllers appear pretty inaccurate about
2194 * the update-IRQ timing. The IRQ is issued before actually the
2195 * data is processed. So, we need to process it afterwords in a
2196 * workqueue.
2197 */
2198static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2199{
e5463720 2200 u32 wallclk;
9ad593f6 2201 unsigned int pos;
beaffc39 2202 int stream;
9ad593f6 2203
f48f606d
JK		 2204 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2205 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2206 return -1; /* bogus (too early) interrupt */
fa00e046 2207
beaffc39 2208 stream = azx_dev->substream->stream;
798cb7e8 2209 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2210
d6d8bf54
TI		 2211 if (WARN_ONCE(!azx_dev->period_bytes,
2212 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2213 return -1; /* this shouldn't happen! */
edb39935 2214 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2215 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2216 /* NG - it's below the first next period boundary */
2217 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2218 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2219 return 1; /* OK, it's fine */
2220}
2221
2222/*
2223 * The work for pending PCM period updates.
2224 */
2225static void azx_irq_pending_work(struct work_struct *work)
2226{
2227 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2228 int i, pending, ok;
9ad593f6 2229
a6a950a8
TI		 2230 if (!chip->irq_pending_warned) {
2231 printk(KERN_WARNING
2232 "hda-intel: IRQ timing workaround is activated "
2233 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2234 chip->card->number);
2235 chip->irq_pending_warned = 1;
2236 }
2237
9ad593f6
TI		 2238 for (;;) {
2239 pending = 0;
2240 spin_lock_irq(&chip->reg_lock);
2241 for (i = 0; i < chip->num_streams; i++) {
2242 struct azx_dev *azx_dev = &chip->azx_dev[i];
2243 if (!azx_dev->irq_pending ||
2244 !azx_dev->substream ||
2245 !azx_dev->running)
2246 continue;
e5463720
JK		 2247 ok = azx_position_ok(chip, azx_dev);
2248 if (ok > 0) {
9ad593f6
TI		 2249 azx_dev->irq_pending = 0;
2250 spin_unlock(&chip->reg_lock);
2251 snd_pcm_period_elapsed(azx_dev->substream);
2252 spin_lock(&chip->reg_lock);
e5463720
JK		 2253 } else if (ok < 0) {
2254 pending = 0; /* too early */
9ad593f6
TI		 2255 } else
2256 pending++;
2257 }
2258 spin_unlock_irq(&chip->reg_lock);
2259 if (!pending)
2260 return;
08af495f 2261 msleep(1);
9ad593f6
TI		 2262 }
2263}
2264
2265/* clear irq_pending flags and assure no on-going workq */
2266static void azx_clear_irq_pending(struct azx *chip)
2267{
2268 int i;
2269
2270 spin_lock_irq(&chip->reg_lock);
2271 for (i = 0; i < chip->num_streams; i++)
2272 chip->azx_dev[i].irq_pending = 0;
2273 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2274}
2275
27fe48d9
TI		 2276#ifdef CONFIG_X86
2277static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2278 struct vm_area_struct *area)
2279{
2280 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2281 struct azx *chip = apcm->chip;
2282 if (!azx_snoop(chip))
2283 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2284 return snd_pcm_lib_default_mmap(substream, area);
2285}
2286#else
2287#define azx_pcm_mmap NULL
2288#endif
2289
a98f90fd 2290static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2291 .open = azx_pcm_open,
2292 .close = azx_pcm_close,
2293 .ioctl = snd_pcm_lib_ioctl,
2294 .hw_params = azx_pcm_hw_params,
2295 .hw_free = azx_pcm_hw_free,
2296 .prepare = azx_pcm_prepare,
2297 .trigger = azx_pcm_trigger,
2298 .pointer = azx_pcm_pointer,
27fe48d9 2299 .mmap = azx_pcm_mmap,
4ce107b9 2300 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2301};
2302
a98f90fd 2303static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2304{
176d5335
TI		 2305 struct azx_pcm *apcm = pcm->private_data;
2306 if (apcm) {
01b65bfb 2307 list_del(&apcm->list);
176d5335
TI		 2308 kfree(apcm);
2309 }
1da177e4
LT		 2310}
2311
acfa634f
TI		 2312#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2313
176d5335 2314static int
33fa35ed
TI		 2315azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2316 struct hda_pcm *cpcm)
1da177e4 2317{
33fa35ed 2318 struct azx *chip = bus->private_data;
a98f90fd 2319 struct snd_pcm *pcm;
1da177e4 2320 struct azx_pcm *apcm;
176d5335 2321 int pcm_dev = cpcm->device;
acfa634f 2322 unsigned int size;
176d5335 2323 int s, err;
1da177e4 2324
01b65bfb
TI		 2325 list_for_each_entry(apcm, &chip->pcm_list, list) {
2326 if (apcm->pcm->device == pcm_dev) {
2327 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2328 return -EBUSY;
2329 }
176d5335
TI		 2330 }
2331 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2332 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2333 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2334 &pcm);
2335 if (err < 0)
2336 return err;
18cb7109 2337 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2338 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2339 if (apcm == NULL)
2340 return -ENOMEM;
2341 apcm->chip = chip;
01b65bfb 2342 apcm->pcm = pcm;
1da177e4 2343 apcm->codec = codec;
1da177e4
LT		 2344 pcm->private_data = apcm;
2345 pcm->private_free = azx_pcm_free;
176d5335
TI		 2346 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2347 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2348 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2349 cpcm->pcm = pcm;
2350 for (s = 0; s < 2; s++) {
2351 apcm->hinfo[s] = &cpcm->stream[s];
2352 if (cpcm->stream[s].substreams)
2353 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2354 }
2355 /* buffer pre-allocation */
acfa634f
TI		 2356 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2357 if (size > MAX_PREALLOC_SIZE)
2358 size = MAX_PREALLOC_SIZE;
4ce107b9 2359 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2360 snd_dma_pci_data(chip->pci),
acfa634f 2361 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2362 return 0;
2363}
2364
2365/*
2366 * mixer creation - all stuff is implemented in hda module
2367 */
a98f90fd 2368static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2369{
2370 return snd_hda_build_controls(chip->bus);
2371}
2372
2373
2374/*
2375 * initialize SD streams
2376 */
a98f90fd 2377static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2378{
2379 int i;
2380
2381 /* initialize each stream (aka device)
d01ce99f
TI		 2382 * assign the starting bdl address to each stream (device)
2383 * and initialize
1da177e4 2384 */
07e4ca50 2385 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2386 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2387 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2388 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2389 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2390 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2391 azx_dev->sd_int_sta_mask = 1 << i;
2392 /* stream tag: must be non-zero and unique */
2393 azx_dev->index = i;
2394 azx_dev->stream_tag = i + 1;
2395 }
2396
2397 return 0;
2398}
2399
68e7fffc
TI		 2400static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2401{
437a5a46
TI		 2402 if (request_irq(chip->pci->irq, azx_interrupt,
2403 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2404 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2405 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2406 "disabling device\n", chip->pci->irq);
2407 if (do_disconnect)
2408 snd_card_disconnect(chip->card);
2409 return -1;
2410 }
2411 chip->irq = chip->pci->irq;
69e13418 2412 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2413 return 0;
2414}
2415
1da177e4 2416
cb53c626
TI		 2417static void azx_stop_chip(struct azx *chip)
2418{
95e99fda 2419 if (!chip->initialized)
cb53c626
TI		 2420 return;
2421
2422 /* disable interrupts */
2423 azx_int_disable(chip);
2424 azx_int_clear(chip);
2425
2426 /* disable CORB/RIRB */
2427 azx_free_cmd_io(chip);
2428
2429 /* disable position buffer */
2430 azx_writel(chip, DPLBASE, 0);
2431 azx_writel(chip, DPUBASE, 0);
2432
2433 chip->initialized = 0;
2434}
2435
83012a7c 2436#ifdef CONFIG_PM
cb53c626 2437/* power-up/down the controller */
68467f51 2438static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2439{
33fa35ed 2440 struct azx *chip = bus->private_data;
cb53c626 2441
2ea3c6a2
TI		 2442 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2443 return;
2444
68467f51 2445 if (power_up)
b8dfc462
ML		 2446 pm_runtime_get_sync(&chip->pci->dev);
2447 else
2448 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2449}
65fcd41d
TI		 2450
2451static DEFINE_MUTEX(card_list_lock);
2452static LIST_HEAD(card_list);
2453
2454static void azx_add_card_list(struct azx *chip)
2455{
2456 mutex_lock(&card_list_lock);
2457 list_add(&chip->list, &card_list);
2458 mutex_unlock(&card_list_lock);
2459}
2460
2461static void azx_del_card_list(struct azx *chip)
2462{
2463 mutex_lock(&card_list_lock);
2464 list_del_init(&chip->list);
2465 mutex_unlock(&card_list_lock);
2466}
2467
2468/* trigger power-save check at writing parameter */
2469static int param_set_xint(const char *val, const struct kernel_param *kp)
2470{
2471 struct azx *chip;
2472 struct hda_codec *c;
2473 int prev = power_save;
2474 int ret = param_set_int(val, kp);
2475
2476 if (ret || prev == power_save)
2477 return ret;
2478
2479 mutex_lock(&card_list_lock);
2480 list_for_each_entry(chip, &card_list, list) {
2481 if (!chip->bus || chip->disabled)
2482 continue;
2483 list_for_each_entry(c, &chip->bus->codec_list, list)
2484 snd_hda_power_sync(c);
2485 }
2486 mutex_unlock(&card_list_lock);
2487 return 0;
2488}
2489#else
2490#define azx_add_card_list(chip) /* NOP */
2491#define azx_del_card_list(chip) /* NOP */
83012a7c 2492#endif /* CONFIG_PM */
5c0b9bec 2493
7ccbde57 2494#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2495/*
2496 * power management
2497 */
68cb2b55 2498static int azx_suspend(struct device *dev)
1da177e4 2499{
68cb2b55
TI		 2500 struct pci_dev *pci = to_pci_dev(dev);
2501 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2502 struct azx *chip = card->private_data;
01b65bfb 2503 struct azx_pcm *p;
1da177e4 2504
421a1252 2505 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2506 azx_clear_irq_pending(chip);
01b65bfb
TI		 2507 list_for_each_entry(p, &chip->pcm_list, list)
2508 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2509 if (chip->initialized)
8dd78330 2510 snd_hda_suspend(chip->bus);
cb53c626 2511 azx_stop_chip(chip);
30b35399 2512 if (chip->irq >= 0) {
43001c95 2513 free_irq(chip->irq, chip);
30b35399
TI		 2514 chip->irq = -1;
2515 }
68e7fffc 2516 if (chip->msi)
43001c95 2517 pci_disable_msi(chip->pci);
421a1252
TI		 2518 pci_disable_device(pci);
2519 pci_save_state(pci);
68cb2b55 2520 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2521 return 0;
2522}
2523
68cb2b55 2524static int azx_resume(struct device *dev)
1da177e4 2525{
68cb2b55
TI		 2526 struct pci_dev *pci = to_pci_dev(dev);
2527 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2528 struct azx *chip = card->private_data;
1da177e4 2529
d14a7e0b
TI		 2530 pci_set_power_state(pci, PCI_D0);
2531 pci_restore_state(pci);
30b35399
TI		 2532 if (pci_enable_device(pci) < 0) {
2533 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2534 "disabling device\n");
2535 snd_card_disconnect(card);
2536 return -EIO;
2537 }
2538 pci_set_master(pci);
68e7fffc
TI		 2539 if (chip->msi)
2540 if (pci_enable_msi(pci) < 0)
2541 chip->msi = 0;
2542 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2543 return -EIO;
cb53c626 2544 azx_init_pci(chip);
d804ad92 2545
7f30830b 2546 azx_init_chip(chip, 1);
d804ad92 2547
1da177e4 2548 snd_hda_resume(chip->bus);
421a1252 2549 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2550 return 0;
2551}
b8dfc462
ML		 2552#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2553
2554#ifdef CONFIG_PM_RUNTIME
2555static int azx_runtime_suspend(struct device *dev)
2556{
2557 struct snd_card *card = dev_get_drvdata(dev);
2558 struct azx *chip = card->private_data;
2559
2ea3c6a2
TI		 2560 if (!power_save_controller ||
2561 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
b8dfc462
ML		 2562 return -EAGAIN;
2563
2564 azx_stop_chip(chip);
2565 azx_clear_irq_pending(chip);
2566 return 0;
2567}
2568
2569static int azx_runtime_resume(struct device *dev)
2570{
2571 struct snd_card *card = dev_get_drvdata(dev);
2572 struct azx *chip = card->private_data;
2573
2574 azx_init_pci(chip);
2575 azx_init_chip(chip, 1);
2576 return 0;
2577}
2578#endif /* CONFIG_PM_RUNTIME */
2579
2580#ifdef CONFIG_PM
2581static const struct dev_pm_ops azx_pm = {
2582 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2583 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2584};
2585
68cb2b55
TI		 2586#define AZX_PM_OPS &azx_pm
2587#else
68cb2b55 2588#define AZX_PM_OPS NULL
b8dfc462 2589#endif /* CONFIG_PM */
1da177e4
LT		 2590
2591
0cbf0098
TI		 2592/*
2593 * reboot notifier for hang-up problem at power-down
2594 */
2595static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2596{
2597 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2598 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2599 azx_stop_chip(chip);
2600 return NOTIFY_OK;
2601}
2602
2603static void azx_notifier_register(struct azx *chip)
2604{
2605 chip->reboot_notifier.notifier_call = azx_halt;
2606 register_reboot_notifier(&chip->reboot_notifier);
2607}
2608
2609static void azx_notifier_unregister(struct azx *chip)
2610{
2611 if (chip->reboot_notifier.notifier_call)
2612 unregister_reboot_notifier(&chip->reboot_notifier);
2613}
2614
a82d51ed
TI		 2615static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2616static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2617
8393ec4a 2618#ifdef SUPPORT_VGA_SWITCHEROO
a82d51ed
TI		 2619static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2620
a82d51ed
TI		 2621static void azx_vs_set_state(struct pci_dev *pci,
2622 enum vga_switcheroo_state state)
2623{
2624 struct snd_card *card = pci_get_drvdata(pci);
2625 struct azx *chip = card->private_data;
2626 bool disabled;
2627
2628 if (chip->init_failed)
2629 return;
2630
2631 disabled = (state == VGA_SWITCHEROO_OFF);
2632 if (chip->disabled == disabled)
2633 return;
2634
2635 if (!chip->bus) {
2636 chip->disabled = disabled;
2637 if (!disabled) {
2638 snd_printk(KERN_INFO SFX
2639 "%s: Start delayed initialization\n",
2640 pci_name(chip->pci));
2641 if (azx_first_init(chip) < 0 ||
2642 azx_probe_continue(chip) < 0) {
2643 snd_printk(KERN_ERR SFX
2644 "%s: initialization error\n",
2645 pci_name(chip->pci));
2646 chip->init_failed = true;
2647 }
2648 }
2649 } else {
2650 snd_printk(KERN_INFO SFX
2651 "%s %s via VGA-switcheroo\n",
2652 disabled ? "Disabling" : "Enabling",
2653 pci_name(chip->pci));
2654 if (disabled) {
68cb2b55 2655 azx_suspend(&pci->dev);
a82d51ed 2656 chip->disabled = true;
128960a9
TI		 2657 if (snd_hda_lock_devices(chip->bus))
2658 snd_printk(KERN_WARNING SFX
2659 "Cannot lock devices!\n");
a82d51ed
TI		 2660 } else {
2661 snd_hda_unlock_devices(chip->bus);
2662 chip->disabled = false;
68cb2b55 2663 azx_resume(&pci->dev);
a82d51ed
TI		 2664 }
2665 }
2666}
2667
2668static bool azx_vs_can_switch(struct pci_dev *pci)
2669{
2670 struct snd_card *card = pci_get_drvdata(pci);
2671 struct azx *chip = card->private_data;
2672
2673 if (chip->init_failed)
2674 return false;
2675 if (chip->disabled || !chip->bus)
2676 return true;
2677 if (snd_hda_lock_devices(chip->bus))
2678 return false;
2679 snd_hda_unlock_devices(chip->bus);
2680 return true;
2681}
2682
2683static void __devinit init_vga_switcheroo(struct azx *chip)
2684{
2685 struct pci_dev *p = get_bound_vga(chip->pci);
2686 if (p) {
2687 snd_printk(KERN_INFO SFX
2688 "%s: Handle VGA-switcheroo audio client\n",
2689 pci_name(chip->pci));
2690 chip->use_vga_switcheroo = 1;
2691 pci_dev_put(p);
2692 }
2693}
2694
2695static const struct vga_switcheroo_client_ops azx_vs_ops = {
2696 .set_gpu_state = azx_vs_set_state,
2697 .can_switch = azx_vs_can_switch,
2698};
2699
2700static int __devinit register_vga_switcheroo(struct azx *chip)
2701{
128960a9
TI		 2702 int err;
2703
a82d51ed
TI		 2704 if (!chip->use_vga_switcheroo)
2705 return 0;
2706 /* FIXME: currently only handling DIS controller
2707 * is there any machine with two switchable HDMI audio controllers?
2708 */
128960a9 2709 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 2710 VGA_SWITCHEROO_DIS,
2711 chip->bus != NULL);
128960a9
TI		 2712 if (err < 0)
2713 return err;
2714 chip->vga_switcheroo_registered = 1;
2715 return 0;
a82d51ed
TI		 2716}
2717#else
2718#define init_vga_switcheroo(chip) /* NOP */
2719#define register_vga_switcheroo(chip) 0
8393ec4a 2720#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2721#endif /* SUPPORT_VGA_SWITCHER */
2722
1da177e4
LT		 2723/*
2724 * destructor
2725 */
a98f90fd 2726static int azx_free(struct azx *chip)
1da177e4 2727{
4ce107b9
TI		 2728 int i;
2729
65fcd41d
TI		 2730 azx_del_card_list(chip);
2731
0cbf0098
TI		 2732 azx_notifier_unregister(chip);
2733
a82d51ed
TI		 2734 if (use_vga_switcheroo(chip)) {
2735 if (chip->disabled && chip->bus)
2736 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 2737 if (chip->vga_switcheroo_registered)
2738 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 2739 }
2740
ce43fbae 2741 if (chip->initialized) {
9ad593f6 2742 azx_clear_irq_pending(chip);
07e4ca50 2743 for (i = 0; i < chip->num_streams; i++)
1da177e4 2744 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2745 azx_stop_chip(chip);
1da177e4
LT		 2746 }
2747
f000fd80 2748 if (chip->irq >= 0)
1da177e4 2749 free_irq(chip->irq, (void*)chip);
68e7fffc 2750 if (chip->msi)
30b35399 2751 pci_disable_msi(chip->pci);
f079c25a
TI		 2752 if (chip->remap_addr)
2753 iounmap(chip->remap_addr);
1da177e4 2754
4ce107b9
TI		 2755 if (chip->azx_dev) {
2756 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2757 if (chip->azx_dev[i].bdl.area) {
2758 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2759 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2760 }
4ce107b9 2761 }
27fe48d9
TI		 2762 if (chip->rb.area) {
2763 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2764 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2765 }
2766 if (chip->posbuf.area) {
2767 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2768 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2769 }
a82d51ed
TI		 2770 if (chip->region_requested)
2771 pci_release_regions(chip->pci);
1da177e4 2772 pci_disable_device(chip->pci);
07e4ca50 2773 kfree(chip->azx_dev);
4918cdab
TI		 2774#ifdef CONFIG_SND_HDA_PATCH_LOADER
2775 if (chip->fw)
2776 release_firmware(chip->fw);
2777#endif
1da177e4
LT		 2778 kfree(chip);
2779
2780 return 0;
2781}
2782
a98f90fd 2783static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2784{
2785 return azx_free(device->device_data);
2786}
2787
8393ec4a 2788#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2789/*
2790 * Check of disabled HDMI controller by vga-switcheroo
2791 */
2792static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2793{
2794 struct pci_dev *p;
2795
2796 /* check only discrete GPU */
2797 switch (pci->vendor) {
2798 case PCI_VENDOR_ID_ATI:
2799 case PCI_VENDOR_ID_AMD:
2800 case PCI_VENDOR_ID_NVIDIA:
2801 if (pci->devfn == 1) {
2802 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2803 pci->bus->number, 0);
2804 if (p) {
2805 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2806 return p;
2807 pci_dev_put(p);
2808 }
2809 }
2810 break;
2811 }
2812 return NULL;
2813}
2814
2815static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2816{
2817 bool vga_inactive = false;
2818 struct pci_dev *p = get_bound_vga(pci);
2819
2820 if (p) {
12b78a7f 2821 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2822 vga_inactive = true;
2823 pci_dev_put(p);
2824 }
2825 return vga_inactive;
2826}
8393ec4a 2827#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2828
3372a153
TI		 2829/*
2830 * white/black-listing for position_fix
2831 */
623ec047 2832static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2833 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2834 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2835 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2836 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2837 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2838 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2839 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2840 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2841 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2842 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2843 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2844 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2845 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2846 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2847 {}
2848};
2849
2850static int __devinit check_position_fix(struct azx *chip, int fix)
2851{
2852 const struct snd_pci_quirk *q;
2853
c673ba1c 2854 switch (fix) {
1dac6695 2855 case POS_FIX_AUTO:
c673ba1c
TI		 2856 case POS_FIX_LPIB:
2857 case POS_FIX_POSBUF:
4cb36310 2858 case POS_FIX_VIACOMBO:
a6f2fd55 2859 case POS_FIX_COMBO:
c673ba1c
TI		 2860 return fix;
2861 }
2862
c673ba1c
TI		 2863 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2864 if (q) {
2865 printk(KERN_INFO
2866 "hda_intel: position_fix set to %d "
2867 "for device %04x:%04x\n",
2868 q->value, q->subvendor, q->subdevice);
2869 return q->value;
3372a153 2870 }
bdd9ef24
DH		 2871
2872 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2873 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2874 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2875 return POS_FIX_VIACOMBO;
9477c58e
TI		 2876 }
2877 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2878 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2879 return POS_FIX_LPIB;
bdd9ef24 2880 }
c673ba1c 2881 return POS_FIX_AUTO;
3372a153
TI		 2882}
2883
669ba27a
TI		 2884/*
2885 * black-lists for probe_mask
2886 */
2887static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2888 /* Thinkpad often breaks the controller communication when accessing
2889 * to the non-working (or non-existing) modem codec slot.
2890 */
2891 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2892 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2893 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2894 /* broken BIOS */
2895 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2896 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2897 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2898 /* forced codec slots */
93574844 2899 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2900 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 2901 /* WinFast VP200 H (Teradici) user reported broken communication */
2902 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 2903 {}
2904};
2905
f1eaaeec
TI		 2906#define AZX_FORCE_CODEC_MASK 0x100
2907
5aba4f8e 2908static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2909{
2910 const struct snd_pci_quirk *q;
2911
f1eaaeec
TI		 2912 chip->codec_probe_mask = probe_mask[dev];
2913 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2914 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2915 if (q) {
2916 printk(KERN_INFO
2917 "hda_intel: probe_mask set to 0x%x "
2918 "for device %04x:%04x\n",
2919 q->value, q->subvendor, q->subdevice);
f1eaaeec 2920 chip->codec_probe_mask = q->value;
669ba27a
TI		 2921 }
2922 }
f1eaaeec
TI		 2923
2924 /* check forced option */
2925 if (chip->codec_probe_mask != -1 &&
2926 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2927 chip->codec_mask = chip->codec_probe_mask & 0xff;
2928 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2929 chip->codec_mask);
2930 }
669ba27a
TI		 2931}
2932
4d8e22e0 2933/*
71623855 2934 * white/black-list for enable_msi
4d8e22e0 2935 */
71623855 2936static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2937 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2938 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2939 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2940 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2941 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2942 {}
2943};
2944
2945static void __devinit check_msi(struct azx *chip)
2946{
2947 const struct snd_pci_quirk *q;
2948
71623855
TI		 2949 if (enable_msi >= 0) {
2950 chip->msi = !!enable_msi;
4d8e22e0 2951 return;
71623855
TI		 2952 }
2953 chip->msi = 1; /* enable MSI as default */
2954 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2955 if (q) {
2956 printk(KERN_INFO
2957 "hda_intel: msi for device %04x:%04x set to %d\n",
2958 q->subvendor, q->subdevice, q->value);
2959 chip->msi = q->value;
80c43ed7
TI		 2960 return;
2961 }
2962
2963 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2964 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2965 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2966 chip->msi = 0;
4d8e22e0
TI		 2967 }
2968}
2969
a1585d76
TI		 2970/* check the snoop mode availability */
2971static void __devinit azx_check_snoop_available(struct azx *chip)
2972{
2973 bool snoop = chip->snoop;
2974
2975 switch (chip->driver_type) {
2976 case AZX_DRIVER_VIA:
2977 /* force to non-snoop mode for a new VIA controller
2978 * when BIOS is set
2979 */
2980 if (snoop) {
2981 u8 val;
2982 pci_read_config_byte(chip->pci, 0x42, &val);
2983 if (!(val & 0x80) && chip->pci->revision == 0x30)
2984 snoop = false;
2985 }
2986 break;
2987 case AZX_DRIVER_ATIHDMI_NS:
2988 /* new ATI HDMI requires non-snoop */
2989 snoop = false;
2990 break;
2991 }
2992
2993 if (snoop != chip->snoop) {
2994 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2995 snoop ? "snoop" : "non-snoop");
2996 chip->snoop = snoop;
2997 }
2998}
669ba27a 2999
1da177e4
LT		 3000/*
3001 * constructor
3002 */
a98f90fd 3003static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 3004 int dev, unsigned int driver_caps,
a98f90fd 3005 struct azx **rchip)
1da177e4 3006{
a98f90fd 3007 static struct snd_device_ops ops = {
1da177e4
LT		 3008 .dev_free = azx_dev_free,
3009 };
a82d51ed
TI		 3010 struct azx *chip;
3011 int err;
1da177e4
LT		 3012
3013 *rchip = NULL;
bcd72003 3014
927fc866
PM		 3015 err = pci_enable_device(pci);
3016 if (err < 0)
1da177e4
LT		 3017 return err;
3018
e560d8d8 3019 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3020 if (!chip) {
1da177e4
LT		 3021 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3022 pci_disable_device(pci);
3023 return -ENOMEM;
3024 }
3025
3026 spin_lock_init(&chip->reg_lock);
62932df8 3027 mutex_init(&chip->open_mutex);
1da177e4
LT		 3028 chip->card = card;
3029 chip->pci = pci;
3030 chip->irq = -1;
9477c58e
TI		 3031 chip->driver_caps = driver_caps;
3032 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3033 check_msi(chip);
555e219f 3034 chip->dev_index = dev;
9ad593f6 3035 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3036 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3037 INIT_LIST_HEAD(&chip->list);
a82d51ed 3038 init_vga_switcheroo(chip);
1da177e4 3039
beaffc39
SG		 3040 chip->position_fix[0] = chip->position_fix[1] =
3041 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3042 /* combo mode uses LPIB for playback */
3043 if (chip->position_fix[0] == POS_FIX_COMBO) {
3044 chip->position_fix[0] = POS_FIX_LPIB;
3045 chip->position_fix[1] = POS_FIX_AUTO;
3046 }
3047
5aba4f8e 3048 check_probe_mask(chip, dev);
3372a153 3049
27346166 3050 chip->single_cmd = single_cmd;
27fe48d9 3051 chip->snoop = hda_snoop;
a1585d76 3052 azx_check_snoop_available(chip);
c74db86b 3053
5c0d7bc1
TI		 3054 if (bdl_pos_adj[dev] < 0) {
3055 switch (chip->driver_type) {
0c6341ac 3056 case AZX_DRIVER_ICH:
32679f95 3057 case AZX_DRIVER_PCH:
0c6341ac 3058 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3059 break;
3060 default:
0c6341ac 3061 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3062 break;
3063 }
3064 }
3065
a82d51ed
TI		 3066 if (check_hdmi_disabled(pci)) {
3067 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3068 pci_name(pci));
3069 if (use_vga_switcheroo(chip)) {
3070 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3071 chip->disabled = true;
3072 goto ok;
3073 }
3074 kfree(chip);
3075 pci_disable_device(pci);
3076 return -ENXIO;
3077 }
3078
3079 err = azx_first_init(chip);
3080 if (err < 0) {
3081 azx_free(chip);
3082 return err;
3083 }
3084
3085 ok:
a82d51ed
TI		 3086 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3087 if (err < 0) {
3088 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3089 azx_free(chip);
3090 return err;
3091 }
3092
3093 *rchip = chip;
3094 return 0;
3095}
3096
3097static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3098{
3099 int dev = chip->dev_index;
3100 struct pci_dev *pci = chip->pci;
3101 struct snd_card *card = chip->card;
3102 int i, err;
3103 unsigned short gcap;
3104
07e4ca50
TI		 3105#if BITS_PER_LONG != 64
3106 /* Fix up base address on ULI M5461 */
3107 if (chip->driver_type == AZX_DRIVER_ULI) {
3108 u16 tmp3;
3109 pci_read_config_word(pci, 0x40, &tmp3);
3110 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3111 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3112 }
3113#endif
3114
927fc866 3115 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3116 if (err < 0)
1da177e4 3117 return err;
a82d51ed 3118 chip->region_requested = 1;
1da177e4 3119
927fc866 3120 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3121 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 3122 if (chip->remap_addr == NULL) {
3123 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 3124 return -ENXIO;
1da177e4
LT		 3125 }
3126
68e7fffc
TI		 3127 if (chip->msi)
3128 if (pci_enable_msi(pci) < 0)
3129 chip->msi = 0;
7376d013 3130
a82d51ed
TI		 3131 if (azx_acquire_irq(chip, 0) < 0)
3132 return -EBUSY;
1da177e4
LT		 3133
3134 pci_set_master(pci);
3135 synchronize_irq(chip->irq);
3136
bcd72003 3137 gcap = azx_readw(chip, GCAP);
4abc1cc2 3138 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3139
dc4c2e6b 3140 /* disable SB600 64bit support for safety */
9477c58e 3141 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3142 struct pci_dev *p_smbus;
3143 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3144 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3145 NULL);
3146 if (p_smbus) {
3147 if (p_smbus->revision < 0x30)
3148 gcap &= ~ICH6_GCAP_64OK;
3149 pci_dev_put(p_smbus);
3150 }
3151 }
09240cf4 3152
9477c58e
TI		 3153 /* disable 64bit DMA address on some devices */
3154 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3155 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3156 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3157 }
396087ea 3158
2ae66c26 3159 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3160 if (align_buffer_size >= 0)
3161 chip->align_buffer_size = !!align_buffer_size;
3162 else {
3163 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3164 chip->align_buffer_size = 0;
3165 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3166 chip->align_buffer_size = 1;
3167 else
3168 chip->align_buffer_size = 1;
3169 }
2ae66c26 3170
cf7aaca8 3171 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3172 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3173 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3174 else {
e930438c
YH		 3175 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3176 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3177 }
cf7aaca8 3178
8b6ed8e7
TI		 3179 /* read number of streams from GCAP register instead of using
3180 * hardcoded value
3181 */
3182 chip->capture_streams = (gcap >> 8) & 0x0f;
3183 chip->playback_streams = (gcap >> 12) & 0x0f;
3184 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3185 /* gcap didn't give any info, switching to old method */
3186
3187 switch (chip->driver_type) {
3188 case AZX_DRIVER_ULI:
3189 chip->playback_streams = ULI_NUM_PLAYBACK;
3190 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3191 break;
3192 case AZX_DRIVER_ATIHDMI:
1815b34a 3193 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3194 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3195 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3196 break;
c4da29ca 3197 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3198 default:
3199 chip->playback_streams = ICH6_NUM_PLAYBACK;
3200 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3201 break;
3202 }
07e4ca50 3203 }
8b6ed8e7
TI		 3204 chip->capture_index_offset = 0;
3205 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3206 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3207 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3208 GFP_KERNEL);
927fc866 3209 if (!chip->azx_dev) {
4abc1cc2 3210 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3211 return -ENOMEM;
07e4ca50
TI		 3212 }
3213
4ce107b9
TI		 3214 for (i = 0; i < chip->num_streams; i++) {
3215 /* allocate memory for the BDL for each stream */
3216 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3217 snd_dma_pci_data(chip->pci),
3218 BDL_SIZE, &chip->azx_dev[i].bdl);
3219 if (err < 0) {
3220 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3221 return -ENOMEM;
4ce107b9 3222 }
27fe48d9 3223 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3224 }
0be3b5d3 3225 /* allocate memory for the position buffer */
d01ce99f
TI		 3226 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3227 snd_dma_pci_data(chip->pci),
3228 chip->num_streams * 8, &chip->posbuf);
3229 if (err < 0) {
0be3b5d3 3230 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3231 return -ENOMEM;
1da177e4 3232 }
27fe48d9 3233 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3234 /* allocate CORB/RIRB */
81740861
TI		 3235 err = azx_alloc_cmd_io(chip);
3236 if (err < 0)
a82d51ed 3237 return err;
1da177e4
LT		 3238
3239 /* initialize streams */
3240 azx_init_stream(chip);
3241
3242 /* initialize chip */
cb53c626 3243 azx_init_pci(chip);
10e77dda 3244 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3245
3246 /* codec detection */
927fc866 3247 if (!chip->codec_mask) {
1da177e4 3248 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3249 return -ENODEV;
1da177e4
LT		 3250 }
3251
07e4ca50 3252 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3253 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3254 sizeof(card->shortname));
3255 snprintf(card->longname, sizeof(card->longname),
3256 "%s at 0x%lx irq %i",
3257 card->shortname, chip->addr, chip->irq);
07e4ca50 3258
1da177e4 3259 return 0;
1da177e4
LT		 3260}
3261
cb53c626
TI		 3262static void power_down_all_codecs(struct azx *chip)
3263{
83012a7c 3264#ifdef CONFIG_PM
cb53c626
TI		 3265 /* The codecs were powered up in snd_hda_codec_new().
3266 * Now all initialization done, so turn them down if possible
3267 */
3268 struct hda_codec *codec;
3269 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3270 snd_hda_power_down(codec);
3271 }
3272#endif
3273}
3274
97c6a3d1 3275#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3276/* callback from request_firmware_nowait() */
3277static void azx_firmware_cb(const struct firmware *fw, void *context)
3278{
3279 struct snd_card *card = context;
3280 struct azx *chip = card->private_data;
3281 struct pci_dev *pci = chip->pci;
3282
3283 if (!fw) {
3284 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3285 goto error;
3286 }
3287
3288 chip->fw = fw;
3289 if (!chip->disabled) {
3290 /* continue probing */
3291 if (azx_probe_continue(chip))
3292 goto error;
3293 }
3294 return; /* OK */
3295
3296 error:
3297 snd_card_free(card);
3298 pci_set_drvdata(pci, NULL);
3299}
97c6a3d1 3300#endif
5cb543db 3301
d01ce99f
TI		 3302static int __devinit azx_probe(struct pci_dev *pci,
3303 const struct pci_device_id *pci_id)
1da177e4 3304{
5aba4f8e 3305 static int dev;
a98f90fd
TI		 3306 struct snd_card *card;
3307 struct azx *chip;
5cb543db 3308 bool probe_now;
927fc866 3309 int err;
1da177e4 3310
5aba4f8e
TI		 3311 if (dev >= SNDRV_CARDS)
3312 return -ENODEV;
3313 if (!enable[dev]) {
3314 dev++;
3315 return -ENOENT;
3316 }
3317
e58de7ba
TI		 3318 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3319 if (err < 0) {
1da177e4 3320 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3321 return err;
1da177e4
LT		 3322 }
3323
4ea6fbc8
TI		 3324 snd_card_set_dev(card, &pci->dev);
3325
5aba4f8e 3326 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3327 if (err < 0)
3328 goto out_free;
421a1252 3329 card->private_data = chip;
5cb543db 3330 probe_now = !chip->disabled;
1da177e4 3331
4918cdab
TI		 3332#ifdef CONFIG_SND_HDA_PATCH_LOADER
3333 if (patch[dev] && *patch[dev]) {
3334 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3335 patch[dev]);
5cb543db
TI		 3336 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3337 &pci->dev, GFP_KERNEL, card,
3338 azx_firmware_cb);
4918cdab
TI		 3339 if (err < 0)
3340 goto out_free;
5cb543db 3341 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3342 }
3343#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3344
5cb543db 3345 if (probe_now) {
a82d51ed
TI		 3346 err = azx_probe_continue(chip);
3347 if (err < 0)
3348 goto out_free;
3349 }
3350
3351 pci_set_drvdata(pci, card);
3352
b8dfc462
ML		 3353 if (pci_dev_run_wake(pci))
3354 pm_runtime_put_noidle(&pci->dev);
3355
128960a9
TI		 3356 err = register_vga_switcheroo(chip);
3357 if (err < 0) {
3358 snd_printk(KERN_ERR SFX
3359 "Error registering VGA-switcheroo client\n");
3360 goto out_free;
3361 }
3362
a82d51ed
TI		 3363 dev++;
3364 return 0;
3365
3366out_free:
3367 snd_card_free(card);
3368 return err;
3369}
3370
3371static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3372{
3373 int dev = chip->dev_index;
3374 int err;
3375
2dca0bba
JK		 3376#ifdef CONFIG_SND_HDA_INPUT_BEEP
3377 chip->beep_mode = beep_mode[dev];
3378#endif
3379
1da177e4 3380 /* create codec instances */
a1e21c90 3381 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3382 if (err < 0)
3383 goto out_free;
4ea6fbc8 3384#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3385 if (chip->fw) {
3386 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3387 chip->fw->data);
4ea6fbc8
TI		 3388 if (err < 0)
3389 goto out_free;
4918cdab
TI		 3390 release_firmware(chip->fw); /* no longer needed */
3391 chip->fw = NULL;
4ea6fbc8
TI		 3392 }
3393#endif
10e77dda 3394 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3395 err = azx_codec_configure(chip);
3396 if (err < 0)
3397 goto out_free;
3398 }
1da177e4
LT		 3399
3400 /* create PCM streams */
176d5335 3401 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3402 if (err < 0)
3403 goto out_free;
1da177e4
LT		 3404
3405 /* create mixer controls */
d01ce99f 3406 err = azx_mixer_create(chip);
41dda0fd
WF		 3407 if (err < 0)
3408 goto out_free;
1da177e4 3409
a82d51ed 3410 err = snd_card_register(chip->card);
41dda0fd
WF		 3411 if (err < 0)
3412 goto out_free;
1da177e4 3413
cb53c626
TI		 3414 chip->running = 1;
3415 power_down_all_codecs(chip);
0cbf0098 3416 azx_notifier_register(chip);
65fcd41d 3417 azx_add_card_list(chip);
1da177e4 3418
9121947d
TI		 3419 return 0;
3420
41dda0fd 3421out_free:
a82d51ed 3422 chip->init_failed = 1;
41dda0fd 3423 return err;
1da177e4
LT		 3424}
3425
3426static void __devexit azx_remove(struct pci_dev *pci)
3427{
9121947d 3428 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3429
3430 if (pci_dev_run_wake(pci))
3431 pm_runtime_get_noresume(&pci->dev);
3432
9121947d
TI		 3433 if (card)
3434 snd_card_free(card);
1da177e4
LT		 3435 pci_set_drvdata(pci, NULL);
3436}
3437
3438/* PCI IDs */
cebe41d4 3439static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3440 /* CPT */
9477c58e 3441 { PCI_DEVICE(0x8086, 0x1c20),
2ea3c6a2 3442 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
cea310e8 3443 /* PBG */
9477c58e 3444 { PCI_DEVICE(0x8086, 0x1d20),
2ea3c6a2 3445 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
d2edeb7c 3446 /* Panther Point */
9477c58e 3447 { PCI_DEVICE(0x8086, 0x1e20),
2ea3c6a2 3448 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 3449 /* Lynx Point */
3450 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3451 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3452 /* Lynx Point-LP */
3453 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3454 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3455 /* Lynx Point-LP */
3456 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3457 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8
WX		 3458 /* Haswell */
3459 { PCI_DEVICE(0x8086, 0x0c0c),
2ea3c6a2 3460 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
d279fae8 3461 { PCI_DEVICE(0x8086, 0x0d0c),
2ea3c6a2 3462 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
99df18b3
PLB		 3463 /* 5 Series/3400 */
3464 { PCI_DEVICE(0x8086, 0x3b56),
2ea3c6a2 3465 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
87218e9c 3466 /* SCH */
9477c58e 3467 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3468 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3469 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3470 { PCI_DEVICE(0x8086, 0x080a),
3471 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3472 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3473 /* ICH */
8b0bd226 3474 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3475 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3476 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3477 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3478 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3479 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3480 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3481 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3482 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3483 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3484 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3485 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3486 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3487 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3488 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3489 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3490 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3491 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3492 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3493 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3494 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3495 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3496 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3497 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3498 /* Generic Intel */
3499 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3500 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3501 .class_mask = 0xffffff,
2ae66c26 3502 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3503 /* ATI SB 450/600/700/800/900 */
3504 { PCI_DEVICE(0x1002, 0x437b),
3505 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3506 { PCI_DEVICE(0x1002, 0x4383),
3507 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3508 /* AMD Hudson */
3509 { PCI_DEVICE(0x1022, 0x780d),
3510 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3511 /* ATI HDMI */
9477c58e
TI		 3512 { PCI_DEVICE(0x1002, 0x793b),
3513 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3514 { PCI_DEVICE(0x1002, 0x7919),
3515 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3516 { PCI_DEVICE(0x1002, 0x960f),
3517 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3518 { PCI_DEVICE(0x1002, 0x970f),
3519 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3520 { PCI_DEVICE(0x1002, 0xaa00),
3521 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3522 { PCI_DEVICE(0x1002, 0xaa08),
3523 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3524 { PCI_DEVICE(0x1002, 0xaa10),
3525 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3526 { PCI_DEVICE(0x1002, 0xaa18),
3527 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3528 { PCI_DEVICE(0x1002, 0xaa20),
3529 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3530 { PCI_DEVICE(0x1002, 0xaa28),
3531 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3532 { PCI_DEVICE(0x1002, 0xaa30),
3533 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3534 { PCI_DEVICE(0x1002, 0xaa38),
3535 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3536 { PCI_DEVICE(0x1002, 0xaa40),
3537 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3538 { PCI_DEVICE(0x1002, 0xaa48),
3539 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3540 { PCI_DEVICE(0x1002, 0x9902),
3541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3542 { PCI_DEVICE(0x1002, 0xaaa0),
3543 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3544 { PCI_DEVICE(0x1002, 0xaaa8),
3545 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3546 { PCI_DEVICE(0x1002, 0xaab0),
3547 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3548 /* VIA VT8251/VT8237A */
9477c58e
TI		 3549 { PCI_DEVICE(0x1106, 0x3288),
3550 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3551 /* VIA GFX VT7122/VX900 */
3552 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3553 /* VIA GFX VT6122/VX11 */
3554 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3555 /* SIS966 */
3556 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3557 /* ULI M5461 */
3558 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3559 /* NVIDIA MCP */
0c2fd1bf
TI		 3560 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3561 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3562 .class_mask = 0xffffff,
9477c58e 3563 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3564 /* Teradici */
9477c58e
TI		 3565 { PCI_DEVICE(0x6549, 0x1200),
3566 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 3567 { PCI_DEVICE(0x6549, 0x2200),
3568 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3569 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3570 /* CTHDA chips */
3571 { PCI_DEVICE(0x1102, 0x0010),
3572 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3573 { PCI_DEVICE(0x1102, 0x0012),
3574 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3575#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3576 /* the following entry conflicts with snd-ctxfi driver,
3577 * as ctxfi driver mutates from HD-audio to native mode with
3578 * a special command sequence.
3579 */
4e01f54b
TI		 3580 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3581 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3582 .class_mask = 0xffffff,
9477c58e 3583 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3584 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3585#else
3586 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3587 { PCI_DEVICE(0x1102, 0x0009),
3588 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3589 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3590#endif
e35d4b11
OS		 3591 /* Vortex86MX */
3592 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3593 /* VMware HDAudio */
3594 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3595 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3596 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3597 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3598 .class_mask = 0xffffff,
9477c58e 3599 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3600 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3601 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3602 .class_mask = 0xffffff,
9477c58e 3603 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3604 { 0, }
3605};
3606MODULE_DEVICE_TABLE(pci, azx_ids);
3607
3608/* pci_driver definition */
e9f66d9b 3609static struct pci_driver azx_driver = {
3733e424 3610 .name = KBUILD_MODNAME,
1da177e4
LT		 3611 .id_table = azx_ids,
3612 .probe = azx_probe,
3613 .remove = __devexit_p(azx_remove),
68cb2b55
TI		 3614 .driver = {
3615 .pm = AZX_PM_OPS,
3616 },
1da177e4
LT		 3617};
3618
e9f66d9b 3619module_pci_driver(azx_driver);
Linux kernel - Deliverables
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