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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
67b90cb8 42#include <sound/hda_chmap.h>
84eb01be
TI		 43#include "hda_codec.h"
44#include "hda_local.h"
1835a0f9 45#include "hda_jack.h"
84eb01be 46
0ebaa24c
TI		 47static bool static_hdmi_pcm;
48module_param(static_hdmi_pcm, bool, 0644);
49MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50
7639a06c
TI		 51#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 54#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 55#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
432ac1a2 56#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a
LY		 57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
75dcbe4d 59
7639a06c
TI		 60#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 62#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 63
384a48d7
SW		 64struct hdmi_spec_per_cvt {
65 hda_nid_t cvt_nid;
66 int assigned;
67 unsigned int channels_min;
68 unsigned int channels_max;
69 u32 rates;
70 u64 formats;
71 unsigned int maxbps;
72};
079d88cc 73
4eea3091
TI		 74/* max. connections to a widget */
75#define HDA_MAX_CONNECTIONS 32
76
384a48d7
SW		 77struct hdmi_spec_per_pin {
78 hda_nid_t pin_nid;
a76056f2
LY		 79 /* pin idx, different device entries on the same pin use the same idx */
80 int pin_nid_idx;
384a48d7
SW		 81 int num_mux_nids;
82 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 83 int mux_idx;
1df5a06a 84 hda_nid_t cvt_nid;
744626da
WF		 85
86 struct hda_codec *codec;
384a48d7 87 struct hdmi_eld sink_eld;
a4e9a38b 88 struct mutex lock;
744626da 89 struct delayed_work work;
2bea241a 90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 92 int repoll_count;
b054087d
TI		 93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
1a6003b5 95 bool non_pcm;
d45e6889
TI		 96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 98#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 99 struct snd_info_entry *proc_entry;
100#endif
384a48d7 101};
079d88cc 102
307229d2
AH		 103/* operations used by generic code that can be overridden by patches */
104struct hdmi_ops {
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
107
307229d2
AH		 108 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int ca, int active_channels, int conn_type);
110
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
113
114 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 hda_nid_t pin_nid, u32 stream_tag, int format);
116
4846a67e
TI		 117 void (*pin_cvt_fixup)(struct hda_codec *codec,
118 struct hdmi_spec_per_pin *per_pin,
119 hda_nid_t cvt_nid);
307229d2
AH		 120};
121
2bea241a
LY		 122struct hdmi_pcm {
123 struct hda_pcm *pcm;
124 struct snd_jack *jack;
fb087eaa 125 struct snd_kcontrol *eld_ctl;
2bea241a
LY		 126};
127
384a48d7
SW		 128struct hdmi_spec {
129 int num_cvts;
bce0d2a8
TI		 130 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
131 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 132
384a48d7 133 int num_pins;
bce0d2a8 134 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 135 struct hdmi_pcm pcm_rec[16];
42b29870 136 struct mutex pcm_lock;
a76056f2
LY		 137 /* pcm_bitmap means which pcms have been assigned to pins*/
138 unsigned long pcm_bitmap;
2bf3c85a 139 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 140 /* bitmap shows whether the pcm is opened in user space
141 * bit 0 means the first playback PCM (PCM3);
142 * bit 1 means the second playback PCM, and so on.
143 */
144 unsigned long pcm_in_use;
079d88cc 145
4bd038f9 146 struct hdmi_eld temp_eld;
307229d2 147 struct hdmi_ops ops;
75fae117
SW		 148
149 bool dyn_pin_out;
6590faab 150 bool dyn_pcm_assign;
079d88cc 151 /*
5a613584 152 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 153 */
154 struct hda_multi_out multiout;
d0b1252d 155 struct hda_pcm_stream pcm_playback;
25adc137
DH		 156
157 /* i915/powerwell (Haswell+/Valleyview+) specific */
691be973 158 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
25adc137 159 struct i915_audio_component_audio_ops i915_audio_ops;
55913110 160 bool i915_bound; /* was i915 bound in this driver? */
67b90cb8
SP		 161
162 struct hdac_chmap chmap;
079d88cc
WF		 163};
164
f4e3040b 165#ifdef CONFIG_SND_HDA_I915
691be973
TI		 166static inline bool codec_has_acomp(struct hda_codec *codec)
167{
168 struct hdmi_spec *spec = codec->spec;
169 return spec->use_acomp_notifier;
170}
f4e3040b
TI		 171#else
172#define codec_has_acomp(codec) false
173#endif
079d88cc
WF		 174
175struct hdmi_audio_infoframe {
176 u8 type; /* 0x84 */
177 u8 ver; /* 0x01 */
178 u8 len; /* 0x0a */
179
53d7d69d
WF		 180 u8 checksum;
181
079d88cc
WF		 182 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
183 u8 SS01_SF24;
184 u8 CXT04;
185 u8 CA;
186 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 187};
188
189struct dp_audio_infoframe {
190 u8 type; /* 0x84 */
191 u8 len; /* 0x1b */
192 u8 ver; /* 0x11 << 2 */
193
194 u8 CC02_CT47; /* match with HDMI infoframe from this on */
195 u8 SS01_SF24;
196 u8 CXT04;
197 u8 CA;
198 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 199};
200
2b203dbb
TI		 201union audio_infoframe {
202 struct hdmi_audio_infoframe hdmi;
203 struct dp_audio_infoframe dp;
204 u8 bytes[0];
205};
206
079d88cc
WF		 207/*
208 * HDMI routines
209 */
210
bce0d2a8
TI		 211#define get_pin(spec, idx) \
212 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
213#define get_cvt(spec, idx) \
214 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 215/* obtain hdmi_pcm object assigned to idx */
216#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
217/* obtain hda_pcm object assigned to idx */
218#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 219
4e76a883 220static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 221{
4e76a883 222 struct hdmi_spec *spec = codec->spec;
384a48d7 223 int pin_idx;
079d88cc 224
384a48d7 225 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 226 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 227 return pin_idx;
079d88cc 228
4e76a883 229 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 230 return -EINVAL;
231}
232
2bf3c85a
LY		 233static int hinfo_to_pcm_index(struct hda_codec *codec,
234 struct hda_pcm_stream *hinfo)
235{
236 struct hdmi_spec *spec = codec->spec;
237 int pcm_idx;
238
239 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
240 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
241 return pcm_idx;
242
243 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
244 return -EINVAL;
245}
246
4e76a883 247static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 248 struct hda_pcm_stream *hinfo)
249{
4e76a883 250 struct hdmi_spec *spec = codec->spec;
6590faab 251 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 252 int pin_idx;
253
6590faab
LY		 254 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
255 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 256 if (per_pin->pcm &&
257 per_pin->pcm->pcm->stream == hinfo)
384a48d7 258 return pin_idx;
6590faab 259 }
384a48d7 260
6590faab 261 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 262 return -EINVAL;
263}
264
022f344b
LY		 265static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
266 int pcm_idx)
267{
268 int i;
269 struct hdmi_spec_per_pin *per_pin;
270
271 for (i = 0; i < spec->num_pins; i++) {
272 per_pin = get_pin(spec, i);
273 if (per_pin->pcm_idx == pcm_idx)
274 return per_pin;
275 }
276 return NULL;
277}
278
4e76a883 279static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 280{
4e76a883 281 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 282 int cvt_idx;
283
284 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 285 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 286 return cvt_idx;
287
4e76a883 288 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 289 return -EINVAL;
290}
291
14bc52b8
PLB		 292static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
293 struct snd_ctl_elem_info *uinfo)
294{
295 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 296 struct hdmi_spec *spec = codec->spec;
a4e9a38b 297 struct hdmi_spec_per_pin *per_pin;
68e03de9 298 struct hdmi_eld *eld;
fb087eaa 299 int pcm_idx;
14bc52b8 300
14bc52b8
PLB		 301 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
302
fb087eaa
LY		 303 pcm_idx = kcontrol->private_value;
304 mutex_lock(&spec->pcm_lock);
305 per_pin = pcm_idx_to_pin(spec, pcm_idx);
306 if (!per_pin) {
307 /* no pin is bound to the pcm */
308 uinfo->count = 0;
309 mutex_unlock(&spec->pcm_lock);
310 return 0;
311 }
a4e9a38b 312 eld = &per_pin->sink_eld;
68e03de9 313 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
fb087eaa 314 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 315
316 return 0;
317}
318
319static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
320 struct snd_ctl_elem_value *ucontrol)
321{
322 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 323 struct hdmi_spec *spec = codec->spec;
a4e9a38b 324 struct hdmi_spec_per_pin *per_pin;
68e03de9 325 struct hdmi_eld *eld;
fb087eaa 326 int pcm_idx;
14bc52b8 327
fb087eaa
LY		 328 pcm_idx = kcontrol->private_value;
329 mutex_lock(&spec->pcm_lock);
330 per_pin = pcm_idx_to_pin(spec, pcm_idx);
331 if (!per_pin) {
332 /* no pin is bound to the pcm */
333 memset(ucontrol->value.bytes.data, 0,
334 ARRAY_SIZE(ucontrol->value.bytes.data));
335 mutex_unlock(&spec->pcm_lock);
336 return 0;
337 }
a4e9a38b 338 eld = &per_pin->sink_eld;
68e03de9 339
360a8245
DH		 340 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
341 eld->eld_size > ELD_MAX_SIZE) {
fb087eaa 342 mutex_unlock(&spec->pcm_lock);
68e03de9
DH		 343 snd_BUG();
344 return -EINVAL;
345 }
346
347 memset(ucontrol->value.bytes.data, 0,
348 ARRAY_SIZE(ucontrol->value.bytes.data));
349 if (eld->eld_valid)
350 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
351 eld->eld_size);
fb087eaa 352 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 353
354 return 0;
355}
356
357static struct snd_kcontrol_new eld_bytes_ctl = {
358 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
359 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
360 .name = "ELD",
361 .info = hdmi_eld_ctl_info,
362 .get = hdmi_eld_ctl_get,
363};
364
fb087eaa 365static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
14bc52b8
PLB		 366 int device)
367{
368 struct snd_kcontrol *kctl;
369 struct hdmi_spec *spec = codec->spec;
370 int err;
371
372 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
373 if (!kctl)
374 return -ENOMEM;
fb087eaa 375 kctl->private_value = pcm_idx;
14bc52b8
PLB		 376 kctl->id.device = device;
377
fb087eaa
LY		 378 /* no pin nid is associated with the kctl now
379 * tbd: associate pin nid to eld ctl later
380 */
381 err = snd_hda_ctl_add(codec, 0, kctl);
14bc52b8
PLB		 382 if (err < 0)
383 return err;
384
fb087eaa 385 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
14bc52b8
PLB		 386 return 0;
387}
388
079d88cc
WF		 389#ifdef BE_PARANOID
390static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
391 int *packet_index, int *byte_index)
392{
393 int val;
394
395 val = snd_hda_codec_read(codec, pin_nid, 0,
396 AC_VERB_GET_HDMI_DIP_INDEX, 0);
397
398 *packet_index = val >> 5;
399 *byte_index = val & 0x1f;
400}
401#endif
402
403static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
404 int packet_index, int byte_index)
405{
406 int val;
407
408 val = (packet_index << 5) | (byte_index & 0x1f);
409
410 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
411}
412
413static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
414 unsigned char val)
415{
416 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
417}
418
384a48d7 419static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 420{
75fae117
SW		 421 struct hdmi_spec *spec = codec->spec;
422 int pin_out;
423
079d88cc
WF		 424 /* Unmute */
425 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
426 snd_hda_codec_write(codec, pin_nid, 0,
427 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 428
429 if (spec->dyn_pin_out)
430 /* Disable pin out until stream is active */
431 pin_out = 0;
432 else
433 /* Enable pin out: some machines with GM965 gets broken output
434 * when the pin is disabled or changed while using with HDMI
435 */
436 pin_out = PIN_OUT;
437
079d88cc 438 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 439 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 440}
441
a4e9a38b
TI		 442/*
443 * ELD proc files
444 */
445
cd6a6503 446#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 447static void print_eld_info(struct snd_info_entry *entry,
448 struct snd_info_buffer *buffer)
449{
450 struct hdmi_spec_per_pin *per_pin = entry->private_data;
451
452 mutex_lock(&per_pin->lock);
453 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
454 mutex_unlock(&per_pin->lock);
455}
456
457static void write_eld_info(struct snd_info_entry *entry,
458 struct snd_info_buffer *buffer)
459{
460 struct hdmi_spec_per_pin *per_pin = entry->private_data;
461
462 mutex_lock(&per_pin->lock);
463 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
464 mutex_unlock(&per_pin->lock);
465}
466
467static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
468{
469 char name[32];
470 struct hda_codec *codec = per_pin->codec;
471 struct snd_info_entry *entry;
472 int err;
473
474 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 475 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 476 if (err < 0)
477 return err;
478
479 snd_info_set_text_ops(entry, per_pin, print_eld_info);
480 entry->c.text.write = write_eld_info;
481 entry->mode |= S_IWUSR;
482 per_pin->proc_entry = entry;
483
484 return 0;
485}
486
487static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
488{
1947a114 489 if (!per_pin->codec->bus->shutdown) {
c560a679 490 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 491 per_pin->proc_entry = NULL;
492 }
493}
494#else
b55447a7
TI		 495static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
496 int index)
a4e9a38b
TI		 497{
498 return 0;
499}
b55447a7 500static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 501{
502}
503#endif
079d88cc 504
079d88cc
WF		 505/*
506 * Audio InfoFrame routines
507 */
508
509/*
510 * Enable Audio InfoFrame Transmission
511 */
512static void hdmi_start_infoframe_trans(struct hda_codec *codec,
513 hda_nid_t pin_nid)
514{
515 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
516 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
517 AC_DIPXMIT_BEST);
518}
519
520/*
521 * Disable Audio InfoFrame Transmission
522 */
523static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
524 hda_nid_t pin_nid)
525{
526 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
527 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
528 AC_DIPXMIT_DISABLE);
529}
530
531static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
532{
533#ifdef CONFIG_SND_DEBUG_VERBOSE
534 int i;
535 int size;
536
537 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 538 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 539
540 for (i = 0; i < 8; i++) {
541 size = snd_hda_codec_read(codec, pin_nid, 0,
542 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 543 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 544 }
545#endif
546}
547
548static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
549{
550#ifdef BE_PARANOID
551 int i, j;
552 int size;
553 int pi, bi;
554 for (i = 0; i < 8; i++) {
555 size = snd_hda_codec_read(codec, pin_nid, 0,
556 AC_VERB_GET_HDMI_DIP_SIZE, i);
557 if (size == 0)
558 continue;
559
560 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
561 for (j = 1; j < 1000; j++) {
562 hdmi_write_dip_byte(codec, pin_nid, 0x0);
563 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
564 if (pi != i)
4e76a883 565 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 566 bi, pi, i);
567 if (bi == 0) /* byte index wrapped around */
568 break;
569 }
4e76a883 570 codec_dbg(codec,
079d88cc
WF		 571 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
572 i, size, j);
573 }
574#endif
575}
576
53d7d69d 577static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 578{
53d7d69d 579 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 580 u8 sum = 0;
581 int i;
582
53d7d69d 583 hdmi_ai->checksum = 0;
079d88cc 584
53d7d69d 585 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 586 sum += bytes[i];
587
53d7d69d 588 hdmi_ai->checksum = -sum;
079d88cc
WF		 589}
590
591static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
592 hda_nid_t pin_nid,
53d7d69d 593 u8 *dip, int size)
079d88cc 594{
079d88cc
WF		 595 int i;
596
597 hdmi_debug_dip_size(codec, pin_nid);
598 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
599
079d88cc 600 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 601 for (i = 0; i < size; i++)
602 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 603}
604
605static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 606 u8 *dip, int size)
079d88cc 607{
079d88cc
WF		 608 u8 val;
609 int i;
610
611 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
612 != AC_DIPXMIT_BEST)
613 return false;
614
615 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 616 for (i = 0; i < size; i++) {
079d88cc
WF		 617 val = snd_hda_codec_read(codec, pin_nid, 0,
618 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 619 if (val != dip[i])
079d88cc
WF		 620 return false;
621 }
622
623 return true;
624}
625
307229d2
AH		 626static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
627 hda_nid_t pin_nid,
628 int ca, int active_channels,
629 int conn_type)
630{
631 union audio_infoframe ai;
632
caaf5ef9 633 memset(&ai, 0, sizeof(ai));
307229d2
AH		 634 if (conn_type == 0) { /* HDMI */
635 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
636
637 hdmi_ai->type = 0x84;
638 hdmi_ai->ver = 0x01;
639 hdmi_ai->len = 0x0a;
640 hdmi_ai->CC02_CT47 = active_channels - 1;
641 hdmi_ai->CA = ca;
642 hdmi_checksum_audio_infoframe(hdmi_ai);
643 } else if (conn_type == 1) { /* DisplayPort */
644 struct dp_audio_infoframe *dp_ai = &ai.dp;
645
646 dp_ai->type = 0x84;
647 dp_ai->len = 0x1b;
648 dp_ai->ver = 0x11 << 2;
649 dp_ai->CC02_CT47 = active_channels - 1;
650 dp_ai->CA = ca;
651 } else {
4e76a883 652 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 653 pin_nid);
654 return;
655 }
656
657 /*
658 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
659 * sizeof(*dp_ai) to avoid partial match/update problems when
660 * the user switches between HDMI/DP monitors.
661 */
662 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
663 sizeof(ai))) {
4e76a883
TI		 664 codec_dbg(codec,
665 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 666 pin_nid,
667 active_channels, ca);
668 hdmi_stop_infoframe_trans(codec, pin_nid);
669 hdmi_fill_audio_infoframe(codec, pin_nid,
670 ai.bytes, sizeof(ai));
671 hdmi_start_infoframe_trans(codec, pin_nid);
672 }
673}
674
b054087d
TI		 675static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
676 struct hdmi_spec_per_pin *per_pin,
677 bool non_pcm)
079d88cc 678{
307229d2 679 struct hdmi_spec *spec = codec->spec;
739ffee9 680 struct hdac_chmap *chmap = &spec->chmap;
384a48d7 681 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 682 int channels = per_pin->channels;
1df5a06a 683 int active_channels;
384a48d7 684 struct hdmi_eld *eld;
828cb4ed 685 int ca;
079d88cc 686
b054087d
TI		 687 if (!channels)
688 return;
689
44bb6d0c
TI		 690 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
691 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
58f7d28d
ML		 692 snd_hda_codec_write(codec, pin_nid, 0,
693 AC_VERB_SET_AMP_GAIN_MUTE,
694 AMP_OUT_UNMUTE);
695
bce0d2a8 696 eld = &per_pin->sink_eld;
079d88cc 697
bb63f726 698 ca = snd_hdac_channel_allocation(&codec->core,
828cb4ed
SP		 699 eld->info.spk_alloc, channels,
700 per_pin->chmap_set, non_pcm, per_pin->chmap);
384a48d7 701
bb63f726 702 active_channels = snd_hdac_get_active_channels(ca);
1df5a06a 703
739ffee9
SP		 704 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
705 active_channels);
1df5a06a 706
39edac70
AH		 707 /*
708 * always configure channel mapping, it may have been changed by the
709 * user in the meantime
710 */
bb63f726 711 snd_hdac_setup_channel_mapping(&spec->chmap,
828cb4ed
SP		 712 pin_nid, non_pcm, ca, channels,
713 per_pin->chmap, per_pin->chmap_set);
39edac70 714
307229d2
AH		 715 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
716 eld->info.conn_type);
433968da 717
1a6003b5 718 per_pin->non_pcm = non_pcm;
079d88cc
WF		 719}
720
079d88cc
WF		 721/*
722 * Unsolicited events
723 */
724
efe47108 725static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 726
1a4f69d5 727static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 728{
729 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 730 int pin_idx = pin_nid_to_pin_index(codec, nid);
731
20ce9029
DH		 732 if (pin_idx < 0)
733 return;
20ce9029
DH		 734 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
735 snd_hda_jack_report_sync(codec);
736}
737
1a4f69d5
TI		 738static void jack_callback(struct hda_codec *codec,
739 struct hda_jack_callback *jack)
740{
2ebab40e 741 check_presence_and_report(codec, jack->nid);
1a4f69d5
TI		 742}
743
20ce9029
DH		 744static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
745{
3a93897e 746 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 747 struct hda_jack_tbl *jack;
2e59e5ab 748 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 749
750 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
751 if (!jack)
752 return;
3a93897e 753 jack->jack_dirty = 1;
079d88cc 754
4e76a883 755 codec_dbg(codec,
2e59e5ab 756 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 757 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 758 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 759
1a4f69d5 760 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 761}
762
763static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
764{
765 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
766 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
767 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
768 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
769
4e76a883 770 codec_info(codec,
e9ea8e8f 771 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 772 codec->addr,
079d88cc
WF		 773 tag,
774 subtag,
775 cp_state,
776 cp_ready);
777
778 /* TODO */
779 if (cp_state)
780 ;
781 if (cp_ready)
782 ;
783}
784
785
786static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
787{
079d88cc
WF		 788 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
789 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
790
3a93897e 791 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 792 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 793 return;
794 }
795
796 if (subtag == 0)
797 hdmi_intrinsic_event(codec, res);
798 else
799 hdmi_non_intrinsic_event(codec, res);
800}
801
58f7d28d 802static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 803 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 804{
58f7d28d 805 int pwr;
83f26ad2 806
53b434f0
WX		 807 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
808 * thus pins could only choose converter 0 for use. Make sure the
809 * converters are in correct power state */
fd678cac 810 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 811 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
812
fd678cac 813 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 814 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
815 AC_PWRST_D0);
816 msleep(40);
817 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
818 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 819 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 820 }
83f26ad2
DH		 821}
822
079d88cc
WF		 823/*
824 * Callbacks
825 */
826
92f10b3f
TI		 827/* HBR should be Non-PCM, 8 channels */
828#define is_hbr_format(format) \
829 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
830
307229d2
AH		 831static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
832 bool hbr)
079d88cc 833{
307229d2 834 int pinctl, new_pinctl;
83f26ad2 835
384a48d7
SW		 836 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
837 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 838 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
839
13122e6e
AH		 840 if (pinctl < 0)
841 return hbr ? -EINVAL : 0;
842
ea87d1c4 843 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 844 if (hbr)
ea87d1c4
AH		 845 new_pinctl |= AC_PINCTL_EPT_HBR;
846 else
847 new_pinctl |= AC_PINCTL_EPT_NATIVE;
848
4e76a883
TI		 849 codec_dbg(codec,
850 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 851 pin_nid,
ea87d1c4
AH		 852 pinctl == new_pinctl ? "" : "new-",
853 new_pinctl);
854
855 if (pinctl != new_pinctl)
384a48d7 856 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 857 AC_VERB_SET_PIN_WIDGET_CONTROL,
858 new_pinctl);
307229d2
AH		 859 } else if (hbr)
860 return -EINVAL;
ea87d1c4 861
307229d2
AH		 862 return 0;
863}
864
865static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
866 hda_nid_t pin_nid, u32 stream_tag, int format)
867{
868 struct hdmi_spec *spec = codec->spec;
869 int err;
870
307229d2
AH		 871 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
872
873 if (err) {
4e76a883 874 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 875 return err;
ea87d1c4 876 }
079d88cc 877
384a48d7 878 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 879 return 0;
079d88cc
WF		 880}
881
42b29870
LY		 882/* Try to find an available converter
883 * If pin_idx is less then zero, just try to find an available converter.
884 * Otherwise, try to find an available converter and get the cvt mux index
885 * of the pin.
886 */
7ef166b8 887static int hdmi_choose_cvt(struct hda_codec *codec,
4846a67e 888 int pin_idx, int *cvt_id)
bbbe3390
TI		 889{
890 struct hdmi_spec *spec = codec->spec;
384a48d7 891 struct hdmi_spec_per_pin *per_pin;
384a48d7 892 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 893 int cvt_idx, mux_idx = 0;
bbbe3390 894
42b29870
LY		 895 /* pin_idx < 0 means no pin will be bound to the converter */
896 if (pin_idx < 0)
897 per_pin = NULL;
898 else
899 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 900
901 /* Dynamically assign converter to stream */
902 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 903 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 904
384a48d7
SW		 905 /* Must not already be assigned */
906 if (per_cvt->assigned)
907 continue;
42b29870
LY		 908 if (per_pin == NULL)
909 break;
384a48d7
SW		 910 /* Must be in pin's mux's list of converters */
911 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
912 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
913 break;
914 /* Not in mux list */
915 if (mux_idx == per_pin->num_mux_nids)
916 continue;
917 break;
918 }
7ef166b8 919
384a48d7
SW		 920 /* No free converters */
921 if (cvt_idx == spec->num_cvts)
42b29870 922 return -EBUSY;
384a48d7 923
42b29870
LY		 924 if (per_pin != NULL)
925 per_pin->mux_idx = mux_idx;
2df6742f 926
7ef166b8
WX		 927 if (cvt_id)
928 *cvt_id = cvt_idx;
7ef166b8
WX		 929
930 return 0;
931}
932
2df6742f
ML		 933/* Assure the pin select the right convetor */
934static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
935 struct hdmi_spec_per_pin *per_pin)
936{
937 hda_nid_t pin_nid = per_pin->pin_nid;
938 int mux_idx, curr;
939
940 mux_idx = per_pin->mux_idx;
941 curr = snd_hda_codec_read(codec, pin_nid, 0,
942 AC_VERB_GET_CONNECT_SEL, 0);
943 if (curr != mux_idx)
944 snd_hda_codec_write_cache(codec, pin_nid, 0,
945 AC_VERB_SET_CONNECT_SEL,
946 mux_idx);
947}
948
42b29870
LY		 949/* get the mux index for the converter of the pins
950 * converter's mux index is the same for all pins on Intel platform
951 */
952static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
953 hda_nid_t cvt_nid)
954{
955 int i;
956
957 for (i = 0; i < spec->num_cvts; i++)
958 if (spec->cvt_nids[i] == cvt_nid)
959 return i;
960 return -EINVAL;
961}
962
300016b9
ML		 963/* Intel HDMI workaround to fix audio routing issue:
964 * For some Intel display codecs, pins share the same connection list.
965 * So a conveter can be selected by multiple pins and playback on any of these
966 * pins will generate sound on the external display, because audio flows from
967 * the same converter to the display pipeline. Also muting one pin may make
968 * other pins have no sound output.
969 * So this function assures that an assigned converter for a pin is not selected
970 * by any other pins.
971 */
972static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 973 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 974{
975 struct hdmi_spec *spec = codec->spec;
7639a06c 976 hda_nid_t nid;
f82d7d16
ML		 977 int cvt_idx, curr;
978 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 979
f82d7d16 980 /* configure all pins, including "no physical connection" ones */
7639a06c 981 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 982 unsigned int wid_caps = get_wcaps(codec, nid);
983 unsigned int wid_type = get_wcaps_type(wid_caps);
984
985 if (wid_type != AC_WID_PIN)
986 continue;
7ef166b8 987
f82d7d16 988 if (nid == pin_nid)
7ef166b8
WX		 989 continue;
990
f82d7d16 991 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 992 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 993 if (curr != mux_idx)
994 continue;
7ef166b8 995
f82d7d16
ML		 996 /* choose an unassigned converter. The conveters in the
997 * connection list are in the same order as in the codec.
998 */
999 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1000 per_cvt = get_cvt(spec, cvt_idx);
1001 if (!per_cvt->assigned) {
4e76a883
TI		 1002 codec_dbg(codec,
1003 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1004 cvt_idx, nid);
1005 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1006 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1007 cvt_idx);
1008 break;
1009 }
7ef166b8
WX		 1010 }
1011 }
1012}
1013
42b29870
LY		 1014/* A wrapper of intel_not_share_asigned_cvt() */
1015static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1016 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1017{
1018 int mux_idx;
1019 struct hdmi_spec *spec = codec->spec;
1020
42b29870
LY		 1021 /* On Intel platform, the mapping of converter nid to
1022 * mux index of the pins are always the same.
1023 * The pin nid may be 0, this means all pins will not
1024 * share the converter.
1025 */
1026 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1027 if (mux_idx >= 0)
1028 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1029}
1030
4846a67e
TI		 1031/* skeleton caller of pin_cvt_fixup ops */
1032static void pin_cvt_fixup(struct hda_codec *codec,
1033 struct hdmi_spec_per_pin *per_pin,
1034 hda_nid_t cvt_nid)
1035{
1036 struct hdmi_spec *spec = codec->spec;
1037
1038 if (spec->ops.pin_cvt_fixup)
1039 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1040}
1041
42b29870
LY		 1042/* called in hdmi_pcm_open when no pin is assigned to the PCM
1043 * in dyn_pcm_assign mode.
1044 */
1045static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1046 struct hda_codec *codec,
1047 struct snd_pcm_substream *substream)
1048{
1049 struct hdmi_spec *spec = codec->spec;
1050 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1051 int cvt_idx, pcm_idx;
42b29870
LY		 1052 struct hdmi_spec_per_cvt *per_cvt = NULL;
1053 int err;
1054
ac98379a
LY		 1055 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1056 if (pcm_idx < 0)
1057 return -EINVAL;
1058
4846a67e 1059 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
42b29870
LY		 1060 if (err)
1061 return err;
1062
1063 per_cvt = get_cvt(spec, cvt_idx);
1064 per_cvt->assigned = 1;
1065 hinfo->nid = per_cvt->cvt_nid;
1066
4846a67e 1067 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
42b29870 1068
ac98379a 1069 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1070 /* todo: setup spdif ctls assign */
1071
1072 /* Initially set the converter's capabilities */
1073 hinfo->channels_min = per_cvt->channels_min;
1074 hinfo->channels_max = per_cvt->channels_max;
1075 hinfo->rates = per_cvt->rates;
1076 hinfo->formats = per_cvt->formats;
1077 hinfo->maxbps = per_cvt->maxbps;
1078
1079 /* Store the updated parameters */
1080 runtime->hw.channels_min = hinfo->channels_min;
1081 runtime->hw.channels_max = hinfo->channels_max;
1082 runtime->hw.formats = hinfo->formats;
1083 runtime->hw.rates = hinfo->rates;
1084
1085 snd_pcm_hw_constraint_step(substream->runtime, 0,
1086 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1087 return 0;
1088}
1089
7ef166b8
WX		 1090/*
1091 * HDA PCM callbacks
1092 */
1093static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1094 struct hda_codec *codec,
1095 struct snd_pcm_substream *substream)
1096{
1097 struct hdmi_spec *spec = codec->spec;
1098 struct snd_pcm_runtime *runtime = substream->runtime;
4846a67e 1099 int pin_idx, cvt_idx, pcm_idx;
7ef166b8
WX		 1100 struct hdmi_spec_per_pin *per_pin;
1101 struct hdmi_eld *eld;
1102 struct hdmi_spec_per_cvt *per_cvt = NULL;
1103 int err;
1104
1105 /* Validate hinfo */
2bf3c85a
LY		 1106 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1107 if (pcm_idx < 0)
7ef166b8 1108 return -EINVAL;
2bf3c85a 1109
42b29870 1110 mutex_lock(&spec->pcm_lock);
4e76a883 1111 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1112 if (!spec->dyn_pcm_assign) {
1113 if (snd_BUG_ON(pin_idx < 0)) {
1114 mutex_unlock(&spec->pcm_lock);
1115 return -EINVAL;
1116 }
1117 } else {
1118 /* no pin is assigned to the PCM
1119 * PA need pcm open successfully when probe
1120 */
1121 if (pin_idx < 0) {
1122 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1123 mutex_unlock(&spec->pcm_lock);
1124 return err;
1125 }
1126 }
7ef166b8 1127
4846a67e 1128 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
42b29870
LY		 1129 if (err < 0) {
1130 mutex_unlock(&spec->pcm_lock);
7ef166b8 1131 return err;
42b29870 1132 }
7ef166b8
WX		 1133
1134 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1135 /* Claim converter */
1136 per_cvt->assigned = 1;
42b29870 1137
ac98379a 1138 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1139 per_pin = get_pin(spec, pin_idx);
1df5a06a 1140 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1141 hinfo->nid = per_cvt->cvt_nid;
1142
bddee96b 1143 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7 1144 AC_VERB_SET_CONNECT_SEL,
4846a67e 1145 per_pin->mux_idx);
7ef166b8
WX		 1146
1147 /* configure unused pins to choose other converters */
4846a67e 1148 pin_cvt_fixup(codec, per_pin, 0);
7ef166b8 1149
2bf3c85a 1150 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1151
2def8172 1152 /* Initially set the converter's capabilities */
384a48d7
SW		 1153 hinfo->channels_min = per_cvt->channels_min;
1154 hinfo->channels_max = per_cvt->channels_max;
1155 hinfo->rates = per_cvt->rates;
1156 hinfo->formats = per_cvt->formats;
1157 hinfo->maxbps = per_cvt->maxbps;
2def8172 1158
42b29870 1159 eld = &per_pin->sink_eld;
384a48d7 1160 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1161 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1162 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1163 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1164 !hinfo->rates || !hinfo->formats) {
1165 per_cvt->assigned = 0;
1166 hinfo->nid = 0;
2bf3c85a 1167 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
42b29870 1168 mutex_unlock(&spec->pcm_lock);
bbbe3390 1169 return -ENODEV;
2ad779b7 1170 }
bbbe3390 1171 }
2def8172 1172
42b29870 1173 mutex_unlock(&spec->pcm_lock);
2def8172 1174 /* Store the updated parameters */
639cef0e
TI		 1175 runtime->hw.channels_min = hinfo->channels_min;
1176 runtime->hw.channels_max = hinfo->channels_max;
1177 runtime->hw.formats = hinfo->formats;
1178 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1179
1180 snd_pcm_hw_constraint_step(substream->runtime, 0,
1181 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1182 return 0;
1183}
1184
079d88cc
WF		 1185/*
1186 * HDA/HDMI auto parsing
1187 */
384a48d7 1188static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1189{
1190 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1191 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1192 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1193
1194 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1195 codec_warn(codec,
1196 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1197 pin_nid, get_wcaps(codec, pin_nid));
1198 return -EINVAL;
1199 }
1200
384a48d7
SW		 1201 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1202 per_pin->mux_nids,
1203 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1204
1205 return 0;
1206}
1207
a76056f2
LY		 1208static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1209 struct hdmi_spec_per_pin *per_pin)
1210{
1211 int i;
1212
1213 /* try the prefer PCM */
1214 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1215 return per_pin->pin_nid_idx;
1216
1217 /* have a second try; check the "reserved area" over num_pins */
1218 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1219 if (!test_bit(i, &spec->pcm_bitmap))
1220 return i;
1221 }
1222
1223 /* the last try; check the empty slots in pins */
1224 for (i = 0; i < spec->num_pins; i++) {
1225 if (!test_bit(i, &spec->pcm_bitmap))
1226 return i;
1227 }
1228 return -EBUSY;
1229}
1230
1231static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1232 struct hdmi_spec_per_pin *per_pin)
1233{
1234 int idx;
1235
1236 /* pcm already be attached to the pin */
1237 if (per_pin->pcm)
1238 return;
1239 idx = hdmi_find_pcm_slot(spec, per_pin);
d10a80de 1240 if (idx == -EBUSY)
a76056f2
LY		 1241 return;
1242 per_pin->pcm_idx = idx;
2bea241a 1243 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1244 set_bit(idx, &spec->pcm_bitmap);
1245}
1246
1247static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1248 struct hdmi_spec_per_pin *per_pin)
1249{
1250 int idx;
1251
1252 /* pcm already be detached from the pin */
1253 if (!per_pin->pcm)
1254 return;
1255 idx = per_pin->pcm_idx;
1256 per_pin->pcm_idx = -1;
1257 per_pin->pcm = NULL;
1258 if (idx >= 0 && idx < spec->pcm_used)
1259 clear_bit(idx, &spec->pcm_bitmap);
1260}
1261
ac98379a
LY		 1262static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1263 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1264{
1265 int mux_idx;
1266
1267 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1268 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1269 break;
1270 return mux_idx;
1271}
1272
1273static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1274
1275static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1276 struct hdmi_spec_per_pin *per_pin)
1277{
1278 struct hda_codec *codec = per_pin->codec;
1279 struct hda_pcm *pcm;
1280 struct hda_pcm_stream *hinfo;
1281 struct snd_pcm_substream *substream;
1282 int mux_idx;
1283 bool non_pcm;
1284
1285 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1286 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1287 else
1288 return;
1289 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1290 return;
1291
1292 /* hdmi audio only uses playback and one substream */
1293 hinfo = pcm->stream;
1294 substream = pcm->pcm->streams[0].substream;
1295
1296 per_pin->cvt_nid = hinfo->nid;
1297
1298 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1299 if (mux_idx < per_pin->num_mux_nids)
1300 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1301 AC_VERB_SET_CONNECT_SEL,
1302 mux_idx);
1303 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1304
1305 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1306 if (substream->runtime)
1307 per_pin->channels = substream->runtime->channels;
1308 per_pin->setup = true;
1309 per_pin->mux_idx = mux_idx;
1310
1311 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1312}
1313
1314static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1315 struct hdmi_spec_per_pin *per_pin)
1316{
1317 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1318 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1319
1320 per_pin->chmap_set = false;
1321 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1322
1323 per_pin->setup = false;
1324 per_pin->channels = 0;
1325}
1326
e90247f9
TI		 1327/* update per_pin ELD from the given new ELD;
1328 * setup info frame and notification accordingly
1329 */
1330static void update_eld(struct hda_codec *codec,
1331 struct hdmi_spec_per_pin *per_pin,
1332 struct hdmi_eld *eld)
1333{
1334 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1335 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1336 bool old_eld_valid = pin_eld->eld_valid;
1337 bool eld_changed;
fb087eaa 1338 int pcm_idx = -1;
e90247f9 1339
fb087eaa
LY		 1340 /* for monitor disconnection, save pcm_idx firstly */
1341 pcm_idx = per_pin->pcm_idx;
a76056f2 1342 if (spec->dyn_pcm_assign) {
ac98379a 1343 if (eld->eld_valid) {
a76056f2 1344 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1345 hdmi_pcm_setup_pin(spec, per_pin);
1346 } else {
1347 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1348 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1349 }
a76056f2 1350 }
fb087eaa
LY		 1351 /* if pcm_idx == -1, it means this is in monitor connection event
1352 * we can get the correct pcm_idx now.
1353 */
1354 if (pcm_idx == -1)
1355 pcm_idx = per_pin->pcm_idx;
a76056f2 1356
e90247f9
TI		 1357 if (eld->eld_valid)
1358 snd_hdmi_show_eld(codec, &eld->info);
1359
1360 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1361 if (eld->eld_valid && pin_eld->eld_valid)
1362 if (pin_eld->eld_size != eld->eld_size ||
1363 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1364 eld->eld_size) != 0)
1365 eld_changed = true;
1366
bd481285 1367 pin_eld->monitor_present = eld->monitor_present;
e90247f9
TI		 1368 pin_eld->eld_valid = eld->eld_valid;
1369 pin_eld->eld_size = eld->eld_size;
1370 if (eld->eld_valid)
1371 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1372 pin_eld->info = eld->info;
1373
1374 /*
1375 * Re-setup pin and infoframe. This is needed e.g. when
1376 * - sink is first plugged-in
1377 * - transcoder can change during stream playback on Haswell
1378 * and this can make HW reset converter selection on a pin.
1379 */
1380 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
4846a67e 1381 pin_cvt_fixup(codec, per_pin, 0);
e90247f9
TI		 1382 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1383 }
1384
fb087eaa 1385 if (eld_changed && pcm_idx >= 0)
e90247f9
TI		 1386 snd_ctl_notify(codec->card,
1387 SNDRV_CTL_EVENT_MASK_VALUE |
1388 SNDRV_CTL_EVENT_MASK_INFO,
fb087eaa 1389 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
e90247f9
TI		 1390}
1391
788d441a
TI		 1392/* update ELD and jack state via HD-audio verbs */
1393static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1394 int repoll)
079d88cc 1395{
464837a7 1396 struct hda_jack_tbl *jack;
744626da 1397 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1398 struct hdmi_spec *spec = codec->spec;
1399 struct hdmi_eld *eld = &spec->temp_eld;
744626da 1400 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1401 /*
1402 * Always execute a GetPinSense verb here, even when called from
1403 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1404 * response's PD bit is not the real PD value, but indicates that
1405 * the real PD value changed. An older version of the HD-audio
1406 * specification worked this way. Hence, we just ignore the data in
1407 * the unsolicited response to avoid custom WARs.
1408 */
da4a7a39 1409 int present;
efe47108 1410 bool ret;
9a5e5234 1411 bool do_repoll = false;
079d88cc 1412
da4a7a39
DH		 1413 present = snd_hda_pin_sense(codec, pin_nid);
1414
a4e9a38b 1415 mutex_lock(&per_pin->lock);
c44da62b
TI		 1416 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1417 if (eld->monitor_present)
4bd038f9
DH		 1418 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1419 else
1420 eld->eld_valid = false;
079d88cc 1421
4e76a883 1422 codec_dbg(codec,
384a48d7 1423 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
c44da62b 1424 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927 1425
4bd038f9 1426 if (eld->eld_valid) {
307229d2 1427 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1428 &eld->eld_size) < 0)
4bd038f9 1429 eld->eld_valid = false;
1613d6b4 1430 else {
79514d47 1431 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1432 eld->eld_size) < 0)
4bd038f9 1433 eld->eld_valid = false;
1613d6b4 1434 }
9a5e5234
TI		 1435 if (!eld->eld_valid && repoll)
1436 do_repoll = true;
744626da 1437 }
4bd038f9 1438
9a5e5234 1439 if (do_repoll)
e90247f9
TI		 1440 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1441 else
1442 update_eld(codec, per_pin, eld);
92c69e79 1443
c44da62b 1444 ret = !repoll || !eld->monitor_present || eld->eld_valid;
464837a7
DH		 1445
1446 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1447 if (jack)
1448 jack->block_report = !ret;
1449
a4e9a38b 1450 mutex_unlock(&per_pin->lock);
efe47108 1451 return ret;
079d88cc
WF		 1452}
1453
3184270e
LY		 1454static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1455 struct hdmi_spec_per_pin *per_pin)
1456{
1457 struct hdmi_spec *spec = codec->spec;
1458 struct snd_jack *jack = NULL;
1459 struct hda_jack_tbl *jack_tbl;
1460
1461 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1462 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1463 * NULL even after snd_hda_jack_tbl_clear() is called to
1464 * free snd_jack. This may cause access invalid memory
1465 * when calling snd_jack_report
1466 */
1467 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1468 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1469 else if (!spec->dyn_pcm_assign) {
1470 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1471 if (jack_tbl)
1472 jack = jack_tbl->jack;
1473 }
1474 return jack;
1475}
1476
788d441a
TI		 1477/* update ELD and jack state via audio component */
1478static void sync_eld_via_acomp(struct hda_codec *codec,
1479 struct hdmi_spec_per_pin *per_pin)
1480{
788d441a
TI		 1481 struct hdmi_spec *spec = codec->spec;
1482 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1483 struct snd_jack *jack = NULL;
788d441a
TI		 1484 int size;
1485
e2dc7d7d 1486 mutex_lock(&per_pin->lock);
c64c1437 1487 eld->monitor_present = false;
d745f5e7 1488 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
e2dc7d7d
TI		 1489 &eld->monitor_present, eld->eld_buffer,
1490 ELD_MAX_SIZE);
e2dc7d7d
TI		 1491 if (size > 0) {
1492 size = min(size, ELD_MAX_SIZE);
1493 if (snd_hdmi_parse_eld(codec, &eld->info,
1494 eld->eld_buffer, size) < 0)
1495 size = -EINVAL;
1496 }
788d441a 1497
e2dc7d7d
TI		 1498 if (size > 0) {
1499 eld->eld_valid = true;
1500 eld->eld_size = size;
1501 } else {
1502 eld->eld_valid = false;
1503 eld->eld_size = 0;
788d441a 1504 }
e2dc7d7d 1505
25e4abb3
LY		 1506 /* pcm_idx >=0 before update_eld() means it is in monitor
1507 * disconnected event. Jack must be fetched before update_eld()
1508 */
3184270e 1509 jack = pin_idx_to_jack(codec, per_pin);
e2dc7d7d 1510 update_eld(codec, per_pin, eld);
3184270e
LY		 1511 if (jack == NULL)
1512 jack = pin_idx_to_jack(codec, per_pin);
25e4abb3
LY		 1513 if (jack == NULL)
1514 goto unlock;
1515 snd_jack_report(jack,
e2dc7d7d
TI		 1516 eld->monitor_present ? SND_JACK_AVOUT : 0);
1517 unlock:
1518 mutex_unlock(&per_pin->lock);
788d441a
TI		 1519}
1520
1521static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1522{
1523 struct hda_codec *codec = per_pin->codec;
a76056f2
LY		 1524 struct hdmi_spec *spec = codec->spec;
1525 int ret;
788d441a 1526
222bde03
TI		 1527 /* no temporary power up/down needed for component notifier */
1528 if (!codec_has_acomp(codec))
1529 snd_hda_power_up_pm(codec);
1530
a76056f2 1531 mutex_lock(&spec->pcm_lock);
788d441a
TI		 1532 if (codec_has_acomp(codec)) {
1533 sync_eld_via_acomp(codec, per_pin);
a76056f2 1534 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 1535 } else {
a76056f2 1536 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
788d441a 1537 }
a76056f2
LY		 1538 mutex_unlock(&spec->pcm_lock);
1539
222bde03
TI		 1540 if (!codec_has_acomp(codec))
1541 snd_hda_power_down_pm(codec);
1542
a76056f2 1543 return ret;
788d441a
TI		 1544}
1545
744626da
WF		 1546static void hdmi_repoll_eld(struct work_struct *work)
1547{
1548 struct hdmi_spec_per_pin *per_pin =
1549 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1550
c6e8453e
WF		 1551 if (per_pin->repoll_count++ > 6)
1552 per_pin->repoll_count = 0;
1553
efe47108
TI		 1554 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1555 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1556}
1557
c88d4e84
TI		 1558static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1559 hda_nid_t nid);
1560
079d88cc
WF		 1561static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1562{
1563 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1564 unsigned int caps, config;
1565 int pin_idx;
1566 struct hdmi_spec_per_pin *per_pin;
07acecc1 1567 int err;
079d88cc 1568
efc2f8de 1569 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1570 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1571 return 0;
1572
efc2f8de 1573 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1574 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1575 return 0;
1576
75dcbe4d 1577 if (is_haswell_plus(codec))
c88d4e84
TI		 1578 intel_haswell_fixup_connect_list(codec, pin_nid);
1579
384a48d7 1580 pin_idx = spec->num_pins;
bce0d2a8
TI		 1581 per_pin = snd_array_new(&spec->pins);
1582 if (!per_pin)
1583 return -ENOMEM;
384a48d7
SW		 1584
1585 per_pin->pin_nid = pin_nid;
1a6003b5 1586 per_pin->non_pcm = false;
a76056f2
LY		 1587 if (spec->dyn_pcm_assign)
1588 per_pin->pcm_idx = -1;
2bea241a
LY		 1589 else {
1590 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
a76056f2 1591 per_pin->pcm_idx = pin_idx;
2bea241a 1592 }
a76056f2 1593 per_pin->pin_nid_idx = pin_idx;
079d88cc 1594
384a48d7
SW		 1595 err = hdmi_read_pin_conn(codec, pin_idx);
1596 if (err < 0)
1597 return err;
079d88cc 1598
079d88cc
WF		 1599 spec->num_pins++;
1600
384a48d7 1601 return 0;
079d88cc
WF		 1602}
1603
384a48d7 1604static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1605{
1606 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1607 struct hdmi_spec_per_cvt *per_cvt;
1608 unsigned int chans;
1609 int err;
079d88cc 1610
384a48d7
SW		 1611 chans = get_wcaps(codec, cvt_nid);
1612 chans = get_wcaps_channels(chans);
1613
bce0d2a8
TI		 1614 per_cvt = snd_array_new(&spec->cvts);
1615 if (!per_cvt)
1616 return -ENOMEM;
384a48d7
SW		 1617
1618 per_cvt->cvt_nid = cvt_nid;
1619 per_cvt->channels_min = 2;
d45e6889 1620 if (chans <= 16) {
384a48d7 1621 per_cvt->channels_max = chans;
67b90cb8
SP		 1622 if (chans > spec->chmap.channels_max)
1623 spec->chmap.channels_max = chans;
d45e6889 1624 }
384a48d7
SW		 1625
1626 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1627 &per_cvt->rates,
1628 &per_cvt->formats,
1629 &per_cvt->maxbps);
1630 if (err < 0)
1631 return err;
1632
bce0d2a8
TI		 1633 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1634 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1635 spec->num_cvts++;
079d88cc
WF		 1636
1637 return 0;
1638}
1639
1640static int hdmi_parse_codec(struct hda_codec *codec)
1641{
1642 hda_nid_t nid;
1643 int i, nodes;
1644
7639a06c 1645 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1646 if (!nid || nodes < 0) {
4e76a883 1647 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1648 return -EINVAL;
1649 }
1650
1651 for (i = 0; i < nodes; i++, nid++) {
1652 unsigned int caps;
1653 unsigned int type;
1654
efc2f8de 1655 caps = get_wcaps(codec, nid);
079d88cc
WF		 1656 type = get_wcaps_type(caps);
1657
1658 if (!(caps & AC_WCAP_DIGITAL))
1659 continue;
1660
1661 switch (type) {
1662 case AC_WID_AUD_OUT:
384a48d7 1663 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1664 break;
1665 case AC_WID_PIN:
3eaead57 1666 hdmi_add_pin(codec, nid);
079d88cc
WF		 1667 break;
1668 }
1669 }
1670
079d88cc
WF		 1671 return 0;
1672}
1673
84eb01be
TI		 1674/*
1675 */
1a6003b5
TI		 1676static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1677{
1678 struct hda_spdif_out *spdif;
1679 bool non_pcm;
1680
1681 mutex_lock(&codec->spdif_mutex);
1682 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1683 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1684 mutex_unlock(&codec->spdif_mutex);
1685 return non_pcm;
1686}
1687
84eb01be
TI		 1688/*
1689 * HDMI callbacks
1690 */
1691
1692static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1693 struct hda_codec *codec,
1694 unsigned int stream_tag,
1695 unsigned int format,
1696 struct snd_pcm_substream *substream)
1697{
384a48d7
SW		 1698 hda_nid_t cvt_nid = hinfo->nid;
1699 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1700 int pin_idx;
1701 struct hdmi_spec_per_pin *per_pin;
1702 hda_nid_t pin_nid;
ddd621fb 1703 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1704 bool non_pcm;
75fae117 1705 int pinctl;
42b29870 1706 int err;
1a6003b5 1707
42b29870
LY		 1708 mutex_lock(&spec->pcm_lock);
1709 pin_idx = hinfo_to_pin_index(codec, hinfo);
1710 if (spec->dyn_pcm_assign && pin_idx < 0) {
1711 /* when dyn_pcm_assign and pcm is not bound to a pin
1712 * skip pin setup and return 0 to make audio playback
1713 * be ongoing
1714 */
4846a67e 1715 pin_cvt_fixup(codec, NULL, cvt_nid);
42b29870
LY		 1716 snd_hda_codec_setup_stream(codec, cvt_nid,
1717 stream_tag, 0, format);
1718 mutex_unlock(&spec->pcm_lock);
1719 return 0;
1720 }
1a6003b5 1721
42b29870
LY		 1722 if (snd_BUG_ON(pin_idx < 0)) {
1723 mutex_unlock(&spec->pcm_lock);
1724 return -EINVAL;
1725 }
1726 per_pin = get_pin(spec, pin_idx);
1727 pin_nid = per_pin->pin_nid;
4846a67e
TI		 1728
1729 /* Verify pin:cvt selections to avoid silent audio after S3.
1730 * After S3, the audio driver restores pin:cvt selections
1731 * but this can happen before gfx is ready and such selection
1732 * is overlooked by HW. Thus multiple pins can share a same
1733 * default convertor and mute control will affect each other,
1734 * which can cause a resumed audio playback become silent
1735 * after S3.
1736 */
1737 pin_cvt_fixup(codec, per_pin, 0);
2df6742f 1738
ddd621fb
LY		 1739 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1740 /* Todo: add DP1.2 MST audio support later */
93a9ff15 1741 if (codec_has_acomp(codec))
d745f5e7 1742 snd_hdac_sync_audio_rate(&codec->core, pin_nid, runtime->rate);
ddd621fb 1743
1a6003b5 1744 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1745 mutex_lock(&per_pin->lock);
b054087d
TI		 1746 per_pin->channels = substream->runtime->channels;
1747 per_pin->setup = true;
384a48d7 1748
b054087d 1749 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1750 mutex_unlock(&per_pin->lock);
75fae117
SW		 1751 if (spec->dyn_pin_out) {
1752 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1753 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1754 snd_hda_codec_write(codec, pin_nid, 0,
1755 AC_VERB_SET_PIN_WIDGET_CONTROL,
1756 pinctl | PIN_OUT);
1757 }
1758
42b29870
LY		 1759 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1760 stream_tag, format);
1761 mutex_unlock(&spec->pcm_lock);
1762 return err;
84eb01be
TI		 1763}
1764
8dfaa573
TI		 1765static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1766 struct hda_codec *codec,
1767 struct snd_pcm_substream *substream)
1768{
1769 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1770 return 0;
1771}
1772
f2ad24fa
TI		 1773static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1774 struct hda_codec *codec,
1775 struct snd_pcm_substream *substream)
384a48d7
SW		 1776{
1777 struct hdmi_spec *spec = codec->spec;
2bf3c85a 1778 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 1779 struct hdmi_spec_per_cvt *per_cvt;
1780 struct hdmi_spec_per_pin *per_pin;
75fae117 1781 int pinctl;
384a48d7 1782
384a48d7 1783 if (hinfo->nid) {
2bf3c85a
LY		 1784 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1785 if (snd_BUG_ON(pcm_idx < 0))
1786 return -EINVAL;
4e76a883 1787 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1788 if (snd_BUG_ON(cvt_idx < 0))
1789 return -EINVAL;
bce0d2a8 1790 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1791
1792 snd_BUG_ON(!per_cvt->assigned);
1793 per_cvt->assigned = 0;
1794 hinfo->nid = 0;
1795
42b29870 1796 mutex_lock(&spec->pcm_lock);
b09887f8 1797 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 1798 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 1799 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1800 if (spec->dyn_pcm_assign && pin_idx < 0) {
1801 mutex_unlock(&spec->pcm_lock);
1802 return 0;
1803 }
1804
1805 if (snd_BUG_ON(pin_idx < 0)) {
1806 mutex_unlock(&spec->pcm_lock);
384a48d7 1807 return -EINVAL;
42b29870 1808 }
bce0d2a8 1809 per_pin = get_pin(spec, pin_idx);
384a48d7 1810
75fae117
SW		 1811 if (spec->dyn_pin_out) {
1812 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1813 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1814 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1815 AC_VERB_SET_PIN_WIDGET_CONTROL,
1816 pinctl & ~PIN_OUT);
1817 }
1818
a4e9a38b 1819 mutex_lock(&per_pin->lock);
d45e6889
TI		 1820 per_pin->chmap_set = false;
1821 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1822
1823 per_pin->setup = false;
1824 per_pin->channels = 0;
a4e9a38b 1825 mutex_unlock(&per_pin->lock);
42b29870 1826 mutex_unlock(&spec->pcm_lock);
384a48d7 1827 }
d45e6889 1828
384a48d7
SW		 1829 return 0;
1830}
1831
1832static const struct hda_pcm_ops generic_ops = {
1833 .open = hdmi_pcm_open,
f2ad24fa 1834 .close = hdmi_pcm_close,
384a48d7 1835 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1836 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1837};
1838
44fde3b8
SP		 1839static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1840{
1841 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1842 struct hdmi_spec *spec = codec->spec;
1843 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1844
1845 if (!per_pin)
1846 return 0;
1847
1848 return per_pin->sink_eld.info.spk_alloc;
1849}
1850
9b3dc8aa
SP		 1851static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1852 unsigned char *chmap)
1853{
1854 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1855 struct hdmi_spec *spec = codec->spec;
1856 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1857
1858 /* chmap is already set to 0 in caller */
1859 if (!per_pin)
1860 return;
1861
1862 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1863}
1864
1865static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1866 unsigned char *chmap, int prepared)
1867{
1868 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1869 struct hdmi_spec *spec = codec->spec;
1870 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1871
ed0739b5
LY		 1872 if (!per_pin)
1873 return;
9b3dc8aa
SP		 1874 mutex_lock(&per_pin->lock);
1875 per_pin->chmap_set = true;
1876 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1877 if (prepared)
1878 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1879 mutex_unlock(&per_pin->lock);
1880}
1881
1882static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1883{
1884 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1885 struct hdmi_spec *spec = codec->spec;
1886 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1887
1888 return per_pin ? true:false;
1889}
1890
84eb01be
TI		 1891static int generic_hdmi_build_pcms(struct hda_codec *codec)
1892{
1893 struct hdmi_spec *spec = codec->spec;
384a48d7 1894 int pin_idx;
84eb01be 1895
384a48d7
SW		 1896 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1897 struct hda_pcm *info;
84eb01be 1898 struct hda_pcm_stream *pstr;
bce0d2a8 1899
bbbc7e85 1900 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 1901 if (!info)
1902 return -ENOMEM;
2bea241a
LY		 1903
1904 spec->pcm_rec[pin_idx].pcm = info;
2bf3c85a 1905 spec->pcm_used++;
84eb01be 1906 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1907 info->own_chmap = true;
384a48d7 1908
84eb01be 1909 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1910 pstr->substreams = 1;
1911 pstr->ops = generic_ops;
1912 /* other pstr fields are set in open */
84eb01be
TI		 1913 }
1914
1915 return 0;
1916}
1917
25e4abb3 1918static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 1919{
25e4abb3 1920 struct hdmi_pcm *pcm = jack->private_data;
788d441a 1921
25e4abb3 1922 pcm->jack = NULL;
788d441a
TI		 1923}
1924
25e4abb3
LY		 1925static int add_hdmi_jack_kctl(struct hda_codec *codec,
1926 struct hdmi_spec *spec,
1927 int pcm_idx,
788d441a
TI		 1928 const char *name)
1929{
1930 struct snd_jack *jack;
1931 int err;
1932
1933 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1934 true, false);
1935 if (err < 0)
1936 return err;
25e4abb3
LY		 1937
1938 spec->pcm_rec[pcm_idx].jack = jack;
1939 jack->private_data = &spec->pcm_rec[pcm_idx];
1940 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 1941 return 0;
1942}
1943
25e4abb3 1944static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 1945{
31ef2257 1946 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1947 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 1948 struct hdmi_spec_per_pin *per_pin;
1949 struct hda_jack_tbl *jack;
1950 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 1951 bool phantom_jack;
25e4abb3 1952 int ret;
0b6c49b5 1953
31ef2257
TI		 1954 if (pcmdev > 0)
1955 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 1956
1957 if (spec->dyn_pcm_assign)
1958 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1959
1960 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1961 /* if !dyn_pcm_assign, it must be non-MST mode.
1962 * This means pcms and pins are statically mapped.
1963 * And pcm_idx is pin_idx.
1964 */
1965 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 1966 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1967 if (phantom_jack)
30efd8de
DH		 1968 strncat(hdmi_str, " Phantom",
1969 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3
LY		 1970 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1971 phantom_jack);
1972 if (ret < 0)
1973 return ret;
1974 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1975 if (jack == NULL)
1976 return 0;
1977 /* assign jack->jack to pcm_rec[].jack to
1978 * align with dyn_pcm_assign mode
1979 */
1980 spec->pcm_rec[pcm_idx].jack = jack->jack;
1981 return 0;
0b6c49b5
DH		 1982}
1983
84eb01be
TI		 1984static int generic_hdmi_build_controls(struct hda_codec *codec)
1985{
1986 struct hdmi_spec *spec = codec->spec;
1987 int err;
25e4abb3 1988 int pin_idx, pcm_idx;
84eb01be 1989
0b6c49b5 1990
25e4abb3
LY		 1991 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
1992 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 1993 if (err < 0)
1994 return err;
1995
b09887f8
LY		 1996 /* create the spdif for each pcm
1997 * pin will be bound when monitor is connected
1998 */
1999 if (spec->dyn_pcm_assign)
2000 err = snd_hda_create_dig_out_ctls(codec,
2001 0, spec->cvt_nids[0],
2002 HDA_PCM_TYPE_HDMI);
2003 else {
2004 struct hdmi_spec_per_pin *per_pin =
2005 get_pin(spec, pcm_idx);
2006 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2007 per_pin->pin_nid,
2008 per_pin->mux_nids[0],
2009 HDA_PCM_TYPE_HDMI);
b09887f8 2010 }
84eb01be
TI		 2011 if (err < 0)
2012 return err;
b09887f8 2013 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
14bc52b8
PLB		 2014
2015 /* add control for ELD Bytes */
fb087eaa
LY		 2016 err = hdmi_create_eld_ctl(codec, pcm_idx,
2017 get_pcm_rec(spec, pcm_idx)->device);
14bc52b8
PLB		 2018 if (err < 0)
2019 return err;
fb087eaa
LY		 2020 }
2021
2022 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2023 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
31ef2257 2024
82b1d73f 2025 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2026 }
2027
d45e6889 2028 /* add channel maps */
022f344b 2029 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2030 struct hda_pcm *pcm;
2ca320e2 2031
022f344b 2032 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2033 if (!pcm || !pcm->pcm)
2ca320e2 2034 break;
2f6e8a85 2035 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
d45e6889
TI		 2036 if (err < 0)
2037 return err;
d45e6889
TI		 2038 }
2039
84eb01be
TI		 2040 return 0;
2041}
2042
8b8d654b 2043static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2044{
2045 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2046 int pin_idx;
2047
2048 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2049 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2050
744626da 2051 per_pin->codec = codec;
a4e9a38b 2052 mutex_init(&per_pin->lock);
744626da 2053 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2054 eld_proc_new(per_pin, pin_idx);
84eb01be 2055 }
8b8d654b
TI		 2056 return 0;
2057}
2058
2059static int generic_hdmi_init(struct hda_codec *codec)
2060{
2061 struct hdmi_spec *spec = codec->spec;
2062 int pin_idx;
2063
2064 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2065 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2066 hda_nid_t pin_nid = per_pin->pin_nid;
2067
2068 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2069 if (!codec_has_acomp(codec))
2070 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2071 codec->jackpoll_interval > 0 ?
2072 jack_callback : NULL);
8b8d654b 2073 }
84eb01be
TI		 2074 return 0;
2075}
2076
bce0d2a8
TI		 2077static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2078{
2079 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2080 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2081}
2082
2083static void hdmi_array_free(struct hdmi_spec *spec)
2084{
2085 snd_array_free(&spec->pins);
2086 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2087}
2088
a686632f
TI		 2089static void generic_spec_free(struct hda_codec *codec)
2090{
2091 struct hdmi_spec *spec = codec->spec;
2092
2093 if (spec) {
e85015a3
TI		 2094 if (spec->i915_bound)
2095 snd_hdac_i915_exit(&codec->bus->core);
a686632f
TI		 2096 hdmi_array_free(spec);
2097 kfree(spec);
2098 codec->spec = NULL;
2099 }
2100 codec->dp_mst = false;
2101}
2102
84eb01be
TI		 2103static void generic_hdmi_free(struct hda_codec *codec)
2104{
2105 struct hdmi_spec *spec = codec->spec;
25e4abb3 2106 int pin_idx, pcm_idx;
384a48d7 2107
6603249d 2108 if (codec_has_acomp(codec))
25adc137
DH		 2109 snd_hdac_i915_register_notifier(NULL);
2110
384a48d7 2111 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2112 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2113 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2114 eld_proc_free(per_pin);
25e4abb3
LY		 2115 }
2116
2117 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2118 if (spec->pcm_rec[pcm_idx].jack == NULL)
2119 continue;
2120 if (spec->dyn_pcm_assign)
2121 snd_device_free(codec->card,
2122 spec->pcm_rec[pcm_idx].jack);
2123 else
2124 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2125 }
84eb01be 2126
a686632f 2127 generic_spec_free(codec);
84eb01be
TI		 2128}
2129
28cb72e5
WX		 2130#ifdef CONFIG_PM
2131static int generic_hdmi_resume(struct hda_codec *codec)
2132{
2133 struct hdmi_spec *spec = codec->spec;
2134 int pin_idx;
2135
a2833683 2136 codec->patch_ops.init(codec);
eeecd9d1 2137 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2138
2139 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2140 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2141 hdmi_present_sense(per_pin, 1);
2142 }
2143 return 0;
2144}
2145#endif
2146
fb79e1e0 2147static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2148 .init = generic_hdmi_init,
2149 .free = generic_hdmi_free,
2150 .build_pcms = generic_hdmi_build_pcms,
2151 .build_controls = generic_hdmi_build_controls,
2152 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2153#ifdef CONFIG_PM
2154 .resume = generic_hdmi_resume,
2155#endif
84eb01be
TI		 2156};
2157
307229d2
AH		 2158static const struct hdmi_ops generic_standard_hdmi_ops = {
2159 .pin_get_eld = snd_hdmi_get_eld,
307229d2
AH		 2160 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2161 .pin_hbr_setup = hdmi_pin_hbr_setup,
2162 .setup_stream = hdmi_setup_stream,
67b90cb8
SP		 2163};
2164
a686632f
TI		 2165/* allocate codec->spec and assign/initialize generic parser ops */
2166static int alloc_generic_hdmi(struct hda_codec *codec)
2167{
2168 struct hdmi_spec *spec;
2169
2170 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2171 if (!spec)
2172 return -ENOMEM;
2173
2174 spec->ops = generic_standard_hdmi_ops;
2175 mutex_init(&spec->pcm_lock);
2176 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2177
2178 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2179 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2180 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
44fde3b8 2181 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
a686632f
TI		 2182
2183 codec->spec = spec;
2184 hdmi_array_init(spec, 4);
2185
2186 codec->patch_ops = generic_hdmi_patch_ops;
2187
2188 return 0;
2189}
2190
2191/* generic HDMI parser */
2192static int patch_generic_hdmi(struct hda_codec *codec)
2193{
2194 int err;
2195
2196 err = alloc_generic_hdmi(codec);
2197 if (err < 0)
2198 return err;
2199
2200 err = hdmi_parse_codec(codec);
2201 if (err < 0) {
2202 generic_spec_free(codec);
2203 return err;
2204 }
2205
2206 generic_hdmi_init_per_pins(codec);
2207 return 0;
2208}
2209
2210/*
2211 * Intel codec parsers and helpers
2212 */
2213
c88d4e84
TI		 2214static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2215 hda_nid_t nid)
2216{
2217 struct hdmi_spec *spec = codec->spec;
2218 hda_nid_t conns[4];
2219 int nconns;
6ffe168f 2220
c88d4e84
TI		 2221 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2222 if (nconns == spec->num_cvts &&
2223 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2224 return;
2225
c88d4e84 2226 /* override pins connection list */
4e76a883 2227 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2228 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2229}
2230
1611a9c9
ML		 2231#define INTEL_VENDOR_NID 0x08
2232#define INTEL_GET_VENDOR_VERB 0xf81
2233#define INTEL_SET_VENDOR_VERB 0x781
2234#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2235#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2236
2237static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2238 bool update_tree)
1611a9c9
ML		 2239{
2240 unsigned int vendor_param;
2241
1611a9c9
ML		 2242 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2243 INTEL_GET_VENDOR_VERB, 0);
2244 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2245 return;
2246
2247 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2248 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2249 INTEL_SET_VENDOR_VERB, vendor_param);
2250 if (vendor_param == -1)
2251 return;
2252
17df3f55
TI		 2253 if (update_tree)
2254 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2255}
2256
c88d4e84
TI		 2257static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2258{
2259 unsigned int vendor_param;
2260
2261 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2262 INTEL_GET_VENDOR_VERB, 0);
2263 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2264 return;
2265
2266 /* enable DP1.2 mode */
2267 vendor_param |= INTEL_EN_DP12;
a551d914 2268 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2269 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2270 INTEL_SET_VENDOR_VERB, vendor_param);
2271}
2272
17df3f55
TI		 2273/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2274 * Otherwise you may get severe h/w communication errors.
2275 */
2276static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2277 unsigned int power_state)
2278{
2279 if (power_state == AC_PWRST_D0) {
2280 intel_haswell_enable_all_pins(codec, false);
2281 intel_haswell_fixup_enable_dp12(codec);
2282 }
c88d4e84 2283
17df3f55
TI		 2284 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2285 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2286}
6ffe168f 2287
f0675d4a 2288static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2289{
2290 struct hda_codec *codec = audio_ptr;
7ff652ff 2291 int pin_nid;
25adc137 2292
4f8e4f35
TI		 2293 /* we assume only from port-B to port-D */
2294 if (port < 1 || port > 3)
2295 return;
2296
7ff652ff
TI		 2297 switch (codec->core.vendor_id) {
2298 case 0x80860054: /* ILK */
2299 case 0x80862804: /* ILK */
2300 case 0x80862882: /* VLV */
2301 pin_nid = port + 0x03;
2302 break;
2303 default:
2304 pin_nid = port + 0x04;
2305 break;
2306 }
2307
8ae743e8
TI		 2308 /* skip notification during system suspend (but not in runtime PM);
2309 * the state will be updated at resume
2310 */
2311 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2312 return;
eb399d3c
TI		 2313 /* ditto during suspend/resume process itself */
2314 if (atomic_read(&(codec)->core.in_pm))
2315 return;
8ae743e8 2316
bb03ed21 2317 snd_hdac_i915_set_bclk(&codec->bus->core);
25adc137
DH		 2318 check_presence_and_report(codec, pin_nid);
2319}
2320
a686632f
TI		 2321/* register i915 component pin_eld_notify callback */
2322static void register_i915_notifier(struct hda_codec *codec)
84eb01be 2323{
a686632f 2324 struct hdmi_spec *spec = codec->spec;
84eb01be 2325
a686632f
TI		 2326 spec->use_acomp_notifier = true;
2327 spec->i915_audio_ops.audio_ptr = codec;
2328 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2329 * will call pin_eld_notify with using audio_ptr pointer
2330 * We need make sure audio_ptr is really setup
2331 */
2332 wmb();
2333 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2334 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2335}
84eb01be 2336
2c1c9b86
TI		 2337/* setup_stream ops override for HSW+ */
2338static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2339 hda_nid_t pin_nid, u32 stream_tag, int format)
2340{
2341 haswell_verify_D0(codec, cvt_nid, pin_nid);
2342 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2343}
739ffee9 2344
4846a67e
TI		 2345/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2346static void i915_pin_cvt_fixup(struct hda_codec *codec,
2347 struct hdmi_spec_per_pin *per_pin,
2348 hda_nid_t cvt_nid)
2349{
2350 if (per_pin) {
2351 intel_verify_pin_cvt_connect(codec, per_pin);
2352 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2353 per_pin->mux_idx);
2354 } else {
2355 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2356 }
2357}
739ffee9 2358
a686632f
TI		 2359/* Intel Haswell and onwards; audio component with eld notifier */
2360static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2361{
2362 struct hdmi_spec *spec;
2363 int err;
6ffe168f 2364
a686632f
TI		 2365 /* HSW+ requires i915 binding */
2366 if (!codec->bus->core.audio_component) {
2367 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2368 return -ENODEV;
691be973 2369 }
55913110 2370
a686632f
TI		 2371 err = alloc_generic_hdmi(codec);
2372 if (err < 0)
2373 return err;
2374 spec = codec->spec;
6ffe168f 2375
a686632f
TI		 2376 intel_haswell_enable_all_pins(codec, true);
2377 intel_haswell_fixup_enable_dp12(codec);
2378
2379 /* For Haswell/Broadwell, the controller is also in the power well and
2bd1f73f 2380 * can cover the codec power request, and so need not set this flag.
2bd1f73f 2381 */
a686632f 2382 if (!is_haswell(codec) && !is_broadwell(codec))
2bd1f73f
ML		 2383 codec->core.link_power_control = 1;
2384
a686632f
TI		 2385 codec->patch_ops.set_power_state = haswell_set_power_state;
2386 codec->dp_mst = true;
2387 codec->depop_delay = 0;
2388 codec->auto_runtime_pm = 1;
2389
2c1c9b86 2390 spec->ops.setup_stream = i915_hsw_setup_stream;
4846a67e 2391 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2c1c9b86 2392
a686632f
TI		 2393 err = hdmi_parse_codec(codec);
2394 if (err < 0) {
2395 generic_spec_free(codec);
2396 return err;
84eb01be 2397 }
a686632f
TI		 2398
2399 generic_hdmi_init_per_pins(codec);
2400 register_i915_notifier(codec);
2401 return 0;
2402}
2403
7ff652ff 2404/* Intel Baytrail and Braswell; with eld notifier */
a686632f
TI		 2405static int patch_i915_byt_hdmi(struct hda_codec *codec)
2406{
2407 struct hdmi_spec *spec;
2408 int err;
2409
2410 /* requires i915 binding */
2411 if (!codec->bus->core.audio_component) {
2412 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2413 return -ENODEV;
5dc989bd 2414 }
17df3f55 2415
a686632f
TI		 2416 err = alloc_generic_hdmi(codec);
2417 if (err < 0)
2418 return err;
2419 spec = codec->spec;
2377c3c3 2420
a686632f
TI		 2421 /* For Valleyview/Cherryview, only the display codec is in the display
2422 * power well and can use link_power ops to request/release the power.
2423 */
2424 codec->core.link_power_control = 1;
84eb01be 2425
a686632f
TI		 2426 codec->depop_delay = 0;
2427 codec->auto_runtime_pm = 1;
84eb01be 2428
4846a67e
TI		 2429 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2430
a686632f
TI		 2431 err = hdmi_parse_codec(codec);
2432 if (err < 0) {
2433 generic_spec_free(codec);
2434 return err;
790b415c
LY		 2435 }
2436
a686632f 2437 generic_hdmi_init_per_pins(codec);
7ff652ff 2438 register_i915_notifier(codec);
84eb01be
TI		 2439 return 0;
2440}
2441
7ff652ff 2442/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
e85015a3
TI		 2443static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2444{
2445 struct hdmi_spec *spec;
2446 int err;
2447
2448 /* no i915 component should have been bound before this */
2449 if (WARN_ON(codec->bus->core.audio_component))
2450 return -EBUSY;
2451
2452 err = alloc_generic_hdmi(codec);
2453 if (err < 0)
2454 return err;
2455 spec = codec->spec;
2456
2457 /* Try to bind with i915 now */
2458 err = snd_hdac_i915_init(&codec->bus->core);
2459 if (err < 0)
2460 goto error;
2461 spec->i915_bound = true;
2462
2463 err = hdmi_parse_codec(codec);
2464 if (err < 0)
2465 goto error;
2466
2467 generic_hdmi_init_per_pins(codec);
2468 register_i915_notifier(codec);
84eb01be 2469 return 0;
e85015a3
TI		 2470
2471 error:
2472 generic_spec_free(codec);
2473 return err;
84eb01be
TI		 2474}
2475
3aaf8980
SW		 2476/*
2477 * Shared non-generic implementations
2478 */
2479
2480static int simple_playback_build_pcms(struct hda_codec *codec)
2481{
2482 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2483 struct hda_pcm *info;
8ceb332d
TI		 2484 unsigned int chans;
2485 struct hda_pcm_stream *pstr;
bce0d2a8 2486 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2487
bce0d2a8
TI		 2488 per_cvt = get_cvt(spec, 0);
2489 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2490 chans = get_wcaps_channels(chans);
3aaf8980 2491
bbbc7e85 2492 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2493 if (!info)
2494 return -ENOMEM;
2bea241a 2495 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2496 info->pcm_type = HDA_PCM_TYPE_HDMI;
2497 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2498 *pstr = spec->pcm_playback;
bce0d2a8 2499 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2500 if (pstr->channels_max <= 2 && chans && chans <= 16)
2501 pstr->channels_max = chans;
3aaf8980
SW		 2502
2503 return 0;
2504}
2505
4b6ace9e
TI		 2506/* unsolicited event for jack sensing */
2507static void simple_hdmi_unsol_event(struct hda_codec *codec,
2508 unsigned int res)
2509{
9dd8cf12 2510 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2511 snd_hda_jack_report_sync(codec);
2512}
2513
2514/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2515 * as long as spec->pins[] is set correctly
2516 */
2517#define simple_hdmi_build_jack generic_hdmi_build_jack
2518
3aaf8980
SW		 2519static int simple_playback_build_controls(struct hda_codec *codec)
2520{
2521 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2522 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2523 int err;
3aaf8980 2524
bce0d2a8 2525 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2526 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2527 per_cvt->cvt_nid,
2528 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2529 if (err < 0)
2530 return err;
2531 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2532}
2533
4f0110ce
TI		 2534static int simple_playback_init(struct hda_codec *codec)
2535{
2536 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2537 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2538 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2539
2540 snd_hda_codec_write(codec, pin, 0,
2541 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2542 /* some codecs require to unmute the pin */
2543 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2544 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2545 AMP_OUT_UNMUTE);
62f949bf 2546 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2547 return 0;
2548}
2549
3aaf8980
SW		 2550static void simple_playback_free(struct hda_codec *codec)
2551{
2552 struct hdmi_spec *spec = codec->spec;
2553
bce0d2a8 2554 hdmi_array_free(spec);
3aaf8980
SW		 2555 kfree(spec);
2556}
2557
84eb01be
TI		 2558/*
2559 * Nvidia specific implementations
2560 */
2561
2562#define Nv_VERB_SET_Channel_Allocation 0xF79
2563#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2564#define Nv_VERB_SET_Audio_Protection_On 0xF98
2565#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2566
2567#define nvhdmi_master_con_nid_7x 0x04
2568#define nvhdmi_master_pin_nid_7x 0x05
2569
fb79e1e0 2570static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2571 /*front, rear, clfe, rear_surr */
2572 0x6, 0x8, 0xa, 0xc,
2573};
2574
ceaa86ba
TI		 2575static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2576 /* set audio protect on */
2577 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2578 /* enable digital output on pin widget */
2579 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2580 {} /* terminator */
2581};
2582
2583static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2584 /* set audio protect on */
2585 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2586 /* enable digital output on pin widget */
2587 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2588 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2589 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2590 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2591 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2592 {} /* terminator */
2593};
2594
2595#ifdef LIMITED_RATE_FMT_SUPPORT
2596/* support only the safe format and rate */
2597#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2598#define SUPPORTED_MAXBPS 16
2599#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2600#else
2601/* support all rates and formats */
2602#define SUPPORTED_RATES \
2603 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2604 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2605 SNDRV_PCM_RATE_192000)
2606#define SUPPORTED_MAXBPS 24
2607#define SUPPORTED_FORMATS \
2608 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2609#endif
2610
ceaa86ba
TI		 2611static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2612{
2613 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2614 return 0;
2615}
2616
2617static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2618{
ceaa86ba 2619 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2620 return 0;
2621}
2622
393004b2
ND		 2623static unsigned int channels_2_6_8[] = {
2624 2, 6, 8
2625};
2626
2627static unsigned int channels_2_8[] = {
2628 2, 8
2629};
2630
2631static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2632 .count = ARRAY_SIZE(channels_2_6_8),
2633 .list = channels_2_6_8,
2634 .mask = 0,
2635};
2636
2637static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2638 .count = ARRAY_SIZE(channels_2_8),
2639 .list = channels_2_8,
2640 .mask = 0,
2641};
2642
84eb01be
TI		 2643static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2644 struct hda_codec *codec,
2645 struct snd_pcm_substream *substream)
2646{
2647 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2648 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2649
b9a94a9c 2650 switch (codec->preset->vendor_id) {
393004b2
ND		 2651 case 0x10de0002:
2652 case 0x10de0003:
2653 case 0x10de0005:
2654 case 0x10de0006:
2655 hw_constraints_channels = &hw_constraints_2_8_channels;
2656 break;
2657 case 0x10de0007:
2658 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2659 break;
2660 default:
2661 break;
2662 }
2663
2664 if (hw_constraints_channels != NULL) {
2665 snd_pcm_hw_constraint_list(substream->runtime, 0,
2666 SNDRV_PCM_HW_PARAM_CHANNELS,
2667 hw_constraints_channels);
ad09fc9d
TI		 2668 } else {
2669 snd_pcm_hw_constraint_step(substream->runtime, 0,
2670 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2671 }
2672
84eb01be
TI		 2673 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2674}
2675
2676static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2677 struct hda_codec *codec,
2678 struct snd_pcm_substream *substream)
2679{
2680 struct hdmi_spec *spec = codec->spec;
2681 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2682}
2683
2684static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2685 struct hda_codec *codec,
2686 unsigned int stream_tag,
2687 unsigned int format,
2688 struct snd_pcm_substream *substream)
2689{
2690 struct hdmi_spec *spec = codec->spec;
2691 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2692 stream_tag, format, substream);
2693}
2694
d0b1252d
TI		 2695static const struct hda_pcm_stream simple_pcm_playback = {
2696 .substreams = 1,
2697 .channels_min = 2,
2698 .channels_max = 2,
2699 .ops = {
2700 .open = simple_playback_pcm_open,
2701 .close = simple_playback_pcm_close,
2702 .prepare = simple_playback_pcm_prepare
2703 },
2704};
2705
2706static const struct hda_codec_ops simple_hdmi_patch_ops = {
2707 .build_controls = simple_playback_build_controls,
2708 .build_pcms = simple_playback_build_pcms,
2709 .init = simple_playback_init,
2710 .free = simple_playback_free,
250e41ac 2711 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2712};
2713
2714static int patch_simple_hdmi(struct hda_codec *codec,
2715 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2716{
2717 struct hdmi_spec *spec;
bce0d2a8
TI		 2718 struct hdmi_spec_per_cvt *per_cvt;
2719 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2720
2721 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2722 if (!spec)
2723 return -ENOMEM;
2724
2725 codec->spec = spec;
bce0d2a8 2726 hdmi_array_init(spec, 1);
d0b1252d
TI		 2727
2728 spec->multiout.num_dacs = 0; /* no analog */
2729 spec->multiout.max_channels = 2;
2730 spec->multiout.dig_out_nid = cvt_nid;
2731 spec->num_cvts = 1;
2732 spec->num_pins = 1;
bce0d2a8
TI		 2733 per_pin = snd_array_new(&spec->pins);
2734 per_cvt = snd_array_new(&spec->cvts);
2735 if (!per_pin || !per_cvt) {
2736 simple_playback_free(codec);
2737 return -ENOMEM;
2738 }
2739 per_cvt->cvt_nid = cvt_nid;
2740 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2741 spec->pcm_playback = simple_pcm_playback;
2742
2743 codec->patch_ops = simple_hdmi_patch_ops;
2744
2745 return 0;
2746}
2747
1f348522
AP		 2748static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2749 int channels)
2750{
2751 unsigned int chanmask;
2752 int chan = channels ? (channels - 1) : 1;
2753
2754 switch (channels) {
2755 default:
2756 case 0:
2757 case 2:
2758 chanmask = 0x00;
2759 break;
2760 case 4:
2761 chanmask = 0x08;
2762 break;
2763 case 6:
2764 chanmask = 0x0b;
2765 break;
2766 case 8:
2767 chanmask = 0x13;
2768 break;
2769 }
2770
2771 /* Set the audio infoframe channel allocation and checksum fields. The
2772 * channel count is computed implicitly by the hardware. */
2773 snd_hda_codec_write(codec, 0x1, 0,
2774 Nv_VERB_SET_Channel_Allocation, chanmask);
2775
2776 snd_hda_codec_write(codec, 0x1, 0,
2777 Nv_VERB_SET_Info_Frame_Checksum,
2778 (0x71 - chan - chanmask));
2779}
2780
84eb01be
TI		 2781static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2782 struct hda_codec *codec,
2783 struct snd_pcm_substream *substream)
2784{
2785 struct hdmi_spec *spec = codec->spec;
2786 int i;
2787
2788 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2789 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2790 for (i = 0; i < 4; i++) {
2791 /* set the stream id */
2792 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2793 AC_VERB_SET_CHANNEL_STREAMID, 0);
2794 /* set the stream format */
2795 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2796 AC_VERB_SET_STREAM_FORMAT, 0);
2797 }
2798
1f348522
AP		 2799 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2800 * streams are disabled. */
2801 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2802
84eb01be
TI		 2803 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2804}
2805
2806static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2807 struct hda_codec *codec,
2808 unsigned int stream_tag,
2809 unsigned int format,
2810 struct snd_pcm_substream *substream)
2811{
2812 int chs;
112daa7a 2813 unsigned int dataDCC2, channel_id;
84eb01be 2814 int i;
7c935976 2815 struct hdmi_spec *spec = codec->spec;
e3245cdd 2816 struct hda_spdif_out *spdif;
bce0d2a8 2817 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2818
2819 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2820 per_cvt = get_cvt(spec, 0);
2821 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2822
2823 chs = substream->runtime->channels;
84eb01be 2824
84eb01be
TI		 2825 dataDCC2 = 0x2;
2826
84eb01be 2827 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2828 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2829 snd_hda_codec_write(codec,
2830 nvhdmi_master_con_nid_7x,
2831 0,
2832 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2833 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2834
2835 /* set the stream id */
2836 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2837 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2838
2839 /* set the stream format */
2840 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2841 AC_VERB_SET_STREAM_FORMAT, format);
2842
2843 /* turn on again (if needed) */
2844 /* enable and set the channel status audio/data flag */
7c935976 2845 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2846 snd_hda_codec_write(codec,
2847 nvhdmi_master_con_nid_7x,
2848 0,
2849 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2850 spdif->ctls & 0xff);
84eb01be
TI		 2851 snd_hda_codec_write(codec,
2852 nvhdmi_master_con_nid_7x,
2853 0,
2854 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2855 }
2856
2857 for (i = 0; i < 4; i++) {
2858 if (chs == 2)
2859 channel_id = 0;
2860 else
2861 channel_id = i * 2;
2862
2863 /* turn off SPDIF once;
2864 *otherwise the IEC958 bits won't be updated
2865 */
2866 if (codec->spdif_status_reset &&
7c935976 2867 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2868 snd_hda_codec_write(codec,
2869 nvhdmi_con_nids_7x[i],
2870 0,
2871 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2872 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2873 /* set the stream id */
2874 snd_hda_codec_write(codec,
2875 nvhdmi_con_nids_7x[i],
2876 0,
2877 AC_VERB_SET_CHANNEL_STREAMID,
2878 (stream_tag << 4) | channel_id);
2879 /* set the stream format */
2880 snd_hda_codec_write(codec,
2881 nvhdmi_con_nids_7x[i],
2882 0,
2883 AC_VERB_SET_STREAM_FORMAT,
2884 format);
2885 /* turn on again (if needed) */
2886 /* enable and set the channel status audio/data flag */
2887 if (codec->spdif_status_reset &&
7c935976 2888 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2889 snd_hda_codec_write(codec,
2890 nvhdmi_con_nids_7x[i],
2891 0,
2892 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2893 spdif->ctls & 0xff);
84eb01be
TI		 2894 snd_hda_codec_write(codec,
2895 nvhdmi_con_nids_7x[i],
2896 0,
2897 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2898 }
2899 }
2900
1f348522 2901 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2902
2903 mutex_unlock(&codec->spdif_mutex);
2904 return 0;
2905}
2906
fb79e1e0 2907static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2908 .substreams = 1,
2909 .channels_min = 2,
2910 .channels_max = 8,
2911 .nid = nvhdmi_master_con_nid_7x,
2912 .rates = SUPPORTED_RATES,
2913 .maxbps = SUPPORTED_MAXBPS,
2914 .formats = SUPPORTED_FORMATS,
2915 .ops = {
2916 .open = simple_playback_pcm_open,
2917 .close = nvhdmi_8ch_7x_pcm_close,
2918 .prepare = nvhdmi_8ch_7x_pcm_prepare
2919 },
2920};
2921
84eb01be
TI		 2922static int patch_nvhdmi_2ch(struct hda_codec *codec)
2923{
2924 struct hdmi_spec *spec;
d0b1252d
TI		 2925 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2926 nvhdmi_master_pin_nid_7x);
2927 if (err < 0)
2928 return err;
84eb01be 2929
ceaa86ba 2930 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2931 /* override the PCM rates, etc, as the codec doesn't give full list */
2932 spec = codec->spec;
2933 spec->pcm_playback.rates = SUPPORTED_RATES;
2934 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2935 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2936 return 0;
2937}
2938
53775b0d
TI		 2939static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2940{
2941 struct hdmi_spec *spec = codec->spec;
2942 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2943 if (!err) {
2944 struct hda_pcm *info = get_pcm_rec(spec, 0);
2945 info->own_chmap = true;
2946 }
53775b0d
TI		 2947 return err;
2948}
2949
2950static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2951{
2952 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2953 struct hda_pcm *info;
53775b0d
TI		 2954 struct snd_pcm_chmap *chmap;
2955 int err;
2956
2957 err = simple_playback_build_controls(codec);
2958 if (err < 0)
2959 return err;
2960
2961 /* add channel maps */
bce0d2a8
TI		 2962 info = get_pcm_rec(spec, 0);
2963 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2964 SNDRV_PCM_STREAM_PLAYBACK,
2965 snd_pcm_alt_chmaps, 8, 0, &chmap);
2966 if (err < 0)
2967 return err;
b9a94a9c 2968 switch (codec->preset->vendor_id) {
53775b0d
TI		 2969 case 0x10de0002:
2970 case 0x10de0003:
2971 case 0x10de0005:
2972 case 0x10de0006:
2973 chmap->channel_mask = (1U << 2) | (1U << 8);
2974 break;
2975 case 0x10de0007:
2976 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2977 }
2978 return 0;
2979}
2980
84eb01be
TI		 2981static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2982{
2983 struct hdmi_spec *spec;
2984 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2985 if (err < 0)
2986 return err;
2987 spec = codec->spec;
2988 spec->multiout.max_channels = 8;
d0b1252d 2989 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2990 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2991 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2992 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2993
2994 /* Initialize the audio infoframe channel mask and checksum to something
2995 * valid */
2996 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2997
84eb01be
TI		 2998 return 0;
2999}
3000
611885bc
AH		 3001/*
3002 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3003 * - 0x10de0015
3004 * - 0x10de0040
3005 */
67b90cb8 3006static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
f302240d 3007 struct hdac_cea_channel_speaker_allocation *cap, int channels)
611885bc
AH		 3008{
3009 if (cap->ca_index == 0x00 && channels == 2)
3010 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3011
028cb68e
SP		 3012 /* If the speaker allocation matches the channel count, it is OK. */
3013 if (cap->channels != channels)
3014 return -1;
3015
3016 /* all channels are remappable freely */
3017 return SNDRV_CTL_TLVT_CHMAP_VAR;
611885bc
AH		 3018}
3019
828cb4ed
SP		 3020static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3021 int ca, int chs, unsigned char *map)
611885bc
AH		 3022{
3023 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3024 return -EINVAL;
3025
3026 return 0;
3027}
3028
3029static int patch_nvhdmi(struct hda_codec *codec)
3030{
3031 struct hdmi_spec *spec;
3032 int err;
3033
3034 err = patch_generic_hdmi(codec);
3035 if (err)
3036 return err;
3037
3038 spec = codec->spec;
75fae117 3039 spec->dyn_pin_out = true;
611885bc 3040
67b90cb8 3041 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
611885bc 3042 nvhdmi_chmap_cea_alloc_validate_get_type;
67b90cb8 3043 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
611885bc
AH		 3044
3045 return 0;
3046}
3047
26e9a960
TR		 3048/*
3049 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3050 * accessed using vendor-defined verbs. These registers can be used for
3051 * interoperability between the HDA and HDMI drivers.
3052 */
3053
3054/* Audio Function Group node */
3055#define NVIDIA_AFG_NID 0x01
3056
3057/*
3058 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3059 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3060 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3061 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3062 * additional bit (at position 30) to signal the validity of the format.
3063 *
3064 * | 31 | 30 | 29 16 | 15 0 |
3065 * +---------+-------+--------+--------+
3066 * | TRIGGER | VALID | UNUSED | FORMAT |
3067 * +-----------------------------------|
3068 *
3069 * Note that for the trigger bit to take effect it needs to change value
3070 * (i.e. it needs to be toggled).
3071 */
3072#define NVIDIA_GET_SCRATCH0 0xfa6
3073#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3074#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3075#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3076#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3077#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3078#define NVIDIA_SCRATCH_VALID (1 << 6)
3079
3080#define NVIDIA_GET_SCRATCH1 0xfab
3081#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3082#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3083#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3084#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3085
3086/*
3087 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3088 * the format is invalidated so that the HDMI codec can be disabled.
3089 */
3090static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3091{
3092 unsigned int value;
3093
3094 /* bits [31:30] contain the trigger and valid bits */
3095 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3096 NVIDIA_GET_SCRATCH0, 0);
3097 value = (value >> 24) & 0xff;
3098
3099 /* bits [15:0] are used to store the HDA format */
3100 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3101 NVIDIA_SET_SCRATCH0_BYTE0,
3102 (format >> 0) & 0xff);
3103 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3104 NVIDIA_SET_SCRATCH0_BYTE1,
3105 (format >> 8) & 0xff);
3106
3107 /* bits [16:24] are unused */
3108 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3109 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3110
3111 /*
3112 * Bit 30 signals that the data is valid and hence that HDMI audio can
3113 * be enabled.
3114 */
3115 if (format == 0)
3116 value &= ~NVIDIA_SCRATCH_VALID;
3117 else
3118 value |= NVIDIA_SCRATCH_VALID;
3119
3120 /*
3121 * Whenever the trigger bit is toggled, an interrupt is raised in the
3122 * HDMI codec. The HDMI driver will use that as trigger to update its
3123 * configuration.
3124 */
3125 value ^= NVIDIA_SCRATCH_TRIGGER;
3126
3127 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3128 NVIDIA_SET_SCRATCH0_BYTE3, value);
3129}
3130
3131static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3132 struct hda_codec *codec,
3133 unsigned int stream_tag,
3134 unsigned int format,
3135 struct snd_pcm_substream *substream)
3136{
3137 int err;
3138
3139 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3140 format, substream);
3141 if (err < 0)
3142 return err;
3143
3144 /* notify the HDMI codec of the format change */
3145 tegra_hdmi_set_format(codec, format);
3146
3147 return 0;
3148}
3149
3150static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3151 struct hda_codec *codec,
3152 struct snd_pcm_substream *substream)
3153{
3154 /* invalidate the format in the HDMI codec */
3155 tegra_hdmi_set_format(codec, 0);
3156
3157 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3158}
3159
3160static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3161{
3162 struct hdmi_spec *spec = codec->spec;
3163 unsigned int i;
3164
3165 for (i = 0; i < spec->num_pins; i++) {
3166 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3167
3168 if (pcm->pcm_type == type)
3169 return pcm;
3170 }
3171
3172 return NULL;
3173}
3174
3175static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3176{
3177 struct hda_pcm_stream *stream;
3178 struct hda_pcm *pcm;
3179 int err;
3180
3181 err = generic_hdmi_build_pcms(codec);
3182 if (err < 0)
3183 return err;
3184
3185 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3186 if (!pcm)
3187 return -ENODEV;
3188
3189 /*
3190 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3191 * codec about format changes.
3192 */
3193 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3194 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3195 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3196
3197 return 0;
3198}
3199
3200static int patch_tegra_hdmi(struct hda_codec *codec)
3201{
3202 int err;
3203
3204 err = patch_generic_hdmi(codec);
3205 if (err)
3206 return err;
3207
3208 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3209
3210 return 0;
3211}
3212
84eb01be 3213/*
5a613584 3214 * ATI/AMD-specific implementations
84eb01be
TI		 3215 */
3216
5a613584 3217#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3218 ((codec)->core.vendor_id == 0x1002aa01 && \
3219 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3220#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3221
3222/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3223#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3224#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3225#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3226#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3227#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3228#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3229#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3230#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3231#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3232#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3233#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3234#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3235#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3236#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3237#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3238#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3239#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3240#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3241#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3242#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3243#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3244#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3245#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3246#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3247
84d69e79
AH		 3248/* AMD specific HDA cvt verbs */
3249#define ATI_VERB_SET_RAMP_RATE 0x770
3250#define ATI_VERB_GET_RAMP_RATE 0xf70
3251
5a613584
AH		 3252#define ATI_OUT_ENABLE 0x1
3253
3254#define ATI_MULTICHANNEL_MODE_PAIRED 0
3255#define ATI_MULTICHANNEL_MODE_SINGLE 1
3256
461cf6b3
AH		 3257#define ATI_HBR_CAPABLE 0x01
3258#define ATI_HBR_ENABLE 0x10
3259
89250f84
AH		 3260static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3261 unsigned char *buf, int *eld_size)
3262{
3263 /* call hda_eld.c ATI/AMD-specific function */
3264 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3265 is_amdhdmi_rev3_or_later(codec));
3266}
3267
5a613584
AH		 3268static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3269 int active_channels, int conn_type)
3270{
3271 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3272}
3273
3274static int atihdmi_paired_swap_fc_lfe(int pos)
3275{
3276 /*
3277 * ATI/AMD have automatic FC/LFE swap built-in
3278 * when in pairwise mapping mode.
3279 */
3280
3281 switch (pos) {
3282 /* see channel_allocations[].speakers[] */
3283 case 2: return 3;
3284 case 3: return 2;
3285 default: break;
3286 }
3287
3288 return pos;
3289}
3290
828cb4ed
SP		 3291static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3292 int ca, int chs, unsigned char *map)
5a613584 3293{
f302240d 3294 struct hdac_cea_channel_speaker_allocation *cap;
5a613584
AH		 3295 int i, j;
3296
3297 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3298
bb63f726 3299 cap = snd_hdac_get_ch_alloc_from_ca(ca);
5a613584 3300 for (i = 0; i < chs; ++i) {
bb63f726 3301 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
5a613584
AH		 3302 bool ok = false;
3303 bool companion_ok = false;
3304
3305 if (!mask)
3306 continue;
3307
3308 for (j = 0 + i % 2; j < 8; j += 2) {
3309 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3310 if (cap->speakers[chan_idx] == mask) {
3311 /* channel is in a supported position */
3312 ok = true;
3313
3314 if (i % 2 == 0 && i + 1 < chs) {
3315 /* even channel, check the odd companion */
3316 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
bb63f726 3317 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
5a613584
AH		 3318 int comp_mask_act = cap->speakers[comp_chan_idx];
3319
3320 if (comp_mask_req == comp_mask_act)
3321 companion_ok = true;
3322 else
3323 return -EINVAL;
3324 }
3325 break;
3326 }
3327 }
3328
3329 if (!ok)
3330 return -EINVAL;
3331
3332 if (companion_ok)
3333 i++; /* companion channel already checked */
3334 }
3335
3336 return 0;
3337}
3338
739ffee9
SP		 3339static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3340 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
5a613584 3341{
739ffee9 3342 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3343 int verb;
3344 int ati_channel_setup = 0;
3345
3346 if (hdmi_slot > 7)
3347 return -EINVAL;
3348
3349 if (!has_amd_full_remap_support(codec)) {
3350 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3351
3352 /* In case this is an odd slot but without stream channel, do not
3353 * disable the slot since the corresponding even slot could have a
3354 * channel. In case neither have a channel, the slot pair will be
3355 * disabled when this function is called for the even slot. */
3356 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3357 return 0;
3358
3359 hdmi_slot -= hdmi_slot % 2;
3360
3361 if (stream_channel != 0xf)
3362 stream_channel -= stream_channel % 2;
3363 }
3364
3365 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3366
3367 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3368
3369 if (stream_channel != 0xf)
3370 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3371
3372 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3373}
3374
739ffee9
SP		 3375static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3376 hda_nid_t pin_nid, int asp_slot)
5a613584 3377{
739ffee9 3378 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3379 bool was_odd = false;
3380 int ati_asp_slot = asp_slot;
3381 int verb;
3382 int ati_channel_setup;
3383
3384 if (asp_slot > 7)
3385 return -EINVAL;
3386
3387 if (!has_amd_full_remap_support(codec)) {
3388 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3389 if (ati_asp_slot % 2 != 0) {
3390 ati_asp_slot -= 1;
3391 was_odd = true;
3392 }
3393 }
3394
3395 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3396
3397 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3398
3399 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3400 return 0xf;
3401
3402 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3403}
84eb01be 3404
67b90cb8
SP		 3405static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3406 struct hdac_chmap *chmap,
f302240d 3407 struct hdac_cea_channel_speaker_allocation *cap,
67b90cb8 3408 int channels)
5a613584
AH		 3409{
3410 int c;
3411
3412 /*
3413 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3414 * we need to take that into account (a single channel may take 2
3415 * channel slots if we need to carry a silent channel next to it).
3416 * On Rev3+ AMD codecs this function is not used.
3417 */
3418 int chanpairs = 0;
3419
3420 /* We only produce even-numbered channel count TLVs */
3421 if ((channels % 2) != 0)
3422 return -1;
3423
3424 for (c = 0; c < 7; c += 2) {
3425 if (cap->speakers[c] || cap->speakers[c+1])
3426 chanpairs++;
3427 }
3428
3429 if (chanpairs * 2 != channels)
3430 return -1;
3431
3432 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3433}
3434
828cb4ed 3435static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
f302240d
SP		 3436 struct hdac_cea_channel_speaker_allocation *cap,
3437 unsigned int *chmap, int channels)
5a613584
AH		 3438{
3439 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3440 int count = 0;
3441 int c;
3442
3443 for (c = 7; c >= 0; c--) {
3444 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3445 int spk = cap->speakers[chan];
3446 if (!spk) {
3447 /* add N/A channel if the companion channel is occupied */
3448 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3449 chmap[count++] = SNDRV_CHMAP_NA;
3450
3451 continue;
3452 }
3453
bb63f726 3454 chmap[count++] = snd_hdac_spk_to_chmap(spk);
5a613584
AH		 3455 }
3456
3457 WARN_ON(count != channels);
3458}
3459
461cf6b3
AH		 3460static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3461 bool hbr)
3462{
3463 int hbr_ctl, hbr_ctl_new;
3464
3465 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3466 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3467 if (hbr)
3468 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3469 else
3470 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3471
4e76a883
TI		 3472 codec_dbg(codec,
3473 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3474 pin_nid,
3475 hbr_ctl == hbr_ctl_new ? "" : "new-",
3476 hbr_ctl_new);
3477
3478 if (hbr_ctl != hbr_ctl_new)
3479 snd_hda_codec_write(codec, pin_nid, 0,
3480 ATI_VERB_SET_HBR_CONTROL,
3481 hbr_ctl_new);
3482
3483 } else if (hbr)
3484 return -EINVAL;
3485
3486 return 0;
3487}
3488
84d69e79
AH		 3489static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3490 hda_nid_t pin_nid, u32 stream_tag, int format)
3491{
3492
3493 if (is_amdhdmi_rev3_or_later(codec)) {
3494 int ramp_rate = 180; /* default as per AMD spec */
3495 /* disable ramp-up/down for non-pcm as per AMD spec */
3496 if (format & AC_FMT_TYPE_NON_PCM)
3497 ramp_rate = 0;
3498
3499 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3500 }
3501
3502 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3503}
3504
3505
5a613584 3506static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3507{
3508 struct hdmi_spec *spec = codec->spec;
5a613584 3509 int pin_idx, err;
84eb01be 3510
5a613584
AH		 3511 err = generic_hdmi_init(codec);
3512
3513 if (err)
84eb01be 3514 return err;
5a613584
AH		 3515
3516 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3517 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3518
3519 /* make sure downmix information in infoframe is zero */
3520 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3521
3522 /* enable channel-wise remap mode if supported */
3523 if (has_amd_full_remap_support(codec))
3524 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3525 ATI_VERB_SET_MULTICHANNEL_MODE,
3526 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3527 }
5a613584 3528
84eb01be
TI		 3529 return 0;
3530}
3531
84eb01be
TI		 3532static int patch_atihdmi(struct hda_codec *codec)
3533{
3534 struct hdmi_spec *spec;
5a613584
AH		 3535 struct hdmi_spec_per_cvt *per_cvt;
3536 int err, cvt_idx;
3537
3538 err = patch_generic_hdmi(codec);
3539
3540 if (err)
d0b1252d 3541 return err;
5a613584
AH		 3542
3543 codec->patch_ops.init = atihdmi_init;
3544
d0b1252d 3545 spec = codec->spec;
5a613584 3546
89250f84 3547 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584 3548 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3549 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3550 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584 3551
39669225
TI		 3552 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3553 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3554
5a613584
AH		 3555 if (!has_amd_full_remap_support(codec)) {
3556 /* override to ATI/AMD-specific versions with pairwise mapping */
67b90cb8 3557 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
5a613584 3558 atihdmi_paired_chmap_cea_alloc_validate_get_type;
67b90cb8
SP		 3559 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3560 atihdmi_paired_cea_alloc_to_tlv_chmap;
3561 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
5a613584
AH		 3562 }
3563
3564 /* ATI/AMD converters do not advertise all of their capabilities */
3565 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3566 per_cvt = get_cvt(spec, cvt_idx);
3567 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3568 per_cvt->rates |= SUPPORTED_RATES;
3569 per_cvt->formats |= SUPPORTED_FORMATS;
3570 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3571 }
3572
67b90cb8 3573 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
5a613584 3574
84eb01be
TI		 3575 return 0;
3576}
3577
3de5ff88
AL		 3578/* VIA HDMI Implementation */
3579#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3580#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3581
3de5ff88
AL		 3582static int patch_via_hdmi(struct hda_codec *codec)
3583{
250e41ac 3584 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3585}
84eb01be
TI		 3586
3587/*
3588 * patch entries
3589 */
b9a94a9c
TI		 3590static const struct hda_device_id snd_hda_id_hdmi[] = {
3591HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3592HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3593HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3594HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3595HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3596HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3597HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3598HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3599HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3600HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3601HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3602HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3603HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3604HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3605HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3606HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3607HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3608HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3609HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3610HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3611HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3612HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3613HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3614/* 17 is known to be absent */
b9a94a9c
TI		 3615HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3616HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3617HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3618HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3619HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3620HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3621HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3622HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3623HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3624HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3625HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3626HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3627HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3628HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3629HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3630HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3631HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3632HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3633HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3634HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3635HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
2d369c74 3636HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3ec622f4 3637HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 3638HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3639HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3640HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3641HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3642HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
7ff652ff 3643HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
b9a94a9c
TI		 3644HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3645HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3646HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
7ff652ff 3647HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
e85015a3
TI		 3648HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3649HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
a686632f
TI		 3650HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3651HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3652HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3653HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3654HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
b9a94a9c 3655HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
a686632f
TI		 3656HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3657HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
b9a94a9c 3658HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3659/* special ID for generic HDMI */
b9a94a9c 3660HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3661{} /* terminator */
3662};
b9a94a9c 3663MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3664
3665MODULE_LICENSE("GPL");
3666MODULE_DESCRIPTION("HDMI HD-audio codec");
3667MODULE_ALIAS("snd-hda-codec-intelhdmi");
3668MODULE_ALIAS("snd-hda-codec-nvhdmi");
3669MODULE_ALIAS("snd-hda-codec-atihdmi");
3670
d8a766a1 3671static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3672 .id = snd_hda_id_hdmi,
84eb01be
TI		 3673};
3674
d8a766a1 3675module_hda_codec_driver(hdmi_driver);
Linux kernel - Deliverables
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