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ALSA: hda - hdmi operate spdif based on pcm
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
84eb01be
TI		 42#include "hda_codec.h"
43#include "hda_local.h"
1835a0f9 44#include "hda_jack.h"
84eb01be 45
0ebaa24c
TI		 46static bool static_hdmi_pcm;
47module_param(static_hdmi_pcm, bool, 0644);
48MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
7639a06c
TI		 50#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 53#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 54#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
432ac1a2 55#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a
LY		 56 || is_skylake(codec) || is_broxton(codec) \
57 || is_kabylake(codec))
75dcbe4d 58
7639a06c
TI		 59#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
60#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 61#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 62
384a48d7
SW		 63struct hdmi_spec_per_cvt {
64 hda_nid_t cvt_nid;
65 int assigned;
66 unsigned int channels_min;
67 unsigned int channels_max;
68 u32 rates;
69 u64 formats;
70 unsigned int maxbps;
71};
079d88cc 72
4eea3091
TI		 73/* max. connections to a widget */
74#define HDA_MAX_CONNECTIONS 32
75
384a48d7
SW		 76struct hdmi_spec_per_pin {
77 hda_nid_t pin_nid;
78 int num_mux_nids;
79 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 80 int mux_idx;
1df5a06a 81 hda_nid_t cvt_nid;
744626da
WF		 82
83 struct hda_codec *codec;
384a48d7 84 struct hdmi_eld sink_eld;
a4e9a38b 85 struct mutex lock;
744626da 86 struct delayed_work work;
92c69e79 87 struct snd_kcontrol *eld_ctl;
788d441a 88 struct snd_jack *acomp_jack; /* jack via audio component */
6590faab 89 struct hda_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
c6e8453e 90 int repoll_count;
b054087d
TI		 91 bool setup; /* the stream has been set up by prepare callback */
92 int channels; /* current number of channels */
1a6003b5 93 bool non_pcm;
d45e6889
TI		 94 bool chmap_set; /* channel-map override by ALSA API? */
95 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 96#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 97 struct snd_info_entry *proc_entry;
98#endif
384a48d7 99};
079d88cc 100
307229d2
AH		 101struct cea_channel_speaker_allocation;
102
103/* operations used by generic code that can be overridden by patches */
104struct hdmi_ops {
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
107
108 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
109 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int asp_slot);
111 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int asp_slot, int channel);
113
114 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
115 int ca, int active_channels, int conn_type);
116
117 /* enable/disable HBR (HD passthrough) */
118 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
119
120 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
121 hda_nid_t pin_nid, u32 stream_tag, int format);
122
123 /* Helpers for producing the channel map TLVs. These can be overridden
124 * for devices that have non-standard mapping requirements. */
125 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
126 int channels);
127 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
128 unsigned int *chmap, int channels);
129
130 /* check that the user-given chmap is supported */
131 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
132};
133
384a48d7
SW		 134struct hdmi_spec {
135 int num_cvts;
bce0d2a8
TI		 136 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
137 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 138
384a48d7 139 int num_pins;
bce0d2a8 140 struct snd_array pins; /* struct hdmi_spec_per_pin */
bbbc7e85 141 struct hda_pcm *pcm_rec[16];
42b29870 142 struct mutex pcm_lock;
2bf3c85a 143 int pcm_used; /* counter of pcm_rec[] */
d45e6889 144 unsigned int channels_max; /* max over all cvts */
079d88cc 145
4bd038f9 146 struct hdmi_eld temp_eld;
307229d2 147 struct hdmi_ops ops;
75fae117
SW		 148
149 bool dyn_pin_out;
6590faab 150 bool dyn_pcm_assign;
079d88cc 151 /*
5a613584 152 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 153 */
154 struct hda_multi_out multiout;
d0b1252d 155 struct hda_pcm_stream pcm_playback;
25adc137
DH		 156
157 /* i915/powerwell (Haswell+/Valleyview+) specific */
158 struct i915_audio_component_audio_ops i915_audio_ops;
55913110 159 bool i915_bound; /* was i915 bound in this driver? */
079d88cc
WF		 160};
161
f4e3040b 162#ifdef CONFIG_SND_HDA_I915
6603249d
TI		 163#define codec_has_acomp(codec) \
164 ((codec)->bus->core.audio_component != NULL)
f4e3040b
TI		 165#else
166#define codec_has_acomp(codec) false
167#endif
079d88cc
WF		 168
169struct hdmi_audio_infoframe {
170 u8 type; /* 0x84 */
171 u8 ver; /* 0x01 */
172 u8 len; /* 0x0a */
173
53d7d69d
WF		 174 u8 checksum;
175
079d88cc
WF		 176 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
177 u8 SS01_SF24;
178 u8 CXT04;
179 u8 CA;
180 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 181};
182
183struct dp_audio_infoframe {
184 u8 type; /* 0x84 */
185 u8 len; /* 0x1b */
186 u8 ver; /* 0x11 << 2 */
187
188 u8 CC02_CT47; /* match with HDMI infoframe from this on */
189 u8 SS01_SF24;
190 u8 CXT04;
191 u8 CA;
192 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 193};
194
2b203dbb
TI		 195union audio_infoframe {
196 struct hdmi_audio_infoframe hdmi;
197 struct dp_audio_infoframe dp;
198 u8 bytes[0];
199};
200
079d88cc
WF		 201/*
202 * CEA speaker placement:
203 *
204 * FLH FCH FRH
205 * FLW FL FLC FC FRC FR FRW
206 *
207 * LFE
208 * TC
209 *
210 * RL RLC RC RRC RR
211 *
212 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
213 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
214 */
215enum cea_speaker_placement {
216 FL = (1 << 0), /* Front Left */
217 FC = (1 << 1), /* Front Center */
218 FR = (1 << 2), /* Front Right */
219 FLC = (1 << 3), /* Front Left Center */
220 FRC = (1 << 4), /* Front Right Center */
221 RL = (1 << 5), /* Rear Left */
222 RC = (1 << 6), /* Rear Center */
223 RR = (1 << 7), /* Rear Right */
224 RLC = (1 << 8), /* Rear Left Center */
225 RRC = (1 << 9), /* Rear Right Center */
226 LFE = (1 << 10), /* Low Frequency Effect */
227 FLW = (1 << 11), /* Front Left Wide */
228 FRW = (1 << 12), /* Front Right Wide */
229 FLH = (1 << 13), /* Front Left High */
230 FCH = (1 << 14), /* Front Center High */
231 FRH = (1 << 15), /* Front Right High */
232 TC = (1 << 16), /* Top Center */
233};
234
235/*
236 * ELD SA bits in the CEA Speaker Allocation data block
237 */
238static int eld_speaker_allocation_bits[] = {
239 [0] = FL | FR,
240 [1] = LFE,
241 [2] = FC,
242 [3] = RL | RR,
243 [4] = RC,
244 [5] = FLC | FRC,
245 [6] = RLC | RRC,
246 /* the following are not defined in ELD yet */
247 [7] = FLW | FRW,
248 [8] = FLH | FRH,
249 [9] = TC,
250 [10] = FCH,
251};
252
253struct cea_channel_speaker_allocation {
254 int ca_index;
255 int speakers[8];
256
257 /* derived values, just for convenience */
258 int channels;
259 int spk_mask;
260};
261
262/*
263 * ALSA sequence is:
264 *
265 * surround40 surround41 surround50 surround51 surround71
266 * ch0 front left = = = =
267 * ch1 front right = = = =
268 * ch2 rear left = = = =
269 * ch3 rear right = = = =
270 * ch4 LFE center center center
271 * ch5 LFE LFE
272 * ch6 side left
273 * ch7 side right
274 *
275 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
276 */
277static int hdmi_channel_mapping[0x32][8] = {
278 /* stereo */
279 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
280 /* 2.1 */
281 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
282 /* Dolby Surround */
283 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
284 /* surround40 */
285 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
286 /* 4ch */
287 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
288 /* surround41 */
9396d317 289 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 290 /* surround50 */
291 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
292 /* surround51 */
293 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
294 /* 7.1 */
295 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
296};
297
298/*
299 * This is an ordered list!
300 *
301 * The preceding ones have better chances to be selected by
53d7d69d 302 * hdmi_channel_allocation().
079d88cc
WF		 303 */
304static struct cea_channel_speaker_allocation channel_allocations[] = {
305/* channel: 7 6 5 4 3 2 1 0 */
306{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
307 /* 2.1 */
308{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
309 /* Dolby Surround */
310{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
311 /* surround40 */
312{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
313 /* surround41 */
314{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
315 /* surround50 */
316{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
317 /* surround51 */
318{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
319 /* 6.1 */
320{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
321 /* surround71 */
322{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
323
324{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
325{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
326{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
327{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
328{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
329{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
330{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
331{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
332{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
333{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
334{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
336{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
337{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
338{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
339{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
340{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
341{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
342{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
343{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
344{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
345{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
346{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
347{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
348{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
349{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
350{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
351{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
352{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
353{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
354{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
355{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
356{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
357{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
358{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
359{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
360{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
361{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
362{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
363{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
364{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
365};
366
367
368/*
369 * HDMI routines
370 */
371
bce0d2a8
TI		 372#define get_pin(spec, idx) \
373 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
374#define get_cvt(spec, idx) \
375 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
bbbc7e85 376#define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
bce0d2a8 377
4e76a883 378static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 379{
4e76a883 380 struct hdmi_spec *spec = codec->spec;
384a48d7 381 int pin_idx;
079d88cc 382
384a48d7 383 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 384 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 385 return pin_idx;
079d88cc 386
4e76a883 387 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 388 return -EINVAL;
389}
390
2bf3c85a
LY		 391static int hinfo_to_pcm_index(struct hda_codec *codec,
392 struct hda_pcm_stream *hinfo)
393{
394 struct hdmi_spec *spec = codec->spec;
395 int pcm_idx;
396
397 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
398 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
399 return pcm_idx;
400
401 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
402 return -EINVAL;
403}
404
4e76a883 405static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 406 struct hda_pcm_stream *hinfo)
407{
4e76a883 408 struct hdmi_spec *spec = codec->spec;
6590faab 409 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 410 int pin_idx;
411
6590faab
LY		 412 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
413 per_pin = get_pin(spec, pin_idx);
414 if (per_pin->pcm && per_pin->pcm->stream == hinfo)
384a48d7 415 return pin_idx;
6590faab 416 }
384a48d7 417
6590faab 418 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 419 return -EINVAL;
420}
421
4e76a883 422static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 423{
4e76a883 424 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 425 int cvt_idx;
426
427 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 428 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 429 return cvt_idx;
430
4e76a883 431 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 432 return -EINVAL;
433}
434
14bc52b8
PLB		 435static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_info *uinfo)
437{
438 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 439 struct hdmi_spec *spec = codec->spec;
a4e9a38b 440 struct hdmi_spec_per_pin *per_pin;
68e03de9 441 struct hdmi_eld *eld;
14bc52b8
PLB		 442 int pin_idx;
443
14bc52b8
PLB		 444 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
445
446 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 447 per_pin = get_pin(spec, pin_idx);
448 eld = &per_pin->sink_eld;
68e03de9 449
a4e9a38b 450 mutex_lock(&per_pin->lock);
68e03de9 451 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 452 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 453
454 return 0;
455}
456
457static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
458 struct snd_ctl_elem_value *ucontrol)
459{
460 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 461 struct hdmi_spec *spec = codec->spec;
a4e9a38b 462 struct hdmi_spec_per_pin *per_pin;
68e03de9 463 struct hdmi_eld *eld;
14bc52b8
PLB		 464 int pin_idx;
465
14bc52b8 466 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 467 per_pin = get_pin(spec, pin_idx);
468 eld = &per_pin->sink_eld;
68e03de9 469
a4e9a38b 470 mutex_lock(&per_pin->lock);
68e03de9 471 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 472 mutex_unlock(&per_pin->lock);
68e03de9
DH		 473 snd_BUG();
474 return -EINVAL;
475 }
476
477 memset(ucontrol->value.bytes.data, 0,
478 ARRAY_SIZE(ucontrol->value.bytes.data));
479 if (eld->eld_valid)
480 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
481 eld->eld_size);
a4e9a38b 482 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 483
484 return 0;
485}
486
487static struct snd_kcontrol_new eld_bytes_ctl = {
488 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
489 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
490 .name = "ELD",
491 .info = hdmi_eld_ctl_info,
492 .get = hdmi_eld_ctl_get,
493};
494
495static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
496 int device)
497{
498 struct snd_kcontrol *kctl;
499 struct hdmi_spec *spec = codec->spec;
500 int err;
501
502 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
503 if (!kctl)
504 return -ENOMEM;
505 kctl->private_value = pin_idx;
506 kctl->id.device = device;
507
bce0d2a8 508 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 509 if (err < 0)
510 return err;
511
bce0d2a8 512 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 513 return 0;
514}
515
079d88cc
WF		 516#ifdef BE_PARANOID
517static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
518 int *packet_index, int *byte_index)
519{
520 int val;
521
522 val = snd_hda_codec_read(codec, pin_nid, 0,
523 AC_VERB_GET_HDMI_DIP_INDEX, 0);
524
525 *packet_index = val >> 5;
526 *byte_index = val & 0x1f;
527}
528#endif
529
530static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
531 int packet_index, int byte_index)
532{
533 int val;
534
535 val = (packet_index << 5) | (byte_index & 0x1f);
536
537 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
538}
539
540static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
541 unsigned char val)
542{
543 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
544}
545
384a48d7 546static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 547{
75fae117
SW		 548 struct hdmi_spec *spec = codec->spec;
549 int pin_out;
550
079d88cc
WF		 551 /* Unmute */
552 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
553 snd_hda_codec_write(codec, pin_nid, 0,
554 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 555
556 if (spec->dyn_pin_out)
557 /* Disable pin out until stream is active */
558 pin_out = 0;
559 else
560 /* Enable pin out: some machines with GM965 gets broken output
561 * when the pin is disabled or changed while using with HDMI
562 */
563 pin_out = PIN_OUT;
564
079d88cc 565 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 566 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 567}
568
384a48d7 569static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 570{
384a48d7 571 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 572 AC_VERB_GET_CVT_CHAN_COUNT, 0);
573}
574
575static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 576 hda_nid_t cvt_nid, int chs)
079d88cc 577{
384a48d7
SW		 578 if (chs != hdmi_get_channel_count(codec, cvt_nid))
579 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 580 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
581}
582
a4e9a38b
TI		 583/*
584 * ELD proc files
585 */
586
cd6a6503 587#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 588static void print_eld_info(struct snd_info_entry *entry,
589 struct snd_info_buffer *buffer)
590{
591 struct hdmi_spec_per_pin *per_pin = entry->private_data;
592
593 mutex_lock(&per_pin->lock);
594 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
595 mutex_unlock(&per_pin->lock);
596}
597
598static void write_eld_info(struct snd_info_entry *entry,
599 struct snd_info_buffer *buffer)
600{
601 struct hdmi_spec_per_pin *per_pin = entry->private_data;
602
603 mutex_lock(&per_pin->lock);
604 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
605 mutex_unlock(&per_pin->lock);
606}
607
608static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
609{
610 char name[32];
611 struct hda_codec *codec = per_pin->codec;
612 struct snd_info_entry *entry;
613 int err;
614
615 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 616 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 617 if (err < 0)
618 return err;
619
620 snd_info_set_text_ops(entry, per_pin, print_eld_info);
621 entry->c.text.write = write_eld_info;
622 entry->mode |= S_IWUSR;
623 per_pin->proc_entry = entry;
624
625 return 0;
626}
627
628static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
629{
1947a114 630 if (!per_pin->codec->bus->shutdown) {
c560a679 631 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 632 per_pin->proc_entry = NULL;
633 }
634}
635#else
b55447a7
TI		 636static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
637 int index)
a4e9a38b
TI		 638{
639 return 0;
640}
b55447a7 641static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 642{
643}
644#endif
079d88cc
WF		 645
646/*
647 * Channel mapping routines
648 */
649
650/*
651 * Compute derived values in channel_allocations[].
652 */
653static void init_channel_allocations(void)
654{
655 int i, j;
656 struct cea_channel_speaker_allocation *p;
657
658 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
659 p = channel_allocations + i;
660 p->channels = 0;
661 p->spk_mask = 0;
662 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
663 if (p->speakers[j]) {
664 p->channels++;
665 p->spk_mask |= p->speakers[j];
666 }
667 }
668}
669
72357c78
WX		 670static int get_channel_allocation_order(int ca)
671{
672 int i;
673
674 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
675 if (channel_allocations[i].ca_index == ca)
676 break;
677 }
678 return i;
679}
680
079d88cc
WF		 681/*
682 * The transformation takes two steps:
683 *
684 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
685 * spk_mask => (channel_allocations[]) => ai->CA
686 *
687 * TODO: it could select the wrong CA from multiple candidates.
688*/
79514d47
TI		 689static int hdmi_channel_allocation(struct hda_codec *codec,
690 struct hdmi_eld *eld, int channels)
079d88cc 691{
079d88cc 692 int i;
53d7d69d 693 int ca = 0;
079d88cc 694 int spk_mask = 0;
079d88cc
WF		 695 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
696
697 /*
698 * CA defaults to 0 for basic stereo audio
699 */
700 if (channels <= 2)
701 return 0;
702
079d88cc
WF		 703 /*
704 * expand ELD's speaker allocation mask
705 *
706 * ELD tells the speaker mask in a compact(paired) form,
707 * expand ELD's notions to match the ones used by Audio InfoFrame.
708 */
709 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 710 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 711 spk_mask |= eld_speaker_allocation_bits[i];
712 }
713
714 /* search for the first working match in the CA table */
715 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
716 if (channels == channel_allocations[i].channels &&
717 (spk_mask & channel_allocations[i].spk_mask) ==
718 channel_allocations[i].spk_mask) {
53d7d69d 719 ca = channel_allocations[i].ca_index;
079d88cc
WF		 720 break;
721 }
722 }
723
18e39186
AH		 724 if (!ca) {
725 /* if there was no match, select the regular ALSA channel
726 * allocation with the matching number of channels */
727 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
728 if (channels == channel_allocations[i].channels) {
729 ca = channel_allocations[i].ca_index;
730 break;
731 }
732 }
733 }
734
1613d6b4 735 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
79514d47 736 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 737 ca, channels, buf);
079d88cc 738
53d7d69d 739 return ca;
079d88cc
WF		 740}
741
742static void hdmi_debug_channel_mapping(struct hda_codec *codec,
743 hda_nid_t pin_nid)
744{
745#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 746 struct hdmi_spec *spec = codec->spec;
079d88cc 747 int i;
307229d2 748 int channel;
079d88cc
WF		 749
750 for (i = 0; i < 8; i++) {
307229d2 751 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 752 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 753 channel, i);
079d88cc
WF		 754 }
755#endif
756}
757
d45e6889 758static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 759 hda_nid_t pin_nid,
433968da 760 bool non_pcm,
53d7d69d 761 int ca)
079d88cc 762{
307229d2 763 struct hdmi_spec *spec = codec->spec;
90f28002 764 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 765 int i;
079d88cc 766 int err;
72357c78 767 int order;
433968da 768 int non_pcm_mapping[8];
079d88cc 769
72357c78 770 order = get_channel_allocation_order(ca);
90f28002 771 ch_alloc = &channel_allocations[order];
433968da 772
079d88cc 773 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 774 int hdmi_slot = 0;
775 /* fill actual channel mappings in ALSA channel (i) order */
776 for (i = 0; i < ch_alloc->channels; i++) {
777 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
778 hdmi_slot++; /* skip zero slots */
779
780 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
781 }
782 /* fill the rest of the slots with ALSA channel 0xf */
783 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
784 if (!ch_alloc->speakers[7 - hdmi_slot])
785 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 786 }
787
433968da 788 if (non_pcm) {
90f28002 789 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 790 non_pcm_mapping[i] = (i << 4) | i;
433968da 791 for (; i < 8; i++)
11f7c52d 792 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 793 }
794
079d88cc 795 for (i = 0; i < 8; i++) {
307229d2
AH		 796 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
797 int hdmi_slot = slotsetup & 0x0f;
798 int channel = (slotsetup & 0xf0) >> 4;
799 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 800 if (err) {
4e76a883 801 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 802 break;
803 }
804 }
079d88cc
WF		 805}
806
d45e6889
TI		 807struct channel_map_table {
808 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 809 int spk_mask; /* speaker position bit mask */
810};
811
812static struct channel_map_table map_tables[] = {
a5b7d510
AH		 813 { SNDRV_CHMAP_FL, FL },
814 { SNDRV_CHMAP_FR, FR },
815 { SNDRV_CHMAP_RL, RL },
816 { SNDRV_CHMAP_RR, RR },
817 { SNDRV_CHMAP_LFE, LFE },
818 { SNDRV_CHMAP_FC, FC },
819 { SNDRV_CHMAP_RLC, RLC },
820 { SNDRV_CHMAP_RRC, RRC },
821 { SNDRV_CHMAP_RC, RC },
822 { SNDRV_CHMAP_FLC, FLC },
823 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 824 { SNDRV_CHMAP_TFL, FLH },
825 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 826 { SNDRV_CHMAP_FLW, FLW },
827 { SNDRV_CHMAP_FRW, FRW },
828 { SNDRV_CHMAP_TC, TC },
94908a39 829 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 830 {} /* terminator */
831};
832
833/* from ALSA API channel position to speaker bit mask */
834static int to_spk_mask(unsigned char c)
835{
836 struct channel_map_table *t = map_tables;
837 for (; t->map; t++) {
838 if (t->map == c)
839 return t->spk_mask;
840 }
841 return 0;
842}
843
844/* from ALSA API channel position to CEA slot */
a5b7d510 845static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 846{
a5b7d510
AH		 847 int mask = to_spk_mask(pos);
848 int i;
d45e6889 849
a5b7d510
AH		 850 if (mask) {
851 for (i = 0; i < 8; i++) {
852 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
853 return i;
854 }
d45e6889 855 }
a5b7d510
AH		 856
857 return -1;
d45e6889
TI		 858}
859
860/* from speaker bit mask to ALSA API channel position */
861static int spk_to_chmap(int spk)
862{
863 struct channel_map_table *t = map_tables;
864 for (; t->map; t++) {
865 if (t->spk_mask == spk)
866 return t->map;
867 }
868 return 0;
869}
870
a5b7d510
AH		 871/* from CEA slot to ALSA API channel position */
872static int from_cea_slot(int ordered_ca, unsigned char slot)
873{
874 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
875
876 return spk_to_chmap(mask);
877}
878
d45e6889
TI		 879/* get the CA index corresponding to the given ALSA API channel map */
880static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
881{
882 int i, spks = 0, spk_mask = 0;
883
884 for (i = 0; i < chs; i++) {
885 int mask = to_spk_mask(map[i]);
886 if (mask) {
887 spk_mask |= mask;
888 spks++;
889 }
890 }
891
892 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
893 if ((chs == channel_allocations[i].channels ||
894 spks == channel_allocations[i].channels) &&
895 (spk_mask & channel_allocations[i].spk_mask) ==
896 channel_allocations[i].spk_mask)
897 return channel_allocations[i].ca_index;
898 }
899 return -1;
900}
901
902/* set up the channel slots for the given ALSA API channel map */
903static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
904 hda_nid_t pin_nid,
a5b7d510
AH		 905 int chs, unsigned char *map,
906 int ca)
d45e6889 907{
307229d2 908 struct hdmi_spec *spec = codec->spec;
a5b7d510 909 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 910 int alsa_pos, hdmi_slot;
911 int assignments[8] = {[0 ... 7] = 0xf};
912
913 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
914
a5b7d510 915 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 916
917 if (hdmi_slot < 0)
918 continue; /* unassigned channel */
919
920 assignments[hdmi_slot] = alsa_pos;
921 }
922
923 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 924 int err;
11f7c52d 925
307229d2
AH		 926 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
927 assignments[hdmi_slot]);
d45e6889
TI		 928 if (err)
929 return -EINVAL;
930 }
931 return 0;
932}
933
934/* store ALSA API channel map from the current default map */
935static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
936{
937 int i;
56cac413 938 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 939 for (i = 0; i < 8; i++) {
56cac413 940 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 941 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 942 else
943 map[i] = 0;
944 }
945}
946
947static void hdmi_setup_channel_mapping(struct hda_codec *codec,
948 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 949 int channels, unsigned char *map,
950 bool chmap_set)
d45e6889 951{
20608731 952 if (!non_pcm && chmap_set) {
d45e6889 953 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 954 channels, map, ca);
d45e6889
TI		 955 } else {
956 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
957 hdmi_setup_fake_chmap(map, ca);
958 }
980b2495
AH		 959
960 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 961}
079d88cc 962
307229d2
AH		 963static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
964 int asp_slot, int channel)
965{
966 return snd_hda_codec_write(codec, pin_nid, 0,
967 AC_VERB_SET_HDMI_CHAN_SLOT,
968 (channel << 4) | asp_slot);
969}
970
971static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
972 int asp_slot)
973{
974 return (snd_hda_codec_read(codec, pin_nid, 0,
975 AC_VERB_GET_HDMI_CHAN_SLOT,
976 asp_slot) & 0xf0) >> 4;
977}
978
079d88cc
WF		 979/*
980 * Audio InfoFrame routines
981 */
982
983/*
984 * Enable Audio InfoFrame Transmission
985 */
986static void hdmi_start_infoframe_trans(struct hda_codec *codec,
987 hda_nid_t pin_nid)
988{
989 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
990 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
991 AC_DIPXMIT_BEST);
992}
993
994/*
995 * Disable Audio InfoFrame Transmission
996 */
997static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
998 hda_nid_t pin_nid)
999{
1000 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1001 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
1002 AC_DIPXMIT_DISABLE);
1003}
1004
1005static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
1006{
1007#ifdef CONFIG_SND_DEBUG_VERBOSE
1008 int i;
1009 int size;
1010
1011 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 1012 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 1013
1014 for (i = 0; i < 8; i++) {
1015 size = snd_hda_codec_read(codec, pin_nid, 0,
1016 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 1017 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 1018 }
1019#endif
1020}
1021
1022static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
1023{
1024#ifdef BE_PARANOID
1025 int i, j;
1026 int size;
1027 int pi, bi;
1028 for (i = 0; i < 8; i++) {
1029 size = snd_hda_codec_read(codec, pin_nid, 0,
1030 AC_VERB_GET_HDMI_DIP_SIZE, i);
1031 if (size == 0)
1032 continue;
1033
1034 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1035 for (j = 1; j < 1000; j++) {
1036 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1037 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1038 if (pi != i)
4e76a883 1039 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1040 bi, pi, i);
1041 if (bi == 0) /* byte index wrapped around */
1042 break;
1043 }
4e76a883 1044 codec_dbg(codec,
079d88cc
WF		 1045 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1046 i, size, j);
1047 }
1048#endif
1049}
1050
53d7d69d 1051static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1052{
53d7d69d 1053 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1054 u8 sum = 0;
1055 int i;
1056
53d7d69d 1057 hdmi_ai->checksum = 0;
079d88cc 1058
53d7d69d 1059 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1060 sum += bytes[i];
1061
53d7d69d 1062 hdmi_ai->checksum = -sum;
079d88cc
WF		 1063}
1064
1065static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1066 hda_nid_t pin_nid,
53d7d69d 1067 u8 *dip, int size)
079d88cc 1068{
079d88cc
WF		 1069 int i;
1070
1071 hdmi_debug_dip_size(codec, pin_nid);
1072 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1073
079d88cc 1074 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1075 for (i = 0; i < size; i++)
1076 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1077}
1078
1079static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1080 u8 *dip, int size)
079d88cc 1081{
079d88cc
WF		 1082 u8 val;
1083 int i;
1084
1085 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1086 != AC_DIPXMIT_BEST)
1087 return false;
1088
1089 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1090 for (i = 0; i < size; i++) {
079d88cc
WF		 1091 val = snd_hda_codec_read(codec, pin_nid, 0,
1092 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1093 if (val != dip[i])
079d88cc
WF		 1094 return false;
1095 }
1096
1097 return true;
1098}
1099
307229d2
AH		 1100static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1101 hda_nid_t pin_nid,
1102 int ca, int active_channels,
1103 int conn_type)
1104{
1105 union audio_infoframe ai;
1106
caaf5ef9 1107 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1108 if (conn_type == 0) { /* HDMI */
1109 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1110
1111 hdmi_ai->type = 0x84;
1112 hdmi_ai->ver = 0x01;
1113 hdmi_ai->len = 0x0a;
1114 hdmi_ai->CC02_CT47 = active_channels - 1;
1115 hdmi_ai->CA = ca;
1116 hdmi_checksum_audio_infoframe(hdmi_ai);
1117 } else if (conn_type == 1) { /* DisplayPort */
1118 struct dp_audio_infoframe *dp_ai = &ai.dp;
1119
1120 dp_ai->type = 0x84;
1121 dp_ai->len = 0x1b;
1122 dp_ai->ver = 0x11 << 2;
1123 dp_ai->CC02_CT47 = active_channels - 1;
1124 dp_ai->CA = ca;
1125 } else {
4e76a883 1126 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1127 pin_nid);
1128 return;
1129 }
1130
1131 /*
1132 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1133 * sizeof(*dp_ai) to avoid partial match/update problems when
1134 * the user switches between HDMI/DP monitors.
1135 */
1136 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1137 sizeof(ai))) {
4e76a883
TI		 1138 codec_dbg(codec,
1139 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1140 pin_nid,
1141 active_channels, ca);
1142 hdmi_stop_infoframe_trans(codec, pin_nid);
1143 hdmi_fill_audio_infoframe(codec, pin_nid,
1144 ai.bytes, sizeof(ai));
1145 hdmi_start_infoframe_trans(codec, pin_nid);
1146 }
1147}
1148
b054087d
TI		 1149static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1150 struct hdmi_spec_per_pin *per_pin,
1151 bool non_pcm)
079d88cc 1152{
307229d2 1153 struct hdmi_spec *spec = codec->spec;
384a48d7 1154 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1155 int channels = per_pin->channels;
1df5a06a 1156 int active_channels;
384a48d7 1157 struct hdmi_eld *eld;
1df5a06a 1158 int ca, ordered_ca;
079d88cc 1159
b054087d
TI		 1160 if (!channels)
1161 return;
1162
75dcbe4d 1163 if (is_haswell_plus(codec))
58f7d28d
ML		 1164 snd_hda_codec_write(codec, pin_nid, 0,
1165 AC_VERB_SET_AMP_GAIN_MUTE,
1166 AMP_OUT_UNMUTE);
1167
bce0d2a8 1168 eld = &per_pin->sink_eld;
079d88cc 1169
d45e6889
TI		 1170 if (!non_pcm && per_pin->chmap_set)
1171 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1172 else
79514d47 1173 ca = hdmi_channel_allocation(codec, eld, channels);
d45e6889
TI		 1174 if (ca < 0)
1175 ca = 0;
384a48d7 1176
1df5a06a
AH		 1177 ordered_ca = get_channel_allocation_order(ca);
1178 active_channels = channel_allocations[ordered_ca].channels;
1179
1180 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1181
39edac70
AH		 1182 /*
1183 * always configure channel mapping, it may have been changed by the
1184 * user in the meantime
1185 */
1186 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1187 channels, per_pin->chmap,
1188 per_pin->chmap_set);
1189
307229d2
AH		 1190 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1191 eld->info.conn_type);
433968da 1192
1a6003b5 1193 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1194}
1195
079d88cc
WF		 1196/*
1197 * Unsolicited events
1198 */
1199
efe47108 1200static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1201
1a4f69d5 1202static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 1203{
1204 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 1205 int pin_idx = pin_nid_to_pin_index(codec, nid);
1206
20ce9029
DH		 1207 if (pin_idx < 0)
1208 return;
20ce9029
DH		 1209 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1210 snd_hda_jack_report_sync(codec);
1211}
1212
1a4f69d5
TI		 1213static void jack_callback(struct hda_codec *codec,
1214 struct hda_jack_callback *jack)
1215{
1216 check_presence_and_report(codec, jack->tbl->nid);
1217}
1218
20ce9029
DH		 1219static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1220{
3a93897e 1221 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1222 struct hda_jack_tbl *jack;
2e59e5ab 1223 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1224
1225 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1226 if (!jack)
1227 return;
3a93897e 1228 jack->jack_dirty = 1;
079d88cc 1229
4e76a883 1230 codec_dbg(codec,
2e59e5ab 1231 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1232 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1233 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1234
1a4f69d5 1235 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 1236}
1237
1238static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1239{
1240 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1241 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1242 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1243 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1244
4e76a883 1245 codec_info(codec,
e9ea8e8f 1246 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1247 codec->addr,
079d88cc
WF		 1248 tag,
1249 subtag,
1250 cp_state,
1251 cp_ready);
1252
1253 /* TODO */
1254 if (cp_state)
1255 ;
1256 if (cp_ready)
1257 ;
1258}
1259
1260
1261static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1262{
079d88cc
WF		 1263 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1264 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1265
3a93897e 1266 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1267 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1268 return;
1269 }
1270
1271 if (subtag == 0)
1272 hdmi_intrinsic_event(codec, res);
1273 else
1274 hdmi_non_intrinsic_event(codec, res);
1275}
1276
58f7d28d 1277static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1278 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1279{
58f7d28d 1280 int pwr;
83f26ad2 1281
53b434f0
WX		 1282 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1283 * thus pins could only choose converter 0 for use. Make sure the
1284 * converters are in correct power state */
fd678cac 1285 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1286 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1287
fd678cac 1288 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1289 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1290 AC_PWRST_D0);
1291 msleep(40);
1292 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1293 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1294 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1295 }
83f26ad2
DH		 1296}
1297
079d88cc
WF		 1298/*
1299 * Callbacks
1300 */
1301
92f10b3f
TI		 1302/* HBR should be Non-PCM, 8 channels */
1303#define is_hbr_format(format) \
1304 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1305
307229d2
AH		 1306static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1307 bool hbr)
079d88cc 1308{
307229d2 1309 int pinctl, new_pinctl;
83f26ad2 1310
384a48d7
SW		 1311 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1312 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1313 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1314
13122e6e
AH		 1315 if (pinctl < 0)
1316 return hbr ? -EINVAL : 0;
1317
ea87d1c4 1318 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1319 if (hbr)
ea87d1c4
AH		 1320 new_pinctl |= AC_PINCTL_EPT_HBR;
1321 else
1322 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1323
4e76a883
TI		 1324 codec_dbg(codec,
1325 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1326 pin_nid,
ea87d1c4
AH		 1327 pinctl == new_pinctl ? "" : "new-",
1328 new_pinctl);
1329
1330 if (pinctl != new_pinctl)
384a48d7 1331 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1332 AC_VERB_SET_PIN_WIDGET_CONTROL,
1333 new_pinctl);
307229d2
AH		 1334 } else if (hbr)
1335 return -EINVAL;
ea87d1c4 1336
307229d2
AH		 1337 return 0;
1338}
1339
1340static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1341 hda_nid_t pin_nid, u32 stream_tag, int format)
1342{
1343 struct hdmi_spec *spec = codec->spec;
1344 int err;
1345
75dcbe4d 1346 if (is_haswell_plus(codec))
307229d2
AH		 1347 haswell_verify_D0(codec, cvt_nid, pin_nid);
1348
1349 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1350
1351 if (err) {
4e76a883 1352 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1353 return err;
ea87d1c4 1354 }
079d88cc 1355
384a48d7 1356 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1357 return 0;
079d88cc
WF		 1358}
1359
42b29870
LY		 1360/* Try to find an available converter
1361 * If pin_idx is less then zero, just try to find an available converter.
1362 * Otherwise, try to find an available converter and get the cvt mux index
1363 * of the pin.
1364 */
7ef166b8
WX		 1365static int hdmi_choose_cvt(struct hda_codec *codec,
1366 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1367{
1368 struct hdmi_spec *spec = codec->spec;
384a48d7 1369 struct hdmi_spec_per_pin *per_pin;
384a48d7 1370 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1371 int cvt_idx, mux_idx = 0;
bbbe3390 1372
42b29870
LY		 1373 /* pin_idx < 0 means no pin will be bound to the converter */
1374 if (pin_idx < 0)
1375 per_pin = NULL;
1376 else
1377 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1378
1379 /* Dynamically assign converter to stream */
1380 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1381 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1382
384a48d7
SW		 1383 /* Must not already be assigned */
1384 if (per_cvt->assigned)
1385 continue;
42b29870
LY		 1386 if (per_pin == NULL)
1387 break;
384a48d7
SW		 1388 /* Must be in pin's mux's list of converters */
1389 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1390 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1391 break;
1392 /* Not in mux list */
1393 if (mux_idx == per_pin->num_mux_nids)
1394 continue;
1395 break;
1396 }
7ef166b8 1397
384a48d7
SW		 1398 /* No free converters */
1399 if (cvt_idx == spec->num_cvts)
42b29870 1400 return -EBUSY;
384a48d7 1401
42b29870
LY		 1402 if (per_pin != NULL)
1403 per_pin->mux_idx = mux_idx;
2df6742f 1404
7ef166b8
WX		 1405 if (cvt_id)
1406 *cvt_id = cvt_idx;
1407 if (mux_id)
1408 *mux_id = mux_idx;
1409
1410 return 0;
1411}
1412
2df6742f
ML		 1413/* Assure the pin select the right convetor */
1414static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1415 struct hdmi_spec_per_pin *per_pin)
1416{
1417 hda_nid_t pin_nid = per_pin->pin_nid;
1418 int mux_idx, curr;
1419
1420 mux_idx = per_pin->mux_idx;
1421 curr = snd_hda_codec_read(codec, pin_nid, 0,
1422 AC_VERB_GET_CONNECT_SEL, 0);
1423 if (curr != mux_idx)
1424 snd_hda_codec_write_cache(codec, pin_nid, 0,
1425 AC_VERB_SET_CONNECT_SEL,
1426 mux_idx);
1427}
1428
42b29870
LY		 1429/* get the mux index for the converter of the pins
1430 * converter's mux index is the same for all pins on Intel platform
1431 */
1432static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1433 hda_nid_t cvt_nid)
1434{
1435 int i;
1436
1437 for (i = 0; i < spec->num_cvts; i++)
1438 if (spec->cvt_nids[i] == cvt_nid)
1439 return i;
1440 return -EINVAL;
1441}
1442
300016b9
ML		 1443/* Intel HDMI workaround to fix audio routing issue:
1444 * For some Intel display codecs, pins share the same connection list.
1445 * So a conveter can be selected by multiple pins and playback on any of these
1446 * pins will generate sound on the external display, because audio flows from
1447 * the same converter to the display pipeline. Also muting one pin may make
1448 * other pins have no sound output.
1449 * So this function assures that an assigned converter for a pin is not selected
1450 * by any other pins.
1451 */
1452static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1453 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1454{
1455 struct hdmi_spec *spec = codec->spec;
7639a06c 1456 hda_nid_t nid;
f82d7d16
ML		 1457 int cvt_idx, curr;
1458 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1459
f82d7d16 1460 /* configure all pins, including "no physical connection" ones */
7639a06c 1461 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 1462 unsigned int wid_caps = get_wcaps(codec, nid);
1463 unsigned int wid_type = get_wcaps_type(wid_caps);
1464
1465 if (wid_type != AC_WID_PIN)
1466 continue;
7ef166b8 1467
f82d7d16 1468 if (nid == pin_nid)
7ef166b8
WX		 1469 continue;
1470
f82d7d16 1471 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1472 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1473 if (curr != mux_idx)
1474 continue;
7ef166b8 1475
f82d7d16
ML		 1476 /* choose an unassigned converter. The conveters in the
1477 * connection list are in the same order as in the codec.
1478 */
1479 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1480 per_cvt = get_cvt(spec, cvt_idx);
1481 if (!per_cvt->assigned) {
4e76a883
TI		 1482 codec_dbg(codec,
1483 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1484 cvt_idx, nid);
1485 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1486 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1487 cvt_idx);
1488 break;
1489 }
7ef166b8
WX		 1490 }
1491 }
1492}
1493
42b29870
LY		 1494/* A wrapper of intel_not_share_asigned_cvt() */
1495static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1496 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1497{
1498 int mux_idx;
1499 struct hdmi_spec *spec = codec->spec;
1500
1501 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1502 return;
1503
1504 /* On Intel platform, the mapping of converter nid to
1505 * mux index of the pins are always the same.
1506 * The pin nid may be 0, this means all pins will not
1507 * share the converter.
1508 */
1509 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1510 if (mux_idx >= 0)
1511 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1512}
1513
1514/* called in hdmi_pcm_open when no pin is assigned to the PCM
1515 * in dyn_pcm_assign mode.
1516 */
1517static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1518 struct hda_codec *codec,
1519 struct snd_pcm_substream *substream)
1520{
1521 struct hdmi_spec *spec = codec->spec;
1522 struct snd_pcm_runtime *runtime = substream->runtime;
1523 int cvt_idx;
1524 struct hdmi_spec_per_cvt *per_cvt = NULL;
1525 int err;
1526
1527 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1528 if (err)
1529 return err;
1530
1531 per_cvt = get_cvt(spec, cvt_idx);
1532 per_cvt->assigned = 1;
1533 hinfo->nid = per_cvt->cvt_nid;
1534
1535 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1536
1537 /* todo: setup spdif ctls assign */
1538
1539 /* Initially set the converter's capabilities */
1540 hinfo->channels_min = per_cvt->channels_min;
1541 hinfo->channels_max = per_cvt->channels_max;
1542 hinfo->rates = per_cvt->rates;
1543 hinfo->formats = per_cvt->formats;
1544 hinfo->maxbps = per_cvt->maxbps;
1545
1546 /* Store the updated parameters */
1547 runtime->hw.channels_min = hinfo->channels_min;
1548 runtime->hw.channels_max = hinfo->channels_max;
1549 runtime->hw.formats = hinfo->formats;
1550 runtime->hw.rates = hinfo->rates;
1551
1552 snd_pcm_hw_constraint_step(substream->runtime, 0,
1553 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1554 return 0;
1555}
1556
7ef166b8
WX		 1557/*
1558 * HDA PCM callbacks
1559 */
1560static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1561 struct hda_codec *codec,
1562 struct snd_pcm_substream *substream)
1563{
1564 struct hdmi_spec *spec = codec->spec;
1565 struct snd_pcm_runtime *runtime = substream->runtime;
2bf3c85a 1566 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
7ef166b8
WX		 1567 struct hdmi_spec_per_pin *per_pin;
1568 struct hdmi_eld *eld;
1569 struct hdmi_spec_per_cvt *per_cvt = NULL;
1570 int err;
1571
1572 /* Validate hinfo */
2bf3c85a
LY		 1573 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1574 if (pcm_idx < 0)
1575 return -EINVAL;
1576
42b29870 1577 mutex_lock(&spec->pcm_lock);
4e76a883 1578 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1579 if (!spec->dyn_pcm_assign) {
1580 if (snd_BUG_ON(pin_idx < 0)) {
1581 mutex_unlock(&spec->pcm_lock);
1582 return -EINVAL;
1583 }
1584 } else {
1585 /* no pin is assigned to the PCM
1586 * PA need pcm open successfully when probe
1587 */
1588 if (pin_idx < 0) {
1589 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1590 mutex_unlock(&spec->pcm_lock);
1591 return err;
1592 }
1593 }
7ef166b8
WX		 1594
1595 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
42b29870
LY		 1596 if (err < 0) {
1597 mutex_unlock(&spec->pcm_lock);
7ef166b8 1598 return err;
42b29870 1599 }
7ef166b8
WX		 1600
1601 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1602 /* Claim converter */
1603 per_cvt->assigned = 1;
42b29870
LY		 1604
1605
1606 per_pin = get_pin(spec, pin_idx);
1df5a06a 1607 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1608 hinfo->nid = per_cvt->cvt_nid;
1609
bddee96b 1610 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1611 AC_VERB_SET_CONNECT_SEL,
1612 mux_idx);
7ef166b8
WX		 1613
1614 /* configure unused pins to choose other converters */
ca2e7224 1615 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
300016b9 1616 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1617
2bf3c85a 1618 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1619
2def8172 1620 /* Initially set the converter's capabilities */
384a48d7
SW		 1621 hinfo->channels_min = per_cvt->channels_min;
1622 hinfo->channels_max = per_cvt->channels_max;
1623 hinfo->rates = per_cvt->rates;
1624 hinfo->formats = per_cvt->formats;
1625 hinfo->maxbps = per_cvt->maxbps;
2def8172 1626
42b29870 1627 eld = &per_pin->sink_eld;
384a48d7 1628 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1629 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1630 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1631 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1632 !hinfo->rates || !hinfo->formats) {
1633 per_cvt->assigned = 0;
1634 hinfo->nid = 0;
2bf3c85a 1635 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
42b29870 1636 mutex_unlock(&spec->pcm_lock);
bbbe3390 1637 return -ENODEV;
2ad779b7 1638 }
bbbe3390 1639 }
2def8172 1640
42b29870 1641 mutex_unlock(&spec->pcm_lock);
2def8172 1642 /* Store the updated parameters */
639cef0e
TI		 1643 runtime->hw.channels_min = hinfo->channels_min;
1644 runtime->hw.channels_max = hinfo->channels_max;
1645 runtime->hw.formats = hinfo->formats;
1646 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1647
1648 snd_pcm_hw_constraint_step(substream->runtime, 0,
1649 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1650 return 0;
1651}
1652
079d88cc
WF		 1653/*
1654 * HDA/HDMI auto parsing
1655 */
384a48d7 1656static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1657{
1658 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1659 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1660 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1661
1662 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1663 codec_warn(codec,
1664 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1665 pin_nid, get_wcaps(codec, pin_nid));
1666 return -EINVAL;
1667 }
1668
384a48d7
SW		 1669 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1670 per_pin->mux_nids,
1671 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1672
1673 return 0;
1674}
1675
e90247f9
TI		 1676/* update per_pin ELD from the given new ELD;
1677 * setup info frame and notification accordingly
1678 */
1679static void update_eld(struct hda_codec *codec,
1680 struct hdmi_spec_per_pin *per_pin,
1681 struct hdmi_eld *eld)
1682{
1683 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1684 bool old_eld_valid = pin_eld->eld_valid;
1685 bool eld_changed;
1686
1687 if (eld->eld_valid)
1688 snd_hdmi_show_eld(codec, &eld->info);
1689
1690 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1691 if (eld->eld_valid && pin_eld->eld_valid)
1692 if (pin_eld->eld_size != eld->eld_size ||
1693 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1694 eld->eld_size) != 0)
1695 eld_changed = true;
1696
1697 pin_eld->eld_valid = eld->eld_valid;
1698 pin_eld->eld_size = eld->eld_size;
1699 if (eld->eld_valid)
1700 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1701 pin_eld->info = eld->info;
1702
1703 /*
1704 * Re-setup pin and infoframe. This is needed e.g. when
1705 * - sink is first plugged-in
1706 * - transcoder can change during stream playback on Haswell
1707 * and this can make HW reset converter selection on a pin.
1708 */
1709 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1710 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1711 intel_verify_pin_cvt_connect(codec, per_pin);
1712 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1713 per_pin->mux_idx);
1714 }
1715
1716 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1717 }
1718
1719 if (eld_changed)
1720 snd_ctl_notify(codec->card,
1721 SNDRV_CTL_EVENT_MASK_VALUE |
1722 SNDRV_CTL_EVENT_MASK_INFO,
1723 &per_pin->eld_ctl->id);
1724}
1725
788d441a
TI		 1726/* update ELD and jack state via HD-audio verbs */
1727static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1728 int repoll)
079d88cc 1729{
464837a7 1730 struct hda_jack_tbl *jack;
744626da 1731 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1732 struct hdmi_spec *spec = codec->spec;
1733 struct hdmi_eld *eld = &spec->temp_eld;
1734 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1735 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1736 /*
1737 * Always execute a GetPinSense verb here, even when called from
1738 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1739 * response's PD bit is not the real PD value, but indicates that
1740 * the real PD value changed. An older version of the HD-audio
1741 * specification worked this way. Hence, we just ignore the data in
1742 * the unsolicited response to avoid custom WARs.
1743 */
da4a7a39 1744 int present;
efe47108 1745 bool ret;
9a5e5234 1746 bool do_repoll = false;
079d88cc 1747
664c7155 1748 snd_hda_power_up_pm(codec);
da4a7a39
DH		 1749 present = snd_hda_pin_sense(codec, pin_nid);
1750
a4e9a38b 1751 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1752 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1753 if (pin_eld->monitor_present)
1754 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1755 else
1756 eld->eld_valid = false;
079d88cc 1757
4e76a883 1758 codec_dbg(codec,
384a48d7 1759 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1760 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1761
4bd038f9 1762 if (eld->eld_valid) {
307229d2 1763 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1764 &eld->eld_size) < 0)
4bd038f9 1765 eld->eld_valid = false;
1613d6b4 1766 else {
79514d47 1767 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1768 eld->eld_size) < 0)
4bd038f9 1769 eld->eld_valid = false;
1613d6b4 1770 }
9a5e5234
TI		 1771 if (!eld->eld_valid && repoll)
1772 do_repoll = true;
744626da 1773 }
4bd038f9 1774
9a5e5234 1775 if (do_repoll)
e90247f9
TI		 1776 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1777 else
1778 update_eld(codec, per_pin, eld);
92c69e79 1779
aff747eb 1780 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1781
1782 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1783 if (jack)
1784 jack->block_report = !ret;
1785
a4e9a38b 1786 mutex_unlock(&per_pin->lock);
664c7155 1787 snd_hda_power_down_pm(codec);
efe47108 1788 return ret;
079d88cc
WF		 1789}
1790
788d441a
TI		 1791/* update ELD and jack state via audio component */
1792static void sync_eld_via_acomp(struct hda_codec *codec,
1793 struct hdmi_spec_per_pin *per_pin)
1794{
788d441a
TI		 1795 struct hdmi_spec *spec = codec->spec;
1796 struct hdmi_eld *eld = &spec->temp_eld;
1797 int size;
1798
e2dc7d7d
TI		 1799 mutex_lock(&per_pin->lock);
1800 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1801 &eld->monitor_present, eld->eld_buffer,
1802 ELD_MAX_SIZE);
1803 if (size < 0)
1804 goto unlock;
1805 if (size > 0) {
1806 size = min(size, ELD_MAX_SIZE);
1807 if (snd_hdmi_parse_eld(codec, &eld->info,
1808 eld->eld_buffer, size) < 0)
1809 size = -EINVAL;
1810 }
788d441a 1811
e2dc7d7d
TI		 1812 if (size > 0) {
1813 eld->eld_valid = true;
1814 eld->eld_size = size;
1815 } else {
1816 eld->eld_valid = false;
1817 eld->eld_size = 0;
788d441a 1818 }
e2dc7d7d
TI		 1819
1820 update_eld(codec, per_pin, eld);
1821 snd_jack_report(per_pin->acomp_jack,
1822 eld->monitor_present ? SND_JACK_AVOUT : 0);
1823 unlock:
1824 mutex_unlock(&per_pin->lock);
788d441a
TI		 1825}
1826
1827static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1828{
1829 struct hda_codec *codec = per_pin->codec;
1830
1831 if (codec_has_acomp(codec)) {
1832 sync_eld_via_acomp(codec, per_pin);
1833 return false; /* don't call snd_hda_jack_report_sync() */
1834 } else {
1835 return hdmi_present_sense_via_verbs(per_pin, repoll);
1836 }
1837}
1838
744626da
WF		 1839static void hdmi_repoll_eld(struct work_struct *work)
1840{
1841 struct hdmi_spec_per_pin *per_pin =
1842 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1843
c6e8453e
WF		 1844 if (per_pin->repoll_count++ > 6)
1845 per_pin->repoll_count = 0;
1846
efe47108
TI		 1847 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1848 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1849}
1850
c88d4e84
TI		 1851static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1852 hda_nid_t nid);
1853
079d88cc
WF		 1854static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1855{
1856 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1857 unsigned int caps, config;
1858 int pin_idx;
1859 struct hdmi_spec_per_pin *per_pin;
07acecc1 1860 int err;
079d88cc 1861
efc2f8de 1862 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1863 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1864 return 0;
1865
efc2f8de 1866 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1867 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1868 return 0;
1869
75dcbe4d 1870 if (is_haswell_plus(codec))
c88d4e84
TI		 1871 intel_haswell_fixup_connect_list(codec, pin_nid);
1872
384a48d7 1873 pin_idx = spec->num_pins;
bce0d2a8
TI		 1874 per_pin = snd_array_new(&spec->pins);
1875 if (!per_pin)
1876 return -ENOMEM;
384a48d7
SW		 1877
1878 per_pin->pin_nid = pin_nid;
1a6003b5 1879 per_pin->non_pcm = false;
079d88cc 1880
384a48d7
SW		 1881 err = hdmi_read_pin_conn(codec, pin_idx);
1882 if (err < 0)
1883 return err;
079d88cc 1884
079d88cc
WF		 1885 spec->num_pins++;
1886
384a48d7 1887 return 0;
079d88cc
WF		 1888}
1889
384a48d7 1890static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1891{
1892 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1893 struct hdmi_spec_per_cvt *per_cvt;
1894 unsigned int chans;
1895 int err;
079d88cc 1896
384a48d7
SW		 1897 chans = get_wcaps(codec, cvt_nid);
1898 chans = get_wcaps_channels(chans);
1899
bce0d2a8
TI		 1900 per_cvt = snd_array_new(&spec->cvts);
1901 if (!per_cvt)
1902 return -ENOMEM;
384a48d7
SW		 1903
1904 per_cvt->cvt_nid = cvt_nid;
1905 per_cvt->channels_min = 2;
d45e6889 1906 if (chans <= 16) {
384a48d7 1907 per_cvt->channels_max = chans;
d45e6889
TI		 1908 if (chans > spec->channels_max)
1909 spec->channels_max = chans;
1910 }
384a48d7
SW		 1911
1912 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1913 &per_cvt->rates,
1914 &per_cvt->formats,
1915 &per_cvt->maxbps);
1916 if (err < 0)
1917 return err;
1918
bce0d2a8
TI		 1919 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1920 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1921 spec->num_cvts++;
079d88cc
WF		 1922
1923 return 0;
1924}
1925
1926static int hdmi_parse_codec(struct hda_codec *codec)
1927{
1928 hda_nid_t nid;
1929 int i, nodes;
1930
7639a06c 1931 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1932 if (!nid || nodes < 0) {
4e76a883 1933 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1934 return -EINVAL;
1935 }
1936
1937 for (i = 0; i < nodes; i++, nid++) {
1938 unsigned int caps;
1939 unsigned int type;
1940
efc2f8de 1941 caps = get_wcaps(codec, nid);
079d88cc
WF		 1942 type = get_wcaps_type(caps);
1943
1944 if (!(caps & AC_WCAP_DIGITAL))
1945 continue;
1946
1947 switch (type) {
1948 case AC_WID_AUD_OUT:
384a48d7 1949 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1950 break;
1951 case AC_WID_PIN:
3eaead57 1952 hdmi_add_pin(codec, nid);
079d88cc
WF		 1953 break;
1954 }
1955 }
1956
079d88cc
WF		 1957 return 0;
1958}
1959
84eb01be
TI		 1960/*
1961 */
1a6003b5
TI		 1962static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1963{
1964 struct hda_spdif_out *spdif;
1965 bool non_pcm;
1966
1967 mutex_lock(&codec->spdif_mutex);
1968 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1969 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1970 mutex_unlock(&codec->spdif_mutex);
1971 return non_pcm;
1972}
1973
84eb01be
TI		 1974/*
1975 * HDMI callbacks
1976 */
1977
1978static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1979 struct hda_codec *codec,
1980 unsigned int stream_tag,
1981 unsigned int format,
1982 struct snd_pcm_substream *substream)
1983{
384a48d7
SW		 1984 hda_nid_t cvt_nid = hinfo->nid;
1985 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1986 int pin_idx;
1987 struct hdmi_spec_per_pin *per_pin;
1988 hda_nid_t pin_nid;
ddd621fb 1989 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1990 bool non_pcm;
75fae117 1991 int pinctl;
42b29870 1992 int err;
1a6003b5 1993
42b29870
LY		 1994 mutex_lock(&spec->pcm_lock);
1995 pin_idx = hinfo_to_pin_index(codec, hinfo);
1996 if (spec->dyn_pcm_assign && pin_idx < 0) {
1997 /* when dyn_pcm_assign and pcm is not bound to a pin
1998 * skip pin setup and return 0 to make audio playback
1999 * be ongoing
2000 */
2001 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2002 snd_hda_codec_setup_stream(codec, cvt_nid,
2003 stream_tag, 0, format);
2004 mutex_unlock(&spec->pcm_lock);
2005 return 0;
2006 }
2007
2008 if (snd_BUG_ON(pin_idx < 0)) {
2009 mutex_unlock(&spec->pcm_lock);
2010 return -EINVAL;
2011 }
2012 per_pin = get_pin(spec, pin_idx);
2013 pin_nid = per_pin->pin_nid;
ca2e7224 2014 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2df6742f
ML		 2015 /* Verify pin:cvt selections to avoid silent audio after S3.
2016 * After S3, the audio driver restores pin:cvt selections
2017 * but this can happen before gfx is ready and such selection
2018 * is overlooked by HW. Thus multiple pins can share a same
2019 * default convertor and mute control will affect each other,
2020 * which can cause a resumed audio playback become silent
2021 * after S3.
2022 */
2023 intel_verify_pin_cvt_connect(codec, per_pin);
2024 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
2025 }
2026
ddd621fb
LY		 2027 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2028 /* Todo: add DP1.2 MST audio support later */
e2dc7d7d 2029 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
ddd621fb 2030
1a6003b5 2031 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 2032 mutex_lock(&per_pin->lock);
b054087d
TI		 2033 per_pin->channels = substream->runtime->channels;
2034 per_pin->setup = true;
384a48d7 2035
b054087d 2036 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 2037 mutex_unlock(&per_pin->lock);
75fae117
SW		 2038 if (spec->dyn_pin_out) {
2039 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
2040 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2041 snd_hda_codec_write(codec, pin_nid, 0,
2042 AC_VERB_SET_PIN_WIDGET_CONTROL,
2043 pinctl | PIN_OUT);
2044 }
2045
42b29870
LY		 2046 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
2047 stream_tag, format);
2048 mutex_unlock(&spec->pcm_lock);
2049 return err;
84eb01be
TI		 2050}
2051
8dfaa573
TI		 2052static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2053 struct hda_codec *codec,
2054 struct snd_pcm_substream *substream)
2055{
2056 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2057 return 0;
2058}
2059
f2ad24fa
TI		 2060static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2061 struct hda_codec *codec,
2062 struct snd_pcm_substream *substream)
384a48d7
SW		 2063{
2064 struct hdmi_spec *spec = codec->spec;
2bf3c85a 2065 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 2066 struct hdmi_spec_per_cvt *per_cvt;
2067 struct hdmi_spec_per_pin *per_pin;
75fae117 2068 int pinctl;
384a48d7 2069
384a48d7 2070 if (hinfo->nid) {
2bf3c85a
LY		 2071 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2072 if (snd_BUG_ON(pcm_idx < 0))
2073 return -EINVAL;
4e76a883 2074 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 2075 if (snd_BUG_ON(cvt_idx < 0))
2076 return -EINVAL;
bce0d2a8 2077 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 2078
2079 snd_BUG_ON(!per_cvt->assigned);
2080 per_cvt->assigned = 0;
2081 hinfo->nid = 0;
2082
42b29870 2083 mutex_lock(&spec->pcm_lock);
4e76a883 2084 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 2085 if (spec->dyn_pcm_assign && pin_idx < 0) {
2086 mutex_unlock(&spec->pcm_lock);
2087 return 0;
2088 }
2089
2090 if (snd_BUG_ON(pin_idx < 0)) {
2091 mutex_unlock(&spec->pcm_lock);
384a48d7 2092 return -EINVAL;
42b29870 2093 }
bce0d2a8 2094 per_pin = get_pin(spec, pin_idx);
384a48d7 2095
75fae117
SW		 2096 if (spec->dyn_pin_out) {
2097 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2098 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2099 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2100 AC_VERB_SET_PIN_WIDGET_CONTROL,
2101 pinctl & ~PIN_OUT);
2102 }
2103
2bf3c85a 2104 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
cbbaa603 2105
a4e9a38b 2106 mutex_lock(&per_pin->lock);
d45e6889
TI		 2107 per_pin->chmap_set = false;
2108 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 2109
2110 per_pin->setup = false;
2111 per_pin->channels = 0;
a4e9a38b 2112 mutex_unlock(&per_pin->lock);
42b29870 2113 mutex_unlock(&spec->pcm_lock);
384a48d7 2114 }
d45e6889 2115
384a48d7
SW		 2116 return 0;
2117}
2118
2119static const struct hda_pcm_ops generic_ops = {
2120 .open = hdmi_pcm_open,
f2ad24fa 2121 .close = hdmi_pcm_close,
384a48d7 2122 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2123 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2124};
2125
d45e6889
TI		 2126/*
2127 * ALSA API channel-map control callbacks
2128 */
2129static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
2130 struct snd_ctl_elem_info *uinfo)
2131{
2132 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2133 struct hda_codec *codec = info->private_data;
2134 struct hdmi_spec *spec = codec->spec;
2135 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2136 uinfo->count = spec->channels_max;
2137 uinfo->value.integer.min = 0;
2138 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
2139 return 0;
2140}
2141
307229d2
AH		 2142static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2143 int channels)
2144{
2145 /* If the speaker allocation matches the channel count, it is OK.*/
2146 if (cap->channels != channels)
2147 return -1;
2148
2149 /* all channels are remappable freely */
2150 return SNDRV_CTL_TLVT_CHMAP_VAR;
2151}
2152
2153static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
2154 unsigned int *chmap, int channels)
2155{
2156 int count = 0;
2157 int c;
2158
2159 for (c = 7; c >= 0; c--) {
2160 int spk = cap->speakers[c];
2161 if (!spk)
2162 continue;
2163
2164 chmap[count++] = spk_to_chmap(spk);
2165 }
2166
2167 WARN_ON(count != channels);
2168}
2169
d45e6889
TI		 2170static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
2171 unsigned int size, unsigned int __user *tlv)
2172{
2173 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2174 struct hda_codec *codec = info->private_data;
2175 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 2176 unsigned int __user *dst;
2177 int chs, count = 0;
2178
2179 if (size < 8)
2180 return -ENOMEM;
2181 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
2182 return -EFAULT;
2183 size -= 8;
2184 dst = tlv + 2;
498dab3a 2185 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 2186 int i;
d45e6889
TI		 2187 struct cea_channel_speaker_allocation *cap;
2188 cap = channel_allocations;
2189 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
2190 int chs_bytes = chs * 4;
307229d2
AH		 2191 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
2192 unsigned int tlv_chmap[8];
2193
2194 if (type < 0)
d45e6889 2195 continue;
d45e6889
TI		 2196 if (size < 8)
2197 return -ENOMEM;
307229d2 2198 if (put_user(type, dst) ||
d45e6889
TI		 2199 put_user(chs_bytes, dst + 1))
2200 return -EFAULT;
2201 dst += 2;
2202 size -= 8;
2203 count += 8;
2204 if (size < chs_bytes)
2205 return -ENOMEM;
2206 size -= chs_bytes;
2207 count += chs_bytes;
307229d2
AH		 2208 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
2209 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2210 return -EFAULT;
2211 dst += chs;
d45e6889
TI		 2212 }
2213 }
2214 if (put_user(count, tlv + 1))
2215 return -EFAULT;
2216 return 0;
2217}
2218
2219static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2220 struct snd_ctl_elem_value *ucontrol)
2221{
2222 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2223 struct hda_codec *codec = info->private_data;
2224 struct hdmi_spec *spec = codec->spec;
2225 int pin_idx = kcontrol->private_value;
bce0d2a8 2226 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2227 int i;
2228
2229 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2230 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2231 return 0;
2232}
2233
2234static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2235 struct snd_ctl_elem_value *ucontrol)
2236{
2237 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2238 struct hda_codec *codec = info->private_data;
2239 struct hdmi_spec *spec = codec->spec;
2240 int pin_idx = kcontrol->private_value;
bce0d2a8 2241 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2242 unsigned int ctl_idx;
2243 struct snd_pcm_substream *substream;
2244 unsigned char chmap[8];
307229d2 2245 int i, err, ca, prepared = 0;
d45e6889
TI		 2246
2247 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2248 substream = snd_pcm_chmap_substream(info, ctl_idx);
2249 if (!substream || !substream->runtime)
6f54c361 2250 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 2251 switch (substream->runtime->status->state) {
2252 case SNDRV_PCM_STATE_OPEN:
2253 case SNDRV_PCM_STATE_SETUP:
2254 break;
2255 case SNDRV_PCM_STATE_PREPARED:
2256 prepared = 1;
2257 break;
2258 default:
2259 return -EBUSY;
2260 }
2261 memset(chmap, 0, sizeof(chmap));
2262 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2263 chmap[i] = ucontrol->value.integer.value[i];
2264 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2265 return 0;
2266 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2267 if (ca < 0)
2268 return -EINVAL;
307229d2
AH		 2269 if (spec->ops.chmap_validate) {
2270 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2271 if (err)
2272 return err;
2273 }
a4e9a38b 2274 mutex_lock(&per_pin->lock);
d45e6889
TI		 2275 per_pin->chmap_set = true;
2276 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2277 if (prepared)
b054087d 2278 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2279 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2280
2281 return 0;
2282}
2283
84eb01be
TI		 2284static int generic_hdmi_build_pcms(struct hda_codec *codec)
2285{
2286 struct hdmi_spec *spec = codec->spec;
6590faab 2287 struct hdmi_spec_per_pin *per_pin;
384a48d7 2288 int pin_idx;
84eb01be 2289
384a48d7
SW		 2290 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2291 struct hda_pcm *info;
84eb01be 2292 struct hda_pcm_stream *pstr;
bce0d2a8 2293
bbbc7e85 2294 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 2295 if (!info)
2296 return -ENOMEM;
6590faab
LY		 2297 if (!spec->dyn_pcm_assign) {
2298 per_pin = get_pin(spec, pin_idx);
2299 per_pin->pcm = info;
2300 }
bbbc7e85 2301 spec->pcm_rec[pin_idx] = info;
2bf3c85a 2302 spec->pcm_used++;
84eb01be 2303 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2304 info->own_chmap = true;
384a48d7 2305
84eb01be 2306 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2307 pstr->substreams = 1;
2308 pstr->ops = generic_ops;
2309 /* other pstr fields are set in open */
84eb01be
TI		 2310 }
2311
2312 return 0;
2313}
2314
788d441a
TI		 2315static void free_acomp_jack_priv(struct snd_jack *jack)
2316{
2317 struct hdmi_spec_per_pin *per_pin = jack->private_data;
2318
2319 per_pin->acomp_jack = NULL;
2320}
2321
2322static int add_acomp_jack_kctl(struct hda_codec *codec,
2323 struct hdmi_spec_per_pin *per_pin,
2324 const char *name)
2325{
2326 struct snd_jack *jack;
2327 int err;
2328
2329 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2330 true, false);
2331 if (err < 0)
2332 return err;
2333 per_pin->acomp_jack = jack;
2334 jack->private_data = per_pin;
2335 jack->private_free = free_acomp_jack_priv;
2336 return 0;
2337}
2338
0b6c49b5
DH		 2339static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2340{
31ef2257 2341 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2342 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2343 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2344 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
909cadc6 2345 bool phantom_jack;
0b6c49b5 2346
31ef2257
TI		 2347 if (pcmdev > 0)
2348 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
788d441a
TI		 2349 if (codec_has_acomp(codec))
2350 return add_acomp_jack_kctl(codec, per_pin, hdmi_str);
909cadc6
TI		 2351 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2352 if (phantom_jack)
30efd8de
DH		 2353 strncat(hdmi_str, " Phantom",
2354 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2355
909cadc6
TI		 2356 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2357 phantom_jack);
0b6c49b5
DH		 2358}
2359
84eb01be
TI		 2360static int generic_hdmi_build_controls(struct hda_codec *codec)
2361{
2362 struct hdmi_spec *spec = codec->spec;
2363 int err;
384a48d7 2364 int pin_idx;
84eb01be 2365
384a48d7 2366 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2367 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2368
2369 err = generic_hdmi_build_jack(codec, pin_idx);
2370 if (err < 0)
2371 return err;
2372
dcda5806
TI		 2373 err = snd_hda_create_dig_out_ctls(codec,
2374 per_pin->pin_nid,
2375 per_pin->mux_nids[0],
2376 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2377 if (err < 0)
2378 return err;
2bf3c85a 2379 /* pin number is the same with pcm number so far */
384a48d7 2380 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2381
2382 /* add control for ELD Bytes */
bce0d2a8
TI		 2383 err = hdmi_create_eld_ctl(codec, pin_idx,
2384 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2385
2386 if (err < 0)
2387 return err;
31ef2257 2388
82b1d73f 2389 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2390 }
2391
d45e6889
TI		 2392 /* add channel maps */
2393 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bbbc7e85 2394 struct hda_pcm *pcm;
d45e6889
TI		 2395 struct snd_pcm_chmap *chmap;
2396 struct snd_kcontrol *kctl;
2397 int i;
2ca320e2 2398
bbbc7e85
TI		 2399 pcm = spec->pcm_rec[pin_idx];
2400 if (!pcm || !pcm->pcm)
2ca320e2 2401 break;
bbbc7e85 2402 err = snd_pcm_add_chmap_ctls(pcm->pcm,
d45e6889
TI		 2403 SNDRV_PCM_STREAM_PLAYBACK,
2404 NULL, 0, pin_idx, &chmap);
2405 if (err < 0)
2406 return err;
2407 /* override handlers */
2408 chmap->private_data = codec;
2409 kctl = chmap->kctl;
2410 for (i = 0; i < kctl->count; i++)
2411 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2412 kctl->info = hdmi_chmap_ctl_info;
2413 kctl->get = hdmi_chmap_ctl_get;
2414 kctl->put = hdmi_chmap_ctl_put;
2415 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2416 }
2417
84eb01be
TI		 2418 return 0;
2419}
2420
8b8d654b 2421static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2422{
2423 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2424 int pin_idx;
2425
2426 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2427 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2428
744626da 2429 per_pin->codec = codec;
a4e9a38b 2430 mutex_init(&per_pin->lock);
744626da 2431 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2432 eld_proc_new(per_pin, pin_idx);
84eb01be 2433 }
8b8d654b
TI		 2434 return 0;
2435}
2436
2437static int generic_hdmi_init(struct hda_codec *codec)
2438{
2439 struct hdmi_spec *spec = codec->spec;
2440 int pin_idx;
2441
2442 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2443 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2444 hda_nid_t pin_nid = per_pin->pin_nid;
2445
2446 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2447 if (!codec_has_acomp(codec))
2448 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2449 codec->jackpoll_interval > 0 ?
2450 jack_callback : NULL);
8b8d654b 2451 }
84eb01be
TI		 2452 return 0;
2453}
2454
bce0d2a8
TI		 2455static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2456{
2457 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2458 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2459}
2460
2461static void hdmi_array_free(struct hdmi_spec *spec)
2462{
2463 snd_array_free(&spec->pins);
2464 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2465}
2466
84eb01be
TI		 2467static void generic_hdmi_free(struct hda_codec *codec)
2468{
2469 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2470 int pin_idx;
2471
6603249d 2472 if (codec_has_acomp(codec))
25adc137
DH		 2473 snd_hdac_i915_register_notifier(NULL);
2474
384a48d7 2475 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2476 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2477
2f35c630 2478 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2479 eld_proc_free(per_pin);
788d441a
TI		 2480 if (per_pin->acomp_jack)
2481 snd_device_free(codec->card, per_pin->acomp_jack);
384a48d7 2482 }
84eb01be 2483
55913110
TI		 2484 if (spec->i915_bound)
2485 snd_hdac_i915_exit(&codec->bus->core);
bce0d2a8 2486 hdmi_array_free(spec);
84eb01be
TI		 2487 kfree(spec);
2488}
2489
28cb72e5
WX		 2490#ifdef CONFIG_PM
2491static int generic_hdmi_resume(struct hda_codec *codec)
2492{
2493 struct hdmi_spec *spec = codec->spec;
2494 int pin_idx;
2495
a2833683 2496 codec->patch_ops.init(codec);
eeecd9d1 2497 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2498
2499 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2500 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2501 hdmi_present_sense(per_pin, 1);
2502 }
2503 return 0;
2504}
2505#endif
2506
fb79e1e0 2507static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2508 .init = generic_hdmi_init,
2509 .free = generic_hdmi_free,
2510 .build_pcms = generic_hdmi_build_pcms,
2511 .build_controls = generic_hdmi_build_controls,
2512 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2513#ifdef CONFIG_PM
2514 .resume = generic_hdmi_resume,
2515#endif
84eb01be
TI		 2516};
2517
307229d2
AH		 2518static const struct hdmi_ops generic_standard_hdmi_ops = {
2519 .pin_get_eld = snd_hdmi_get_eld,
2520 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2521 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2522 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2523 .pin_hbr_setup = hdmi_pin_hbr_setup,
2524 .setup_stream = hdmi_setup_stream,
2525 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2526 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2527};
2528
6ffe168f 2529
c88d4e84
TI		 2530static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2531 hda_nid_t nid)
2532{
2533 struct hdmi_spec *spec = codec->spec;
2534 hda_nid_t conns[4];
2535 int nconns;
6ffe168f 2536
c88d4e84
TI		 2537 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2538 if (nconns == spec->num_cvts &&
2539 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2540 return;
2541
c88d4e84 2542 /* override pins connection list */
4e76a883 2543 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2544 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2545}
2546
1611a9c9
ML		 2547#define INTEL_VENDOR_NID 0x08
2548#define INTEL_GET_VENDOR_VERB 0xf81
2549#define INTEL_SET_VENDOR_VERB 0x781
2550#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2551#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2552
2553static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2554 bool update_tree)
1611a9c9
ML		 2555{
2556 unsigned int vendor_param;
2557
1611a9c9
ML		 2558 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2559 INTEL_GET_VENDOR_VERB, 0);
2560 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2561 return;
2562
2563 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2564 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2565 INTEL_SET_VENDOR_VERB, vendor_param);
2566 if (vendor_param == -1)
2567 return;
2568
17df3f55
TI		 2569 if (update_tree)
2570 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2571}
2572
c88d4e84
TI		 2573static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2574{
2575 unsigned int vendor_param;
2576
2577 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2578 INTEL_GET_VENDOR_VERB, 0);
2579 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2580 return;
2581
2582 /* enable DP1.2 mode */
2583 vendor_param |= INTEL_EN_DP12;
a551d914 2584 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2585 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2586 INTEL_SET_VENDOR_VERB, vendor_param);
2587}
2588
17df3f55
TI		 2589/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2590 * Otherwise you may get severe h/w communication errors.
2591 */
2592static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2593 unsigned int power_state)
2594{
2595 if (power_state == AC_PWRST_D0) {
2596 intel_haswell_enable_all_pins(codec, false);
2597 intel_haswell_fixup_enable_dp12(codec);
2598 }
c88d4e84 2599
17df3f55
TI		 2600 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2601 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2602}
6ffe168f 2603
f0675d4a 2604static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2605{
2606 struct hda_codec *codec = audio_ptr;
2607 int pin_nid = port + 0x04;
2608
8ae743e8
TI		 2609 /* skip notification during system suspend (but not in runtime PM);
2610 * the state will be updated at resume
2611 */
2612 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2613 return;
eb399d3c
TI		 2614 /* ditto during suspend/resume process itself */
2615 if (atomic_read(&(codec)->core.in_pm))
2616 return;
8ae743e8 2617
25adc137
DH		 2618 check_presence_and_report(codec, pin_nid);
2619}
2620
84eb01be
TI		 2621static int patch_generic_hdmi(struct hda_codec *codec)
2622{
2623 struct hdmi_spec *spec;
84eb01be
TI		 2624
2625 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2626 if (spec == NULL)
2627 return -ENOMEM;
2628
307229d2 2629 spec->ops = generic_standard_hdmi_ops;
42b29870 2630 mutex_init(&spec->pcm_lock);
84eb01be 2631 codec->spec = spec;
bce0d2a8 2632 hdmi_array_init(spec, 4);
6ffe168f 2633
55913110
TI		 2634 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2635 if (!codec_has_acomp(codec) &&
2636 (codec->core.vendor_id >> 16) == 0x8086)
2637 if (!snd_hdac_i915_init(&codec->bus->core))
2638 spec->i915_bound = true;
2639
75dcbe4d 2640 if (is_haswell_plus(codec)) {
17df3f55 2641 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2642 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2643 }
6ffe168f 2644
2bd1f73f
ML		 2645 /* For Valleyview/Cherryview, only the display codec is in the display
2646 * power well and can use link_power ops to request/release the power.
2647 * For Haswell/Broadwell, the controller is also in the power well and
2648 * can cover the codec power request, and so need not set this flag.
2649 * For previous platforms, there is no such power well feature.
2650 */
ff9d8859
LH		 2651 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2652 is_broxton(codec))
2bd1f73f
ML		 2653 codec->core.link_power_control = 1;
2654
6603249d 2655 if (codec_has_acomp(codec)) {
5b8620bb 2656 codec->depop_delay = 0;
25adc137
DH		 2657 spec->i915_audio_ops.audio_ptr = codec;
2658 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2659 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2660 }
5b8620bb 2661
84eb01be 2662 if (hdmi_parse_codec(codec) < 0) {
55913110
TI		 2663 if (spec->i915_bound)
2664 snd_hdac_i915_exit(&codec->bus->core);
84eb01be
TI		 2665 codec->spec = NULL;
2666 kfree(spec);
2667 return -EINVAL;
2668 }
2669 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2670 if (is_haswell_plus(codec)) {
17df3f55 2671 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2672 codec->dp_mst = true;
2673 }
17df3f55 2674
2377c3c3
LH		 2675 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2676 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2677 codec->auto_runtime_pm = 1;
2678
8b8d654b 2679 generic_hdmi_init_per_pins(codec);
84eb01be 2680
84eb01be
TI		 2681 init_channel_allocations();
2682
2683 return 0;
2684}
2685
3aaf8980
SW		 2686/*
2687 * Shared non-generic implementations
2688 */
2689
2690static int simple_playback_build_pcms(struct hda_codec *codec)
2691{
2692 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2693 struct hda_pcm *info;
8ceb332d
TI		 2694 unsigned int chans;
2695 struct hda_pcm_stream *pstr;
bce0d2a8 2696 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2697
bce0d2a8
TI		 2698 per_cvt = get_cvt(spec, 0);
2699 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2700 chans = get_wcaps_channels(chans);
3aaf8980 2701
bbbc7e85 2702 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2703 if (!info)
2704 return -ENOMEM;
bbbc7e85 2705 spec->pcm_rec[0] = info;
8ceb332d
TI		 2706 info->pcm_type = HDA_PCM_TYPE_HDMI;
2707 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2708 *pstr = spec->pcm_playback;
bce0d2a8 2709 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2710 if (pstr->channels_max <= 2 && chans && chans <= 16)
2711 pstr->channels_max = chans;
3aaf8980
SW		 2712
2713 return 0;
2714}
2715
4b6ace9e
TI		 2716/* unsolicited event for jack sensing */
2717static void simple_hdmi_unsol_event(struct hda_codec *codec,
2718 unsigned int res)
2719{
9dd8cf12 2720 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2721 snd_hda_jack_report_sync(codec);
2722}
2723
2724/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2725 * as long as spec->pins[] is set correctly
2726 */
2727#define simple_hdmi_build_jack generic_hdmi_build_jack
2728
3aaf8980
SW		 2729static int simple_playback_build_controls(struct hda_codec *codec)
2730{
2731 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2732 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2733 int err;
3aaf8980 2734
bce0d2a8 2735 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2736 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2737 per_cvt->cvt_nid,
2738 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2739 if (err < 0)
2740 return err;
2741 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2742}
2743
4f0110ce
TI		 2744static int simple_playback_init(struct hda_codec *codec)
2745{
2746 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2747 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2748 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2749
2750 snd_hda_codec_write(codec, pin, 0,
2751 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2752 /* some codecs require to unmute the pin */
2753 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2754 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2755 AMP_OUT_UNMUTE);
62f949bf 2756 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2757 return 0;
2758}
2759
3aaf8980
SW		 2760static void simple_playback_free(struct hda_codec *codec)
2761{
2762 struct hdmi_spec *spec = codec->spec;
2763
bce0d2a8 2764 hdmi_array_free(spec);
3aaf8980
SW		 2765 kfree(spec);
2766}
2767
84eb01be
TI		 2768/*
2769 * Nvidia specific implementations
2770 */
2771
2772#define Nv_VERB_SET_Channel_Allocation 0xF79
2773#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2774#define Nv_VERB_SET_Audio_Protection_On 0xF98
2775#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2776
2777#define nvhdmi_master_con_nid_7x 0x04
2778#define nvhdmi_master_pin_nid_7x 0x05
2779
fb79e1e0 2780static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2781 /*front, rear, clfe, rear_surr */
2782 0x6, 0x8, 0xa, 0xc,
2783};
2784
ceaa86ba
TI		 2785static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2786 /* set audio protect on */
2787 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2788 /* enable digital output on pin widget */
2789 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2790 {} /* terminator */
2791};
2792
2793static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2794 /* set audio protect on */
2795 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2796 /* enable digital output on pin widget */
2797 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2798 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2799 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2800 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2801 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2802 {} /* terminator */
2803};
2804
2805#ifdef LIMITED_RATE_FMT_SUPPORT
2806/* support only the safe format and rate */
2807#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2808#define SUPPORTED_MAXBPS 16
2809#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2810#else
2811/* support all rates and formats */
2812#define SUPPORTED_RATES \
2813 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2814 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2815 SNDRV_PCM_RATE_192000)
2816#define SUPPORTED_MAXBPS 24
2817#define SUPPORTED_FORMATS \
2818 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2819#endif
2820
ceaa86ba
TI		 2821static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2822{
2823 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2824 return 0;
2825}
2826
2827static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2828{
ceaa86ba 2829 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2830 return 0;
2831}
2832
393004b2
ND		 2833static unsigned int channels_2_6_8[] = {
2834 2, 6, 8
2835};
2836
2837static unsigned int channels_2_8[] = {
2838 2, 8
2839};
2840
2841static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2842 .count = ARRAY_SIZE(channels_2_6_8),
2843 .list = channels_2_6_8,
2844 .mask = 0,
2845};
2846
2847static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2848 .count = ARRAY_SIZE(channels_2_8),
2849 .list = channels_2_8,
2850 .mask = 0,
2851};
2852
84eb01be
TI		 2853static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2854 struct hda_codec *codec,
2855 struct snd_pcm_substream *substream)
2856{
2857 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2858 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2859
b9a94a9c 2860 switch (codec->preset->vendor_id) {
393004b2
ND		 2861 case 0x10de0002:
2862 case 0x10de0003:
2863 case 0x10de0005:
2864 case 0x10de0006:
2865 hw_constraints_channels = &hw_constraints_2_8_channels;
2866 break;
2867 case 0x10de0007:
2868 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2869 break;
2870 default:
2871 break;
2872 }
2873
2874 if (hw_constraints_channels != NULL) {
2875 snd_pcm_hw_constraint_list(substream->runtime, 0,
2876 SNDRV_PCM_HW_PARAM_CHANNELS,
2877 hw_constraints_channels);
ad09fc9d
TI		 2878 } else {
2879 snd_pcm_hw_constraint_step(substream->runtime, 0,
2880 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2881 }
2882
84eb01be
TI		 2883 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2884}
2885
2886static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2887 struct hda_codec *codec,
2888 struct snd_pcm_substream *substream)
2889{
2890 struct hdmi_spec *spec = codec->spec;
2891 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2892}
2893
2894static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2895 struct hda_codec *codec,
2896 unsigned int stream_tag,
2897 unsigned int format,
2898 struct snd_pcm_substream *substream)
2899{
2900 struct hdmi_spec *spec = codec->spec;
2901 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2902 stream_tag, format, substream);
2903}
2904
d0b1252d
TI		 2905static const struct hda_pcm_stream simple_pcm_playback = {
2906 .substreams = 1,
2907 .channels_min = 2,
2908 .channels_max = 2,
2909 .ops = {
2910 .open = simple_playback_pcm_open,
2911 .close = simple_playback_pcm_close,
2912 .prepare = simple_playback_pcm_prepare
2913 },
2914};
2915
2916static const struct hda_codec_ops simple_hdmi_patch_ops = {
2917 .build_controls = simple_playback_build_controls,
2918 .build_pcms = simple_playback_build_pcms,
2919 .init = simple_playback_init,
2920 .free = simple_playback_free,
250e41ac 2921 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2922};
2923
2924static int patch_simple_hdmi(struct hda_codec *codec,
2925 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2926{
2927 struct hdmi_spec *spec;
bce0d2a8
TI		 2928 struct hdmi_spec_per_cvt *per_cvt;
2929 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2930
2931 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2932 if (!spec)
2933 return -ENOMEM;
2934
2935 codec->spec = spec;
bce0d2a8 2936 hdmi_array_init(spec, 1);
d0b1252d
TI		 2937
2938 spec->multiout.num_dacs = 0; /* no analog */
2939 spec->multiout.max_channels = 2;
2940 spec->multiout.dig_out_nid = cvt_nid;
2941 spec->num_cvts = 1;
2942 spec->num_pins = 1;
bce0d2a8
TI		 2943 per_pin = snd_array_new(&spec->pins);
2944 per_cvt = snd_array_new(&spec->cvts);
2945 if (!per_pin || !per_cvt) {
2946 simple_playback_free(codec);
2947 return -ENOMEM;
2948 }
2949 per_cvt->cvt_nid = cvt_nid;
2950 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2951 spec->pcm_playback = simple_pcm_playback;
2952
2953 codec->patch_ops = simple_hdmi_patch_ops;
2954
2955 return 0;
2956}
2957
1f348522
AP		 2958static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2959 int channels)
2960{
2961 unsigned int chanmask;
2962 int chan = channels ? (channels - 1) : 1;
2963
2964 switch (channels) {
2965 default:
2966 case 0:
2967 case 2:
2968 chanmask = 0x00;
2969 break;
2970 case 4:
2971 chanmask = 0x08;
2972 break;
2973 case 6:
2974 chanmask = 0x0b;
2975 break;
2976 case 8:
2977 chanmask = 0x13;
2978 break;
2979 }
2980
2981 /* Set the audio infoframe channel allocation and checksum fields. The
2982 * channel count is computed implicitly by the hardware. */
2983 snd_hda_codec_write(codec, 0x1, 0,
2984 Nv_VERB_SET_Channel_Allocation, chanmask);
2985
2986 snd_hda_codec_write(codec, 0x1, 0,
2987 Nv_VERB_SET_Info_Frame_Checksum,
2988 (0x71 - chan - chanmask));
2989}
2990
84eb01be
TI		 2991static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2992 struct hda_codec *codec,
2993 struct snd_pcm_substream *substream)
2994{
2995 struct hdmi_spec *spec = codec->spec;
2996 int i;
2997
2998 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2999 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3000 for (i = 0; i < 4; i++) {
3001 /* set the stream id */
3002 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3003 AC_VERB_SET_CHANNEL_STREAMID, 0);
3004 /* set the stream format */
3005 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3006 AC_VERB_SET_STREAM_FORMAT, 0);
3007 }
3008
1f348522
AP		 3009 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3010 * streams are disabled. */
3011 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3012
84eb01be
TI		 3013 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3014}
3015
3016static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3017 struct hda_codec *codec,
3018 unsigned int stream_tag,
3019 unsigned int format,
3020 struct snd_pcm_substream *substream)
3021{
3022 int chs;
112daa7a 3023 unsigned int dataDCC2, channel_id;
84eb01be 3024 int i;
7c935976 3025 struct hdmi_spec *spec = codec->spec;
e3245cdd 3026 struct hda_spdif_out *spdif;
bce0d2a8 3027 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3028
3029 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3030 per_cvt = get_cvt(spec, 0);
3031 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3032
3033 chs = substream->runtime->channels;
84eb01be 3034
84eb01be
TI		 3035 dataDCC2 = 0x2;
3036
84eb01be 3037 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3038 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3039 snd_hda_codec_write(codec,
3040 nvhdmi_master_con_nid_7x,
3041 0,
3042 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3043 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3044
3045 /* set the stream id */
3046 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3047 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3048
3049 /* set the stream format */
3050 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3051 AC_VERB_SET_STREAM_FORMAT, format);
3052
3053 /* turn on again (if needed) */
3054 /* enable and set the channel status audio/data flag */
7c935976 3055 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3056 snd_hda_codec_write(codec,
3057 nvhdmi_master_con_nid_7x,
3058 0,
3059 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3060 spdif->ctls & 0xff);
84eb01be
TI		 3061 snd_hda_codec_write(codec,
3062 nvhdmi_master_con_nid_7x,
3063 0,
3064 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3065 }
3066
3067 for (i = 0; i < 4; i++) {
3068 if (chs == 2)
3069 channel_id = 0;
3070 else
3071 channel_id = i * 2;
3072
3073 /* turn off SPDIF once;
3074 *otherwise the IEC958 bits won't be updated
3075 */
3076 if (codec->spdif_status_reset &&
7c935976 3077 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3078 snd_hda_codec_write(codec,
3079 nvhdmi_con_nids_7x[i],
3080 0,
3081 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3082 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3083 /* set the stream id */
3084 snd_hda_codec_write(codec,
3085 nvhdmi_con_nids_7x[i],
3086 0,
3087 AC_VERB_SET_CHANNEL_STREAMID,
3088 (stream_tag << 4) | channel_id);
3089 /* set the stream format */
3090 snd_hda_codec_write(codec,
3091 nvhdmi_con_nids_7x[i],
3092 0,
3093 AC_VERB_SET_STREAM_FORMAT,
3094 format);
3095 /* turn on again (if needed) */
3096 /* enable and set the channel status audio/data flag */
3097 if (codec->spdif_status_reset &&
7c935976 3098 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3099 snd_hda_codec_write(codec,
3100 nvhdmi_con_nids_7x[i],
3101 0,
3102 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3103 spdif->ctls & 0xff);
84eb01be
TI		 3104 snd_hda_codec_write(codec,
3105 nvhdmi_con_nids_7x[i],
3106 0,
3107 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3108 }
3109 }
3110
1f348522 3111 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3112
3113 mutex_unlock(&codec->spdif_mutex);
3114 return 0;
3115}
3116
fb79e1e0 3117static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3118 .substreams = 1,
3119 .channels_min = 2,
3120 .channels_max = 8,
3121 .nid = nvhdmi_master_con_nid_7x,
3122 .rates = SUPPORTED_RATES,
3123 .maxbps = SUPPORTED_MAXBPS,
3124 .formats = SUPPORTED_FORMATS,
3125 .ops = {
3126 .open = simple_playback_pcm_open,
3127 .close = nvhdmi_8ch_7x_pcm_close,
3128 .prepare = nvhdmi_8ch_7x_pcm_prepare
3129 },
3130};
3131
84eb01be
TI		 3132static int patch_nvhdmi_2ch(struct hda_codec *codec)
3133{
3134 struct hdmi_spec *spec;
d0b1252d
TI		 3135 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3136 nvhdmi_master_pin_nid_7x);
3137 if (err < 0)
3138 return err;
84eb01be 3139
ceaa86ba 3140 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3141 /* override the PCM rates, etc, as the codec doesn't give full list */
3142 spec = codec->spec;
3143 spec->pcm_playback.rates = SUPPORTED_RATES;
3144 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3145 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3146 return 0;
3147}
3148
53775b0d
TI		 3149static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3150{
3151 struct hdmi_spec *spec = codec->spec;
3152 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3153 if (!err) {
3154 struct hda_pcm *info = get_pcm_rec(spec, 0);
3155 info->own_chmap = true;
3156 }
53775b0d
TI		 3157 return err;
3158}
3159
3160static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3161{
3162 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3163 struct hda_pcm *info;
53775b0d
TI		 3164 struct snd_pcm_chmap *chmap;
3165 int err;
3166
3167 err = simple_playback_build_controls(codec);
3168 if (err < 0)
3169 return err;
3170
3171 /* add channel maps */
bce0d2a8
TI		 3172 info = get_pcm_rec(spec, 0);
3173 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3174 SNDRV_PCM_STREAM_PLAYBACK,
3175 snd_pcm_alt_chmaps, 8, 0, &chmap);
3176 if (err < 0)
3177 return err;
b9a94a9c 3178 switch (codec->preset->vendor_id) {
53775b0d
TI		 3179 case 0x10de0002:
3180 case 0x10de0003:
3181 case 0x10de0005:
3182 case 0x10de0006:
3183 chmap->channel_mask = (1U << 2) | (1U << 8);
3184 break;
3185 case 0x10de0007:
3186 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3187 }
3188 return 0;
3189}
3190
84eb01be
TI		 3191static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3192{
3193 struct hdmi_spec *spec;
3194 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3195 if (err < 0)
3196 return err;
3197 spec = codec->spec;
3198 spec->multiout.max_channels = 8;
d0b1252d 3199 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3200 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3201 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3202 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3203
3204 /* Initialize the audio infoframe channel mask and checksum to something
3205 * valid */
3206 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3207
84eb01be
TI		 3208 return 0;
3209}
3210
611885bc
AH		 3211/*
3212 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3213 * - 0x10de0015
3214 * - 0x10de0040
3215 */
3216static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3217 int channels)
3218{
3219 if (cap->ca_index == 0x00 && channels == 2)
3220 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3221
3222 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
3223}
3224
3225static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
3226{
3227 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3228 return -EINVAL;
3229
3230 return 0;
3231}
3232
3233static int patch_nvhdmi(struct hda_codec *codec)
3234{
3235 struct hdmi_spec *spec;
3236 int err;
3237
3238 err = patch_generic_hdmi(codec);
3239 if (err)
3240 return err;
3241
3242 spec = codec->spec;
75fae117 3243 spec->dyn_pin_out = true;
611885bc
AH		 3244
3245 spec->ops.chmap_cea_alloc_validate_get_type =
3246 nvhdmi_chmap_cea_alloc_validate_get_type;
3247 spec->ops.chmap_validate = nvhdmi_chmap_validate;
3248
3249 return 0;
3250}
3251
26e9a960
TR		 3252/*
3253 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3254 * accessed using vendor-defined verbs. These registers can be used for
3255 * interoperability between the HDA and HDMI drivers.
3256 */
3257
3258/* Audio Function Group node */
3259#define NVIDIA_AFG_NID 0x01
3260
3261/*
3262 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3263 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3264 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3265 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3266 * additional bit (at position 30) to signal the validity of the format.
3267 *
3268 * | 31 | 30 | 29 16 | 15 0 |
3269 * +---------+-------+--------+--------+
3270 * | TRIGGER | VALID | UNUSED | FORMAT |
3271 * +-----------------------------------|
3272 *
3273 * Note that for the trigger bit to take effect it needs to change value
3274 * (i.e. it needs to be toggled).
3275 */
3276#define NVIDIA_GET_SCRATCH0 0xfa6
3277#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3278#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3279#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3280#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3281#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3282#define NVIDIA_SCRATCH_VALID (1 << 6)
3283
3284#define NVIDIA_GET_SCRATCH1 0xfab
3285#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3286#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3287#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3288#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3289
3290/*
3291 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3292 * the format is invalidated so that the HDMI codec can be disabled.
3293 */
3294static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3295{
3296 unsigned int value;
3297
3298 /* bits [31:30] contain the trigger and valid bits */
3299 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3300 NVIDIA_GET_SCRATCH0, 0);
3301 value = (value >> 24) & 0xff;
3302
3303 /* bits [15:0] are used to store the HDA format */
3304 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3305 NVIDIA_SET_SCRATCH0_BYTE0,
3306 (format >> 0) & 0xff);
3307 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3308 NVIDIA_SET_SCRATCH0_BYTE1,
3309 (format >> 8) & 0xff);
3310
3311 /* bits [16:24] are unused */
3312 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3313 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3314
3315 /*
3316 * Bit 30 signals that the data is valid and hence that HDMI audio can
3317 * be enabled.
3318 */
3319 if (format == 0)
3320 value &= ~NVIDIA_SCRATCH_VALID;
3321 else
3322 value |= NVIDIA_SCRATCH_VALID;
3323
3324 /*
3325 * Whenever the trigger bit is toggled, an interrupt is raised in the
3326 * HDMI codec. The HDMI driver will use that as trigger to update its
3327 * configuration.
3328 */
3329 value ^= NVIDIA_SCRATCH_TRIGGER;
3330
3331 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3332 NVIDIA_SET_SCRATCH0_BYTE3, value);
3333}
3334
3335static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3336 struct hda_codec *codec,
3337 unsigned int stream_tag,
3338 unsigned int format,
3339 struct snd_pcm_substream *substream)
3340{
3341 int err;
3342
3343 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3344 format, substream);
3345 if (err < 0)
3346 return err;
3347
3348 /* notify the HDMI codec of the format change */
3349 tegra_hdmi_set_format(codec, format);
3350
3351 return 0;
3352}
3353
3354static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3355 struct hda_codec *codec,
3356 struct snd_pcm_substream *substream)
3357{
3358 /* invalidate the format in the HDMI codec */
3359 tegra_hdmi_set_format(codec, 0);
3360
3361 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3362}
3363
3364static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3365{
3366 struct hdmi_spec *spec = codec->spec;
3367 unsigned int i;
3368
3369 for (i = 0; i < spec->num_pins; i++) {
3370 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3371
3372 if (pcm->pcm_type == type)
3373 return pcm;
3374 }
3375
3376 return NULL;
3377}
3378
3379static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3380{
3381 struct hda_pcm_stream *stream;
3382 struct hda_pcm *pcm;
3383 int err;
3384
3385 err = generic_hdmi_build_pcms(codec);
3386 if (err < 0)
3387 return err;
3388
3389 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3390 if (!pcm)
3391 return -ENODEV;
3392
3393 /*
3394 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3395 * codec about format changes.
3396 */
3397 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3398 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3399 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3400
3401 return 0;
3402}
3403
3404static int patch_tegra_hdmi(struct hda_codec *codec)
3405{
3406 int err;
3407
3408 err = patch_generic_hdmi(codec);
3409 if (err)
3410 return err;
3411
3412 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3413
3414 return 0;
3415}
3416
84eb01be 3417/*
5a613584 3418 * ATI/AMD-specific implementations
84eb01be
TI		 3419 */
3420
5a613584 3421#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3422 ((codec)->core.vendor_id == 0x1002aa01 && \
3423 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3424#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3425
3426/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3427#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3428#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3429#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3430#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3431#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3432#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3433#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3434#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3435#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3436#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3437#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3438#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3439#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3440#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3441#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3442#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3443#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3444#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3445#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3446#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3447#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3448#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3449#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3450#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3451
84d69e79
AH		 3452/* AMD specific HDA cvt verbs */
3453#define ATI_VERB_SET_RAMP_RATE 0x770
3454#define ATI_VERB_GET_RAMP_RATE 0xf70
3455
5a613584
AH		 3456#define ATI_OUT_ENABLE 0x1
3457
3458#define ATI_MULTICHANNEL_MODE_PAIRED 0
3459#define ATI_MULTICHANNEL_MODE_SINGLE 1
3460
461cf6b3
AH		 3461#define ATI_HBR_CAPABLE 0x01
3462#define ATI_HBR_ENABLE 0x10
3463
89250f84
AH		 3464static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3465 unsigned char *buf, int *eld_size)
3466{
3467 /* call hda_eld.c ATI/AMD-specific function */
3468 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3469 is_amdhdmi_rev3_or_later(codec));
3470}
3471
5a613584
AH		 3472static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3473 int active_channels, int conn_type)
3474{
3475 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3476}
3477
3478static int atihdmi_paired_swap_fc_lfe(int pos)
3479{
3480 /*
3481 * ATI/AMD have automatic FC/LFE swap built-in
3482 * when in pairwise mapping mode.
3483 */
3484
3485 switch (pos) {
3486 /* see channel_allocations[].speakers[] */
3487 case 2: return 3;
3488 case 3: return 2;
3489 default: break;
3490 }
3491
3492 return pos;
3493}
3494
3495static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3496{
3497 struct cea_channel_speaker_allocation *cap;
3498 int i, j;
3499
3500 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3501
3502 cap = &channel_allocations[get_channel_allocation_order(ca)];
3503 for (i = 0; i < chs; ++i) {
3504 int mask = to_spk_mask(map[i]);
3505 bool ok = false;
3506 bool companion_ok = false;
3507
3508 if (!mask)
3509 continue;
3510
3511 for (j = 0 + i % 2; j < 8; j += 2) {
3512 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3513 if (cap->speakers[chan_idx] == mask) {
3514 /* channel is in a supported position */
3515 ok = true;
3516
3517 if (i % 2 == 0 && i + 1 < chs) {
3518 /* even channel, check the odd companion */
3519 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3520 int comp_mask_req = to_spk_mask(map[i+1]);
3521 int comp_mask_act = cap->speakers[comp_chan_idx];
3522
3523 if (comp_mask_req == comp_mask_act)
3524 companion_ok = true;
3525 else
3526 return -EINVAL;
3527 }
3528 break;
3529 }
3530 }
3531
3532 if (!ok)
3533 return -EINVAL;
3534
3535 if (companion_ok)
3536 i++; /* companion channel already checked */
3537 }
3538
3539 return 0;
3540}
3541
3542static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3543 int hdmi_slot, int stream_channel)
3544{
3545 int verb;
3546 int ati_channel_setup = 0;
3547
3548 if (hdmi_slot > 7)
3549 return -EINVAL;
3550
3551 if (!has_amd_full_remap_support(codec)) {
3552 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3553
3554 /* In case this is an odd slot but without stream channel, do not
3555 * disable the slot since the corresponding even slot could have a
3556 * channel. In case neither have a channel, the slot pair will be
3557 * disabled when this function is called for the even slot. */
3558 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3559 return 0;
3560
3561 hdmi_slot -= hdmi_slot % 2;
3562
3563 if (stream_channel != 0xf)
3564 stream_channel -= stream_channel % 2;
3565 }
3566
3567 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3568
3569 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3570
3571 if (stream_channel != 0xf)
3572 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3573
3574 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3575}
3576
3577static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3578 int asp_slot)
3579{
3580 bool was_odd = false;
3581 int ati_asp_slot = asp_slot;
3582 int verb;
3583 int ati_channel_setup;
3584
3585 if (asp_slot > 7)
3586 return -EINVAL;
3587
3588 if (!has_amd_full_remap_support(codec)) {
3589 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3590 if (ati_asp_slot % 2 != 0) {
3591 ati_asp_slot -= 1;
3592 was_odd = true;
3593 }
3594 }
3595
3596 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3597
3598 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3599
3600 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3601 return 0xf;
3602
3603 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3604}
84eb01be 3605
5a613584
AH		 3606static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3607 int channels)
3608{
3609 int c;
3610
3611 /*
3612 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3613 * we need to take that into account (a single channel may take 2
3614 * channel slots if we need to carry a silent channel next to it).
3615 * On Rev3+ AMD codecs this function is not used.
3616 */
3617 int chanpairs = 0;
3618
3619 /* We only produce even-numbered channel count TLVs */
3620 if ((channels % 2) != 0)
3621 return -1;
3622
3623 for (c = 0; c < 7; c += 2) {
3624 if (cap->speakers[c] || cap->speakers[c+1])
3625 chanpairs++;
3626 }
3627
3628 if (chanpairs * 2 != channels)
3629 return -1;
3630
3631 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3632}
3633
3634static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3635 unsigned int *chmap, int channels)
3636{
3637 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3638 int count = 0;
3639 int c;
3640
3641 for (c = 7; c >= 0; c--) {
3642 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3643 int spk = cap->speakers[chan];
3644 if (!spk) {
3645 /* add N/A channel if the companion channel is occupied */
3646 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3647 chmap[count++] = SNDRV_CHMAP_NA;
3648
3649 continue;
3650 }
3651
3652 chmap[count++] = spk_to_chmap(spk);
3653 }
3654
3655 WARN_ON(count != channels);
3656}
3657
461cf6b3
AH		 3658static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3659 bool hbr)
3660{
3661 int hbr_ctl, hbr_ctl_new;
3662
3663 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3664 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3665 if (hbr)
3666 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3667 else
3668 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3669
4e76a883
TI		 3670 codec_dbg(codec,
3671 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3672 pin_nid,
3673 hbr_ctl == hbr_ctl_new ? "" : "new-",
3674 hbr_ctl_new);
3675
3676 if (hbr_ctl != hbr_ctl_new)
3677 snd_hda_codec_write(codec, pin_nid, 0,
3678 ATI_VERB_SET_HBR_CONTROL,
3679 hbr_ctl_new);
3680
3681 } else if (hbr)
3682 return -EINVAL;
3683
3684 return 0;
3685}
3686
84d69e79
AH		 3687static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3688 hda_nid_t pin_nid, u32 stream_tag, int format)
3689{
3690
3691 if (is_amdhdmi_rev3_or_later(codec)) {
3692 int ramp_rate = 180; /* default as per AMD spec */
3693 /* disable ramp-up/down for non-pcm as per AMD spec */
3694 if (format & AC_FMT_TYPE_NON_PCM)
3695 ramp_rate = 0;
3696
3697 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3698 }
3699
3700 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3701}
3702
3703
5a613584 3704static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3705{
3706 struct hdmi_spec *spec = codec->spec;
5a613584 3707 int pin_idx, err;
84eb01be 3708
5a613584
AH		 3709 err = generic_hdmi_init(codec);
3710
3711 if (err)
84eb01be 3712 return err;
5a613584
AH		 3713
3714 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3715 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3716
3717 /* make sure downmix information in infoframe is zero */
3718 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3719
3720 /* enable channel-wise remap mode if supported */
3721 if (has_amd_full_remap_support(codec))
3722 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3723 ATI_VERB_SET_MULTICHANNEL_MODE,
3724 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3725 }
5a613584 3726
84eb01be
TI		 3727 return 0;
3728}
3729
84eb01be
TI		 3730static int patch_atihdmi(struct hda_codec *codec)
3731{
3732 struct hdmi_spec *spec;
5a613584
AH		 3733 struct hdmi_spec_per_cvt *per_cvt;
3734 int err, cvt_idx;
3735
3736 err = patch_generic_hdmi(codec);
3737
3738 if (err)
d0b1252d 3739 return err;
5a613584
AH		 3740
3741 codec->patch_ops.init = atihdmi_init;
3742
d0b1252d 3743 spec = codec->spec;
5a613584 3744
89250f84 3745 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3746 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3747 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3748 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3749 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3750 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3751
3752 if (!has_amd_full_remap_support(codec)) {
3753 /* override to ATI/AMD-specific versions with pairwise mapping */
3754 spec->ops.chmap_cea_alloc_validate_get_type =
3755 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3756 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3757 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3758 }
3759
3760 /* ATI/AMD converters do not advertise all of their capabilities */
3761 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3762 per_cvt = get_cvt(spec, cvt_idx);
3763 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3764 per_cvt->rates |= SUPPORTED_RATES;
3765 per_cvt->formats |= SUPPORTED_FORMATS;
3766 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3767 }
3768
3769 spec->channels_max = max(spec->channels_max, 8u);
3770
84eb01be
TI		 3771 return 0;
3772}
3773
3de5ff88
AL		 3774/* VIA HDMI Implementation */
3775#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3776#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3777
3de5ff88
AL		 3778static int patch_via_hdmi(struct hda_codec *codec)
3779{
250e41ac 3780 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3781}
84eb01be
TI		 3782
3783/*
3784 * patch entries
3785 */
b9a94a9c
TI		 3786static const struct hda_device_id snd_hda_id_hdmi[] = {
3787HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3788HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3789HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3790HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3791HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3792HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3793HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3794HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3795HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3796HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3797HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3798HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3799HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3800HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3801HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3802HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3803HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3804HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3805HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3806HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3807HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3808HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3809HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3810/* 17 is known to be absent */
b9a94a9c
TI		 3811HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3812HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3813HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3814HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3815HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3816HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3817HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3818HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3819HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3820HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3821HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3822HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3823HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3824HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3825HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3826HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3827HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3828HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3829HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3830HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3831HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3832HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3833HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3834HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3835HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3836HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3837HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3838HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3839HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3840HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3841HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3842HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3843HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3844HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3845HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3846HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3847HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
91815d8a 3848HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
b9a94a9c
TI		 3849HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3850HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3851HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3852HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3853/* special ID for generic HDMI */
b9a94a9c 3854HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3855{} /* terminator */
3856};
b9a94a9c 3857MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3858
3859MODULE_LICENSE("GPL");
3860MODULE_DESCRIPTION("HDMI HD-audio codec");
3861MODULE_ALIAS("snd-hda-codec-intelhdmi");
3862MODULE_ALIAS("snd-hda-codec-nvhdmi");
3863MODULE_ALIAS("snd-hda-codec-atihdmi");
3864
d8a766a1 3865static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3866 .id = snd_hda_id_hdmi,
84eb01be
TI		 3867};
3868
d8a766a1 3869module_hda_codec_driver(hdmi_driver);
Linux kernel - Deliverables
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