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ALSA: hda - hdmi playback without monitor in dynamic pcm bind mode
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
84eb01be
TI		 42#include "hda_codec.h"
43#include "hda_local.h"
1835a0f9 44#include "hda_jack.h"
84eb01be 45
0ebaa24c
TI		 46static bool static_hdmi_pcm;
47module_param(static_hdmi_pcm, bool, 0644);
48MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
7639a06c
TI		 50#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 53#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 54#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
432ac1a2 55#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a
LY		 56 || is_skylake(codec) || is_broxton(codec) \
57 || is_kabylake(codec))
75dcbe4d 58
7639a06c
TI		 59#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
60#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 61#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 62
384a48d7
SW		 63struct hdmi_spec_per_cvt {
64 hda_nid_t cvt_nid;
65 int assigned;
66 unsigned int channels_min;
67 unsigned int channels_max;
68 u32 rates;
69 u64 formats;
70 unsigned int maxbps;
71};
079d88cc 72
4eea3091
TI		 73/* max. connections to a widget */
74#define HDA_MAX_CONNECTIONS 32
75
384a48d7
SW		 76struct hdmi_spec_per_pin {
77 hda_nid_t pin_nid;
78 int num_mux_nids;
79 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 80 int mux_idx;
1df5a06a 81 hda_nid_t cvt_nid;
744626da
WF		 82
83 struct hda_codec *codec;
384a48d7 84 struct hdmi_eld sink_eld;
a4e9a38b 85 struct mutex lock;
744626da 86 struct delayed_work work;
92c69e79 87 struct snd_kcontrol *eld_ctl;
788d441a 88 struct snd_jack *acomp_jack; /* jack via audio component */
6590faab 89 struct hda_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
c6e8453e 90 int repoll_count;
b054087d
TI		 91 bool setup; /* the stream has been set up by prepare callback */
92 int channels; /* current number of channels */
1a6003b5 93 bool non_pcm;
d45e6889
TI		 94 bool chmap_set; /* channel-map override by ALSA API? */
95 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 96#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 97 struct snd_info_entry *proc_entry;
98#endif
384a48d7 99};
079d88cc 100
307229d2
AH		 101struct cea_channel_speaker_allocation;
102
103/* operations used by generic code that can be overridden by patches */
104struct hdmi_ops {
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
107
108 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
109 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int asp_slot);
111 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int asp_slot, int channel);
113
114 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
115 int ca, int active_channels, int conn_type);
116
117 /* enable/disable HBR (HD passthrough) */
118 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
119
120 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
121 hda_nid_t pin_nid, u32 stream_tag, int format);
122
123 /* Helpers for producing the channel map TLVs. These can be overridden
124 * for devices that have non-standard mapping requirements. */
125 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
126 int channels);
127 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
128 unsigned int *chmap, int channels);
129
130 /* check that the user-given chmap is supported */
131 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
132};
133
384a48d7
SW		 134struct hdmi_spec {
135 int num_cvts;
bce0d2a8
TI		 136 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
137 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 138
384a48d7 139 int num_pins;
bce0d2a8 140 struct snd_array pins; /* struct hdmi_spec_per_pin */
bbbc7e85 141 struct hda_pcm *pcm_rec[16];
42b29870 142 struct mutex pcm_lock;
d45e6889 143 unsigned int channels_max; /* max over all cvts */
079d88cc 144
4bd038f9 145 struct hdmi_eld temp_eld;
307229d2 146 struct hdmi_ops ops;
75fae117
SW		 147
148 bool dyn_pin_out;
6590faab 149 bool dyn_pcm_assign;
079d88cc 150 /*
5a613584 151 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 152 */
153 struct hda_multi_out multiout;
d0b1252d 154 struct hda_pcm_stream pcm_playback;
25adc137
DH		 155
156 /* i915/powerwell (Haswell+/Valleyview+) specific */
157 struct i915_audio_component_audio_ops i915_audio_ops;
55913110 158 bool i915_bound; /* was i915 bound in this driver? */
079d88cc
WF		 159};
160
f4e3040b 161#ifdef CONFIG_SND_HDA_I915
6603249d
TI		 162#define codec_has_acomp(codec) \
163 ((codec)->bus->core.audio_component != NULL)
f4e3040b
TI		 164#else
165#define codec_has_acomp(codec) false
166#endif
079d88cc
WF		 167
168struct hdmi_audio_infoframe {
169 u8 type; /* 0x84 */
170 u8 ver; /* 0x01 */
171 u8 len; /* 0x0a */
172
53d7d69d
WF		 173 u8 checksum;
174
079d88cc
WF		 175 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
176 u8 SS01_SF24;
177 u8 CXT04;
178 u8 CA;
179 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 180};
181
182struct dp_audio_infoframe {
183 u8 type; /* 0x84 */
184 u8 len; /* 0x1b */
185 u8 ver; /* 0x11 << 2 */
186
187 u8 CC02_CT47; /* match with HDMI infoframe from this on */
188 u8 SS01_SF24;
189 u8 CXT04;
190 u8 CA;
191 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 192};
193
2b203dbb
TI		 194union audio_infoframe {
195 struct hdmi_audio_infoframe hdmi;
196 struct dp_audio_infoframe dp;
197 u8 bytes[0];
198};
199
079d88cc
WF		 200/*
201 * CEA speaker placement:
202 *
203 * FLH FCH FRH
204 * FLW FL FLC FC FRC FR FRW
205 *
206 * LFE
207 * TC
208 *
209 * RL RLC RC RRC RR
210 *
211 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
212 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
213 */
214enum cea_speaker_placement {
215 FL = (1 << 0), /* Front Left */
216 FC = (1 << 1), /* Front Center */
217 FR = (1 << 2), /* Front Right */
218 FLC = (1 << 3), /* Front Left Center */
219 FRC = (1 << 4), /* Front Right Center */
220 RL = (1 << 5), /* Rear Left */
221 RC = (1 << 6), /* Rear Center */
222 RR = (1 << 7), /* Rear Right */
223 RLC = (1 << 8), /* Rear Left Center */
224 RRC = (1 << 9), /* Rear Right Center */
225 LFE = (1 << 10), /* Low Frequency Effect */
226 FLW = (1 << 11), /* Front Left Wide */
227 FRW = (1 << 12), /* Front Right Wide */
228 FLH = (1 << 13), /* Front Left High */
229 FCH = (1 << 14), /* Front Center High */
230 FRH = (1 << 15), /* Front Right High */
231 TC = (1 << 16), /* Top Center */
232};
233
234/*
235 * ELD SA bits in the CEA Speaker Allocation data block
236 */
237static int eld_speaker_allocation_bits[] = {
238 [0] = FL | FR,
239 [1] = LFE,
240 [2] = FC,
241 [3] = RL | RR,
242 [4] = RC,
243 [5] = FLC | FRC,
244 [6] = RLC | RRC,
245 /* the following are not defined in ELD yet */
246 [7] = FLW | FRW,
247 [8] = FLH | FRH,
248 [9] = TC,
249 [10] = FCH,
250};
251
252struct cea_channel_speaker_allocation {
253 int ca_index;
254 int speakers[8];
255
256 /* derived values, just for convenience */
257 int channels;
258 int spk_mask;
259};
260
261/*
262 * ALSA sequence is:
263 *
264 * surround40 surround41 surround50 surround51 surround71
265 * ch0 front left = = = =
266 * ch1 front right = = = =
267 * ch2 rear left = = = =
268 * ch3 rear right = = = =
269 * ch4 LFE center center center
270 * ch5 LFE LFE
271 * ch6 side left
272 * ch7 side right
273 *
274 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
275 */
276static int hdmi_channel_mapping[0x32][8] = {
277 /* stereo */
278 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
279 /* 2.1 */
280 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
281 /* Dolby Surround */
282 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
283 /* surround40 */
284 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
285 /* 4ch */
286 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
287 /* surround41 */
9396d317 288 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 289 /* surround50 */
290 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
291 /* surround51 */
292 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
293 /* 7.1 */
294 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
295};
296
297/*
298 * This is an ordered list!
299 *
300 * The preceding ones have better chances to be selected by
53d7d69d 301 * hdmi_channel_allocation().
079d88cc
WF		 302 */
303static struct cea_channel_speaker_allocation channel_allocations[] = {
304/* channel: 7 6 5 4 3 2 1 0 */
305{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
306 /* 2.1 */
307{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
308 /* Dolby Surround */
309{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
310 /* surround40 */
311{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
312 /* surround41 */
313{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
314 /* surround50 */
315{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
316 /* surround51 */
317{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
318 /* 6.1 */
319{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
320 /* surround71 */
321{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
322
323{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
324{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
325{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
326{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
327{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
328{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
329{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
330{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
331{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
332{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
333{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
334{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
335{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
336{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
337{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
338{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
339{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
340{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
341{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
342{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
343{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
344{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
345{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
346{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
347{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
348{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
349{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
350{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
351{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
352{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
353{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
354{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
355{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
356{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
357{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
358{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
359{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
360{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
361{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
362{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
363{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
364};
365
366
367/*
368 * HDMI routines
369 */
370
bce0d2a8
TI		 371#define get_pin(spec, idx) \
372 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
373#define get_cvt(spec, idx) \
374 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
bbbc7e85 375#define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
bce0d2a8 376
4e76a883 377static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 378{
4e76a883 379 struct hdmi_spec *spec = codec->spec;
384a48d7 380 int pin_idx;
079d88cc 381
384a48d7 382 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 383 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 384 return pin_idx;
079d88cc 385
4e76a883 386 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 387 return -EINVAL;
388}
389
4e76a883 390static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 391 struct hda_pcm_stream *hinfo)
392{
4e76a883 393 struct hdmi_spec *spec = codec->spec;
6590faab 394 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 395 int pin_idx;
396
6590faab
LY		 397 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
398 per_pin = get_pin(spec, pin_idx);
399 if (per_pin->pcm && per_pin->pcm->stream == hinfo)
384a48d7 400 return pin_idx;
6590faab 401 }
384a48d7 402
6590faab 403 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 404 return -EINVAL;
405}
406
4e76a883 407static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 408{
4e76a883 409 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 410 int cvt_idx;
411
412 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 413 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 414 return cvt_idx;
415
4e76a883 416 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 417 return -EINVAL;
418}
419
14bc52b8
PLB		 420static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
421 struct snd_ctl_elem_info *uinfo)
422{
423 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 424 struct hdmi_spec *spec = codec->spec;
a4e9a38b 425 struct hdmi_spec_per_pin *per_pin;
68e03de9 426 struct hdmi_eld *eld;
14bc52b8
PLB		 427 int pin_idx;
428
14bc52b8
PLB		 429 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
430
431 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 432 per_pin = get_pin(spec, pin_idx);
433 eld = &per_pin->sink_eld;
68e03de9 434
a4e9a38b 435 mutex_lock(&per_pin->lock);
68e03de9 436 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 437 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 438
439 return 0;
440}
441
442static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
443 struct snd_ctl_elem_value *ucontrol)
444{
445 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 446 struct hdmi_spec *spec = codec->spec;
a4e9a38b 447 struct hdmi_spec_per_pin *per_pin;
68e03de9 448 struct hdmi_eld *eld;
14bc52b8
PLB		 449 int pin_idx;
450
14bc52b8 451 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 452 per_pin = get_pin(spec, pin_idx);
453 eld = &per_pin->sink_eld;
68e03de9 454
a4e9a38b 455 mutex_lock(&per_pin->lock);
68e03de9 456 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 457 mutex_unlock(&per_pin->lock);
68e03de9
DH		 458 snd_BUG();
459 return -EINVAL;
460 }
461
462 memset(ucontrol->value.bytes.data, 0,
463 ARRAY_SIZE(ucontrol->value.bytes.data));
464 if (eld->eld_valid)
465 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
466 eld->eld_size);
a4e9a38b 467 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 468
469 return 0;
470}
471
472static struct snd_kcontrol_new eld_bytes_ctl = {
473 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
474 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
475 .name = "ELD",
476 .info = hdmi_eld_ctl_info,
477 .get = hdmi_eld_ctl_get,
478};
479
480static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
481 int device)
482{
483 struct snd_kcontrol *kctl;
484 struct hdmi_spec *spec = codec->spec;
485 int err;
486
487 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
488 if (!kctl)
489 return -ENOMEM;
490 kctl->private_value = pin_idx;
491 kctl->id.device = device;
492
bce0d2a8 493 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 494 if (err < 0)
495 return err;
496
bce0d2a8 497 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 498 return 0;
499}
500
079d88cc
WF		 501#ifdef BE_PARANOID
502static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
503 int *packet_index, int *byte_index)
504{
505 int val;
506
507 val = snd_hda_codec_read(codec, pin_nid, 0,
508 AC_VERB_GET_HDMI_DIP_INDEX, 0);
509
510 *packet_index = val >> 5;
511 *byte_index = val & 0x1f;
512}
513#endif
514
515static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
516 int packet_index, int byte_index)
517{
518 int val;
519
520 val = (packet_index << 5) | (byte_index & 0x1f);
521
522 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
523}
524
525static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
526 unsigned char val)
527{
528 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
529}
530
384a48d7 531static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 532{
75fae117
SW		 533 struct hdmi_spec *spec = codec->spec;
534 int pin_out;
535
079d88cc
WF		 536 /* Unmute */
537 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
538 snd_hda_codec_write(codec, pin_nid, 0,
539 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 540
541 if (spec->dyn_pin_out)
542 /* Disable pin out until stream is active */
543 pin_out = 0;
544 else
545 /* Enable pin out: some machines with GM965 gets broken output
546 * when the pin is disabled or changed while using with HDMI
547 */
548 pin_out = PIN_OUT;
549
079d88cc 550 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 551 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 552}
553
384a48d7 554static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 555{
384a48d7 556 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 557 AC_VERB_GET_CVT_CHAN_COUNT, 0);
558}
559
560static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 561 hda_nid_t cvt_nid, int chs)
079d88cc 562{
384a48d7
SW		 563 if (chs != hdmi_get_channel_count(codec, cvt_nid))
564 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 565 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
566}
567
a4e9a38b
TI		 568/*
569 * ELD proc files
570 */
571
cd6a6503 572#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 573static void print_eld_info(struct snd_info_entry *entry,
574 struct snd_info_buffer *buffer)
575{
576 struct hdmi_spec_per_pin *per_pin = entry->private_data;
577
578 mutex_lock(&per_pin->lock);
579 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
580 mutex_unlock(&per_pin->lock);
581}
582
583static void write_eld_info(struct snd_info_entry *entry,
584 struct snd_info_buffer *buffer)
585{
586 struct hdmi_spec_per_pin *per_pin = entry->private_data;
587
588 mutex_lock(&per_pin->lock);
589 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
590 mutex_unlock(&per_pin->lock);
591}
592
593static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
594{
595 char name[32];
596 struct hda_codec *codec = per_pin->codec;
597 struct snd_info_entry *entry;
598 int err;
599
600 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 601 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 602 if (err < 0)
603 return err;
604
605 snd_info_set_text_ops(entry, per_pin, print_eld_info);
606 entry->c.text.write = write_eld_info;
607 entry->mode |= S_IWUSR;
608 per_pin->proc_entry = entry;
609
610 return 0;
611}
612
613static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
614{
1947a114 615 if (!per_pin->codec->bus->shutdown) {
c560a679 616 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 617 per_pin->proc_entry = NULL;
618 }
619}
620#else
b55447a7
TI		 621static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
622 int index)
a4e9a38b
TI		 623{
624 return 0;
625}
b55447a7 626static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 627{
628}
629#endif
079d88cc
WF		 630
631/*
632 * Channel mapping routines
633 */
634
635/*
636 * Compute derived values in channel_allocations[].
637 */
638static void init_channel_allocations(void)
639{
640 int i, j;
641 struct cea_channel_speaker_allocation *p;
642
643 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
644 p = channel_allocations + i;
645 p->channels = 0;
646 p->spk_mask = 0;
647 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
648 if (p->speakers[j]) {
649 p->channels++;
650 p->spk_mask |= p->speakers[j];
651 }
652 }
653}
654
72357c78
WX		 655static int get_channel_allocation_order(int ca)
656{
657 int i;
658
659 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
660 if (channel_allocations[i].ca_index == ca)
661 break;
662 }
663 return i;
664}
665
079d88cc
WF		 666/*
667 * The transformation takes two steps:
668 *
669 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
670 * spk_mask => (channel_allocations[]) => ai->CA
671 *
672 * TODO: it could select the wrong CA from multiple candidates.
673*/
79514d47
TI		 674static int hdmi_channel_allocation(struct hda_codec *codec,
675 struct hdmi_eld *eld, int channels)
079d88cc 676{
079d88cc 677 int i;
53d7d69d 678 int ca = 0;
079d88cc 679 int spk_mask = 0;
079d88cc
WF		 680 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
681
682 /*
683 * CA defaults to 0 for basic stereo audio
684 */
685 if (channels <= 2)
686 return 0;
687
079d88cc
WF		 688 /*
689 * expand ELD's speaker allocation mask
690 *
691 * ELD tells the speaker mask in a compact(paired) form,
692 * expand ELD's notions to match the ones used by Audio InfoFrame.
693 */
694 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 695 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 696 spk_mask |= eld_speaker_allocation_bits[i];
697 }
698
699 /* search for the first working match in the CA table */
700 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
701 if (channels == channel_allocations[i].channels &&
702 (spk_mask & channel_allocations[i].spk_mask) ==
703 channel_allocations[i].spk_mask) {
53d7d69d 704 ca = channel_allocations[i].ca_index;
079d88cc
WF		 705 break;
706 }
707 }
708
18e39186
AH		 709 if (!ca) {
710 /* if there was no match, select the regular ALSA channel
711 * allocation with the matching number of channels */
712 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
713 if (channels == channel_allocations[i].channels) {
714 ca = channel_allocations[i].ca_index;
715 break;
716 }
717 }
718 }
719
1613d6b4 720 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
79514d47 721 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 722 ca, channels, buf);
079d88cc 723
53d7d69d 724 return ca;
079d88cc
WF		 725}
726
727static void hdmi_debug_channel_mapping(struct hda_codec *codec,
728 hda_nid_t pin_nid)
729{
730#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 731 struct hdmi_spec *spec = codec->spec;
079d88cc 732 int i;
307229d2 733 int channel;
079d88cc
WF		 734
735 for (i = 0; i < 8; i++) {
307229d2 736 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 737 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 738 channel, i);
079d88cc
WF		 739 }
740#endif
741}
742
d45e6889 743static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 744 hda_nid_t pin_nid,
433968da 745 bool non_pcm,
53d7d69d 746 int ca)
079d88cc 747{
307229d2 748 struct hdmi_spec *spec = codec->spec;
90f28002 749 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 750 int i;
079d88cc 751 int err;
72357c78 752 int order;
433968da 753 int non_pcm_mapping[8];
079d88cc 754
72357c78 755 order = get_channel_allocation_order(ca);
90f28002 756 ch_alloc = &channel_allocations[order];
433968da 757
079d88cc 758 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 759 int hdmi_slot = 0;
760 /* fill actual channel mappings in ALSA channel (i) order */
761 for (i = 0; i < ch_alloc->channels; i++) {
762 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
763 hdmi_slot++; /* skip zero slots */
764
765 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
766 }
767 /* fill the rest of the slots with ALSA channel 0xf */
768 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
769 if (!ch_alloc->speakers[7 - hdmi_slot])
770 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 771 }
772
433968da 773 if (non_pcm) {
90f28002 774 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 775 non_pcm_mapping[i] = (i << 4) | i;
433968da 776 for (; i < 8; i++)
11f7c52d 777 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 778 }
779
079d88cc 780 for (i = 0; i < 8; i++) {
307229d2
AH		 781 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
782 int hdmi_slot = slotsetup & 0x0f;
783 int channel = (slotsetup & 0xf0) >> 4;
784 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 785 if (err) {
4e76a883 786 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 787 break;
788 }
789 }
079d88cc
WF		 790}
791
d45e6889
TI		 792struct channel_map_table {
793 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 794 int spk_mask; /* speaker position bit mask */
795};
796
797static struct channel_map_table map_tables[] = {
a5b7d510
AH		 798 { SNDRV_CHMAP_FL, FL },
799 { SNDRV_CHMAP_FR, FR },
800 { SNDRV_CHMAP_RL, RL },
801 { SNDRV_CHMAP_RR, RR },
802 { SNDRV_CHMAP_LFE, LFE },
803 { SNDRV_CHMAP_FC, FC },
804 { SNDRV_CHMAP_RLC, RLC },
805 { SNDRV_CHMAP_RRC, RRC },
806 { SNDRV_CHMAP_RC, RC },
807 { SNDRV_CHMAP_FLC, FLC },
808 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 809 { SNDRV_CHMAP_TFL, FLH },
810 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 811 { SNDRV_CHMAP_FLW, FLW },
812 { SNDRV_CHMAP_FRW, FRW },
813 { SNDRV_CHMAP_TC, TC },
94908a39 814 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 815 {} /* terminator */
816};
817
818/* from ALSA API channel position to speaker bit mask */
819static int to_spk_mask(unsigned char c)
820{
821 struct channel_map_table *t = map_tables;
822 for (; t->map; t++) {
823 if (t->map == c)
824 return t->spk_mask;
825 }
826 return 0;
827}
828
829/* from ALSA API channel position to CEA slot */
a5b7d510 830static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 831{
a5b7d510
AH		 832 int mask = to_spk_mask(pos);
833 int i;
d45e6889 834
a5b7d510
AH		 835 if (mask) {
836 for (i = 0; i < 8; i++) {
837 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
838 return i;
839 }
d45e6889 840 }
a5b7d510
AH		 841
842 return -1;
d45e6889
TI		 843}
844
845/* from speaker bit mask to ALSA API channel position */
846static int spk_to_chmap(int spk)
847{
848 struct channel_map_table *t = map_tables;
849 for (; t->map; t++) {
850 if (t->spk_mask == spk)
851 return t->map;
852 }
853 return 0;
854}
855
a5b7d510
AH		 856/* from CEA slot to ALSA API channel position */
857static int from_cea_slot(int ordered_ca, unsigned char slot)
858{
859 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
860
861 return spk_to_chmap(mask);
862}
863
d45e6889
TI		 864/* get the CA index corresponding to the given ALSA API channel map */
865static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
866{
867 int i, spks = 0, spk_mask = 0;
868
869 for (i = 0; i < chs; i++) {
870 int mask = to_spk_mask(map[i]);
871 if (mask) {
872 spk_mask |= mask;
873 spks++;
874 }
875 }
876
877 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
878 if ((chs == channel_allocations[i].channels ||
879 spks == channel_allocations[i].channels) &&
880 (spk_mask & channel_allocations[i].spk_mask) ==
881 channel_allocations[i].spk_mask)
882 return channel_allocations[i].ca_index;
883 }
884 return -1;
885}
886
887/* set up the channel slots for the given ALSA API channel map */
888static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
889 hda_nid_t pin_nid,
a5b7d510
AH		 890 int chs, unsigned char *map,
891 int ca)
d45e6889 892{
307229d2 893 struct hdmi_spec *spec = codec->spec;
a5b7d510 894 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 895 int alsa_pos, hdmi_slot;
896 int assignments[8] = {[0 ... 7] = 0xf};
897
898 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
899
a5b7d510 900 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 901
902 if (hdmi_slot < 0)
903 continue; /* unassigned channel */
904
905 assignments[hdmi_slot] = alsa_pos;
906 }
907
908 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 909 int err;
11f7c52d 910
307229d2
AH		 911 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
912 assignments[hdmi_slot]);
d45e6889
TI		 913 if (err)
914 return -EINVAL;
915 }
916 return 0;
917}
918
919/* store ALSA API channel map from the current default map */
920static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
921{
922 int i;
56cac413 923 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 924 for (i = 0; i < 8; i++) {
56cac413 925 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 926 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 927 else
928 map[i] = 0;
929 }
930}
931
932static void hdmi_setup_channel_mapping(struct hda_codec *codec,
933 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 934 int channels, unsigned char *map,
935 bool chmap_set)
d45e6889 936{
20608731 937 if (!non_pcm && chmap_set) {
d45e6889 938 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 939 channels, map, ca);
d45e6889
TI		 940 } else {
941 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
942 hdmi_setup_fake_chmap(map, ca);
943 }
980b2495
AH		 944
945 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 946}
079d88cc 947
307229d2
AH		 948static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
949 int asp_slot, int channel)
950{
951 return snd_hda_codec_write(codec, pin_nid, 0,
952 AC_VERB_SET_HDMI_CHAN_SLOT,
953 (channel << 4) | asp_slot);
954}
955
956static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
957 int asp_slot)
958{
959 return (snd_hda_codec_read(codec, pin_nid, 0,
960 AC_VERB_GET_HDMI_CHAN_SLOT,
961 asp_slot) & 0xf0) >> 4;
962}
963
079d88cc
WF		 964/*
965 * Audio InfoFrame routines
966 */
967
968/*
969 * Enable Audio InfoFrame Transmission
970 */
971static void hdmi_start_infoframe_trans(struct hda_codec *codec,
972 hda_nid_t pin_nid)
973{
974 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
975 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
976 AC_DIPXMIT_BEST);
977}
978
979/*
980 * Disable Audio InfoFrame Transmission
981 */
982static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
983 hda_nid_t pin_nid)
984{
985 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
986 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
987 AC_DIPXMIT_DISABLE);
988}
989
990static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
991{
992#ifdef CONFIG_SND_DEBUG_VERBOSE
993 int i;
994 int size;
995
996 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 997 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 998
999 for (i = 0; i < 8; i++) {
1000 size = snd_hda_codec_read(codec, pin_nid, 0,
1001 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 1002 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 1003 }
1004#endif
1005}
1006
1007static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
1008{
1009#ifdef BE_PARANOID
1010 int i, j;
1011 int size;
1012 int pi, bi;
1013 for (i = 0; i < 8; i++) {
1014 size = snd_hda_codec_read(codec, pin_nid, 0,
1015 AC_VERB_GET_HDMI_DIP_SIZE, i);
1016 if (size == 0)
1017 continue;
1018
1019 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1020 for (j = 1; j < 1000; j++) {
1021 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1022 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1023 if (pi != i)
4e76a883 1024 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1025 bi, pi, i);
1026 if (bi == 0) /* byte index wrapped around */
1027 break;
1028 }
4e76a883 1029 codec_dbg(codec,
079d88cc
WF		 1030 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1031 i, size, j);
1032 }
1033#endif
1034}
1035
53d7d69d 1036static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1037{
53d7d69d 1038 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1039 u8 sum = 0;
1040 int i;
1041
53d7d69d 1042 hdmi_ai->checksum = 0;
079d88cc 1043
53d7d69d 1044 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1045 sum += bytes[i];
1046
53d7d69d 1047 hdmi_ai->checksum = -sum;
079d88cc
WF		 1048}
1049
1050static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1051 hda_nid_t pin_nid,
53d7d69d 1052 u8 *dip, int size)
079d88cc 1053{
079d88cc
WF		 1054 int i;
1055
1056 hdmi_debug_dip_size(codec, pin_nid);
1057 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1058
079d88cc 1059 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1060 for (i = 0; i < size; i++)
1061 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1062}
1063
1064static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1065 u8 *dip, int size)
079d88cc 1066{
079d88cc
WF		 1067 u8 val;
1068 int i;
1069
1070 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1071 != AC_DIPXMIT_BEST)
1072 return false;
1073
1074 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1075 for (i = 0; i < size; i++) {
079d88cc
WF		 1076 val = snd_hda_codec_read(codec, pin_nid, 0,
1077 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1078 if (val != dip[i])
079d88cc
WF		 1079 return false;
1080 }
1081
1082 return true;
1083}
1084
307229d2
AH		 1085static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1086 hda_nid_t pin_nid,
1087 int ca, int active_channels,
1088 int conn_type)
1089{
1090 union audio_infoframe ai;
1091
caaf5ef9 1092 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1093 if (conn_type == 0) { /* HDMI */
1094 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1095
1096 hdmi_ai->type = 0x84;
1097 hdmi_ai->ver = 0x01;
1098 hdmi_ai->len = 0x0a;
1099 hdmi_ai->CC02_CT47 = active_channels - 1;
1100 hdmi_ai->CA = ca;
1101 hdmi_checksum_audio_infoframe(hdmi_ai);
1102 } else if (conn_type == 1) { /* DisplayPort */
1103 struct dp_audio_infoframe *dp_ai = &ai.dp;
1104
1105 dp_ai->type = 0x84;
1106 dp_ai->len = 0x1b;
1107 dp_ai->ver = 0x11 << 2;
1108 dp_ai->CC02_CT47 = active_channels - 1;
1109 dp_ai->CA = ca;
1110 } else {
4e76a883 1111 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1112 pin_nid);
1113 return;
1114 }
1115
1116 /*
1117 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1118 * sizeof(*dp_ai) to avoid partial match/update problems when
1119 * the user switches between HDMI/DP monitors.
1120 */
1121 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1122 sizeof(ai))) {
4e76a883
TI		 1123 codec_dbg(codec,
1124 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1125 pin_nid,
1126 active_channels, ca);
1127 hdmi_stop_infoframe_trans(codec, pin_nid);
1128 hdmi_fill_audio_infoframe(codec, pin_nid,
1129 ai.bytes, sizeof(ai));
1130 hdmi_start_infoframe_trans(codec, pin_nid);
1131 }
1132}
1133
b054087d
TI		 1134static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1135 struct hdmi_spec_per_pin *per_pin,
1136 bool non_pcm)
079d88cc 1137{
307229d2 1138 struct hdmi_spec *spec = codec->spec;
384a48d7 1139 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1140 int channels = per_pin->channels;
1df5a06a 1141 int active_channels;
384a48d7 1142 struct hdmi_eld *eld;
1df5a06a 1143 int ca, ordered_ca;
079d88cc 1144
b054087d
TI		 1145 if (!channels)
1146 return;
1147
75dcbe4d 1148 if (is_haswell_plus(codec))
58f7d28d
ML		 1149 snd_hda_codec_write(codec, pin_nid, 0,
1150 AC_VERB_SET_AMP_GAIN_MUTE,
1151 AMP_OUT_UNMUTE);
1152
bce0d2a8 1153 eld = &per_pin->sink_eld;
079d88cc 1154
d45e6889
TI		 1155 if (!non_pcm && per_pin->chmap_set)
1156 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1157 else
79514d47 1158 ca = hdmi_channel_allocation(codec, eld, channels);
d45e6889
TI		 1159 if (ca < 0)
1160 ca = 0;
384a48d7 1161
1df5a06a
AH		 1162 ordered_ca = get_channel_allocation_order(ca);
1163 active_channels = channel_allocations[ordered_ca].channels;
1164
1165 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1166
39edac70
AH		 1167 /*
1168 * always configure channel mapping, it may have been changed by the
1169 * user in the meantime
1170 */
1171 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1172 channels, per_pin->chmap,
1173 per_pin->chmap_set);
1174
307229d2
AH		 1175 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1176 eld->info.conn_type);
433968da 1177
1a6003b5 1178 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1179}
1180
079d88cc
WF		 1181/*
1182 * Unsolicited events
1183 */
1184
efe47108 1185static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1186
1a4f69d5 1187static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 1188{
1189 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 1190 int pin_idx = pin_nid_to_pin_index(codec, nid);
1191
20ce9029
DH		 1192 if (pin_idx < 0)
1193 return;
20ce9029
DH		 1194 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1195 snd_hda_jack_report_sync(codec);
1196}
1197
1a4f69d5
TI		 1198static void jack_callback(struct hda_codec *codec,
1199 struct hda_jack_callback *jack)
1200{
1201 check_presence_and_report(codec, jack->tbl->nid);
1202}
1203
20ce9029
DH		 1204static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1205{
3a93897e 1206 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1207 struct hda_jack_tbl *jack;
2e59e5ab 1208 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1209
1210 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1211 if (!jack)
1212 return;
3a93897e 1213 jack->jack_dirty = 1;
079d88cc 1214
4e76a883 1215 codec_dbg(codec,
2e59e5ab 1216 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1217 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1218 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1219
1a4f69d5 1220 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 1221}
1222
1223static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1224{
1225 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1226 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1227 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1228 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1229
4e76a883 1230 codec_info(codec,
e9ea8e8f 1231 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1232 codec->addr,
079d88cc
WF		 1233 tag,
1234 subtag,
1235 cp_state,
1236 cp_ready);
1237
1238 /* TODO */
1239 if (cp_state)
1240 ;
1241 if (cp_ready)
1242 ;
1243}
1244
1245
1246static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1247{
079d88cc
WF		 1248 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1249 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1250
3a93897e 1251 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1252 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1253 return;
1254 }
1255
1256 if (subtag == 0)
1257 hdmi_intrinsic_event(codec, res);
1258 else
1259 hdmi_non_intrinsic_event(codec, res);
1260}
1261
58f7d28d 1262static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1263 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1264{
58f7d28d 1265 int pwr;
83f26ad2 1266
53b434f0
WX		 1267 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1268 * thus pins could only choose converter 0 for use. Make sure the
1269 * converters are in correct power state */
fd678cac 1270 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1271 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1272
fd678cac 1273 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1274 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1275 AC_PWRST_D0);
1276 msleep(40);
1277 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1278 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1279 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1280 }
83f26ad2
DH		 1281}
1282
079d88cc
WF		 1283/*
1284 * Callbacks
1285 */
1286
92f10b3f
TI		 1287/* HBR should be Non-PCM, 8 channels */
1288#define is_hbr_format(format) \
1289 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1290
307229d2
AH		 1291static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1292 bool hbr)
079d88cc 1293{
307229d2 1294 int pinctl, new_pinctl;
83f26ad2 1295
384a48d7
SW		 1296 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1297 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1298 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1299
13122e6e
AH		 1300 if (pinctl < 0)
1301 return hbr ? -EINVAL : 0;
1302
ea87d1c4 1303 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1304 if (hbr)
ea87d1c4
AH		 1305 new_pinctl |= AC_PINCTL_EPT_HBR;
1306 else
1307 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1308
4e76a883
TI		 1309 codec_dbg(codec,
1310 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1311 pin_nid,
ea87d1c4
AH		 1312 pinctl == new_pinctl ? "" : "new-",
1313 new_pinctl);
1314
1315 if (pinctl != new_pinctl)
384a48d7 1316 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1317 AC_VERB_SET_PIN_WIDGET_CONTROL,
1318 new_pinctl);
307229d2
AH		 1319 } else if (hbr)
1320 return -EINVAL;
ea87d1c4 1321
307229d2
AH		 1322 return 0;
1323}
1324
1325static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1326 hda_nid_t pin_nid, u32 stream_tag, int format)
1327{
1328 struct hdmi_spec *spec = codec->spec;
1329 int err;
1330
75dcbe4d 1331 if (is_haswell_plus(codec))
307229d2
AH		 1332 haswell_verify_D0(codec, cvt_nid, pin_nid);
1333
1334 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1335
1336 if (err) {
4e76a883 1337 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1338 return err;
ea87d1c4 1339 }
079d88cc 1340
384a48d7 1341 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1342 return 0;
079d88cc
WF		 1343}
1344
42b29870
LY		 1345/* Try to find an available converter
1346 * If pin_idx is less then zero, just try to find an available converter.
1347 * Otherwise, try to find an available converter and get the cvt mux index
1348 * of the pin.
1349 */
7ef166b8
WX		 1350static int hdmi_choose_cvt(struct hda_codec *codec,
1351 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1352{
1353 struct hdmi_spec *spec = codec->spec;
384a48d7 1354 struct hdmi_spec_per_pin *per_pin;
384a48d7 1355 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1356 int cvt_idx, mux_idx = 0;
bbbe3390 1357
42b29870
LY		 1358 /* pin_idx < 0 means no pin will be bound to the converter */
1359 if (pin_idx < 0)
1360 per_pin = NULL;
1361 else
1362 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1363
1364 /* Dynamically assign converter to stream */
1365 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1366 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1367
384a48d7
SW		 1368 /* Must not already be assigned */
1369 if (per_cvt->assigned)
1370 continue;
42b29870
LY		 1371 if (per_pin == NULL)
1372 break;
384a48d7
SW		 1373 /* Must be in pin's mux's list of converters */
1374 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1375 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1376 break;
1377 /* Not in mux list */
1378 if (mux_idx == per_pin->num_mux_nids)
1379 continue;
1380 break;
1381 }
7ef166b8 1382
384a48d7
SW		 1383 /* No free converters */
1384 if (cvt_idx == spec->num_cvts)
42b29870 1385 return -EBUSY;
384a48d7 1386
42b29870
LY		 1387 if (per_pin != NULL)
1388 per_pin->mux_idx = mux_idx;
2df6742f 1389
7ef166b8
WX		 1390 if (cvt_id)
1391 *cvt_id = cvt_idx;
1392 if (mux_id)
1393 *mux_id = mux_idx;
1394
1395 return 0;
1396}
1397
2df6742f
ML		 1398/* Assure the pin select the right convetor */
1399static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1400 struct hdmi_spec_per_pin *per_pin)
1401{
1402 hda_nid_t pin_nid = per_pin->pin_nid;
1403 int mux_idx, curr;
1404
1405 mux_idx = per_pin->mux_idx;
1406 curr = snd_hda_codec_read(codec, pin_nid, 0,
1407 AC_VERB_GET_CONNECT_SEL, 0);
1408 if (curr != mux_idx)
1409 snd_hda_codec_write_cache(codec, pin_nid, 0,
1410 AC_VERB_SET_CONNECT_SEL,
1411 mux_idx);
1412}
1413
42b29870
LY		 1414/* get the mux index for the converter of the pins
1415 * converter's mux index is the same for all pins on Intel platform
1416 */
1417static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1418 hda_nid_t cvt_nid)
1419{
1420 int i;
1421
1422 for (i = 0; i < spec->num_cvts; i++)
1423 if (spec->cvt_nids[i] == cvt_nid)
1424 return i;
1425 return -EINVAL;
1426}
1427
300016b9
ML		 1428/* Intel HDMI workaround to fix audio routing issue:
1429 * For some Intel display codecs, pins share the same connection list.
1430 * So a conveter can be selected by multiple pins and playback on any of these
1431 * pins will generate sound on the external display, because audio flows from
1432 * the same converter to the display pipeline. Also muting one pin may make
1433 * other pins have no sound output.
1434 * So this function assures that an assigned converter for a pin is not selected
1435 * by any other pins.
1436 */
1437static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1438 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1439{
1440 struct hdmi_spec *spec = codec->spec;
7639a06c 1441 hda_nid_t nid;
f82d7d16
ML		 1442 int cvt_idx, curr;
1443 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1444
f82d7d16 1445 /* configure all pins, including "no physical connection" ones */
7639a06c 1446 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 1447 unsigned int wid_caps = get_wcaps(codec, nid);
1448 unsigned int wid_type = get_wcaps_type(wid_caps);
1449
1450 if (wid_type != AC_WID_PIN)
1451 continue;
7ef166b8 1452
f82d7d16 1453 if (nid == pin_nid)
7ef166b8
WX		 1454 continue;
1455
f82d7d16 1456 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1457 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1458 if (curr != mux_idx)
1459 continue;
7ef166b8 1460
f82d7d16
ML		 1461 /* choose an unassigned converter. The conveters in the
1462 * connection list are in the same order as in the codec.
1463 */
1464 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1465 per_cvt = get_cvt(spec, cvt_idx);
1466 if (!per_cvt->assigned) {
4e76a883
TI		 1467 codec_dbg(codec,
1468 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1469 cvt_idx, nid);
1470 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1471 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1472 cvt_idx);
1473 break;
1474 }
7ef166b8
WX		 1475 }
1476 }
1477}
1478
42b29870
LY		 1479/* A wrapper of intel_not_share_asigned_cvt() */
1480static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1481 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1482{
1483 int mux_idx;
1484 struct hdmi_spec *spec = codec->spec;
1485
1486 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1487 return;
1488
1489 /* On Intel platform, the mapping of converter nid to
1490 * mux index of the pins are always the same.
1491 * The pin nid may be 0, this means all pins will not
1492 * share the converter.
1493 */
1494 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1495 if (mux_idx >= 0)
1496 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1497}
1498
1499/* called in hdmi_pcm_open when no pin is assigned to the PCM
1500 * in dyn_pcm_assign mode.
1501 */
1502static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1503 struct hda_codec *codec,
1504 struct snd_pcm_substream *substream)
1505{
1506 struct hdmi_spec *spec = codec->spec;
1507 struct snd_pcm_runtime *runtime = substream->runtime;
1508 int cvt_idx;
1509 struct hdmi_spec_per_cvt *per_cvt = NULL;
1510 int err;
1511
1512 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1513 if (err)
1514 return err;
1515
1516 per_cvt = get_cvt(spec, cvt_idx);
1517 per_cvt->assigned = 1;
1518 hinfo->nid = per_cvt->cvt_nid;
1519
1520 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1521
1522 /* todo: setup spdif ctls assign */
1523
1524 /* Initially set the converter's capabilities */
1525 hinfo->channels_min = per_cvt->channels_min;
1526 hinfo->channels_max = per_cvt->channels_max;
1527 hinfo->rates = per_cvt->rates;
1528 hinfo->formats = per_cvt->formats;
1529 hinfo->maxbps = per_cvt->maxbps;
1530
1531 /* Store the updated parameters */
1532 runtime->hw.channels_min = hinfo->channels_min;
1533 runtime->hw.channels_max = hinfo->channels_max;
1534 runtime->hw.formats = hinfo->formats;
1535 runtime->hw.rates = hinfo->rates;
1536
1537 snd_pcm_hw_constraint_step(substream->runtime, 0,
1538 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1539 return 0;
1540}
1541
7ef166b8
WX		 1542/*
1543 * HDA PCM callbacks
1544 */
1545static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1546 struct hda_codec *codec,
1547 struct snd_pcm_substream *substream)
1548{
1549 struct hdmi_spec *spec = codec->spec;
1550 struct snd_pcm_runtime *runtime = substream->runtime;
1551 int pin_idx, cvt_idx, mux_idx = 0;
1552 struct hdmi_spec_per_pin *per_pin;
1553 struct hdmi_eld *eld;
1554 struct hdmi_spec_per_cvt *per_cvt = NULL;
1555 int err;
1556
1557 /* Validate hinfo */
42b29870 1558 mutex_lock(&spec->pcm_lock);
4e76a883 1559 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1560 if (!spec->dyn_pcm_assign) {
1561 if (snd_BUG_ON(pin_idx < 0)) {
1562 mutex_unlock(&spec->pcm_lock);
1563 return -EINVAL;
1564 }
1565 } else {
1566 /* no pin is assigned to the PCM
1567 * PA need pcm open successfully when probe
1568 */
1569 if (pin_idx < 0) {
1570 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1571 mutex_unlock(&spec->pcm_lock);
1572 return err;
1573 }
1574 }
7ef166b8
WX		 1575
1576 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
42b29870
LY		 1577 if (err < 0) {
1578 mutex_unlock(&spec->pcm_lock);
7ef166b8 1579 return err;
42b29870 1580 }
7ef166b8
WX		 1581
1582 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1583 /* Claim converter */
1584 per_cvt->assigned = 1;
42b29870
LY		 1585
1586
1587 per_pin = get_pin(spec, pin_idx);
1df5a06a 1588 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1589 hinfo->nid = per_cvt->cvt_nid;
1590
bddee96b 1591 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1592 AC_VERB_SET_CONNECT_SEL,
1593 mux_idx);
7ef166b8
WX		 1594
1595 /* configure unused pins to choose other converters */
ca2e7224 1596 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
300016b9 1597 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1598
384a48d7 1599 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1600
2def8172 1601 /* Initially set the converter's capabilities */
384a48d7
SW		 1602 hinfo->channels_min = per_cvt->channels_min;
1603 hinfo->channels_max = per_cvt->channels_max;
1604 hinfo->rates = per_cvt->rates;
1605 hinfo->formats = per_cvt->formats;
1606 hinfo->maxbps = per_cvt->maxbps;
2def8172 1607
42b29870 1608 eld = &per_pin->sink_eld;
384a48d7 1609 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1610 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1611 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1612 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1613 !hinfo->rates || !hinfo->formats) {
1614 per_cvt->assigned = 0;
1615 hinfo->nid = 0;
1616 snd_hda_spdif_ctls_unassign(codec, pin_idx);
42b29870 1617 mutex_unlock(&spec->pcm_lock);
bbbe3390 1618 return -ENODEV;
2ad779b7 1619 }
bbbe3390 1620 }
2def8172 1621
42b29870 1622 mutex_unlock(&spec->pcm_lock);
2def8172 1623 /* Store the updated parameters */
639cef0e
TI		 1624 runtime->hw.channels_min = hinfo->channels_min;
1625 runtime->hw.channels_max = hinfo->channels_max;
1626 runtime->hw.formats = hinfo->formats;
1627 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1628
1629 snd_pcm_hw_constraint_step(substream->runtime, 0,
1630 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1631 return 0;
1632}
1633
079d88cc
WF		 1634/*
1635 * HDA/HDMI auto parsing
1636 */
384a48d7 1637static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1638{
1639 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1640 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1641 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1642
1643 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1644 codec_warn(codec,
1645 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1646 pin_nid, get_wcaps(codec, pin_nid));
1647 return -EINVAL;
1648 }
1649
384a48d7
SW		 1650 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1651 per_pin->mux_nids,
1652 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1653
1654 return 0;
1655}
1656
e90247f9
TI		 1657/* update per_pin ELD from the given new ELD;
1658 * setup info frame and notification accordingly
1659 */
1660static void update_eld(struct hda_codec *codec,
1661 struct hdmi_spec_per_pin *per_pin,
1662 struct hdmi_eld *eld)
1663{
1664 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1665 bool old_eld_valid = pin_eld->eld_valid;
1666 bool eld_changed;
1667
1668 if (eld->eld_valid)
1669 snd_hdmi_show_eld(codec, &eld->info);
1670
1671 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1672 if (eld->eld_valid && pin_eld->eld_valid)
1673 if (pin_eld->eld_size != eld->eld_size ||
1674 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1675 eld->eld_size) != 0)
1676 eld_changed = true;
1677
1678 pin_eld->eld_valid = eld->eld_valid;
1679 pin_eld->eld_size = eld->eld_size;
1680 if (eld->eld_valid)
1681 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1682 pin_eld->info = eld->info;
1683
1684 /*
1685 * Re-setup pin and infoframe. This is needed e.g. when
1686 * - sink is first plugged-in
1687 * - transcoder can change during stream playback on Haswell
1688 * and this can make HW reset converter selection on a pin.
1689 */
1690 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1691 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1692 intel_verify_pin_cvt_connect(codec, per_pin);
1693 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1694 per_pin->mux_idx);
1695 }
1696
1697 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1698 }
1699
1700 if (eld_changed)
1701 snd_ctl_notify(codec->card,
1702 SNDRV_CTL_EVENT_MASK_VALUE |
1703 SNDRV_CTL_EVENT_MASK_INFO,
1704 &per_pin->eld_ctl->id);
1705}
1706
788d441a
TI		 1707/* update ELD and jack state via HD-audio verbs */
1708static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1709 int repoll)
079d88cc 1710{
464837a7 1711 struct hda_jack_tbl *jack;
744626da 1712 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1713 struct hdmi_spec *spec = codec->spec;
1714 struct hdmi_eld *eld = &spec->temp_eld;
1715 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1716 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1717 /*
1718 * Always execute a GetPinSense verb here, even when called from
1719 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1720 * response's PD bit is not the real PD value, but indicates that
1721 * the real PD value changed. An older version of the HD-audio
1722 * specification worked this way. Hence, we just ignore the data in
1723 * the unsolicited response to avoid custom WARs.
1724 */
da4a7a39 1725 int present;
efe47108 1726 bool ret;
9a5e5234 1727 bool do_repoll = false;
079d88cc 1728
664c7155 1729 snd_hda_power_up_pm(codec);
da4a7a39
DH		 1730 present = snd_hda_pin_sense(codec, pin_nid);
1731
a4e9a38b 1732 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1733 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1734 if (pin_eld->monitor_present)
1735 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1736 else
1737 eld->eld_valid = false;
079d88cc 1738
4e76a883 1739 codec_dbg(codec,
384a48d7 1740 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1741 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1742
4bd038f9 1743 if (eld->eld_valid) {
307229d2 1744 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1745 &eld->eld_size) < 0)
4bd038f9 1746 eld->eld_valid = false;
1613d6b4 1747 else {
79514d47 1748 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1749 eld->eld_size) < 0)
4bd038f9 1750 eld->eld_valid = false;
1613d6b4 1751 }
9a5e5234
TI		 1752 if (!eld->eld_valid && repoll)
1753 do_repoll = true;
744626da 1754 }
4bd038f9 1755
9a5e5234 1756 if (do_repoll)
e90247f9
TI		 1757 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1758 else
1759 update_eld(codec, per_pin, eld);
92c69e79 1760
aff747eb 1761 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1762
1763 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1764 if (jack)
1765 jack->block_report = !ret;
1766
a4e9a38b 1767 mutex_unlock(&per_pin->lock);
664c7155 1768 snd_hda_power_down_pm(codec);
efe47108 1769 return ret;
079d88cc
WF		 1770}
1771
788d441a
TI		 1772/* update ELD and jack state via audio component */
1773static void sync_eld_via_acomp(struct hda_codec *codec,
1774 struct hdmi_spec_per_pin *per_pin)
1775{
788d441a
TI		 1776 struct hdmi_spec *spec = codec->spec;
1777 struct hdmi_eld *eld = &spec->temp_eld;
1778 int size;
1779
e2dc7d7d
TI		 1780 mutex_lock(&per_pin->lock);
1781 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1782 &eld->monitor_present, eld->eld_buffer,
1783 ELD_MAX_SIZE);
1784 if (size < 0)
1785 goto unlock;
1786 if (size > 0) {
1787 size = min(size, ELD_MAX_SIZE);
1788 if (snd_hdmi_parse_eld(codec, &eld->info,
1789 eld->eld_buffer, size) < 0)
1790 size = -EINVAL;
1791 }
788d441a 1792
e2dc7d7d
TI		 1793 if (size > 0) {
1794 eld->eld_valid = true;
1795 eld->eld_size = size;
1796 } else {
1797 eld->eld_valid = false;
1798 eld->eld_size = 0;
788d441a 1799 }
e2dc7d7d
TI		 1800
1801 update_eld(codec, per_pin, eld);
1802 snd_jack_report(per_pin->acomp_jack,
1803 eld->monitor_present ? SND_JACK_AVOUT : 0);
1804 unlock:
1805 mutex_unlock(&per_pin->lock);
788d441a
TI		 1806}
1807
1808static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1809{
1810 struct hda_codec *codec = per_pin->codec;
1811
1812 if (codec_has_acomp(codec)) {
1813 sync_eld_via_acomp(codec, per_pin);
1814 return false; /* don't call snd_hda_jack_report_sync() */
1815 } else {
1816 return hdmi_present_sense_via_verbs(per_pin, repoll);
1817 }
1818}
1819
744626da
WF		 1820static void hdmi_repoll_eld(struct work_struct *work)
1821{
1822 struct hdmi_spec_per_pin *per_pin =
1823 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1824
c6e8453e
WF		 1825 if (per_pin->repoll_count++ > 6)
1826 per_pin->repoll_count = 0;
1827
efe47108
TI		 1828 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1829 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1830}
1831
c88d4e84
TI		 1832static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1833 hda_nid_t nid);
1834
079d88cc
WF		 1835static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1836{
1837 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1838 unsigned int caps, config;
1839 int pin_idx;
1840 struct hdmi_spec_per_pin *per_pin;
07acecc1 1841 int err;
079d88cc 1842
efc2f8de 1843 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1844 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1845 return 0;
1846
efc2f8de 1847 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1848 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1849 return 0;
1850
75dcbe4d 1851 if (is_haswell_plus(codec))
c88d4e84
TI		 1852 intel_haswell_fixup_connect_list(codec, pin_nid);
1853
384a48d7 1854 pin_idx = spec->num_pins;
bce0d2a8
TI		 1855 per_pin = snd_array_new(&spec->pins);
1856 if (!per_pin)
1857 return -ENOMEM;
384a48d7
SW		 1858
1859 per_pin->pin_nid = pin_nid;
1a6003b5 1860 per_pin->non_pcm = false;
079d88cc 1861
384a48d7
SW		 1862 err = hdmi_read_pin_conn(codec, pin_idx);
1863 if (err < 0)
1864 return err;
079d88cc 1865
079d88cc
WF		 1866 spec->num_pins++;
1867
384a48d7 1868 return 0;
079d88cc
WF		 1869}
1870
384a48d7 1871static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1872{
1873 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1874 struct hdmi_spec_per_cvt *per_cvt;
1875 unsigned int chans;
1876 int err;
079d88cc 1877
384a48d7
SW		 1878 chans = get_wcaps(codec, cvt_nid);
1879 chans = get_wcaps_channels(chans);
1880
bce0d2a8
TI		 1881 per_cvt = snd_array_new(&spec->cvts);
1882 if (!per_cvt)
1883 return -ENOMEM;
384a48d7
SW		 1884
1885 per_cvt->cvt_nid = cvt_nid;
1886 per_cvt->channels_min = 2;
d45e6889 1887 if (chans <= 16) {
384a48d7 1888 per_cvt->channels_max = chans;
d45e6889
TI		 1889 if (chans > spec->channels_max)
1890 spec->channels_max = chans;
1891 }
384a48d7
SW		 1892
1893 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1894 &per_cvt->rates,
1895 &per_cvt->formats,
1896 &per_cvt->maxbps);
1897 if (err < 0)
1898 return err;
1899
bce0d2a8
TI		 1900 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1901 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1902 spec->num_cvts++;
079d88cc
WF		 1903
1904 return 0;
1905}
1906
1907static int hdmi_parse_codec(struct hda_codec *codec)
1908{
1909 hda_nid_t nid;
1910 int i, nodes;
1911
7639a06c 1912 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1913 if (!nid || nodes < 0) {
4e76a883 1914 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1915 return -EINVAL;
1916 }
1917
1918 for (i = 0; i < nodes; i++, nid++) {
1919 unsigned int caps;
1920 unsigned int type;
1921
efc2f8de 1922 caps = get_wcaps(codec, nid);
079d88cc
WF		 1923 type = get_wcaps_type(caps);
1924
1925 if (!(caps & AC_WCAP_DIGITAL))
1926 continue;
1927
1928 switch (type) {
1929 case AC_WID_AUD_OUT:
384a48d7 1930 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1931 break;
1932 case AC_WID_PIN:
3eaead57 1933 hdmi_add_pin(codec, nid);
079d88cc
WF		 1934 break;
1935 }
1936 }
1937
079d88cc
WF		 1938 return 0;
1939}
1940
84eb01be
TI		 1941/*
1942 */
1a6003b5
TI		 1943static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1944{
1945 struct hda_spdif_out *spdif;
1946 bool non_pcm;
1947
1948 mutex_lock(&codec->spdif_mutex);
1949 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1950 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1951 mutex_unlock(&codec->spdif_mutex);
1952 return non_pcm;
1953}
1954
84eb01be
TI		 1955/*
1956 * HDMI callbacks
1957 */
1958
1959static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1960 struct hda_codec *codec,
1961 unsigned int stream_tag,
1962 unsigned int format,
1963 struct snd_pcm_substream *substream)
1964{
384a48d7
SW		 1965 hda_nid_t cvt_nid = hinfo->nid;
1966 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1967 int pin_idx;
1968 struct hdmi_spec_per_pin *per_pin;
1969 hda_nid_t pin_nid;
ddd621fb 1970 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1971 bool non_pcm;
75fae117 1972 int pinctl;
42b29870 1973 int err;
1a6003b5 1974
42b29870
LY		 1975 mutex_lock(&spec->pcm_lock);
1976 pin_idx = hinfo_to_pin_index(codec, hinfo);
1977 if (spec->dyn_pcm_assign && pin_idx < 0) {
1978 /* when dyn_pcm_assign and pcm is not bound to a pin
1979 * skip pin setup and return 0 to make audio playback
1980 * be ongoing
1981 */
1982 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
1983 snd_hda_codec_setup_stream(codec, cvt_nid,
1984 stream_tag, 0, format);
1985 mutex_unlock(&spec->pcm_lock);
1986 return 0;
1987 }
1988
1989 if (snd_BUG_ON(pin_idx < 0)) {
1990 mutex_unlock(&spec->pcm_lock);
1991 return -EINVAL;
1992 }
1993 per_pin = get_pin(spec, pin_idx);
1994 pin_nid = per_pin->pin_nid;
ca2e7224 1995 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2df6742f
ML		 1996 /* Verify pin:cvt selections to avoid silent audio after S3.
1997 * After S3, the audio driver restores pin:cvt selections
1998 * but this can happen before gfx is ready and such selection
1999 * is overlooked by HW. Thus multiple pins can share a same
2000 * default convertor and mute control will affect each other,
2001 * which can cause a resumed audio playback become silent
2002 * after S3.
2003 */
2004 intel_verify_pin_cvt_connect(codec, per_pin);
2005 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
2006 }
2007
ddd621fb
LY		 2008 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2009 /* Todo: add DP1.2 MST audio support later */
e2dc7d7d 2010 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
ddd621fb 2011
1a6003b5 2012 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 2013 mutex_lock(&per_pin->lock);
b054087d
TI		 2014 per_pin->channels = substream->runtime->channels;
2015 per_pin->setup = true;
384a48d7 2016
b054087d 2017 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 2018 mutex_unlock(&per_pin->lock);
75fae117
SW		 2019 if (spec->dyn_pin_out) {
2020 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
2021 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2022 snd_hda_codec_write(codec, pin_nid, 0,
2023 AC_VERB_SET_PIN_WIDGET_CONTROL,
2024 pinctl | PIN_OUT);
2025 }
2026
42b29870
LY		 2027 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
2028 stream_tag, format);
2029 mutex_unlock(&spec->pcm_lock);
2030 return err;
84eb01be
TI		 2031}
2032
8dfaa573
TI		 2033static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2034 struct hda_codec *codec,
2035 struct snd_pcm_substream *substream)
2036{
2037 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2038 return 0;
2039}
2040
f2ad24fa
TI		 2041static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2042 struct hda_codec *codec,
2043 struct snd_pcm_substream *substream)
384a48d7
SW		 2044{
2045 struct hdmi_spec *spec = codec->spec;
2046 int cvt_idx, pin_idx;
2047 struct hdmi_spec_per_cvt *per_cvt;
2048 struct hdmi_spec_per_pin *per_pin;
75fae117 2049 int pinctl;
384a48d7 2050
384a48d7 2051 if (hinfo->nid) {
4e76a883 2052 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 2053 if (snd_BUG_ON(cvt_idx < 0))
2054 return -EINVAL;
bce0d2a8 2055 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 2056
2057 snd_BUG_ON(!per_cvt->assigned);
2058 per_cvt->assigned = 0;
2059 hinfo->nid = 0;
2060
42b29870 2061 mutex_lock(&spec->pcm_lock);
4e76a883 2062 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 2063 if (spec->dyn_pcm_assign && pin_idx < 0) {
2064 mutex_unlock(&spec->pcm_lock);
2065 return 0;
2066 }
2067
2068 if (snd_BUG_ON(pin_idx < 0)) {
2069 mutex_unlock(&spec->pcm_lock);
384a48d7 2070 return -EINVAL;
42b29870 2071 }
bce0d2a8 2072 per_pin = get_pin(spec, pin_idx);
384a48d7 2073
75fae117
SW		 2074 if (spec->dyn_pin_out) {
2075 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2076 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2077 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2078 AC_VERB_SET_PIN_WIDGET_CONTROL,
2079 pinctl & ~PIN_OUT);
2080 }
2081
384a48d7 2082 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 2083
a4e9a38b 2084 mutex_lock(&per_pin->lock);
d45e6889
TI		 2085 per_pin->chmap_set = false;
2086 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 2087
2088 per_pin->setup = false;
2089 per_pin->channels = 0;
a4e9a38b 2090 mutex_unlock(&per_pin->lock);
42b29870 2091 mutex_unlock(&spec->pcm_lock);
384a48d7 2092 }
d45e6889 2093
384a48d7
SW		 2094 return 0;
2095}
2096
2097static const struct hda_pcm_ops generic_ops = {
2098 .open = hdmi_pcm_open,
f2ad24fa 2099 .close = hdmi_pcm_close,
384a48d7 2100 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2101 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2102};
2103
d45e6889
TI		 2104/*
2105 * ALSA API channel-map control callbacks
2106 */
2107static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
2108 struct snd_ctl_elem_info *uinfo)
2109{
2110 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2111 struct hda_codec *codec = info->private_data;
2112 struct hdmi_spec *spec = codec->spec;
2113 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2114 uinfo->count = spec->channels_max;
2115 uinfo->value.integer.min = 0;
2116 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
2117 return 0;
2118}
2119
307229d2
AH		 2120static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2121 int channels)
2122{
2123 /* If the speaker allocation matches the channel count, it is OK.*/
2124 if (cap->channels != channels)
2125 return -1;
2126
2127 /* all channels are remappable freely */
2128 return SNDRV_CTL_TLVT_CHMAP_VAR;
2129}
2130
2131static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
2132 unsigned int *chmap, int channels)
2133{
2134 int count = 0;
2135 int c;
2136
2137 for (c = 7; c >= 0; c--) {
2138 int spk = cap->speakers[c];
2139 if (!spk)
2140 continue;
2141
2142 chmap[count++] = spk_to_chmap(spk);
2143 }
2144
2145 WARN_ON(count != channels);
2146}
2147
d45e6889
TI		 2148static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
2149 unsigned int size, unsigned int __user *tlv)
2150{
2151 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2152 struct hda_codec *codec = info->private_data;
2153 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 2154 unsigned int __user *dst;
2155 int chs, count = 0;
2156
2157 if (size < 8)
2158 return -ENOMEM;
2159 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
2160 return -EFAULT;
2161 size -= 8;
2162 dst = tlv + 2;
498dab3a 2163 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 2164 int i;
d45e6889
TI		 2165 struct cea_channel_speaker_allocation *cap;
2166 cap = channel_allocations;
2167 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
2168 int chs_bytes = chs * 4;
307229d2
AH		 2169 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
2170 unsigned int tlv_chmap[8];
2171
2172 if (type < 0)
d45e6889 2173 continue;
d45e6889
TI		 2174 if (size < 8)
2175 return -ENOMEM;
307229d2 2176 if (put_user(type, dst) ||
d45e6889
TI		 2177 put_user(chs_bytes, dst + 1))
2178 return -EFAULT;
2179 dst += 2;
2180 size -= 8;
2181 count += 8;
2182 if (size < chs_bytes)
2183 return -ENOMEM;
2184 size -= chs_bytes;
2185 count += chs_bytes;
307229d2
AH		 2186 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
2187 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2188 return -EFAULT;
2189 dst += chs;
d45e6889
TI		 2190 }
2191 }
2192 if (put_user(count, tlv + 1))
2193 return -EFAULT;
2194 return 0;
2195}
2196
2197static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2198 struct snd_ctl_elem_value *ucontrol)
2199{
2200 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2201 struct hda_codec *codec = info->private_data;
2202 struct hdmi_spec *spec = codec->spec;
2203 int pin_idx = kcontrol->private_value;
bce0d2a8 2204 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2205 int i;
2206
2207 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2208 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2209 return 0;
2210}
2211
2212static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2213 struct snd_ctl_elem_value *ucontrol)
2214{
2215 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2216 struct hda_codec *codec = info->private_data;
2217 struct hdmi_spec *spec = codec->spec;
2218 int pin_idx = kcontrol->private_value;
bce0d2a8 2219 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2220 unsigned int ctl_idx;
2221 struct snd_pcm_substream *substream;
2222 unsigned char chmap[8];
307229d2 2223 int i, err, ca, prepared = 0;
d45e6889
TI		 2224
2225 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2226 substream = snd_pcm_chmap_substream(info, ctl_idx);
2227 if (!substream || !substream->runtime)
6f54c361 2228 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 2229 switch (substream->runtime->status->state) {
2230 case SNDRV_PCM_STATE_OPEN:
2231 case SNDRV_PCM_STATE_SETUP:
2232 break;
2233 case SNDRV_PCM_STATE_PREPARED:
2234 prepared = 1;
2235 break;
2236 default:
2237 return -EBUSY;
2238 }
2239 memset(chmap, 0, sizeof(chmap));
2240 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2241 chmap[i] = ucontrol->value.integer.value[i];
2242 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2243 return 0;
2244 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2245 if (ca < 0)
2246 return -EINVAL;
307229d2
AH		 2247 if (spec->ops.chmap_validate) {
2248 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2249 if (err)
2250 return err;
2251 }
a4e9a38b 2252 mutex_lock(&per_pin->lock);
d45e6889
TI		 2253 per_pin->chmap_set = true;
2254 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2255 if (prepared)
b054087d 2256 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2257 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2258
2259 return 0;
2260}
2261
84eb01be
TI		 2262static int generic_hdmi_build_pcms(struct hda_codec *codec)
2263{
2264 struct hdmi_spec *spec = codec->spec;
6590faab 2265 struct hdmi_spec_per_pin *per_pin;
384a48d7 2266 int pin_idx;
84eb01be 2267
384a48d7
SW		 2268 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2269 struct hda_pcm *info;
84eb01be 2270 struct hda_pcm_stream *pstr;
bce0d2a8 2271
bbbc7e85 2272 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 2273 if (!info)
2274 return -ENOMEM;
6590faab
LY		 2275 if (!spec->dyn_pcm_assign) {
2276 per_pin = get_pin(spec, pin_idx);
2277 per_pin->pcm = info;
2278 }
bbbc7e85 2279 spec->pcm_rec[pin_idx] = info;
84eb01be 2280 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2281 info->own_chmap = true;
384a48d7 2282
84eb01be 2283 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2284 pstr->substreams = 1;
2285 pstr->ops = generic_ops;
2286 /* other pstr fields are set in open */
84eb01be
TI		 2287 }
2288
2289 return 0;
2290}
2291
788d441a
TI		 2292static void free_acomp_jack_priv(struct snd_jack *jack)
2293{
2294 struct hdmi_spec_per_pin *per_pin = jack->private_data;
2295
2296 per_pin->acomp_jack = NULL;
2297}
2298
2299static int add_acomp_jack_kctl(struct hda_codec *codec,
2300 struct hdmi_spec_per_pin *per_pin,
2301 const char *name)
2302{
2303 struct snd_jack *jack;
2304 int err;
2305
2306 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2307 true, false);
2308 if (err < 0)
2309 return err;
2310 per_pin->acomp_jack = jack;
2311 jack->private_data = per_pin;
2312 jack->private_free = free_acomp_jack_priv;
2313 return 0;
2314}
2315
0b6c49b5
DH		 2316static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2317{
31ef2257 2318 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2319 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2320 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2321 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
909cadc6 2322 bool phantom_jack;
0b6c49b5 2323
31ef2257
TI		 2324 if (pcmdev > 0)
2325 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
788d441a
TI		 2326 if (codec_has_acomp(codec))
2327 return add_acomp_jack_kctl(codec, per_pin, hdmi_str);
909cadc6
TI		 2328 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2329 if (phantom_jack)
30efd8de
DH		 2330 strncat(hdmi_str, " Phantom",
2331 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2332
909cadc6
TI		 2333 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2334 phantom_jack);
0b6c49b5
DH		 2335}
2336
84eb01be
TI		 2337static int generic_hdmi_build_controls(struct hda_codec *codec)
2338{
2339 struct hdmi_spec *spec = codec->spec;
2340 int err;
384a48d7 2341 int pin_idx;
84eb01be 2342
384a48d7 2343 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2344 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2345
2346 err = generic_hdmi_build_jack(codec, pin_idx);
2347 if (err < 0)
2348 return err;
2349
dcda5806
TI		 2350 err = snd_hda_create_dig_out_ctls(codec,
2351 per_pin->pin_nid,
2352 per_pin->mux_nids[0],
2353 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2354 if (err < 0)
2355 return err;
384a48d7 2356 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2357
2358 /* add control for ELD Bytes */
bce0d2a8
TI		 2359 err = hdmi_create_eld_ctl(codec, pin_idx,
2360 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2361
2362 if (err < 0)
2363 return err;
31ef2257 2364
82b1d73f 2365 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2366 }
2367
d45e6889
TI		 2368 /* add channel maps */
2369 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bbbc7e85 2370 struct hda_pcm *pcm;
d45e6889
TI		 2371 struct snd_pcm_chmap *chmap;
2372 struct snd_kcontrol *kctl;
2373 int i;
2ca320e2 2374
bbbc7e85
TI		 2375 pcm = spec->pcm_rec[pin_idx];
2376 if (!pcm || !pcm->pcm)
2ca320e2 2377 break;
bbbc7e85 2378 err = snd_pcm_add_chmap_ctls(pcm->pcm,
d45e6889
TI		 2379 SNDRV_PCM_STREAM_PLAYBACK,
2380 NULL, 0, pin_idx, &chmap);
2381 if (err < 0)
2382 return err;
2383 /* override handlers */
2384 chmap->private_data = codec;
2385 kctl = chmap->kctl;
2386 for (i = 0; i < kctl->count; i++)
2387 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2388 kctl->info = hdmi_chmap_ctl_info;
2389 kctl->get = hdmi_chmap_ctl_get;
2390 kctl->put = hdmi_chmap_ctl_put;
2391 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2392 }
2393
84eb01be
TI		 2394 return 0;
2395}
2396
8b8d654b 2397static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2398{
2399 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2400 int pin_idx;
2401
2402 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2403 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2404
744626da 2405 per_pin->codec = codec;
a4e9a38b 2406 mutex_init(&per_pin->lock);
744626da 2407 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2408 eld_proc_new(per_pin, pin_idx);
84eb01be 2409 }
8b8d654b
TI		 2410 return 0;
2411}
2412
2413static int generic_hdmi_init(struct hda_codec *codec)
2414{
2415 struct hdmi_spec *spec = codec->spec;
2416 int pin_idx;
2417
2418 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2419 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2420 hda_nid_t pin_nid = per_pin->pin_nid;
2421
2422 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2423 if (!codec_has_acomp(codec))
2424 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2425 codec->jackpoll_interval > 0 ?
2426 jack_callback : NULL);
8b8d654b 2427 }
84eb01be
TI		 2428 return 0;
2429}
2430
bce0d2a8
TI		 2431static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2432{
2433 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2434 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2435}
2436
2437static void hdmi_array_free(struct hdmi_spec *spec)
2438{
2439 snd_array_free(&spec->pins);
2440 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2441}
2442
84eb01be
TI		 2443static void generic_hdmi_free(struct hda_codec *codec)
2444{
2445 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2446 int pin_idx;
2447
6603249d 2448 if (codec_has_acomp(codec))
25adc137
DH		 2449 snd_hdac_i915_register_notifier(NULL);
2450
384a48d7 2451 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2452 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2453
2f35c630 2454 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2455 eld_proc_free(per_pin);
788d441a
TI		 2456 if (per_pin->acomp_jack)
2457 snd_device_free(codec->card, per_pin->acomp_jack);
384a48d7 2458 }
84eb01be 2459
55913110
TI		 2460 if (spec->i915_bound)
2461 snd_hdac_i915_exit(&codec->bus->core);
bce0d2a8 2462 hdmi_array_free(spec);
84eb01be
TI		 2463 kfree(spec);
2464}
2465
28cb72e5
WX		 2466#ifdef CONFIG_PM
2467static int generic_hdmi_resume(struct hda_codec *codec)
2468{
2469 struct hdmi_spec *spec = codec->spec;
2470 int pin_idx;
2471
a2833683 2472 codec->patch_ops.init(codec);
eeecd9d1 2473 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2474
2475 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2476 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2477 hdmi_present_sense(per_pin, 1);
2478 }
2479 return 0;
2480}
2481#endif
2482
fb79e1e0 2483static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2484 .init = generic_hdmi_init,
2485 .free = generic_hdmi_free,
2486 .build_pcms = generic_hdmi_build_pcms,
2487 .build_controls = generic_hdmi_build_controls,
2488 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2489#ifdef CONFIG_PM
2490 .resume = generic_hdmi_resume,
2491#endif
84eb01be
TI		 2492};
2493
307229d2
AH		 2494static const struct hdmi_ops generic_standard_hdmi_ops = {
2495 .pin_get_eld = snd_hdmi_get_eld,
2496 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2497 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2498 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2499 .pin_hbr_setup = hdmi_pin_hbr_setup,
2500 .setup_stream = hdmi_setup_stream,
2501 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2502 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2503};
2504
6ffe168f 2505
c88d4e84
TI		 2506static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2507 hda_nid_t nid)
2508{
2509 struct hdmi_spec *spec = codec->spec;
2510 hda_nid_t conns[4];
2511 int nconns;
6ffe168f 2512
c88d4e84
TI		 2513 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2514 if (nconns == spec->num_cvts &&
2515 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2516 return;
2517
c88d4e84 2518 /* override pins connection list */
4e76a883 2519 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2520 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2521}
2522
1611a9c9
ML		 2523#define INTEL_VENDOR_NID 0x08
2524#define INTEL_GET_VENDOR_VERB 0xf81
2525#define INTEL_SET_VENDOR_VERB 0x781
2526#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2527#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2528
2529static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2530 bool update_tree)
1611a9c9
ML		 2531{
2532 unsigned int vendor_param;
2533
1611a9c9
ML		 2534 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2535 INTEL_GET_VENDOR_VERB, 0);
2536 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2537 return;
2538
2539 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2540 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2541 INTEL_SET_VENDOR_VERB, vendor_param);
2542 if (vendor_param == -1)
2543 return;
2544
17df3f55
TI		 2545 if (update_tree)
2546 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2547}
2548
c88d4e84
TI		 2549static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2550{
2551 unsigned int vendor_param;
2552
2553 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2554 INTEL_GET_VENDOR_VERB, 0);
2555 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2556 return;
2557
2558 /* enable DP1.2 mode */
2559 vendor_param |= INTEL_EN_DP12;
a551d914 2560 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2561 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2562 INTEL_SET_VENDOR_VERB, vendor_param);
2563}
2564
17df3f55
TI		 2565/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2566 * Otherwise you may get severe h/w communication errors.
2567 */
2568static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2569 unsigned int power_state)
2570{
2571 if (power_state == AC_PWRST_D0) {
2572 intel_haswell_enable_all_pins(codec, false);
2573 intel_haswell_fixup_enable_dp12(codec);
2574 }
c88d4e84 2575
17df3f55
TI		 2576 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2577 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2578}
6ffe168f 2579
f0675d4a 2580static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2581{
2582 struct hda_codec *codec = audio_ptr;
2583 int pin_nid = port + 0x04;
2584
8ae743e8
TI		 2585 /* skip notification during system suspend (but not in runtime PM);
2586 * the state will be updated at resume
2587 */
2588 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2589 return;
eb399d3c
TI		 2590 /* ditto during suspend/resume process itself */
2591 if (atomic_read(&(codec)->core.in_pm))
2592 return;
8ae743e8 2593
25adc137
DH		 2594 check_presence_and_report(codec, pin_nid);
2595}
2596
84eb01be
TI		 2597static int patch_generic_hdmi(struct hda_codec *codec)
2598{
2599 struct hdmi_spec *spec;
84eb01be
TI		 2600
2601 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2602 if (spec == NULL)
2603 return -ENOMEM;
2604
307229d2 2605 spec->ops = generic_standard_hdmi_ops;
42b29870 2606 mutex_init(&spec->pcm_lock);
84eb01be 2607 codec->spec = spec;
bce0d2a8 2608 hdmi_array_init(spec, 4);
6ffe168f 2609
55913110
TI		 2610 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2611 if (!codec_has_acomp(codec) &&
2612 (codec->core.vendor_id >> 16) == 0x8086)
2613 if (!snd_hdac_i915_init(&codec->bus->core))
2614 spec->i915_bound = true;
2615
75dcbe4d 2616 if (is_haswell_plus(codec)) {
17df3f55 2617 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2618 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2619 }
6ffe168f 2620
2bd1f73f
ML		 2621 /* For Valleyview/Cherryview, only the display codec is in the display
2622 * power well and can use link_power ops to request/release the power.
2623 * For Haswell/Broadwell, the controller is also in the power well and
2624 * can cover the codec power request, and so need not set this flag.
2625 * For previous platforms, there is no such power well feature.
2626 */
ff9d8859
LH		 2627 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2628 is_broxton(codec))
2bd1f73f
ML		 2629 codec->core.link_power_control = 1;
2630
6603249d 2631 if (codec_has_acomp(codec)) {
5b8620bb 2632 codec->depop_delay = 0;
25adc137
DH		 2633 spec->i915_audio_ops.audio_ptr = codec;
2634 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2635 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2636 }
5b8620bb 2637
84eb01be 2638 if (hdmi_parse_codec(codec) < 0) {
55913110
TI		 2639 if (spec->i915_bound)
2640 snd_hdac_i915_exit(&codec->bus->core);
84eb01be
TI		 2641 codec->spec = NULL;
2642 kfree(spec);
2643 return -EINVAL;
2644 }
2645 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2646 if (is_haswell_plus(codec)) {
17df3f55 2647 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2648 codec->dp_mst = true;
2649 }
17df3f55 2650
2377c3c3
LH		 2651 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2652 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2653 codec->auto_runtime_pm = 1;
2654
8b8d654b 2655 generic_hdmi_init_per_pins(codec);
84eb01be 2656
84eb01be
TI		 2657 init_channel_allocations();
2658
2659 return 0;
2660}
2661
3aaf8980
SW		 2662/*
2663 * Shared non-generic implementations
2664 */
2665
2666static int simple_playback_build_pcms(struct hda_codec *codec)
2667{
2668 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2669 struct hda_pcm *info;
8ceb332d
TI		 2670 unsigned int chans;
2671 struct hda_pcm_stream *pstr;
bce0d2a8 2672 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2673
bce0d2a8
TI		 2674 per_cvt = get_cvt(spec, 0);
2675 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2676 chans = get_wcaps_channels(chans);
3aaf8980 2677
bbbc7e85 2678 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2679 if (!info)
2680 return -ENOMEM;
bbbc7e85 2681 spec->pcm_rec[0] = info;
8ceb332d
TI		 2682 info->pcm_type = HDA_PCM_TYPE_HDMI;
2683 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2684 *pstr = spec->pcm_playback;
bce0d2a8 2685 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2686 if (pstr->channels_max <= 2 && chans && chans <= 16)
2687 pstr->channels_max = chans;
3aaf8980
SW		 2688
2689 return 0;
2690}
2691
4b6ace9e
TI		 2692/* unsolicited event for jack sensing */
2693static void simple_hdmi_unsol_event(struct hda_codec *codec,
2694 unsigned int res)
2695{
9dd8cf12 2696 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2697 snd_hda_jack_report_sync(codec);
2698}
2699
2700/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2701 * as long as spec->pins[] is set correctly
2702 */
2703#define simple_hdmi_build_jack generic_hdmi_build_jack
2704
3aaf8980
SW		 2705static int simple_playback_build_controls(struct hda_codec *codec)
2706{
2707 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2708 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2709 int err;
3aaf8980 2710
bce0d2a8 2711 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2712 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2713 per_cvt->cvt_nid,
2714 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2715 if (err < 0)
2716 return err;
2717 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2718}
2719
4f0110ce
TI		 2720static int simple_playback_init(struct hda_codec *codec)
2721{
2722 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2723 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2724 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2725
2726 snd_hda_codec_write(codec, pin, 0,
2727 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2728 /* some codecs require to unmute the pin */
2729 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2730 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2731 AMP_OUT_UNMUTE);
62f949bf 2732 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2733 return 0;
2734}
2735
3aaf8980
SW		 2736static void simple_playback_free(struct hda_codec *codec)
2737{
2738 struct hdmi_spec *spec = codec->spec;
2739
bce0d2a8 2740 hdmi_array_free(spec);
3aaf8980
SW		 2741 kfree(spec);
2742}
2743
84eb01be
TI		 2744/*
2745 * Nvidia specific implementations
2746 */
2747
2748#define Nv_VERB_SET_Channel_Allocation 0xF79
2749#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2750#define Nv_VERB_SET_Audio_Protection_On 0xF98
2751#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2752
2753#define nvhdmi_master_con_nid_7x 0x04
2754#define nvhdmi_master_pin_nid_7x 0x05
2755
fb79e1e0 2756static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2757 /*front, rear, clfe, rear_surr */
2758 0x6, 0x8, 0xa, 0xc,
2759};
2760
ceaa86ba
TI		 2761static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2762 /* set audio protect on */
2763 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2764 /* enable digital output on pin widget */
2765 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2766 {} /* terminator */
2767};
2768
2769static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2770 /* set audio protect on */
2771 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2772 /* enable digital output on pin widget */
2773 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2774 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2775 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2776 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2777 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2778 {} /* terminator */
2779};
2780
2781#ifdef LIMITED_RATE_FMT_SUPPORT
2782/* support only the safe format and rate */
2783#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2784#define SUPPORTED_MAXBPS 16
2785#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2786#else
2787/* support all rates and formats */
2788#define SUPPORTED_RATES \
2789 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2790 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2791 SNDRV_PCM_RATE_192000)
2792#define SUPPORTED_MAXBPS 24
2793#define SUPPORTED_FORMATS \
2794 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2795#endif
2796
ceaa86ba
TI		 2797static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2798{
2799 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2800 return 0;
2801}
2802
2803static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2804{
ceaa86ba 2805 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2806 return 0;
2807}
2808
393004b2
ND		 2809static unsigned int channels_2_6_8[] = {
2810 2, 6, 8
2811};
2812
2813static unsigned int channels_2_8[] = {
2814 2, 8
2815};
2816
2817static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2818 .count = ARRAY_SIZE(channels_2_6_8),
2819 .list = channels_2_6_8,
2820 .mask = 0,
2821};
2822
2823static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2824 .count = ARRAY_SIZE(channels_2_8),
2825 .list = channels_2_8,
2826 .mask = 0,
2827};
2828
84eb01be
TI		 2829static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2830 struct hda_codec *codec,
2831 struct snd_pcm_substream *substream)
2832{
2833 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2834 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2835
b9a94a9c 2836 switch (codec->preset->vendor_id) {
393004b2
ND		 2837 case 0x10de0002:
2838 case 0x10de0003:
2839 case 0x10de0005:
2840 case 0x10de0006:
2841 hw_constraints_channels = &hw_constraints_2_8_channels;
2842 break;
2843 case 0x10de0007:
2844 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2845 break;
2846 default:
2847 break;
2848 }
2849
2850 if (hw_constraints_channels != NULL) {
2851 snd_pcm_hw_constraint_list(substream->runtime, 0,
2852 SNDRV_PCM_HW_PARAM_CHANNELS,
2853 hw_constraints_channels);
ad09fc9d
TI		 2854 } else {
2855 snd_pcm_hw_constraint_step(substream->runtime, 0,
2856 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2857 }
2858
84eb01be
TI		 2859 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2860}
2861
2862static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2863 struct hda_codec *codec,
2864 struct snd_pcm_substream *substream)
2865{
2866 struct hdmi_spec *spec = codec->spec;
2867 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2868}
2869
2870static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2871 struct hda_codec *codec,
2872 unsigned int stream_tag,
2873 unsigned int format,
2874 struct snd_pcm_substream *substream)
2875{
2876 struct hdmi_spec *spec = codec->spec;
2877 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2878 stream_tag, format, substream);
2879}
2880
d0b1252d
TI		 2881static const struct hda_pcm_stream simple_pcm_playback = {
2882 .substreams = 1,
2883 .channels_min = 2,
2884 .channels_max = 2,
2885 .ops = {
2886 .open = simple_playback_pcm_open,
2887 .close = simple_playback_pcm_close,
2888 .prepare = simple_playback_pcm_prepare
2889 },
2890};
2891
2892static const struct hda_codec_ops simple_hdmi_patch_ops = {
2893 .build_controls = simple_playback_build_controls,
2894 .build_pcms = simple_playback_build_pcms,
2895 .init = simple_playback_init,
2896 .free = simple_playback_free,
250e41ac 2897 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2898};
2899
2900static int patch_simple_hdmi(struct hda_codec *codec,
2901 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2902{
2903 struct hdmi_spec *spec;
bce0d2a8
TI		 2904 struct hdmi_spec_per_cvt *per_cvt;
2905 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2906
2907 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2908 if (!spec)
2909 return -ENOMEM;
2910
2911 codec->spec = spec;
bce0d2a8 2912 hdmi_array_init(spec, 1);
d0b1252d
TI		 2913
2914 spec->multiout.num_dacs = 0; /* no analog */
2915 spec->multiout.max_channels = 2;
2916 spec->multiout.dig_out_nid = cvt_nid;
2917 spec->num_cvts = 1;
2918 spec->num_pins = 1;
bce0d2a8
TI		 2919 per_pin = snd_array_new(&spec->pins);
2920 per_cvt = snd_array_new(&spec->cvts);
2921 if (!per_pin || !per_cvt) {
2922 simple_playback_free(codec);
2923 return -ENOMEM;
2924 }
2925 per_cvt->cvt_nid = cvt_nid;
2926 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2927 spec->pcm_playback = simple_pcm_playback;
2928
2929 codec->patch_ops = simple_hdmi_patch_ops;
2930
2931 return 0;
2932}
2933
1f348522
AP		 2934static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2935 int channels)
2936{
2937 unsigned int chanmask;
2938 int chan = channels ? (channels - 1) : 1;
2939
2940 switch (channels) {
2941 default:
2942 case 0:
2943 case 2:
2944 chanmask = 0x00;
2945 break;
2946 case 4:
2947 chanmask = 0x08;
2948 break;
2949 case 6:
2950 chanmask = 0x0b;
2951 break;
2952 case 8:
2953 chanmask = 0x13;
2954 break;
2955 }
2956
2957 /* Set the audio infoframe channel allocation and checksum fields. The
2958 * channel count is computed implicitly by the hardware. */
2959 snd_hda_codec_write(codec, 0x1, 0,
2960 Nv_VERB_SET_Channel_Allocation, chanmask);
2961
2962 snd_hda_codec_write(codec, 0x1, 0,
2963 Nv_VERB_SET_Info_Frame_Checksum,
2964 (0x71 - chan - chanmask));
2965}
2966
84eb01be
TI		 2967static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2968 struct hda_codec *codec,
2969 struct snd_pcm_substream *substream)
2970{
2971 struct hdmi_spec *spec = codec->spec;
2972 int i;
2973
2974 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2975 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2976 for (i = 0; i < 4; i++) {
2977 /* set the stream id */
2978 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2979 AC_VERB_SET_CHANNEL_STREAMID, 0);
2980 /* set the stream format */
2981 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2982 AC_VERB_SET_STREAM_FORMAT, 0);
2983 }
2984
1f348522
AP		 2985 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2986 * streams are disabled. */
2987 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2988
84eb01be
TI		 2989 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2990}
2991
2992static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2993 struct hda_codec *codec,
2994 unsigned int stream_tag,
2995 unsigned int format,
2996 struct snd_pcm_substream *substream)
2997{
2998 int chs;
112daa7a 2999 unsigned int dataDCC2, channel_id;
84eb01be 3000 int i;
7c935976 3001 struct hdmi_spec *spec = codec->spec;
e3245cdd 3002 struct hda_spdif_out *spdif;
bce0d2a8 3003 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3004
3005 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3006 per_cvt = get_cvt(spec, 0);
3007 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3008
3009 chs = substream->runtime->channels;
84eb01be 3010
84eb01be
TI		 3011 dataDCC2 = 0x2;
3012
84eb01be 3013 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3014 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3015 snd_hda_codec_write(codec,
3016 nvhdmi_master_con_nid_7x,
3017 0,
3018 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3019 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3020
3021 /* set the stream id */
3022 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3023 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3024
3025 /* set the stream format */
3026 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3027 AC_VERB_SET_STREAM_FORMAT, format);
3028
3029 /* turn on again (if needed) */
3030 /* enable and set the channel status audio/data flag */
7c935976 3031 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3032 snd_hda_codec_write(codec,
3033 nvhdmi_master_con_nid_7x,
3034 0,
3035 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3036 spdif->ctls & 0xff);
84eb01be
TI		 3037 snd_hda_codec_write(codec,
3038 nvhdmi_master_con_nid_7x,
3039 0,
3040 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3041 }
3042
3043 for (i = 0; i < 4; i++) {
3044 if (chs == 2)
3045 channel_id = 0;
3046 else
3047 channel_id = i * 2;
3048
3049 /* turn off SPDIF once;
3050 *otherwise the IEC958 bits won't be updated
3051 */
3052 if (codec->spdif_status_reset &&
7c935976 3053 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3054 snd_hda_codec_write(codec,
3055 nvhdmi_con_nids_7x[i],
3056 0,
3057 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3058 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3059 /* set the stream id */
3060 snd_hda_codec_write(codec,
3061 nvhdmi_con_nids_7x[i],
3062 0,
3063 AC_VERB_SET_CHANNEL_STREAMID,
3064 (stream_tag << 4) | channel_id);
3065 /* set the stream format */
3066 snd_hda_codec_write(codec,
3067 nvhdmi_con_nids_7x[i],
3068 0,
3069 AC_VERB_SET_STREAM_FORMAT,
3070 format);
3071 /* turn on again (if needed) */
3072 /* enable and set the channel status audio/data flag */
3073 if (codec->spdif_status_reset &&
7c935976 3074 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3075 snd_hda_codec_write(codec,
3076 nvhdmi_con_nids_7x[i],
3077 0,
3078 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3079 spdif->ctls & 0xff);
84eb01be
TI		 3080 snd_hda_codec_write(codec,
3081 nvhdmi_con_nids_7x[i],
3082 0,
3083 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3084 }
3085 }
3086
1f348522 3087 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3088
3089 mutex_unlock(&codec->spdif_mutex);
3090 return 0;
3091}
3092
fb79e1e0 3093static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3094 .substreams = 1,
3095 .channels_min = 2,
3096 .channels_max = 8,
3097 .nid = nvhdmi_master_con_nid_7x,
3098 .rates = SUPPORTED_RATES,
3099 .maxbps = SUPPORTED_MAXBPS,
3100 .formats = SUPPORTED_FORMATS,
3101 .ops = {
3102 .open = simple_playback_pcm_open,
3103 .close = nvhdmi_8ch_7x_pcm_close,
3104 .prepare = nvhdmi_8ch_7x_pcm_prepare
3105 },
3106};
3107
84eb01be
TI		 3108static int patch_nvhdmi_2ch(struct hda_codec *codec)
3109{
3110 struct hdmi_spec *spec;
d0b1252d
TI		 3111 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3112 nvhdmi_master_pin_nid_7x);
3113 if (err < 0)
3114 return err;
84eb01be 3115
ceaa86ba 3116 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3117 /* override the PCM rates, etc, as the codec doesn't give full list */
3118 spec = codec->spec;
3119 spec->pcm_playback.rates = SUPPORTED_RATES;
3120 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3121 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3122 return 0;
3123}
3124
53775b0d
TI		 3125static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3126{
3127 struct hdmi_spec *spec = codec->spec;
3128 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3129 if (!err) {
3130 struct hda_pcm *info = get_pcm_rec(spec, 0);
3131 info->own_chmap = true;
3132 }
53775b0d
TI		 3133 return err;
3134}
3135
3136static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3137{
3138 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3139 struct hda_pcm *info;
53775b0d
TI		 3140 struct snd_pcm_chmap *chmap;
3141 int err;
3142
3143 err = simple_playback_build_controls(codec);
3144 if (err < 0)
3145 return err;
3146
3147 /* add channel maps */
bce0d2a8
TI		 3148 info = get_pcm_rec(spec, 0);
3149 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3150 SNDRV_PCM_STREAM_PLAYBACK,
3151 snd_pcm_alt_chmaps, 8, 0, &chmap);
3152 if (err < 0)
3153 return err;
b9a94a9c 3154 switch (codec->preset->vendor_id) {
53775b0d
TI		 3155 case 0x10de0002:
3156 case 0x10de0003:
3157 case 0x10de0005:
3158 case 0x10de0006:
3159 chmap->channel_mask = (1U << 2) | (1U << 8);
3160 break;
3161 case 0x10de0007:
3162 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3163 }
3164 return 0;
3165}
3166
84eb01be
TI		 3167static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3168{
3169 struct hdmi_spec *spec;
3170 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3171 if (err < 0)
3172 return err;
3173 spec = codec->spec;
3174 spec->multiout.max_channels = 8;
d0b1252d 3175 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3176 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3177 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3178 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3179
3180 /* Initialize the audio infoframe channel mask and checksum to something
3181 * valid */
3182 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3183
84eb01be
TI		 3184 return 0;
3185}
3186
611885bc
AH		 3187/*
3188 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3189 * - 0x10de0015
3190 * - 0x10de0040
3191 */
3192static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3193 int channels)
3194{
3195 if (cap->ca_index == 0x00 && channels == 2)
3196 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3197
3198 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
3199}
3200
3201static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
3202{
3203 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3204 return -EINVAL;
3205
3206 return 0;
3207}
3208
3209static int patch_nvhdmi(struct hda_codec *codec)
3210{
3211 struct hdmi_spec *spec;
3212 int err;
3213
3214 err = patch_generic_hdmi(codec);
3215 if (err)
3216 return err;
3217
3218 spec = codec->spec;
75fae117 3219 spec->dyn_pin_out = true;
611885bc
AH		 3220
3221 spec->ops.chmap_cea_alloc_validate_get_type =
3222 nvhdmi_chmap_cea_alloc_validate_get_type;
3223 spec->ops.chmap_validate = nvhdmi_chmap_validate;
3224
3225 return 0;
3226}
3227
26e9a960
TR		 3228/*
3229 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3230 * accessed using vendor-defined verbs. These registers can be used for
3231 * interoperability between the HDA and HDMI drivers.
3232 */
3233
3234/* Audio Function Group node */
3235#define NVIDIA_AFG_NID 0x01
3236
3237/*
3238 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3239 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3240 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3241 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3242 * additional bit (at position 30) to signal the validity of the format.
3243 *
3244 * | 31 | 30 | 29 16 | 15 0 |
3245 * +---------+-------+--------+--------+
3246 * | TRIGGER | VALID | UNUSED | FORMAT |
3247 * +-----------------------------------|
3248 *
3249 * Note that for the trigger bit to take effect it needs to change value
3250 * (i.e. it needs to be toggled).
3251 */
3252#define NVIDIA_GET_SCRATCH0 0xfa6
3253#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3254#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3255#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3256#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3257#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3258#define NVIDIA_SCRATCH_VALID (1 << 6)
3259
3260#define NVIDIA_GET_SCRATCH1 0xfab
3261#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3262#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3263#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3264#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3265
3266/*
3267 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3268 * the format is invalidated so that the HDMI codec can be disabled.
3269 */
3270static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3271{
3272 unsigned int value;
3273
3274 /* bits [31:30] contain the trigger and valid bits */
3275 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3276 NVIDIA_GET_SCRATCH0, 0);
3277 value = (value >> 24) & 0xff;
3278
3279 /* bits [15:0] are used to store the HDA format */
3280 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3281 NVIDIA_SET_SCRATCH0_BYTE0,
3282 (format >> 0) & 0xff);
3283 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3284 NVIDIA_SET_SCRATCH0_BYTE1,
3285 (format >> 8) & 0xff);
3286
3287 /* bits [16:24] are unused */
3288 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3289 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3290
3291 /*
3292 * Bit 30 signals that the data is valid and hence that HDMI audio can
3293 * be enabled.
3294 */
3295 if (format == 0)
3296 value &= ~NVIDIA_SCRATCH_VALID;
3297 else
3298 value |= NVIDIA_SCRATCH_VALID;
3299
3300 /*
3301 * Whenever the trigger bit is toggled, an interrupt is raised in the
3302 * HDMI codec. The HDMI driver will use that as trigger to update its
3303 * configuration.
3304 */
3305 value ^= NVIDIA_SCRATCH_TRIGGER;
3306
3307 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3308 NVIDIA_SET_SCRATCH0_BYTE3, value);
3309}
3310
3311static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3312 struct hda_codec *codec,
3313 unsigned int stream_tag,
3314 unsigned int format,
3315 struct snd_pcm_substream *substream)
3316{
3317 int err;
3318
3319 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3320 format, substream);
3321 if (err < 0)
3322 return err;
3323
3324 /* notify the HDMI codec of the format change */
3325 tegra_hdmi_set_format(codec, format);
3326
3327 return 0;
3328}
3329
3330static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3331 struct hda_codec *codec,
3332 struct snd_pcm_substream *substream)
3333{
3334 /* invalidate the format in the HDMI codec */
3335 tegra_hdmi_set_format(codec, 0);
3336
3337 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3338}
3339
3340static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3341{
3342 struct hdmi_spec *spec = codec->spec;
3343 unsigned int i;
3344
3345 for (i = 0; i < spec->num_pins; i++) {
3346 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3347
3348 if (pcm->pcm_type == type)
3349 return pcm;
3350 }
3351
3352 return NULL;
3353}
3354
3355static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3356{
3357 struct hda_pcm_stream *stream;
3358 struct hda_pcm *pcm;
3359 int err;
3360
3361 err = generic_hdmi_build_pcms(codec);
3362 if (err < 0)
3363 return err;
3364
3365 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3366 if (!pcm)
3367 return -ENODEV;
3368
3369 /*
3370 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3371 * codec about format changes.
3372 */
3373 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3374 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3375 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3376
3377 return 0;
3378}
3379
3380static int patch_tegra_hdmi(struct hda_codec *codec)
3381{
3382 int err;
3383
3384 err = patch_generic_hdmi(codec);
3385 if (err)
3386 return err;
3387
3388 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3389
3390 return 0;
3391}
3392
84eb01be 3393/*
5a613584 3394 * ATI/AMD-specific implementations
84eb01be
TI		 3395 */
3396
5a613584 3397#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3398 ((codec)->core.vendor_id == 0x1002aa01 && \
3399 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3400#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3401
3402/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3403#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3404#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3405#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3406#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3407#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3408#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3409#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3410#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3411#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3412#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3413#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3414#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3415#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3416#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3417#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3418#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3419#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3420#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3421#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3422#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3423#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3424#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3425#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3426#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3427
84d69e79
AH		 3428/* AMD specific HDA cvt verbs */
3429#define ATI_VERB_SET_RAMP_RATE 0x770
3430#define ATI_VERB_GET_RAMP_RATE 0xf70
3431
5a613584
AH		 3432#define ATI_OUT_ENABLE 0x1
3433
3434#define ATI_MULTICHANNEL_MODE_PAIRED 0
3435#define ATI_MULTICHANNEL_MODE_SINGLE 1
3436
461cf6b3
AH		 3437#define ATI_HBR_CAPABLE 0x01
3438#define ATI_HBR_ENABLE 0x10
3439
89250f84
AH		 3440static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3441 unsigned char *buf, int *eld_size)
3442{
3443 /* call hda_eld.c ATI/AMD-specific function */
3444 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3445 is_amdhdmi_rev3_or_later(codec));
3446}
3447
5a613584
AH		 3448static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3449 int active_channels, int conn_type)
3450{
3451 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3452}
3453
3454static int atihdmi_paired_swap_fc_lfe(int pos)
3455{
3456 /*
3457 * ATI/AMD have automatic FC/LFE swap built-in
3458 * when in pairwise mapping mode.
3459 */
3460
3461 switch (pos) {
3462 /* see channel_allocations[].speakers[] */
3463 case 2: return 3;
3464 case 3: return 2;
3465 default: break;
3466 }
3467
3468 return pos;
3469}
3470
3471static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3472{
3473 struct cea_channel_speaker_allocation *cap;
3474 int i, j;
3475
3476 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3477
3478 cap = &channel_allocations[get_channel_allocation_order(ca)];
3479 for (i = 0; i < chs; ++i) {
3480 int mask = to_spk_mask(map[i]);
3481 bool ok = false;
3482 bool companion_ok = false;
3483
3484 if (!mask)
3485 continue;
3486
3487 for (j = 0 + i % 2; j < 8; j += 2) {
3488 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3489 if (cap->speakers[chan_idx] == mask) {
3490 /* channel is in a supported position */
3491 ok = true;
3492
3493 if (i % 2 == 0 && i + 1 < chs) {
3494 /* even channel, check the odd companion */
3495 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3496 int comp_mask_req = to_spk_mask(map[i+1]);
3497 int comp_mask_act = cap->speakers[comp_chan_idx];
3498
3499 if (comp_mask_req == comp_mask_act)
3500 companion_ok = true;
3501 else
3502 return -EINVAL;
3503 }
3504 break;
3505 }
3506 }
3507
3508 if (!ok)
3509 return -EINVAL;
3510
3511 if (companion_ok)
3512 i++; /* companion channel already checked */
3513 }
3514
3515 return 0;
3516}
3517
3518static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3519 int hdmi_slot, int stream_channel)
3520{
3521 int verb;
3522 int ati_channel_setup = 0;
3523
3524 if (hdmi_slot > 7)
3525 return -EINVAL;
3526
3527 if (!has_amd_full_remap_support(codec)) {
3528 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3529
3530 /* In case this is an odd slot but without stream channel, do not
3531 * disable the slot since the corresponding even slot could have a
3532 * channel. In case neither have a channel, the slot pair will be
3533 * disabled when this function is called for the even slot. */
3534 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3535 return 0;
3536
3537 hdmi_slot -= hdmi_slot % 2;
3538
3539 if (stream_channel != 0xf)
3540 stream_channel -= stream_channel % 2;
3541 }
3542
3543 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3544
3545 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3546
3547 if (stream_channel != 0xf)
3548 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3549
3550 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3551}
3552
3553static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3554 int asp_slot)
3555{
3556 bool was_odd = false;
3557 int ati_asp_slot = asp_slot;
3558 int verb;
3559 int ati_channel_setup;
3560
3561 if (asp_slot > 7)
3562 return -EINVAL;
3563
3564 if (!has_amd_full_remap_support(codec)) {
3565 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3566 if (ati_asp_slot % 2 != 0) {
3567 ati_asp_slot -= 1;
3568 was_odd = true;
3569 }
3570 }
3571
3572 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3573
3574 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3575
3576 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3577 return 0xf;
3578
3579 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3580}
84eb01be 3581
5a613584
AH		 3582static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3583 int channels)
3584{
3585 int c;
3586
3587 /*
3588 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3589 * we need to take that into account (a single channel may take 2
3590 * channel slots if we need to carry a silent channel next to it).
3591 * On Rev3+ AMD codecs this function is not used.
3592 */
3593 int chanpairs = 0;
3594
3595 /* We only produce even-numbered channel count TLVs */
3596 if ((channels % 2) != 0)
3597 return -1;
3598
3599 for (c = 0; c < 7; c += 2) {
3600 if (cap->speakers[c] || cap->speakers[c+1])
3601 chanpairs++;
3602 }
3603
3604 if (chanpairs * 2 != channels)
3605 return -1;
3606
3607 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3608}
3609
3610static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3611 unsigned int *chmap, int channels)
3612{
3613 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3614 int count = 0;
3615 int c;
3616
3617 for (c = 7; c >= 0; c--) {
3618 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3619 int spk = cap->speakers[chan];
3620 if (!spk) {
3621 /* add N/A channel if the companion channel is occupied */
3622 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3623 chmap[count++] = SNDRV_CHMAP_NA;
3624
3625 continue;
3626 }
3627
3628 chmap[count++] = spk_to_chmap(spk);
3629 }
3630
3631 WARN_ON(count != channels);
3632}
3633
461cf6b3
AH		 3634static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3635 bool hbr)
3636{
3637 int hbr_ctl, hbr_ctl_new;
3638
3639 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3640 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3641 if (hbr)
3642 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3643 else
3644 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3645
4e76a883
TI		 3646 codec_dbg(codec,
3647 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3648 pin_nid,
3649 hbr_ctl == hbr_ctl_new ? "" : "new-",
3650 hbr_ctl_new);
3651
3652 if (hbr_ctl != hbr_ctl_new)
3653 snd_hda_codec_write(codec, pin_nid, 0,
3654 ATI_VERB_SET_HBR_CONTROL,
3655 hbr_ctl_new);
3656
3657 } else if (hbr)
3658 return -EINVAL;
3659
3660 return 0;
3661}
3662
84d69e79
AH		 3663static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3664 hda_nid_t pin_nid, u32 stream_tag, int format)
3665{
3666
3667 if (is_amdhdmi_rev3_or_later(codec)) {
3668 int ramp_rate = 180; /* default as per AMD spec */
3669 /* disable ramp-up/down for non-pcm as per AMD spec */
3670 if (format & AC_FMT_TYPE_NON_PCM)
3671 ramp_rate = 0;
3672
3673 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3674 }
3675
3676 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3677}
3678
3679
5a613584 3680static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3681{
3682 struct hdmi_spec *spec = codec->spec;
5a613584 3683 int pin_idx, err;
84eb01be 3684
5a613584
AH		 3685 err = generic_hdmi_init(codec);
3686
3687 if (err)
84eb01be 3688 return err;
5a613584
AH		 3689
3690 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3691 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3692
3693 /* make sure downmix information in infoframe is zero */
3694 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3695
3696 /* enable channel-wise remap mode if supported */
3697 if (has_amd_full_remap_support(codec))
3698 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3699 ATI_VERB_SET_MULTICHANNEL_MODE,
3700 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3701 }
5a613584 3702
84eb01be
TI		 3703 return 0;
3704}
3705
84eb01be
TI		 3706static int patch_atihdmi(struct hda_codec *codec)
3707{
3708 struct hdmi_spec *spec;
5a613584
AH		 3709 struct hdmi_spec_per_cvt *per_cvt;
3710 int err, cvt_idx;
3711
3712 err = patch_generic_hdmi(codec);
3713
3714 if (err)
d0b1252d 3715 return err;
5a613584
AH		 3716
3717 codec->patch_ops.init = atihdmi_init;
3718
d0b1252d 3719 spec = codec->spec;
5a613584 3720
89250f84 3721 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3722 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3723 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3724 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3725 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3726 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3727
3728 if (!has_amd_full_remap_support(codec)) {
3729 /* override to ATI/AMD-specific versions with pairwise mapping */
3730 spec->ops.chmap_cea_alloc_validate_get_type =
3731 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3732 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3733 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3734 }
3735
3736 /* ATI/AMD converters do not advertise all of their capabilities */
3737 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3738 per_cvt = get_cvt(spec, cvt_idx);
3739 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3740 per_cvt->rates |= SUPPORTED_RATES;
3741 per_cvt->formats |= SUPPORTED_FORMATS;
3742 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3743 }
3744
3745 spec->channels_max = max(spec->channels_max, 8u);
3746
84eb01be
TI		 3747 return 0;
3748}
3749
3de5ff88
AL		 3750/* VIA HDMI Implementation */
3751#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3752#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3753
3de5ff88
AL		 3754static int patch_via_hdmi(struct hda_codec *codec)
3755{
250e41ac 3756 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3757}
84eb01be
TI		 3758
3759/*
3760 * patch entries
3761 */
b9a94a9c
TI		 3762static const struct hda_device_id snd_hda_id_hdmi[] = {
3763HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3764HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3765HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3766HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3767HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3768HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3769HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3770HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3771HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3772HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3773HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3774HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3775HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3776HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3777HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3778HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3779HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3780HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3781HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3782HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3783HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3784HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3785HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3786/* 17 is known to be absent */
b9a94a9c
TI		 3787HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3788HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3789HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3790HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3791HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3792HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3793HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3794HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3795HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3796HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3797HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3798HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3799HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3800HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3801HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3802HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3803HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3804HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3805HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3806HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3807HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3808HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3809HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3810HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3811HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3812HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3813HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3814HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3815HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3816HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3817HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3818HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3819HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3820HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3821HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3822HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3823HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
91815d8a 3824HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
b9a94a9c
TI		 3825HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3826HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3827HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3828HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3829/* special ID for generic HDMI */
b9a94a9c 3830HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3831{} /* terminator */
3832};
b9a94a9c 3833MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3834
3835MODULE_LICENSE("GPL");
3836MODULE_DESCRIPTION("HDMI HD-audio codec");
3837MODULE_ALIAS("snd-hda-codec-intelhdmi");
3838MODULE_ALIAS("snd-hda-codec-nvhdmi");
3839MODULE_ALIAS("snd-hda-codec-atihdmi");
3840
d8a766a1 3841static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3842 .id = snd_hda_id_hdmi,
84eb01be
TI		 3843};
3844
d8a766a1 3845module_hda_codec_driver(hdmi_driver);
Linux kernel - Deliverables
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