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ALSA: hda - Create common chmap object
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
67b90cb8 42#include <sound/hda_chmap.h>
84eb01be
TI		 43#include "hda_codec.h"
44#include "hda_local.h"
1835a0f9 45#include "hda_jack.h"
84eb01be 46
0ebaa24c
TI		 47static bool static_hdmi_pcm;
48module_param(static_hdmi_pcm, bool, 0644);
49MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50
7639a06c
TI		 51#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 54#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 55#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
432ac1a2 56#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a
LY		 57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
75dcbe4d 59
7639a06c
TI		 60#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 62#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 63
384a48d7
SW		 64struct hdmi_spec_per_cvt {
65 hda_nid_t cvt_nid;
66 int assigned;
67 unsigned int channels_min;
68 unsigned int channels_max;
69 u32 rates;
70 u64 formats;
71 unsigned int maxbps;
72};
079d88cc 73
4eea3091
TI		 74/* max. connections to a widget */
75#define HDA_MAX_CONNECTIONS 32
76
384a48d7
SW		 77struct hdmi_spec_per_pin {
78 hda_nid_t pin_nid;
a76056f2
LY		 79 /* pin idx, different device entries on the same pin use the same idx */
80 int pin_nid_idx;
384a48d7
SW		 81 int num_mux_nids;
82 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 83 int mux_idx;
1df5a06a 84 hda_nid_t cvt_nid;
744626da
WF		 85
86 struct hda_codec *codec;
384a48d7 87 struct hdmi_eld sink_eld;
a4e9a38b 88 struct mutex lock;
744626da 89 struct delayed_work work;
2bea241a 90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 92 int repoll_count;
b054087d
TI		 93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
1a6003b5 95 bool non_pcm;
d45e6889
TI		 96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 98#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 99 struct snd_info_entry *proc_entry;
100#endif
384a48d7 101};
079d88cc 102
307229d2
AH		 103struct cea_channel_speaker_allocation;
104
105/* operations used by generic code that can be overridden by patches */
106struct hdmi_ops {
107 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
108 unsigned char *buf, int *eld_size);
109
110 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
111 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int asp_slot);
113 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int asp_slot, int channel);
115
116 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
117 int ca, int active_channels, int conn_type);
118
119 /* enable/disable HBR (HD passthrough) */
120 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
121
122 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
123 hda_nid_t pin_nid, u32 stream_tag, int format);
124
307229d2
AH		 125};
126
2bea241a
LY		 127struct hdmi_pcm {
128 struct hda_pcm *pcm;
129 struct snd_jack *jack;
fb087eaa 130 struct snd_kcontrol *eld_ctl;
2bea241a
LY		 131};
132
384a48d7
SW		 133struct hdmi_spec {
134 int num_cvts;
bce0d2a8
TI		 135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
136 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 137
384a48d7 138 int num_pins;
bce0d2a8 139 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 140 struct hdmi_pcm pcm_rec[16];
42b29870 141 struct mutex pcm_lock;
a76056f2
LY		 142 /* pcm_bitmap means which pcms have been assigned to pins*/
143 unsigned long pcm_bitmap;
2bf3c85a 144 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 145 /* bitmap shows whether the pcm is opened in user space
146 * bit 0 means the first playback PCM (PCM3);
147 * bit 1 means the second playback PCM, and so on.
148 */
149 unsigned long pcm_in_use;
079d88cc 150
4bd038f9 151 struct hdmi_eld temp_eld;
307229d2 152 struct hdmi_ops ops;
75fae117
SW		 153
154 bool dyn_pin_out;
6590faab 155 bool dyn_pcm_assign;
079d88cc 156 /*
5a613584 157 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 158 */
159 struct hda_multi_out multiout;
d0b1252d 160 struct hda_pcm_stream pcm_playback;
25adc137
DH		 161
162 /* i915/powerwell (Haswell+/Valleyview+) specific */
163 struct i915_audio_component_audio_ops i915_audio_ops;
55913110 164 bool i915_bound; /* was i915 bound in this driver? */
67b90cb8
SP		 165
166 struct hdac_chmap chmap;
079d88cc
WF		 167};
168
f4e3040b 169#ifdef CONFIG_SND_HDA_I915
6603249d
TI		 170#define codec_has_acomp(codec) \
171 ((codec)->bus->core.audio_component != NULL)
f4e3040b
TI		 172#else
173#define codec_has_acomp(codec) false
174#endif
079d88cc
WF		 175
176struct hdmi_audio_infoframe {
177 u8 type; /* 0x84 */
178 u8 ver; /* 0x01 */
179 u8 len; /* 0x0a */
180
53d7d69d
WF		 181 u8 checksum;
182
079d88cc
WF		 183 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
184 u8 SS01_SF24;
185 u8 CXT04;
186 u8 CA;
187 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 188};
189
190struct dp_audio_infoframe {
191 u8 type; /* 0x84 */
192 u8 len; /* 0x1b */
193 u8 ver; /* 0x11 << 2 */
194
195 u8 CC02_CT47; /* match with HDMI infoframe from this on */
196 u8 SS01_SF24;
197 u8 CXT04;
198 u8 CA;
199 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 200};
201
2b203dbb
TI		 202union audio_infoframe {
203 struct hdmi_audio_infoframe hdmi;
204 struct dp_audio_infoframe dp;
205 u8 bytes[0];
206};
207
079d88cc
WF		 208/*
209 * CEA speaker placement:
210 *
211 * FLH FCH FRH
212 * FLW FL FLC FC FRC FR FRW
213 *
214 * LFE
215 * TC
216 *
217 * RL RLC RC RRC RR
218 *
219 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
220 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
221 */
222enum cea_speaker_placement {
223 FL = (1 << 0), /* Front Left */
224 FC = (1 << 1), /* Front Center */
225 FR = (1 << 2), /* Front Right */
226 FLC = (1 << 3), /* Front Left Center */
227 FRC = (1 << 4), /* Front Right Center */
228 RL = (1 << 5), /* Rear Left */
229 RC = (1 << 6), /* Rear Center */
230 RR = (1 << 7), /* Rear Right */
231 RLC = (1 << 8), /* Rear Left Center */
232 RRC = (1 << 9), /* Rear Right Center */
233 LFE = (1 << 10), /* Low Frequency Effect */
234 FLW = (1 << 11), /* Front Left Wide */
235 FRW = (1 << 12), /* Front Right Wide */
236 FLH = (1 << 13), /* Front Left High */
237 FCH = (1 << 14), /* Front Center High */
238 FRH = (1 << 15), /* Front Right High */
239 TC = (1 << 16), /* Top Center */
240};
241
242/*
243 * ELD SA bits in the CEA Speaker Allocation data block
244 */
245static int eld_speaker_allocation_bits[] = {
246 [0] = FL | FR,
247 [1] = LFE,
248 [2] = FC,
249 [3] = RL | RR,
250 [4] = RC,
251 [5] = FLC | FRC,
252 [6] = RLC | RRC,
253 /* the following are not defined in ELD yet */
254 [7] = FLW | FRW,
255 [8] = FLH | FRH,
256 [9] = TC,
257 [10] = FCH,
258};
259
079d88cc
WF		 260/*
261 * ALSA sequence is:
262 *
263 * surround40 surround41 surround50 surround51 surround71
264 * ch0 front left = = = =
265 * ch1 front right = = = =
266 * ch2 rear left = = = =
267 * ch3 rear right = = = =
268 * ch4 LFE center center center
269 * ch5 LFE LFE
270 * ch6 side left
271 * ch7 side right
272 *
273 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
274 */
275static int hdmi_channel_mapping[0x32][8] = {
276 /* stereo */
277 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
278 /* 2.1 */
279 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
280 /* Dolby Surround */
281 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
282 /* surround40 */
283 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
284 /* 4ch */
285 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
286 /* surround41 */
9396d317 287 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 288 /* surround50 */
289 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
290 /* surround51 */
291 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
292 /* 7.1 */
293 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
294};
295
296/*
297 * This is an ordered list!
298 *
299 * The preceding ones have better chances to be selected by
53d7d69d 300 * hdmi_channel_allocation().
079d88cc
WF		 301 */
302static struct cea_channel_speaker_allocation channel_allocations[] = {
303/* channel: 7 6 5 4 3 2 1 0 */
304{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
305 /* 2.1 */
306{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
307 /* Dolby Surround */
308{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
309 /* surround40 */
310{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
311 /* surround41 */
312{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
313 /* surround50 */
314{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
315 /* surround51 */
316{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
317 /* 6.1 */
318{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
319 /* surround71 */
320{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
321
322{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
323{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
324{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
325{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
326{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
327{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
328{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
329{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
330{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
331{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
332{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
334{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
335{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
336{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
337{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
338{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
339{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
340{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
341{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
342{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
343{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
344{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
345{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
346{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
347{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
348{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
349{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
350{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
351{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
352{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
353{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
354{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
355{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
356{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
357{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
358{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
359{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
360{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
361{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
362{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
363};
364
365
366/*
367 * HDMI routines
368 */
369
bce0d2a8
TI		 370#define get_pin(spec, idx) \
371 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
372#define get_cvt(spec, idx) \
373 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 374/* obtain hdmi_pcm object assigned to idx */
375#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
376/* obtain hda_pcm object assigned to idx */
377#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 378
4e76a883 379static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 380{
4e76a883 381 struct hdmi_spec *spec = codec->spec;
384a48d7 382 int pin_idx;
079d88cc 383
384a48d7 384 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 385 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 386 return pin_idx;
079d88cc 387
4e76a883 388 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 389 return -EINVAL;
390}
391
2bf3c85a
LY		 392static int hinfo_to_pcm_index(struct hda_codec *codec,
393 struct hda_pcm_stream *hinfo)
394{
395 struct hdmi_spec *spec = codec->spec;
396 int pcm_idx;
397
398 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
399 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
400 return pcm_idx;
401
402 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
403 return -EINVAL;
404}
405
4e76a883 406static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 407 struct hda_pcm_stream *hinfo)
408{
4e76a883 409 struct hdmi_spec *spec = codec->spec;
6590faab 410 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 411 int pin_idx;
412
6590faab
LY		 413 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
414 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 415 if (per_pin->pcm &&
416 per_pin->pcm->pcm->stream == hinfo)
384a48d7 417 return pin_idx;
6590faab 418 }
384a48d7 419
6590faab 420 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 421 return -EINVAL;
422}
423
022f344b
LY		 424static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
425 int pcm_idx)
426{
427 int i;
428 struct hdmi_spec_per_pin *per_pin;
429
430 for (i = 0; i < spec->num_pins; i++) {
431 per_pin = get_pin(spec, i);
432 if (per_pin->pcm_idx == pcm_idx)
433 return per_pin;
434 }
435 return NULL;
436}
437
4e76a883 438static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 439{
4e76a883 440 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 441 int cvt_idx;
442
443 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 444 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 445 return cvt_idx;
446
4e76a883 447 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 448 return -EINVAL;
449}
450
14bc52b8
PLB		 451static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
452 struct snd_ctl_elem_info *uinfo)
453{
454 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 455 struct hdmi_spec *spec = codec->spec;
a4e9a38b 456 struct hdmi_spec_per_pin *per_pin;
68e03de9 457 struct hdmi_eld *eld;
fb087eaa 458 int pcm_idx;
14bc52b8 459
14bc52b8
PLB		 460 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
461
fb087eaa
LY		 462 pcm_idx = kcontrol->private_value;
463 mutex_lock(&spec->pcm_lock);
464 per_pin = pcm_idx_to_pin(spec, pcm_idx);
465 if (!per_pin) {
466 /* no pin is bound to the pcm */
467 uinfo->count = 0;
468 mutex_unlock(&spec->pcm_lock);
469 return 0;
470 }
a4e9a38b 471 eld = &per_pin->sink_eld;
68e03de9 472 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
fb087eaa 473 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 474
475 return 0;
476}
477
478static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
479 struct snd_ctl_elem_value *ucontrol)
480{
481 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 482 struct hdmi_spec *spec = codec->spec;
a4e9a38b 483 struct hdmi_spec_per_pin *per_pin;
68e03de9 484 struct hdmi_eld *eld;
fb087eaa 485 int pcm_idx;
14bc52b8 486
fb087eaa
LY		 487 pcm_idx = kcontrol->private_value;
488 mutex_lock(&spec->pcm_lock);
489 per_pin = pcm_idx_to_pin(spec, pcm_idx);
490 if (!per_pin) {
491 /* no pin is bound to the pcm */
492 memset(ucontrol->value.bytes.data, 0,
493 ARRAY_SIZE(ucontrol->value.bytes.data));
494 mutex_unlock(&spec->pcm_lock);
495 return 0;
496 }
a4e9a38b 497 eld = &per_pin->sink_eld;
68e03de9 498
360a8245
DH		 499 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
500 eld->eld_size > ELD_MAX_SIZE) {
fb087eaa 501 mutex_unlock(&spec->pcm_lock);
68e03de9
DH		 502 snd_BUG();
503 return -EINVAL;
504 }
505
506 memset(ucontrol->value.bytes.data, 0,
507 ARRAY_SIZE(ucontrol->value.bytes.data));
508 if (eld->eld_valid)
509 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
510 eld->eld_size);
fb087eaa 511 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 512
513 return 0;
514}
515
516static struct snd_kcontrol_new eld_bytes_ctl = {
517 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
518 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
519 .name = "ELD",
520 .info = hdmi_eld_ctl_info,
521 .get = hdmi_eld_ctl_get,
522};
523
fb087eaa 524static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
14bc52b8
PLB		 525 int device)
526{
527 struct snd_kcontrol *kctl;
528 struct hdmi_spec *spec = codec->spec;
529 int err;
530
531 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
532 if (!kctl)
533 return -ENOMEM;
fb087eaa 534 kctl->private_value = pcm_idx;
14bc52b8
PLB		 535 kctl->id.device = device;
536
fb087eaa
LY		 537 /* no pin nid is associated with the kctl now
538 * tbd: associate pin nid to eld ctl later
539 */
540 err = snd_hda_ctl_add(codec, 0, kctl);
14bc52b8
PLB		 541 if (err < 0)
542 return err;
543
fb087eaa 544 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
14bc52b8
PLB		 545 return 0;
546}
547
079d88cc
WF		 548#ifdef BE_PARANOID
549static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
550 int *packet_index, int *byte_index)
551{
552 int val;
553
554 val = snd_hda_codec_read(codec, pin_nid, 0,
555 AC_VERB_GET_HDMI_DIP_INDEX, 0);
556
557 *packet_index = val >> 5;
558 *byte_index = val & 0x1f;
559}
560#endif
561
562static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
563 int packet_index, int byte_index)
564{
565 int val;
566
567 val = (packet_index << 5) | (byte_index & 0x1f);
568
569 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
570}
571
572static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
573 unsigned char val)
574{
575 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
576}
577
384a48d7 578static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 579{
75fae117
SW		 580 struct hdmi_spec *spec = codec->spec;
581 int pin_out;
582
079d88cc
WF		 583 /* Unmute */
584 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
585 snd_hda_codec_write(codec, pin_nid, 0,
586 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 587
588 if (spec->dyn_pin_out)
589 /* Disable pin out until stream is active */
590 pin_out = 0;
591 else
592 /* Enable pin out: some machines with GM965 gets broken output
593 * when the pin is disabled or changed while using with HDMI
594 */
595 pin_out = PIN_OUT;
596
079d88cc 597 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 598 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 599}
600
384a48d7 601static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 602{
384a48d7 603 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 604 AC_VERB_GET_CVT_CHAN_COUNT, 0);
605}
606
607static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 608 hda_nid_t cvt_nid, int chs)
079d88cc 609{
384a48d7
SW		 610 if (chs != hdmi_get_channel_count(codec, cvt_nid))
611 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 612 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
613}
614
a4e9a38b
TI		 615/*
616 * ELD proc files
617 */
618
cd6a6503 619#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 620static void print_eld_info(struct snd_info_entry *entry,
621 struct snd_info_buffer *buffer)
622{
623 struct hdmi_spec_per_pin *per_pin = entry->private_data;
624
625 mutex_lock(&per_pin->lock);
626 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
627 mutex_unlock(&per_pin->lock);
628}
629
630static void write_eld_info(struct snd_info_entry *entry,
631 struct snd_info_buffer *buffer)
632{
633 struct hdmi_spec_per_pin *per_pin = entry->private_data;
634
635 mutex_lock(&per_pin->lock);
636 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
637 mutex_unlock(&per_pin->lock);
638}
639
640static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
641{
642 char name[32];
643 struct hda_codec *codec = per_pin->codec;
644 struct snd_info_entry *entry;
645 int err;
646
647 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 648 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 649 if (err < 0)
650 return err;
651
652 snd_info_set_text_ops(entry, per_pin, print_eld_info);
653 entry->c.text.write = write_eld_info;
654 entry->mode |= S_IWUSR;
655 per_pin->proc_entry = entry;
656
657 return 0;
658}
659
660static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
661{
1947a114 662 if (!per_pin->codec->bus->shutdown) {
c560a679 663 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 664 per_pin->proc_entry = NULL;
665 }
666}
667#else
b55447a7
TI		 668static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
669 int index)
a4e9a38b
TI		 670{
671 return 0;
672}
b55447a7 673static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 674{
675}
676#endif
079d88cc
WF		 677
678/*
679 * Channel mapping routines
680 */
681
682/*
683 * Compute derived values in channel_allocations[].
684 */
685static void init_channel_allocations(void)
686{
687 int i, j;
688 struct cea_channel_speaker_allocation *p;
689
690 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
691 p = channel_allocations + i;
692 p->channels = 0;
693 p->spk_mask = 0;
694 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
695 if (p->speakers[j]) {
696 p->channels++;
697 p->spk_mask |= p->speakers[j];
698 }
699 }
700}
701
72357c78
WX		 702static int get_channel_allocation_order(int ca)
703{
704 int i;
705
706 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
707 if (channel_allocations[i].ca_index == ca)
708 break;
709 }
710 return i;
711}
712
079d88cc
WF		 713/*
714 * The transformation takes two steps:
715 *
716 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
717 * spk_mask => (channel_allocations[]) => ai->CA
718 *
719 * TODO: it could select the wrong CA from multiple candidates.
720*/
79514d47
TI		 721static int hdmi_channel_allocation(struct hda_codec *codec,
722 struct hdmi_eld *eld, int channels)
079d88cc 723{
079d88cc 724 int i;
53d7d69d 725 int ca = 0;
079d88cc 726 int spk_mask = 0;
079d88cc
WF		 727 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
728
729 /*
730 * CA defaults to 0 for basic stereo audio
731 */
732 if (channels <= 2)
733 return 0;
734
079d88cc
WF		 735 /*
736 * expand ELD's speaker allocation mask
737 *
738 * ELD tells the speaker mask in a compact(paired) form,
739 * expand ELD's notions to match the ones used by Audio InfoFrame.
740 */
741 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 742 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 743 spk_mask |= eld_speaker_allocation_bits[i];
744 }
745
746 /* search for the first working match in the CA table */
747 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
748 if (channels == channel_allocations[i].channels &&
749 (spk_mask & channel_allocations[i].spk_mask) ==
750 channel_allocations[i].spk_mask) {
53d7d69d 751 ca = channel_allocations[i].ca_index;
079d88cc
WF		 752 break;
753 }
754 }
755
18e39186
AH		 756 if (!ca) {
757 /* if there was no match, select the regular ALSA channel
758 * allocation with the matching number of channels */
759 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
760 if (channels == channel_allocations[i].channels) {
761 ca = channel_allocations[i].ca_index;
762 break;
763 }
764 }
765 }
766
1613d6b4 767 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
79514d47 768 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 769 ca, channels, buf);
079d88cc 770
53d7d69d 771 return ca;
079d88cc
WF		 772}
773
774static void hdmi_debug_channel_mapping(struct hda_codec *codec,
775 hda_nid_t pin_nid)
776{
777#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 778 struct hdmi_spec *spec = codec->spec;
079d88cc 779 int i;
307229d2 780 int channel;
079d88cc
WF		 781
782 for (i = 0; i < 8; i++) {
307229d2 783 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 784 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 785 channel, i);
079d88cc
WF		 786 }
787#endif
788}
789
d45e6889 790static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 791 hda_nid_t pin_nid,
433968da 792 bool non_pcm,
53d7d69d 793 int ca)
079d88cc 794{
307229d2 795 struct hdmi_spec *spec = codec->spec;
90f28002 796 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 797 int i;
079d88cc 798 int err;
72357c78 799 int order;
433968da 800 int non_pcm_mapping[8];
079d88cc 801
72357c78 802 order = get_channel_allocation_order(ca);
90f28002 803 ch_alloc = &channel_allocations[order];
433968da 804
079d88cc 805 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 806 int hdmi_slot = 0;
807 /* fill actual channel mappings in ALSA channel (i) order */
808 for (i = 0; i < ch_alloc->channels; i++) {
809 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
810 hdmi_slot++; /* skip zero slots */
811
812 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
813 }
814 /* fill the rest of the slots with ALSA channel 0xf */
815 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
816 if (!ch_alloc->speakers[7 - hdmi_slot])
817 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 818 }
819
433968da 820 if (non_pcm) {
90f28002 821 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 822 non_pcm_mapping[i] = (i << 4) | i;
433968da 823 for (; i < 8; i++)
11f7c52d 824 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 825 }
826
079d88cc 827 for (i = 0; i < 8; i++) {
307229d2
AH		 828 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
829 int hdmi_slot = slotsetup & 0x0f;
830 int channel = (slotsetup & 0xf0) >> 4;
831 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 832 if (err) {
4e76a883 833 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 834 break;
835 }
836 }
079d88cc
WF		 837}
838
d45e6889
TI		 839struct channel_map_table {
840 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 841 int spk_mask; /* speaker position bit mask */
842};
843
844static struct channel_map_table map_tables[] = {
a5b7d510
AH		 845 { SNDRV_CHMAP_FL, FL },
846 { SNDRV_CHMAP_FR, FR },
847 { SNDRV_CHMAP_RL, RL },
848 { SNDRV_CHMAP_RR, RR },
849 { SNDRV_CHMAP_LFE, LFE },
850 { SNDRV_CHMAP_FC, FC },
851 { SNDRV_CHMAP_RLC, RLC },
852 { SNDRV_CHMAP_RRC, RRC },
853 { SNDRV_CHMAP_RC, RC },
854 { SNDRV_CHMAP_FLC, FLC },
855 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 856 { SNDRV_CHMAP_TFL, FLH },
857 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 858 { SNDRV_CHMAP_FLW, FLW },
859 { SNDRV_CHMAP_FRW, FRW },
860 { SNDRV_CHMAP_TC, TC },
94908a39 861 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 862 {} /* terminator */
863};
864
865/* from ALSA API channel position to speaker bit mask */
866static int to_spk_mask(unsigned char c)
867{
868 struct channel_map_table *t = map_tables;
869 for (; t->map; t++) {
870 if (t->map == c)
871 return t->spk_mask;
872 }
873 return 0;
874}
875
876/* from ALSA API channel position to CEA slot */
a5b7d510 877static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 878{
a5b7d510
AH		 879 int mask = to_spk_mask(pos);
880 int i;
d45e6889 881
a5b7d510
AH		 882 if (mask) {
883 for (i = 0; i < 8; i++) {
884 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
885 return i;
886 }
d45e6889 887 }
a5b7d510
AH		 888
889 return -1;
d45e6889
TI		 890}
891
892/* from speaker bit mask to ALSA API channel position */
893static int spk_to_chmap(int spk)
894{
895 struct channel_map_table *t = map_tables;
896 for (; t->map; t++) {
897 if (t->spk_mask == spk)
898 return t->map;
899 }
900 return 0;
901}
902
a5b7d510
AH		 903/* from CEA slot to ALSA API channel position */
904static int from_cea_slot(int ordered_ca, unsigned char slot)
905{
906 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
907
908 return spk_to_chmap(mask);
909}
910
d45e6889
TI		 911/* get the CA index corresponding to the given ALSA API channel map */
912static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
913{
914 int i, spks = 0, spk_mask = 0;
915
916 for (i = 0; i < chs; i++) {
917 int mask = to_spk_mask(map[i]);
918 if (mask) {
919 spk_mask |= mask;
920 spks++;
921 }
922 }
923
924 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
925 if ((chs == channel_allocations[i].channels ||
926 spks == channel_allocations[i].channels) &&
927 (spk_mask & channel_allocations[i].spk_mask) ==
928 channel_allocations[i].spk_mask)
929 return channel_allocations[i].ca_index;
930 }
931 return -1;
932}
933
934/* set up the channel slots for the given ALSA API channel map */
935static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
936 hda_nid_t pin_nid,
a5b7d510
AH		 937 int chs, unsigned char *map,
938 int ca)
d45e6889 939{
307229d2 940 struct hdmi_spec *spec = codec->spec;
a5b7d510 941 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 942 int alsa_pos, hdmi_slot;
943 int assignments[8] = {[0 ... 7] = 0xf};
944
945 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
946
a5b7d510 947 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 948
949 if (hdmi_slot < 0)
950 continue; /* unassigned channel */
951
952 assignments[hdmi_slot] = alsa_pos;
953 }
954
955 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 956 int err;
11f7c52d 957
307229d2
AH		 958 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
959 assignments[hdmi_slot]);
d45e6889
TI		 960 if (err)
961 return -EINVAL;
962 }
963 return 0;
964}
965
966/* store ALSA API channel map from the current default map */
967static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
968{
969 int i;
56cac413 970 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 971 for (i = 0; i < 8; i++) {
56cac413 972 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 973 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 974 else
975 map[i] = 0;
976 }
977}
978
979static void hdmi_setup_channel_mapping(struct hda_codec *codec,
980 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 981 int channels, unsigned char *map,
982 bool chmap_set)
d45e6889 983{
20608731 984 if (!non_pcm && chmap_set) {
d45e6889 985 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 986 channels, map, ca);
d45e6889
TI		 987 } else {
988 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
989 hdmi_setup_fake_chmap(map, ca);
990 }
980b2495
AH		 991
992 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 993}
079d88cc 994
307229d2
AH		 995static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
996 int asp_slot, int channel)
997{
998 return snd_hda_codec_write(codec, pin_nid, 0,
999 AC_VERB_SET_HDMI_CHAN_SLOT,
1000 (channel << 4) | asp_slot);
1001}
1002
1003static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
1004 int asp_slot)
1005{
1006 return (snd_hda_codec_read(codec, pin_nid, 0,
1007 AC_VERB_GET_HDMI_CHAN_SLOT,
1008 asp_slot) & 0xf0) >> 4;
1009}
1010
079d88cc
WF		 1011/*
1012 * Audio InfoFrame routines
1013 */
1014
1015/*
1016 * Enable Audio InfoFrame Transmission
1017 */
1018static void hdmi_start_infoframe_trans(struct hda_codec *codec,
1019 hda_nid_t pin_nid)
1020{
1021 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1022 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
1023 AC_DIPXMIT_BEST);
1024}
1025
1026/*
1027 * Disable Audio InfoFrame Transmission
1028 */
1029static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
1030 hda_nid_t pin_nid)
1031{
1032 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1033 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
1034 AC_DIPXMIT_DISABLE);
1035}
1036
1037static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
1038{
1039#ifdef CONFIG_SND_DEBUG_VERBOSE
1040 int i;
1041 int size;
1042
1043 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 1044 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 1045
1046 for (i = 0; i < 8; i++) {
1047 size = snd_hda_codec_read(codec, pin_nid, 0,
1048 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 1049 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 1050 }
1051#endif
1052}
1053
1054static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
1055{
1056#ifdef BE_PARANOID
1057 int i, j;
1058 int size;
1059 int pi, bi;
1060 for (i = 0; i < 8; i++) {
1061 size = snd_hda_codec_read(codec, pin_nid, 0,
1062 AC_VERB_GET_HDMI_DIP_SIZE, i);
1063 if (size == 0)
1064 continue;
1065
1066 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1067 for (j = 1; j < 1000; j++) {
1068 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1069 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1070 if (pi != i)
4e76a883 1071 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1072 bi, pi, i);
1073 if (bi == 0) /* byte index wrapped around */
1074 break;
1075 }
4e76a883 1076 codec_dbg(codec,
079d88cc
WF		 1077 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1078 i, size, j);
1079 }
1080#endif
1081}
1082
53d7d69d 1083static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1084{
53d7d69d 1085 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1086 u8 sum = 0;
1087 int i;
1088
53d7d69d 1089 hdmi_ai->checksum = 0;
079d88cc 1090
53d7d69d 1091 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1092 sum += bytes[i];
1093
53d7d69d 1094 hdmi_ai->checksum = -sum;
079d88cc
WF		 1095}
1096
1097static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1098 hda_nid_t pin_nid,
53d7d69d 1099 u8 *dip, int size)
079d88cc 1100{
079d88cc
WF		 1101 int i;
1102
1103 hdmi_debug_dip_size(codec, pin_nid);
1104 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1105
079d88cc 1106 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1107 for (i = 0; i < size; i++)
1108 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1109}
1110
1111static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1112 u8 *dip, int size)
079d88cc 1113{
079d88cc
WF		 1114 u8 val;
1115 int i;
1116
1117 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1118 != AC_DIPXMIT_BEST)
1119 return false;
1120
1121 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1122 for (i = 0; i < size; i++) {
079d88cc
WF		 1123 val = snd_hda_codec_read(codec, pin_nid, 0,
1124 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1125 if (val != dip[i])
079d88cc
WF		 1126 return false;
1127 }
1128
1129 return true;
1130}
1131
307229d2
AH		 1132static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1133 hda_nid_t pin_nid,
1134 int ca, int active_channels,
1135 int conn_type)
1136{
1137 union audio_infoframe ai;
1138
caaf5ef9 1139 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1140 if (conn_type == 0) { /* HDMI */
1141 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1142
1143 hdmi_ai->type = 0x84;
1144 hdmi_ai->ver = 0x01;
1145 hdmi_ai->len = 0x0a;
1146 hdmi_ai->CC02_CT47 = active_channels - 1;
1147 hdmi_ai->CA = ca;
1148 hdmi_checksum_audio_infoframe(hdmi_ai);
1149 } else if (conn_type == 1) { /* DisplayPort */
1150 struct dp_audio_infoframe *dp_ai = &ai.dp;
1151
1152 dp_ai->type = 0x84;
1153 dp_ai->len = 0x1b;
1154 dp_ai->ver = 0x11 << 2;
1155 dp_ai->CC02_CT47 = active_channels - 1;
1156 dp_ai->CA = ca;
1157 } else {
4e76a883 1158 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1159 pin_nid);
1160 return;
1161 }
1162
1163 /*
1164 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1165 * sizeof(*dp_ai) to avoid partial match/update problems when
1166 * the user switches between HDMI/DP monitors.
1167 */
1168 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1169 sizeof(ai))) {
4e76a883
TI		 1170 codec_dbg(codec,
1171 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1172 pin_nid,
1173 active_channels, ca);
1174 hdmi_stop_infoframe_trans(codec, pin_nid);
1175 hdmi_fill_audio_infoframe(codec, pin_nid,
1176 ai.bytes, sizeof(ai));
1177 hdmi_start_infoframe_trans(codec, pin_nid);
1178 }
1179}
1180
b054087d
TI		 1181static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1182 struct hdmi_spec_per_pin *per_pin,
1183 bool non_pcm)
079d88cc 1184{
307229d2 1185 struct hdmi_spec *spec = codec->spec;
384a48d7 1186 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1187 int channels = per_pin->channels;
1df5a06a 1188 int active_channels;
384a48d7 1189 struct hdmi_eld *eld;
1df5a06a 1190 int ca, ordered_ca;
079d88cc 1191
b054087d
TI		 1192 if (!channels)
1193 return;
1194
75dcbe4d 1195 if (is_haswell_plus(codec))
58f7d28d
ML		 1196 snd_hda_codec_write(codec, pin_nid, 0,
1197 AC_VERB_SET_AMP_GAIN_MUTE,
1198 AMP_OUT_UNMUTE);
1199
bce0d2a8 1200 eld = &per_pin->sink_eld;
079d88cc 1201
d45e6889
TI		 1202 if (!non_pcm && per_pin->chmap_set)
1203 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1204 else
79514d47 1205 ca = hdmi_channel_allocation(codec, eld, channels);
d45e6889
TI		 1206 if (ca < 0)
1207 ca = 0;
384a48d7 1208
1df5a06a
AH		 1209 ordered_ca = get_channel_allocation_order(ca);
1210 active_channels = channel_allocations[ordered_ca].channels;
1211
1212 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1213
39edac70
AH		 1214 /*
1215 * always configure channel mapping, it may have been changed by the
1216 * user in the meantime
1217 */
1218 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1219 channels, per_pin->chmap,
1220 per_pin->chmap_set);
1221
307229d2
AH		 1222 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1223 eld->info.conn_type);
433968da 1224
1a6003b5 1225 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1226}
1227
079d88cc
WF		 1228/*
1229 * Unsolicited events
1230 */
1231
efe47108 1232static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1233
1a4f69d5 1234static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 1235{
1236 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 1237 int pin_idx = pin_nid_to_pin_index(codec, nid);
1238
20ce9029
DH		 1239 if (pin_idx < 0)
1240 return;
20ce9029
DH		 1241 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1242 snd_hda_jack_report_sync(codec);
1243}
1244
1a4f69d5
TI		 1245static void jack_callback(struct hda_codec *codec,
1246 struct hda_jack_callback *jack)
1247{
2ebab40e 1248 check_presence_and_report(codec, jack->nid);
1a4f69d5
TI		 1249}
1250
20ce9029
DH		 1251static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1252{
3a93897e 1253 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1254 struct hda_jack_tbl *jack;
2e59e5ab 1255 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1256
1257 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1258 if (!jack)
1259 return;
3a93897e 1260 jack->jack_dirty = 1;
079d88cc 1261
4e76a883 1262 codec_dbg(codec,
2e59e5ab 1263 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1264 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1265 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1266
1a4f69d5 1267 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 1268}
1269
1270static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1271{
1272 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1273 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1274 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1275 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1276
4e76a883 1277 codec_info(codec,
e9ea8e8f 1278 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1279 codec->addr,
079d88cc
WF		 1280 tag,
1281 subtag,
1282 cp_state,
1283 cp_ready);
1284
1285 /* TODO */
1286 if (cp_state)
1287 ;
1288 if (cp_ready)
1289 ;
1290}
1291
1292
1293static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1294{
079d88cc
WF		 1295 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1296 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1297
3a93897e 1298 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1299 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1300 return;
1301 }
1302
1303 if (subtag == 0)
1304 hdmi_intrinsic_event(codec, res);
1305 else
1306 hdmi_non_intrinsic_event(codec, res);
1307}
1308
58f7d28d 1309static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1310 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1311{
58f7d28d 1312 int pwr;
83f26ad2 1313
53b434f0
WX		 1314 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1315 * thus pins could only choose converter 0 for use. Make sure the
1316 * converters are in correct power state */
fd678cac 1317 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1318 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1319
fd678cac 1320 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1321 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1322 AC_PWRST_D0);
1323 msleep(40);
1324 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1325 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1326 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1327 }
83f26ad2
DH		 1328}
1329
079d88cc
WF		 1330/*
1331 * Callbacks
1332 */
1333
92f10b3f
TI		 1334/* HBR should be Non-PCM, 8 channels */
1335#define is_hbr_format(format) \
1336 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1337
307229d2
AH		 1338static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1339 bool hbr)
079d88cc 1340{
307229d2 1341 int pinctl, new_pinctl;
83f26ad2 1342
384a48d7
SW		 1343 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1344 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1345 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1346
13122e6e
AH		 1347 if (pinctl < 0)
1348 return hbr ? -EINVAL : 0;
1349
ea87d1c4 1350 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1351 if (hbr)
ea87d1c4
AH		 1352 new_pinctl |= AC_PINCTL_EPT_HBR;
1353 else
1354 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1355
4e76a883
TI		 1356 codec_dbg(codec,
1357 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1358 pin_nid,
ea87d1c4
AH		 1359 pinctl == new_pinctl ? "" : "new-",
1360 new_pinctl);
1361
1362 if (pinctl != new_pinctl)
384a48d7 1363 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1364 AC_VERB_SET_PIN_WIDGET_CONTROL,
1365 new_pinctl);
307229d2
AH		 1366 } else if (hbr)
1367 return -EINVAL;
ea87d1c4 1368
307229d2
AH		 1369 return 0;
1370}
1371
1372static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1373 hda_nid_t pin_nid, u32 stream_tag, int format)
1374{
1375 struct hdmi_spec *spec = codec->spec;
1376 int err;
1377
75dcbe4d 1378 if (is_haswell_plus(codec))
307229d2
AH		 1379 haswell_verify_D0(codec, cvt_nid, pin_nid);
1380
1381 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1382
1383 if (err) {
4e76a883 1384 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1385 return err;
ea87d1c4 1386 }
079d88cc 1387
384a48d7 1388 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1389 return 0;
079d88cc
WF		 1390}
1391
42b29870
LY		 1392/* Try to find an available converter
1393 * If pin_idx is less then zero, just try to find an available converter.
1394 * Otherwise, try to find an available converter and get the cvt mux index
1395 * of the pin.
1396 */
7ef166b8
WX		 1397static int hdmi_choose_cvt(struct hda_codec *codec,
1398 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1399{
1400 struct hdmi_spec *spec = codec->spec;
384a48d7 1401 struct hdmi_spec_per_pin *per_pin;
384a48d7 1402 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1403 int cvt_idx, mux_idx = 0;
bbbe3390 1404
42b29870
LY		 1405 /* pin_idx < 0 means no pin will be bound to the converter */
1406 if (pin_idx < 0)
1407 per_pin = NULL;
1408 else
1409 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1410
1411 /* Dynamically assign converter to stream */
1412 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1413 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1414
384a48d7
SW		 1415 /* Must not already be assigned */
1416 if (per_cvt->assigned)
1417 continue;
42b29870
LY		 1418 if (per_pin == NULL)
1419 break;
384a48d7
SW		 1420 /* Must be in pin's mux's list of converters */
1421 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1422 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1423 break;
1424 /* Not in mux list */
1425 if (mux_idx == per_pin->num_mux_nids)
1426 continue;
1427 break;
1428 }
7ef166b8 1429
384a48d7
SW		 1430 /* No free converters */
1431 if (cvt_idx == spec->num_cvts)
42b29870 1432 return -EBUSY;
384a48d7 1433
42b29870
LY		 1434 if (per_pin != NULL)
1435 per_pin->mux_idx = mux_idx;
2df6742f 1436
7ef166b8
WX		 1437 if (cvt_id)
1438 *cvt_id = cvt_idx;
1439 if (mux_id)
1440 *mux_id = mux_idx;
1441
1442 return 0;
1443}
1444
2df6742f
ML		 1445/* Assure the pin select the right convetor */
1446static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1447 struct hdmi_spec_per_pin *per_pin)
1448{
1449 hda_nid_t pin_nid = per_pin->pin_nid;
1450 int mux_idx, curr;
1451
1452 mux_idx = per_pin->mux_idx;
1453 curr = snd_hda_codec_read(codec, pin_nid, 0,
1454 AC_VERB_GET_CONNECT_SEL, 0);
1455 if (curr != mux_idx)
1456 snd_hda_codec_write_cache(codec, pin_nid, 0,
1457 AC_VERB_SET_CONNECT_SEL,
1458 mux_idx);
1459}
1460
42b29870
LY		 1461/* get the mux index for the converter of the pins
1462 * converter's mux index is the same for all pins on Intel platform
1463 */
1464static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1465 hda_nid_t cvt_nid)
1466{
1467 int i;
1468
1469 for (i = 0; i < spec->num_cvts; i++)
1470 if (spec->cvt_nids[i] == cvt_nid)
1471 return i;
1472 return -EINVAL;
1473}
1474
300016b9
ML		 1475/* Intel HDMI workaround to fix audio routing issue:
1476 * For some Intel display codecs, pins share the same connection list.
1477 * So a conveter can be selected by multiple pins and playback on any of these
1478 * pins will generate sound on the external display, because audio flows from
1479 * the same converter to the display pipeline. Also muting one pin may make
1480 * other pins have no sound output.
1481 * So this function assures that an assigned converter for a pin is not selected
1482 * by any other pins.
1483 */
1484static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1485 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1486{
1487 struct hdmi_spec *spec = codec->spec;
7639a06c 1488 hda_nid_t nid;
f82d7d16
ML		 1489 int cvt_idx, curr;
1490 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1491
f82d7d16 1492 /* configure all pins, including "no physical connection" ones */
7639a06c 1493 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 1494 unsigned int wid_caps = get_wcaps(codec, nid);
1495 unsigned int wid_type = get_wcaps_type(wid_caps);
1496
1497 if (wid_type != AC_WID_PIN)
1498 continue;
7ef166b8 1499
f82d7d16 1500 if (nid == pin_nid)
7ef166b8
WX		 1501 continue;
1502
f82d7d16 1503 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1504 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1505 if (curr != mux_idx)
1506 continue;
7ef166b8 1507
f82d7d16
ML		 1508 /* choose an unassigned converter. The conveters in the
1509 * connection list are in the same order as in the codec.
1510 */
1511 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1512 per_cvt = get_cvt(spec, cvt_idx);
1513 if (!per_cvt->assigned) {
4e76a883
TI		 1514 codec_dbg(codec,
1515 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1516 cvt_idx, nid);
1517 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1518 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1519 cvt_idx);
1520 break;
1521 }
7ef166b8
WX		 1522 }
1523 }
1524}
1525
42b29870
LY		 1526/* A wrapper of intel_not_share_asigned_cvt() */
1527static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1528 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1529{
1530 int mux_idx;
1531 struct hdmi_spec *spec = codec->spec;
1532
1533 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1534 return;
1535
1536 /* On Intel platform, the mapping of converter nid to
1537 * mux index of the pins are always the same.
1538 * The pin nid may be 0, this means all pins will not
1539 * share the converter.
1540 */
1541 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1542 if (mux_idx >= 0)
1543 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1544}
1545
1546/* called in hdmi_pcm_open when no pin is assigned to the PCM
1547 * in dyn_pcm_assign mode.
1548 */
1549static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1550 struct hda_codec *codec,
1551 struct snd_pcm_substream *substream)
1552{
1553 struct hdmi_spec *spec = codec->spec;
1554 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1555 int cvt_idx, pcm_idx;
42b29870
LY		 1556 struct hdmi_spec_per_cvt *per_cvt = NULL;
1557 int err;
1558
ac98379a
LY		 1559 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1560 if (pcm_idx < 0)
1561 return -EINVAL;
1562
42b29870
LY		 1563 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1564 if (err)
1565 return err;
1566
1567 per_cvt = get_cvt(spec, cvt_idx);
1568 per_cvt->assigned = 1;
1569 hinfo->nid = per_cvt->cvt_nid;
1570
1571 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1572
ac98379a 1573 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1574 /* todo: setup spdif ctls assign */
1575
1576 /* Initially set the converter's capabilities */
1577 hinfo->channels_min = per_cvt->channels_min;
1578 hinfo->channels_max = per_cvt->channels_max;
1579 hinfo->rates = per_cvt->rates;
1580 hinfo->formats = per_cvt->formats;
1581 hinfo->maxbps = per_cvt->maxbps;
1582
1583 /* Store the updated parameters */
1584 runtime->hw.channels_min = hinfo->channels_min;
1585 runtime->hw.channels_max = hinfo->channels_max;
1586 runtime->hw.formats = hinfo->formats;
1587 runtime->hw.rates = hinfo->rates;
1588
1589 snd_pcm_hw_constraint_step(substream->runtime, 0,
1590 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1591 return 0;
1592}
1593
7ef166b8
WX		 1594/*
1595 * HDA PCM callbacks
1596 */
1597static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1598 struct hda_codec *codec,
1599 struct snd_pcm_substream *substream)
1600{
1601 struct hdmi_spec *spec = codec->spec;
1602 struct snd_pcm_runtime *runtime = substream->runtime;
2bf3c85a 1603 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
7ef166b8
WX		 1604 struct hdmi_spec_per_pin *per_pin;
1605 struct hdmi_eld *eld;
1606 struct hdmi_spec_per_cvt *per_cvt = NULL;
1607 int err;
1608
1609 /* Validate hinfo */
2bf3c85a
LY		 1610 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1611 if (pcm_idx < 0)
7ef166b8 1612 return -EINVAL;
2bf3c85a 1613
42b29870 1614 mutex_lock(&spec->pcm_lock);
4e76a883 1615 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1616 if (!spec->dyn_pcm_assign) {
1617 if (snd_BUG_ON(pin_idx < 0)) {
1618 mutex_unlock(&spec->pcm_lock);
1619 return -EINVAL;
1620 }
1621 } else {
1622 /* no pin is assigned to the PCM
1623 * PA need pcm open successfully when probe
1624 */
1625 if (pin_idx < 0) {
1626 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1627 mutex_unlock(&spec->pcm_lock);
1628 return err;
1629 }
1630 }
7ef166b8
WX		 1631
1632 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
42b29870
LY		 1633 if (err < 0) {
1634 mutex_unlock(&spec->pcm_lock);
7ef166b8 1635 return err;
42b29870 1636 }
7ef166b8
WX		 1637
1638 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1639 /* Claim converter */
1640 per_cvt->assigned = 1;
42b29870 1641
ac98379a 1642 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1643 per_pin = get_pin(spec, pin_idx);
1df5a06a 1644 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1645 hinfo->nid = per_cvt->cvt_nid;
1646
bddee96b 1647 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1648 AC_VERB_SET_CONNECT_SEL,
1649 mux_idx);
7ef166b8
WX		 1650
1651 /* configure unused pins to choose other converters */
ca2e7224 1652 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
300016b9 1653 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1654
2bf3c85a 1655 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1656
2def8172 1657 /* Initially set the converter's capabilities */
384a48d7
SW		 1658 hinfo->channels_min = per_cvt->channels_min;
1659 hinfo->channels_max = per_cvt->channels_max;
1660 hinfo->rates = per_cvt->rates;
1661 hinfo->formats = per_cvt->formats;
1662 hinfo->maxbps = per_cvt->maxbps;
2def8172 1663
42b29870 1664 eld = &per_pin->sink_eld;
384a48d7 1665 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1666 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1667 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1668 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1669 !hinfo->rates || !hinfo->formats) {
1670 per_cvt->assigned = 0;
1671 hinfo->nid = 0;
2bf3c85a 1672 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
42b29870 1673 mutex_unlock(&spec->pcm_lock);
bbbe3390 1674 return -ENODEV;
2ad779b7 1675 }
bbbe3390 1676 }
2def8172 1677
42b29870 1678 mutex_unlock(&spec->pcm_lock);
2def8172 1679 /* Store the updated parameters */
639cef0e
TI		 1680 runtime->hw.channels_min = hinfo->channels_min;
1681 runtime->hw.channels_max = hinfo->channels_max;
1682 runtime->hw.formats = hinfo->formats;
1683 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1684
1685 snd_pcm_hw_constraint_step(substream->runtime, 0,
1686 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1687 return 0;
1688}
1689
079d88cc
WF		 1690/*
1691 * HDA/HDMI auto parsing
1692 */
384a48d7 1693static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1694{
1695 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1696 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1697 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1698
1699 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1700 codec_warn(codec,
1701 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1702 pin_nid, get_wcaps(codec, pin_nid));
1703 return -EINVAL;
1704 }
1705
384a48d7
SW		 1706 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1707 per_pin->mux_nids,
1708 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1709
1710 return 0;
1711}
1712
a76056f2
LY		 1713static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1714 struct hdmi_spec_per_pin *per_pin)
1715{
1716 int i;
1717
1718 /* try the prefer PCM */
1719 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1720 return per_pin->pin_nid_idx;
1721
1722 /* have a second try; check the "reserved area" over num_pins */
1723 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1724 if (!test_bit(i, &spec->pcm_bitmap))
1725 return i;
1726 }
1727
1728 /* the last try; check the empty slots in pins */
1729 for (i = 0; i < spec->num_pins; i++) {
1730 if (!test_bit(i, &spec->pcm_bitmap))
1731 return i;
1732 }
1733 return -EBUSY;
1734}
1735
1736static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1737 struct hdmi_spec_per_pin *per_pin)
1738{
1739 int idx;
1740
1741 /* pcm already be attached to the pin */
1742 if (per_pin->pcm)
1743 return;
1744 idx = hdmi_find_pcm_slot(spec, per_pin);
d10a80de 1745 if (idx == -EBUSY)
a76056f2
LY		 1746 return;
1747 per_pin->pcm_idx = idx;
2bea241a 1748 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1749 set_bit(idx, &spec->pcm_bitmap);
1750}
1751
1752static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1753 struct hdmi_spec_per_pin *per_pin)
1754{
1755 int idx;
1756
1757 /* pcm already be detached from the pin */
1758 if (!per_pin->pcm)
1759 return;
1760 idx = per_pin->pcm_idx;
1761 per_pin->pcm_idx = -1;
1762 per_pin->pcm = NULL;
1763 if (idx >= 0 && idx < spec->pcm_used)
1764 clear_bit(idx, &spec->pcm_bitmap);
1765}
1766
ac98379a
LY		 1767static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1768 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1769{
1770 int mux_idx;
1771
1772 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1773 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1774 break;
1775 return mux_idx;
1776}
1777
1778static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1779
1780static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1781 struct hdmi_spec_per_pin *per_pin)
1782{
1783 struct hda_codec *codec = per_pin->codec;
1784 struct hda_pcm *pcm;
1785 struct hda_pcm_stream *hinfo;
1786 struct snd_pcm_substream *substream;
1787 int mux_idx;
1788 bool non_pcm;
1789
1790 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1791 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1792 else
1793 return;
1794 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1795 return;
1796
1797 /* hdmi audio only uses playback and one substream */
1798 hinfo = pcm->stream;
1799 substream = pcm->pcm->streams[0].substream;
1800
1801 per_pin->cvt_nid = hinfo->nid;
1802
1803 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1804 if (mux_idx < per_pin->num_mux_nids)
1805 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1806 AC_VERB_SET_CONNECT_SEL,
1807 mux_idx);
1808 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1809
1810 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1811 if (substream->runtime)
1812 per_pin->channels = substream->runtime->channels;
1813 per_pin->setup = true;
1814 per_pin->mux_idx = mux_idx;
1815
1816 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1817}
1818
1819static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1820 struct hdmi_spec_per_pin *per_pin)
1821{
1822 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1823 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1824
1825 per_pin->chmap_set = false;
1826 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1827
1828 per_pin->setup = false;
1829 per_pin->channels = 0;
1830}
1831
e90247f9
TI		 1832/* update per_pin ELD from the given new ELD;
1833 * setup info frame and notification accordingly
1834 */
1835static void update_eld(struct hda_codec *codec,
1836 struct hdmi_spec_per_pin *per_pin,
1837 struct hdmi_eld *eld)
1838{
1839 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1840 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1841 bool old_eld_valid = pin_eld->eld_valid;
1842 bool eld_changed;
fb087eaa 1843 int pcm_idx = -1;
e90247f9 1844
fb087eaa
LY		 1845 /* for monitor disconnection, save pcm_idx firstly */
1846 pcm_idx = per_pin->pcm_idx;
a76056f2 1847 if (spec->dyn_pcm_assign) {
ac98379a 1848 if (eld->eld_valid) {
a76056f2 1849 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1850 hdmi_pcm_setup_pin(spec, per_pin);
1851 } else {
1852 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1853 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1854 }
a76056f2 1855 }
fb087eaa
LY		 1856 /* if pcm_idx == -1, it means this is in monitor connection event
1857 * we can get the correct pcm_idx now.
1858 */
1859 if (pcm_idx == -1)
1860 pcm_idx = per_pin->pcm_idx;
a76056f2 1861
e90247f9
TI		 1862 if (eld->eld_valid)
1863 snd_hdmi_show_eld(codec, &eld->info);
1864
1865 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1866 if (eld->eld_valid && pin_eld->eld_valid)
1867 if (pin_eld->eld_size != eld->eld_size ||
1868 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1869 eld->eld_size) != 0)
1870 eld_changed = true;
1871
1872 pin_eld->eld_valid = eld->eld_valid;
1873 pin_eld->eld_size = eld->eld_size;
1874 if (eld->eld_valid)
1875 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1876 pin_eld->info = eld->info;
1877
1878 /*
1879 * Re-setup pin and infoframe. This is needed e.g. when
1880 * - sink is first plugged-in
1881 * - transcoder can change during stream playback on Haswell
1882 * and this can make HW reset converter selection on a pin.
1883 */
1884 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1885 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1886 intel_verify_pin_cvt_connect(codec, per_pin);
1887 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1888 per_pin->mux_idx);
1889 }
1890
1891 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1892 }
1893
fb087eaa 1894 if (eld_changed && pcm_idx >= 0)
e90247f9
TI		 1895 snd_ctl_notify(codec->card,
1896 SNDRV_CTL_EVENT_MASK_VALUE |
1897 SNDRV_CTL_EVENT_MASK_INFO,
fb087eaa 1898 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
e90247f9
TI		 1899}
1900
788d441a
TI		 1901/* update ELD and jack state via HD-audio verbs */
1902static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1903 int repoll)
079d88cc 1904{
464837a7 1905 struct hda_jack_tbl *jack;
744626da 1906 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1907 struct hdmi_spec *spec = codec->spec;
1908 struct hdmi_eld *eld = &spec->temp_eld;
1909 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1910 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1911 /*
1912 * Always execute a GetPinSense verb here, even when called from
1913 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1914 * response's PD bit is not the real PD value, but indicates that
1915 * the real PD value changed. An older version of the HD-audio
1916 * specification worked this way. Hence, we just ignore the data in
1917 * the unsolicited response to avoid custom WARs.
1918 */
da4a7a39 1919 int present;
efe47108 1920 bool ret;
9a5e5234 1921 bool do_repoll = false;
079d88cc 1922
664c7155 1923 snd_hda_power_up_pm(codec);
da4a7a39
DH		 1924 present = snd_hda_pin_sense(codec, pin_nid);
1925
a4e9a38b 1926 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1927 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1928 if (pin_eld->monitor_present)
1929 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1930 else
1931 eld->eld_valid = false;
079d88cc 1932
4e76a883 1933 codec_dbg(codec,
384a48d7 1934 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1935 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1936
4bd038f9 1937 if (eld->eld_valid) {
307229d2 1938 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1939 &eld->eld_size) < 0)
4bd038f9 1940 eld->eld_valid = false;
1613d6b4 1941 else {
79514d47 1942 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1943 eld->eld_size) < 0)
4bd038f9 1944 eld->eld_valid = false;
1613d6b4 1945 }
9a5e5234
TI		 1946 if (!eld->eld_valid && repoll)
1947 do_repoll = true;
744626da 1948 }
4bd038f9 1949
9a5e5234 1950 if (do_repoll)
e90247f9
TI		 1951 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1952 else
1953 update_eld(codec, per_pin, eld);
92c69e79 1954
aff747eb 1955 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1956
1957 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1958 if (jack)
1959 jack->block_report = !ret;
1960
a4e9a38b 1961 mutex_unlock(&per_pin->lock);
664c7155 1962 snd_hda_power_down_pm(codec);
efe47108 1963 return ret;
079d88cc
WF		 1964}
1965
3184270e
LY		 1966static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1967 struct hdmi_spec_per_pin *per_pin)
1968{
1969 struct hdmi_spec *spec = codec->spec;
1970 struct snd_jack *jack = NULL;
1971 struct hda_jack_tbl *jack_tbl;
1972
1973 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1974 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1975 * NULL even after snd_hda_jack_tbl_clear() is called to
1976 * free snd_jack. This may cause access invalid memory
1977 * when calling snd_jack_report
1978 */
1979 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1980 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1981 else if (!spec->dyn_pcm_assign) {
1982 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1983 if (jack_tbl)
1984 jack = jack_tbl->jack;
1985 }
1986 return jack;
1987}
1988
788d441a
TI		 1989/* update ELD and jack state via audio component */
1990static void sync_eld_via_acomp(struct hda_codec *codec,
1991 struct hdmi_spec_per_pin *per_pin)
1992{
788d441a
TI		 1993 struct hdmi_spec *spec = codec->spec;
1994 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1995 struct snd_jack *jack = NULL;
788d441a
TI		 1996 int size;
1997
e2dc7d7d
TI		 1998 mutex_lock(&per_pin->lock);
1999 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
2000 &eld->monitor_present, eld->eld_buffer,
2001 ELD_MAX_SIZE);
2002 if (size < 0)
2003 goto unlock;
2004 if (size > 0) {
2005 size = min(size, ELD_MAX_SIZE);
2006 if (snd_hdmi_parse_eld(codec, &eld->info,
2007 eld->eld_buffer, size) < 0)
2008 size = -EINVAL;
2009 }
788d441a 2010
e2dc7d7d
TI		 2011 if (size > 0) {
2012 eld->eld_valid = true;
2013 eld->eld_size = size;
2014 } else {
2015 eld->eld_valid = false;
2016 eld->eld_size = 0;
788d441a 2017 }
e2dc7d7d 2018
25e4abb3
LY		 2019 /* pcm_idx >=0 before update_eld() means it is in monitor
2020 * disconnected event. Jack must be fetched before update_eld()
2021 */
3184270e 2022 jack = pin_idx_to_jack(codec, per_pin);
e2dc7d7d 2023 update_eld(codec, per_pin, eld);
3184270e
LY		 2024 if (jack == NULL)
2025 jack = pin_idx_to_jack(codec, per_pin);
25e4abb3
LY		 2026 if (jack == NULL)
2027 goto unlock;
2028 snd_jack_report(jack,
e2dc7d7d
TI		 2029 eld->monitor_present ? SND_JACK_AVOUT : 0);
2030 unlock:
2031 mutex_unlock(&per_pin->lock);
788d441a
TI		 2032}
2033
2034static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
2035{
2036 struct hda_codec *codec = per_pin->codec;
a76056f2
LY		 2037 struct hdmi_spec *spec = codec->spec;
2038 int ret;
788d441a 2039
a76056f2 2040 mutex_lock(&spec->pcm_lock);
788d441a
TI		 2041 if (codec_has_acomp(codec)) {
2042 sync_eld_via_acomp(codec, per_pin);
a76056f2 2043 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 2044 } else {
a76056f2 2045 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
788d441a 2046 }
a76056f2
LY		 2047 mutex_unlock(&spec->pcm_lock);
2048
2049 return ret;
788d441a
TI		 2050}
2051
744626da
WF		 2052static void hdmi_repoll_eld(struct work_struct *work)
2053{
2054 struct hdmi_spec_per_pin *per_pin =
2055 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
2056
c6e8453e
WF		 2057 if (per_pin->repoll_count++ > 6)
2058 per_pin->repoll_count = 0;
2059
efe47108
TI		 2060 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
2061 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 2062}
2063
c88d4e84
TI		 2064static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2065 hda_nid_t nid);
2066
079d88cc
WF		 2067static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
2068{
2069 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2070 unsigned int caps, config;
2071 int pin_idx;
2072 struct hdmi_spec_per_pin *per_pin;
07acecc1 2073 int err;
079d88cc 2074
efc2f8de 2075 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 2076 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
2077 return 0;
2078
efc2f8de 2079 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 2080 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
2081 return 0;
2082
75dcbe4d 2083 if (is_haswell_plus(codec))
c88d4e84
TI		 2084 intel_haswell_fixup_connect_list(codec, pin_nid);
2085
384a48d7 2086 pin_idx = spec->num_pins;
bce0d2a8
TI		 2087 per_pin = snd_array_new(&spec->pins);
2088 if (!per_pin)
2089 return -ENOMEM;
384a48d7
SW		 2090
2091 per_pin->pin_nid = pin_nid;
1a6003b5 2092 per_pin->non_pcm = false;
a76056f2
LY		 2093 if (spec->dyn_pcm_assign)
2094 per_pin->pcm_idx = -1;
2bea241a
LY		 2095 else {
2096 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
a76056f2 2097 per_pin->pcm_idx = pin_idx;
2bea241a 2098 }
a76056f2 2099 per_pin->pin_nid_idx = pin_idx;
079d88cc 2100
384a48d7
SW		 2101 err = hdmi_read_pin_conn(codec, pin_idx);
2102 if (err < 0)
2103 return err;
079d88cc 2104
079d88cc
WF		 2105 spec->num_pins++;
2106
384a48d7 2107 return 0;
079d88cc
WF		 2108}
2109
384a48d7 2110static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 2111{
2112 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2113 struct hdmi_spec_per_cvt *per_cvt;
2114 unsigned int chans;
2115 int err;
079d88cc 2116
384a48d7
SW		 2117 chans = get_wcaps(codec, cvt_nid);
2118 chans = get_wcaps_channels(chans);
2119
bce0d2a8
TI		 2120 per_cvt = snd_array_new(&spec->cvts);
2121 if (!per_cvt)
2122 return -ENOMEM;
384a48d7
SW		 2123
2124 per_cvt->cvt_nid = cvt_nid;
2125 per_cvt->channels_min = 2;
d45e6889 2126 if (chans <= 16) {
384a48d7 2127 per_cvt->channels_max = chans;
67b90cb8
SP		 2128 if (chans > spec->chmap.channels_max)
2129 spec->chmap.channels_max = chans;
d45e6889 2130 }
384a48d7
SW		 2131
2132 err = snd_hda_query_supported_pcm(codec, cvt_nid,
2133 &per_cvt->rates,
2134 &per_cvt->formats,
2135 &per_cvt->maxbps);
2136 if (err < 0)
2137 return err;
2138
bce0d2a8
TI		 2139 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
2140 spec->cvt_nids[spec->num_cvts] = cvt_nid;
2141 spec->num_cvts++;
079d88cc
WF		 2142
2143 return 0;
2144}
2145
2146static int hdmi_parse_codec(struct hda_codec *codec)
2147{
2148 hda_nid_t nid;
2149 int i, nodes;
2150
7639a06c 2151 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 2152 if (!nid || nodes < 0) {
4e76a883 2153 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 2154 return -EINVAL;
2155 }
2156
2157 for (i = 0; i < nodes; i++, nid++) {
2158 unsigned int caps;
2159 unsigned int type;
2160
efc2f8de 2161 caps = get_wcaps(codec, nid);
079d88cc
WF		 2162 type = get_wcaps_type(caps);
2163
2164 if (!(caps & AC_WCAP_DIGITAL))
2165 continue;
2166
2167 switch (type) {
2168 case AC_WID_AUD_OUT:
384a48d7 2169 hdmi_add_cvt(codec, nid);
079d88cc
WF		 2170 break;
2171 case AC_WID_PIN:
3eaead57 2172 hdmi_add_pin(codec, nid);
079d88cc
WF		 2173 break;
2174 }
2175 }
2176
079d88cc
WF		 2177 return 0;
2178}
2179
84eb01be
TI		 2180/*
2181 */
1a6003b5
TI		 2182static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2183{
2184 struct hda_spdif_out *spdif;
2185 bool non_pcm;
2186
2187 mutex_lock(&codec->spdif_mutex);
2188 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2189 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2190 mutex_unlock(&codec->spdif_mutex);
2191 return non_pcm;
2192}
2193
84eb01be
TI		 2194/*
2195 * HDMI callbacks
2196 */
2197
2198static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2199 struct hda_codec *codec,
2200 unsigned int stream_tag,
2201 unsigned int format,
2202 struct snd_pcm_substream *substream)
2203{
384a48d7
SW		 2204 hda_nid_t cvt_nid = hinfo->nid;
2205 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 2206 int pin_idx;
2207 struct hdmi_spec_per_pin *per_pin;
2208 hda_nid_t pin_nid;
ddd621fb 2209 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 2210 bool non_pcm;
75fae117 2211 int pinctl;
42b29870 2212 int err;
1a6003b5 2213
42b29870
LY		 2214 mutex_lock(&spec->pcm_lock);
2215 pin_idx = hinfo_to_pin_index(codec, hinfo);
2216 if (spec->dyn_pcm_assign && pin_idx < 0) {
2217 /* when dyn_pcm_assign and pcm is not bound to a pin
2218 * skip pin setup and return 0 to make audio playback
2219 * be ongoing
2220 */
2221 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2222 snd_hda_codec_setup_stream(codec, cvt_nid,
2223 stream_tag, 0, format);
2224 mutex_unlock(&spec->pcm_lock);
2225 return 0;
2226 }
1a6003b5 2227
42b29870
LY		 2228 if (snd_BUG_ON(pin_idx < 0)) {
2229 mutex_unlock(&spec->pcm_lock);
2230 return -EINVAL;
2231 }
2232 per_pin = get_pin(spec, pin_idx);
2233 pin_nid = per_pin->pin_nid;
ca2e7224 2234 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2df6742f
ML		 2235 /* Verify pin:cvt selections to avoid silent audio after S3.
2236 * After S3, the audio driver restores pin:cvt selections
2237 * but this can happen before gfx is ready and such selection
2238 * is overlooked by HW. Thus multiple pins can share a same
2239 * default convertor and mute control will affect each other,
2240 * which can cause a resumed audio playback become silent
2241 * after S3.
2242 */
2243 intel_verify_pin_cvt_connect(codec, per_pin);
2244 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
2245 }
2246
ddd621fb
LY		 2247 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2248 /* Todo: add DP1.2 MST audio support later */
e2dc7d7d 2249 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
ddd621fb 2250
1a6003b5 2251 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 2252 mutex_lock(&per_pin->lock);
b054087d
TI		 2253 per_pin->channels = substream->runtime->channels;
2254 per_pin->setup = true;
384a48d7 2255
b054087d 2256 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 2257 mutex_unlock(&per_pin->lock);
75fae117
SW		 2258 if (spec->dyn_pin_out) {
2259 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
2260 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2261 snd_hda_codec_write(codec, pin_nid, 0,
2262 AC_VERB_SET_PIN_WIDGET_CONTROL,
2263 pinctl | PIN_OUT);
2264 }
2265
42b29870
LY		 2266 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
2267 stream_tag, format);
2268 mutex_unlock(&spec->pcm_lock);
2269 return err;
84eb01be
TI		 2270}
2271
8dfaa573
TI		 2272static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2273 struct hda_codec *codec,
2274 struct snd_pcm_substream *substream)
2275{
2276 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2277 return 0;
2278}
2279
f2ad24fa
TI		 2280static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2281 struct hda_codec *codec,
2282 struct snd_pcm_substream *substream)
384a48d7
SW		 2283{
2284 struct hdmi_spec *spec = codec->spec;
2bf3c85a 2285 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 2286 struct hdmi_spec_per_cvt *per_cvt;
2287 struct hdmi_spec_per_pin *per_pin;
75fae117 2288 int pinctl;
384a48d7 2289
384a48d7 2290 if (hinfo->nid) {
2bf3c85a
LY		 2291 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2292 if (snd_BUG_ON(pcm_idx < 0))
2293 return -EINVAL;
4e76a883 2294 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 2295 if (snd_BUG_ON(cvt_idx < 0))
2296 return -EINVAL;
bce0d2a8 2297 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 2298
2299 snd_BUG_ON(!per_cvt->assigned);
2300 per_cvt->assigned = 0;
2301 hinfo->nid = 0;
2302
42b29870 2303 mutex_lock(&spec->pcm_lock);
b09887f8 2304 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 2305 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 2306 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 2307 if (spec->dyn_pcm_assign && pin_idx < 0) {
2308 mutex_unlock(&spec->pcm_lock);
2309 return 0;
2310 }
2311
2312 if (snd_BUG_ON(pin_idx < 0)) {
2313 mutex_unlock(&spec->pcm_lock);
384a48d7 2314 return -EINVAL;
42b29870 2315 }
bce0d2a8 2316 per_pin = get_pin(spec, pin_idx);
384a48d7 2317
75fae117
SW		 2318 if (spec->dyn_pin_out) {
2319 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2320 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2321 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2322 AC_VERB_SET_PIN_WIDGET_CONTROL,
2323 pinctl & ~PIN_OUT);
2324 }
2325
a4e9a38b 2326 mutex_lock(&per_pin->lock);
d45e6889
TI		 2327 per_pin->chmap_set = false;
2328 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 2329
2330 per_pin->setup = false;
2331 per_pin->channels = 0;
a4e9a38b 2332 mutex_unlock(&per_pin->lock);
42b29870 2333 mutex_unlock(&spec->pcm_lock);
384a48d7 2334 }
d45e6889 2335
384a48d7
SW		 2336 return 0;
2337}
2338
2339static const struct hda_pcm_ops generic_ops = {
2340 .open = hdmi_pcm_open,
f2ad24fa 2341 .close = hdmi_pcm_close,
384a48d7 2342 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2343 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2344};
2345
d45e6889
TI		 2346/*
2347 * ALSA API channel-map control callbacks
2348 */
2349static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
2350 struct snd_ctl_elem_info *uinfo)
2351{
2352 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2353 struct hda_codec *codec = info->private_data;
2354 struct hdmi_spec *spec = codec->spec;
67b90cb8
SP		 2355 struct hdac_chmap *chmap = &spec->chmap;
2356
d45e6889 2357 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
67b90cb8 2358 uinfo->count = chmap->channels_max;
d45e6889
TI		 2359 uinfo->value.integer.min = 0;
2360 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
2361 return 0;
2362}
2363
67b90cb8
SP		 2364static int hdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
2365 struct cea_channel_speaker_allocation *cap, int channels)
307229d2
AH		 2366{
2367 /* If the speaker allocation matches the channel count, it is OK.*/
2368 if (cap->channels != channels)
2369 return -1;
2370
2371 /* all channels are remappable freely */
2372 return SNDRV_CTL_TLVT_CHMAP_VAR;
2373}
2374
2375static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
2376 unsigned int *chmap, int channels)
2377{
2378 int count = 0;
2379 int c;
2380
2381 for (c = 7; c >= 0; c--) {
2382 int spk = cap->speakers[c];
2383 if (!spk)
2384 continue;
2385
2386 chmap[count++] = spk_to_chmap(spk);
2387 }
2388
2389 WARN_ON(count != channels);
2390}
2391
d45e6889
TI		 2392static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
2393 unsigned int size, unsigned int __user *tlv)
2394{
2395 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2396 struct hda_codec *codec = info->private_data;
2397 struct hdmi_spec *spec = codec->spec;
67b90cb8 2398 struct hdac_chmap *chmap = &spec->chmap;
d45e6889
TI		 2399 unsigned int __user *dst;
2400 int chs, count = 0;
2401
2402 if (size < 8)
2403 return -ENOMEM;
2404 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
2405 return -EFAULT;
2406 size -= 8;
2407 dst = tlv + 2;
67b90cb8 2408 for (chs = 2; chs <= chmap->channels_max; chs++) {
307229d2 2409 int i;
d45e6889
TI		 2410 struct cea_channel_speaker_allocation *cap;
2411 cap = channel_allocations;
2412 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
2413 int chs_bytes = chs * 4;
67b90cb8
SP		 2414 int type = chmap->ops.chmap_cea_alloc_validate_get_type(
2415 chmap, cap, chs);
307229d2
AH		 2416 unsigned int tlv_chmap[8];
2417
2418 if (type < 0)
d45e6889 2419 continue;
d45e6889
TI		 2420 if (size < 8)
2421 return -ENOMEM;
307229d2 2422 if (put_user(type, dst) ||
d45e6889
TI		 2423 put_user(chs_bytes, dst + 1))
2424 return -EFAULT;
2425 dst += 2;
2426 size -= 8;
2427 count += 8;
2428 if (size < chs_bytes)
2429 return -ENOMEM;
2430 size -= chs_bytes;
2431 count += chs_bytes;
67b90cb8 2432 chmap->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
307229d2
AH		 2433 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2434 return -EFAULT;
2435 dst += chs;
d45e6889
TI		 2436 }
2437 }
2438 if (put_user(count, tlv + 1))
2439 return -EFAULT;
2440 return 0;
2441}
2442
2443static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2444 struct snd_ctl_elem_value *ucontrol)
2445{
2446 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2447 struct hda_codec *codec = info->private_data;
2448 struct hdmi_spec *spec = codec->spec;
67b90cb8 2449 struct hdac_chmap *chmap = &spec->chmap;
022f344b
LY		 2450 int pcm_idx = kcontrol->private_value;
2451 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
d45e6889
TI		 2452 int i;
2453
022f344b 2454 if (!per_pin) {
67b90cb8 2455 for (i = 0; i < chmap->channels_max; i++)
022f344b
LY		 2456 ucontrol->value.integer.value[i] = 0;
2457 return 0;
2458 }
2459
d45e6889
TI		 2460 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2461 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2462 return 0;
2463}
2464
2465static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2466 struct snd_ctl_elem_value *ucontrol)
2467{
2468 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2469 struct hda_codec *codec = info->private_data;
2470 struct hdmi_spec *spec = codec->spec;
67b90cb8 2471 struct hdac_chmap *hchmap = &spec->chmap;
022f344b
LY		 2472 int pcm_idx = kcontrol->private_value;
2473 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
d45e6889
TI		 2474 unsigned int ctl_idx;
2475 struct snd_pcm_substream *substream;
2476 unsigned char chmap[8];
307229d2 2477 int i, err, ca, prepared = 0;
d45e6889 2478
022f344b
LY		 2479 /* No monitor is connected in dyn_pcm_assign.
2480 * It's invalid to setup the chmap
2481 */
2482 if (!per_pin)
2483 return 0;
2484
d45e6889
TI		 2485 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2486 substream = snd_pcm_chmap_substream(info, ctl_idx);
2487 if (!substream || !substream->runtime)
6f54c361 2488 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 2489 switch (substream->runtime->status->state) {
2490 case SNDRV_PCM_STATE_OPEN:
2491 case SNDRV_PCM_STATE_SETUP:
2492 break;
2493 case SNDRV_PCM_STATE_PREPARED:
2494 prepared = 1;
2495 break;
2496 default:
2497 return -EBUSY;
2498 }
2499 memset(chmap, 0, sizeof(chmap));
2500 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2501 chmap[i] = ucontrol->value.integer.value[i];
2502 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2503 return 0;
2504 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2505 if (ca < 0)
2506 return -EINVAL;
67b90cb8
SP		 2507 if (hchmap->ops.chmap_validate) {
2508 err = hchmap->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
307229d2
AH		 2509 if (err)
2510 return err;
2511 }
a4e9a38b 2512 mutex_lock(&per_pin->lock);
d45e6889
TI		 2513 per_pin->chmap_set = true;
2514 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2515 if (prepared)
b054087d 2516 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2517 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2518
2519 return 0;
2520}
2521
84eb01be
TI		 2522static int generic_hdmi_build_pcms(struct hda_codec *codec)
2523{
2524 struct hdmi_spec *spec = codec->spec;
384a48d7 2525 int pin_idx;
84eb01be 2526
384a48d7
SW		 2527 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2528 struct hda_pcm *info;
84eb01be 2529 struct hda_pcm_stream *pstr;
bce0d2a8 2530
bbbc7e85 2531 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 2532 if (!info)
2533 return -ENOMEM;
2bea241a
LY		 2534
2535 spec->pcm_rec[pin_idx].pcm = info;
2bf3c85a 2536 spec->pcm_used++;
84eb01be 2537 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2538 info->own_chmap = true;
384a48d7 2539
84eb01be 2540 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2541 pstr->substreams = 1;
2542 pstr->ops = generic_ops;
2543 /* other pstr fields are set in open */
84eb01be
TI		 2544 }
2545
2546 return 0;
2547}
2548
25e4abb3 2549static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 2550{
25e4abb3 2551 struct hdmi_pcm *pcm = jack->private_data;
788d441a 2552
25e4abb3 2553 pcm->jack = NULL;
788d441a
TI		 2554}
2555
25e4abb3
LY		 2556static int add_hdmi_jack_kctl(struct hda_codec *codec,
2557 struct hdmi_spec *spec,
2558 int pcm_idx,
788d441a
TI		 2559 const char *name)
2560{
2561 struct snd_jack *jack;
2562 int err;
2563
2564 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2565 true, false);
2566 if (err < 0)
2567 return err;
25e4abb3
LY		 2568
2569 spec->pcm_rec[pcm_idx].jack = jack;
2570 jack->private_data = &spec->pcm_rec[pcm_idx];
2571 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 2572 return 0;
2573}
2574
25e4abb3 2575static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 2576{
31ef2257 2577 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2578 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 2579 struct hdmi_spec_per_pin *per_pin;
2580 struct hda_jack_tbl *jack;
2581 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 2582 bool phantom_jack;
25e4abb3 2583 int ret;
0b6c49b5 2584
31ef2257
TI		 2585 if (pcmdev > 0)
2586 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 2587
2588 if (spec->dyn_pcm_assign)
2589 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2590
2591 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2592 /* if !dyn_pcm_assign, it must be non-MST mode.
2593 * This means pcms and pins are statically mapped.
2594 * And pcm_idx is pin_idx.
2595 */
2596 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 2597 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2598 if (phantom_jack)
30efd8de
DH		 2599 strncat(hdmi_str, " Phantom",
2600 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3
LY		 2601 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2602 phantom_jack);
2603 if (ret < 0)
2604 return ret;
2605 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2606 if (jack == NULL)
2607 return 0;
2608 /* assign jack->jack to pcm_rec[].jack to
2609 * align with dyn_pcm_assign mode
2610 */
2611 spec->pcm_rec[pcm_idx].jack = jack->jack;
2612 return 0;
0b6c49b5
DH		 2613}
2614
84eb01be
TI		 2615static int generic_hdmi_build_controls(struct hda_codec *codec)
2616{
2617 struct hdmi_spec *spec = codec->spec;
2618 int err;
25e4abb3 2619 int pin_idx, pcm_idx;
84eb01be 2620
0b6c49b5 2621
25e4abb3
LY		 2622 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2623 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 2624 if (err < 0)
2625 return err;
2626
b09887f8
LY		 2627 /* create the spdif for each pcm
2628 * pin will be bound when monitor is connected
2629 */
2630 if (spec->dyn_pcm_assign)
2631 err = snd_hda_create_dig_out_ctls(codec,
2632 0, spec->cvt_nids[0],
2633 HDA_PCM_TYPE_HDMI);
2634 else {
2635 struct hdmi_spec_per_pin *per_pin =
2636 get_pin(spec, pcm_idx);
2637 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2638 per_pin->pin_nid,
2639 per_pin->mux_nids[0],
2640 HDA_PCM_TYPE_HDMI);
b09887f8 2641 }
84eb01be
TI		 2642 if (err < 0)
2643 return err;
b09887f8 2644 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
14bc52b8
PLB		 2645
2646 /* add control for ELD Bytes */
fb087eaa
LY		 2647 err = hdmi_create_eld_ctl(codec, pcm_idx,
2648 get_pcm_rec(spec, pcm_idx)->device);
14bc52b8
PLB		 2649 if (err < 0)
2650 return err;
fb087eaa
LY		 2651 }
2652
2653 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2654 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
31ef2257 2655
82b1d73f 2656 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2657 }
2658
d45e6889 2659 /* add channel maps */
022f344b 2660 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2661 struct hda_pcm *pcm;
d45e6889
TI		 2662 struct snd_pcm_chmap *chmap;
2663 struct snd_kcontrol *kctl;
2664 int i;
2ca320e2 2665
022f344b 2666 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2667 if (!pcm || !pcm->pcm)
2ca320e2 2668 break;
bbbc7e85 2669 err = snd_pcm_add_chmap_ctls(pcm->pcm,
d45e6889 2670 SNDRV_PCM_STREAM_PLAYBACK,
022f344b 2671 NULL, 0, pcm_idx, &chmap);
d45e6889
TI		 2672 if (err < 0)
2673 return err;
2674 /* override handlers */
2675 chmap->private_data = codec;
2676 kctl = chmap->kctl;
2677 for (i = 0; i < kctl->count; i++)
2678 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2679 kctl->info = hdmi_chmap_ctl_info;
2680 kctl->get = hdmi_chmap_ctl_get;
2681 kctl->put = hdmi_chmap_ctl_put;
2682 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2683 }
2684
84eb01be
TI		 2685 return 0;
2686}
2687
8b8d654b 2688static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2689{
2690 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2691 int pin_idx;
2692
2693 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2694 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2695
744626da 2696 per_pin->codec = codec;
a4e9a38b 2697 mutex_init(&per_pin->lock);
744626da 2698 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2699 eld_proc_new(per_pin, pin_idx);
84eb01be 2700 }
8b8d654b
TI		 2701 return 0;
2702}
2703
2704static int generic_hdmi_init(struct hda_codec *codec)
2705{
2706 struct hdmi_spec *spec = codec->spec;
2707 int pin_idx;
2708
2709 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2710 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2711 hda_nid_t pin_nid = per_pin->pin_nid;
2712
2713 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2714 if (!codec_has_acomp(codec))
2715 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2716 codec->jackpoll_interval > 0 ?
2717 jack_callback : NULL);
8b8d654b 2718 }
84eb01be
TI		 2719 return 0;
2720}
2721
bce0d2a8
TI		 2722static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2723{
2724 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2725 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2726}
2727
2728static void hdmi_array_free(struct hdmi_spec *spec)
2729{
2730 snd_array_free(&spec->pins);
2731 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2732}
2733
84eb01be
TI		 2734static void generic_hdmi_free(struct hda_codec *codec)
2735{
2736 struct hdmi_spec *spec = codec->spec;
25e4abb3 2737 int pin_idx, pcm_idx;
384a48d7 2738
6603249d 2739 if (codec_has_acomp(codec))
25adc137
DH		 2740 snd_hdac_i915_register_notifier(NULL);
2741
384a48d7 2742 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2743 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2744 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2745 eld_proc_free(per_pin);
25e4abb3
LY		 2746 }
2747
2748 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2749 if (spec->pcm_rec[pcm_idx].jack == NULL)
2750 continue;
2751 if (spec->dyn_pcm_assign)
2752 snd_device_free(codec->card,
2753 spec->pcm_rec[pcm_idx].jack);
2754 else
2755 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2756 }
84eb01be 2757
55913110
TI		 2758 if (spec->i915_bound)
2759 snd_hdac_i915_exit(&codec->bus->core);
bce0d2a8 2760 hdmi_array_free(spec);
84eb01be
TI		 2761 kfree(spec);
2762}
2763
28cb72e5
WX		 2764#ifdef CONFIG_PM
2765static int generic_hdmi_resume(struct hda_codec *codec)
2766{
2767 struct hdmi_spec *spec = codec->spec;
2768 int pin_idx;
2769
a2833683 2770 codec->patch_ops.init(codec);
eeecd9d1 2771 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2772
2773 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2774 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2775 hdmi_present_sense(per_pin, 1);
2776 }
2777 return 0;
2778}
2779#endif
2780
fb79e1e0 2781static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2782 .init = generic_hdmi_init,
2783 .free = generic_hdmi_free,
2784 .build_pcms = generic_hdmi_build_pcms,
2785 .build_controls = generic_hdmi_build_controls,
2786 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2787#ifdef CONFIG_PM
2788 .resume = generic_hdmi_resume,
2789#endif
84eb01be
TI		 2790};
2791
307229d2
AH		 2792static const struct hdmi_ops generic_standard_hdmi_ops = {
2793 .pin_get_eld = snd_hdmi_get_eld,
2794 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2795 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2796 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2797 .pin_hbr_setup = hdmi_pin_hbr_setup,
2798 .setup_stream = hdmi_setup_stream,
67b90cb8
SP		 2799};
2800
2801static const struct hdac_chmap_ops chmap_ops = {
307229d2
AH		 2802 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2803 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2804};
2805
6ffe168f 2806
c88d4e84
TI		 2807static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2808 hda_nid_t nid)
2809{
2810 struct hdmi_spec *spec = codec->spec;
2811 hda_nid_t conns[4];
2812 int nconns;
6ffe168f 2813
c88d4e84
TI		 2814 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2815 if (nconns == spec->num_cvts &&
2816 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2817 return;
2818
c88d4e84 2819 /* override pins connection list */
4e76a883 2820 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2821 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2822}
2823
1611a9c9
ML		 2824#define INTEL_VENDOR_NID 0x08
2825#define INTEL_GET_VENDOR_VERB 0xf81
2826#define INTEL_SET_VENDOR_VERB 0x781
2827#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2828#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2829
2830static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2831 bool update_tree)
1611a9c9
ML		 2832{
2833 unsigned int vendor_param;
2834
1611a9c9
ML		 2835 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2836 INTEL_GET_VENDOR_VERB, 0);
2837 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2838 return;
2839
2840 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2841 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2842 INTEL_SET_VENDOR_VERB, vendor_param);
2843 if (vendor_param == -1)
2844 return;
2845
17df3f55
TI		 2846 if (update_tree)
2847 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2848}
2849
c88d4e84
TI		 2850static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2851{
2852 unsigned int vendor_param;
2853
2854 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2855 INTEL_GET_VENDOR_VERB, 0);
2856 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2857 return;
2858
2859 /* enable DP1.2 mode */
2860 vendor_param |= INTEL_EN_DP12;
a551d914 2861 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2862 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2863 INTEL_SET_VENDOR_VERB, vendor_param);
2864}
2865
17df3f55
TI		 2866/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2867 * Otherwise you may get severe h/w communication errors.
2868 */
2869static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2870 unsigned int power_state)
2871{
2872 if (power_state == AC_PWRST_D0) {
2873 intel_haswell_enable_all_pins(codec, false);
2874 intel_haswell_fixup_enable_dp12(codec);
2875 }
c88d4e84 2876
17df3f55
TI		 2877 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2878 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2879}
6ffe168f 2880
f0675d4a 2881static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2882{
2883 struct hda_codec *codec = audio_ptr;
2884 int pin_nid = port + 0x04;
2885
8ae743e8
TI		 2886 /* skip notification during system suspend (but not in runtime PM);
2887 * the state will be updated at resume
2888 */
2889 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2890 return;
eb399d3c
TI		 2891 /* ditto during suspend/resume process itself */
2892 if (atomic_read(&(codec)->core.in_pm))
2893 return;
8ae743e8 2894
25adc137
DH		 2895 check_presence_and_report(codec, pin_nid);
2896}
2897
84eb01be
TI		 2898static int patch_generic_hdmi(struct hda_codec *codec)
2899{
2900 struct hdmi_spec *spec;
84eb01be
TI		 2901
2902 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2903 if (spec == NULL)
2904 return -ENOMEM;
2905
307229d2 2906 spec->ops = generic_standard_hdmi_ops;
42b29870 2907 mutex_init(&spec->pcm_lock);
67b90cb8
SP		 2908 spec->chmap.ops = chmap_ops;
2909 spec->chmap.hdac = &codec->core;
84eb01be 2910 codec->spec = spec;
bce0d2a8 2911 hdmi_array_init(spec, 4);
6ffe168f 2912
55913110
TI		 2913 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2914 if (!codec_has_acomp(codec) &&
2915 (codec->core.vendor_id >> 16) == 0x8086)
2916 if (!snd_hdac_i915_init(&codec->bus->core))
2917 spec->i915_bound = true;
2918
75dcbe4d 2919 if (is_haswell_plus(codec)) {
17df3f55 2920 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2921 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2922 }
6ffe168f 2923
2bd1f73f
ML		 2924 /* For Valleyview/Cherryview, only the display codec is in the display
2925 * power well and can use link_power ops to request/release the power.
2926 * For Haswell/Broadwell, the controller is also in the power well and
2927 * can cover the codec power request, and so need not set this flag.
2928 * For previous platforms, there is no such power well feature.
2929 */
ff9d8859
LH		 2930 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2931 is_broxton(codec))
2bd1f73f
ML		 2932 codec->core.link_power_control = 1;
2933
84eb01be 2934 if (hdmi_parse_codec(codec) < 0) {
55913110
TI		 2935 if (spec->i915_bound)
2936 snd_hdac_i915_exit(&codec->bus->core);
84eb01be
TI		 2937 codec->spec = NULL;
2938 kfree(spec);
2939 return -EINVAL;
2940 }
2941 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2942 if (is_haswell_plus(codec)) {
17df3f55 2943 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2944 codec->dp_mst = true;
2945 }
17df3f55 2946
2377c3c3
LH		 2947 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2948 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2949 codec->auto_runtime_pm = 1;
2950
8b8d654b 2951 generic_hdmi_init_per_pins(codec);
84eb01be 2952
84eb01be
TI		 2953 init_channel_allocations();
2954
790b415c
LY		 2955 if (codec_has_acomp(codec)) {
2956 codec->depop_delay = 0;
2957 spec->i915_audio_ops.audio_ptr = codec;
2958 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2959 * will call pin_eld_notify with using audio_ptr pointer
2960 * We need make sure audio_ptr is really setup
2961 */
2962 wmb();
2963 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2964 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2965 }
2966
25e4abb3 2967 WARN_ON(spec->dyn_pcm_assign && !codec_has_acomp(codec));
84eb01be
TI		 2968 return 0;
2969}
2970
3aaf8980
SW		 2971/*
2972 * Shared non-generic implementations
2973 */
2974
2975static int simple_playback_build_pcms(struct hda_codec *codec)
2976{
2977 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2978 struct hda_pcm *info;
8ceb332d
TI		 2979 unsigned int chans;
2980 struct hda_pcm_stream *pstr;
bce0d2a8 2981 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2982
bce0d2a8
TI		 2983 per_cvt = get_cvt(spec, 0);
2984 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2985 chans = get_wcaps_channels(chans);
3aaf8980 2986
bbbc7e85 2987 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2988 if (!info)
2989 return -ENOMEM;
2bea241a 2990 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2991 info->pcm_type = HDA_PCM_TYPE_HDMI;
2992 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2993 *pstr = spec->pcm_playback;
bce0d2a8 2994 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2995 if (pstr->channels_max <= 2 && chans && chans <= 16)
2996 pstr->channels_max = chans;
3aaf8980
SW		 2997
2998 return 0;
2999}
3000
4b6ace9e
TI		 3001/* unsolicited event for jack sensing */
3002static void simple_hdmi_unsol_event(struct hda_codec *codec,
3003 unsigned int res)
3004{
9dd8cf12 3005 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 3006 snd_hda_jack_report_sync(codec);
3007}
3008
3009/* generic_hdmi_build_jack can be used for simple_hdmi, too,
3010 * as long as spec->pins[] is set correctly
3011 */
3012#define simple_hdmi_build_jack generic_hdmi_build_jack
3013
3aaf8980
SW		 3014static int simple_playback_build_controls(struct hda_codec *codec)
3015{
3016 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3017 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 3018 int err;
3aaf8980 3019
bce0d2a8 3020 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 3021 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3022 per_cvt->cvt_nid,
3023 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 3024 if (err < 0)
3025 return err;
3026 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 3027}
3028
4f0110ce
TI		 3029static int simple_playback_init(struct hda_codec *codec)
3030{
3031 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 3032 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3033 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 3034
3035 snd_hda_codec_write(codec, pin, 0,
3036 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3037 /* some codecs require to unmute the pin */
3038 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3039 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3040 AMP_OUT_UNMUTE);
62f949bf 3041 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 3042 return 0;
3043}
3044
3aaf8980
SW		 3045static void simple_playback_free(struct hda_codec *codec)
3046{
3047 struct hdmi_spec *spec = codec->spec;
3048
bce0d2a8 3049 hdmi_array_free(spec);
3aaf8980
SW		 3050 kfree(spec);
3051}
3052
84eb01be
TI		 3053/*
3054 * Nvidia specific implementations
3055 */
3056
3057#define Nv_VERB_SET_Channel_Allocation 0xF79
3058#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3059#define Nv_VERB_SET_Audio_Protection_On 0xF98
3060#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3061
3062#define nvhdmi_master_con_nid_7x 0x04
3063#define nvhdmi_master_pin_nid_7x 0x05
3064
fb79e1e0 3065static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 3066 /*front, rear, clfe, rear_surr */
3067 0x6, 0x8, 0xa, 0xc,
3068};
3069
ceaa86ba
TI		 3070static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3071 /* set audio protect on */
3072 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3073 /* enable digital output on pin widget */
3074 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3075 {} /* terminator */
3076};
3077
3078static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 3079 /* set audio protect on */
3080 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3081 /* enable digital output on pin widget */
3082 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3083 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3084 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3085 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3086 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3087 {} /* terminator */
3088};
3089
3090#ifdef LIMITED_RATE_FMT_SUPPORT
3091/* support only the safe format and rate */
3092#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3093#define SUPPORTED_MAXBPS 16
3094#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3095#else
3096/* support all rates and formats */
3097#define SUPPORTED_RATES \
3098 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3099 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3100 SNDRV_PCM_RATE_192000)
3101#define SUPPORTED_MAXBPS 24
3102#define SUPPORTED_FORMATS \
3103 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3104#endif
3105
ceaa86ba
TI		 3106static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3107{
3108 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3109 return 0;
3110}
3111
3112static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 3113{
ceaa86ba 3114 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 3115 return 0;
3116}
3117
393004b2
ND		 3118static unsigned int channels_2_6_8[] = {
3119 2, 6, 8
3120};
3121
3122static unsigned int channels_2_8[] = {
3123 2, 8
3124};
3125
3126static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3127 .count = ARRAY_SIZE(channels_2_6_8),
3128 .list = channels_2_6_8,
3129 .mask = 0,
3130};
3131
3132static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3133 .count = ARRAY_SIZE(channels_2_8),
3134 .list = channels_2_8,
3135 .mask = 0,
3136};
3137
84eb01be
TI		 3138static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3139 struct hda_codec *codec,
3140 struct snd_pcm_substream *substream)
3141{
3142 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 3143 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3144
b9a94a9c 3145 switch (codec->preset->vendor_id) {
393004b2
ND		 3146 case 0x10de0002:
3147 case 0x10de0003:
3148 case 0x10de0005:
3149 case 0x10de0006:
3150 hw_constraints_channels = &hw_constraints_2_8_channels;
3151 break;
3152 case 0x10de0007:
3153 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3154 break;
3155 default:
3156 break;
3157 }
3158
3159 if (hw_constraints_channels != NULL) {
3160 snd_pcm_hw_constraint_list(substream->runtime, 0,
3161 SNDRV_PCM_HW_PARAM_CHANNELS,
3162 hw_constraints_channels);
ad09fc9d
TI		 3163 } else {
3164 snd_pcm_hw_constraint_step(substream->runtime, 0,
3165 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 3166 }
3167
84eb01be
TI		 3168 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3169}
3170
3171static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3172 struct hda_codec *codec,
3173 struct snd_pcm_substream *substream)
3174{
3175 struct hdmi_spec *spec = codec->spec;
3176 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3177}
3178
3179static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3180 struct hda_codec *codec,
3181 unsigned int stream_tag,
3182 unsigned int format,
3183 struct snd_pcm_substream *substream)
3184{
3185 struct hdmi_spec *spec = codec->spec;
3186 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3187 stream_tag, format, substream);
3188}
3189
d0b1252d
TI		 3190static const struct hda_pcm_stream simple_pcm_playback = {
3191 .substreams = 1,
3192 .channels_min = 2,
3193 .channels_max = 2,
3194 .ops = {
3195 .open = simple_playback_pcm_open,
3196 .close = simple_playback_pcm_close,
3197 .prepare = simple_playback_pcm_prepare
3198 },
3199};
3200
3201static const struct hda_codec_ops simple_hdmi_patch_ops = {
3202 .build_controls = simple_playback_build_controls,
3203 .build_pcms = simple_playback_build_pcms,
3204 .init = simple_playback_init,
3205 .free = simple_playback_free,
250e41ac 3206 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 3207};
3208
3209static int patch_simple_hdmi(struct hda_codec *codec,
3210 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3211{
3212 struct hdmi_spec *spec;
bce0d2a8
TI		 3213 struct hdmi_spec_per_cvt *per_cvt;
3214 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 3215
3216 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3217 if (!spec)
3218 return -ENOMEM;
3219
3220 codec->spec = spec;
bce0d2a8 3221 hdmi_array_init(spec, 1);
d0b1252d
TI		 3222
3223 spec->multiout.num_dacs = 0; /* no analog */
3224 spec->multiout.max_channels = 2;
3225 spec->multiout.dig_out_nid = cvt_nid;
3226 spec->num_cvts = 1;
3227 spec->num_pins = 1;
bce0d2a8
TI		 3228 per_pin = snd_array_new(&spec->pins);
3229 per_cvt = snd_array_new(&spec->cvts);
3230 if (!per_pin || !per_cvt) {
3231 simple_playback_free(codec);
3232 return -ENOMEM;
3233 }
3234 per_cvt->cvt_nid = cvt_nid;
3235 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 3236 spec->pcm_playback = simple_pcm_playback;
3237
3238 codec->patch_ops = simple_hdmi_patch_ops;
3239
3240 return 0;
3241}
3242
1f348522
AP		 3243static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3244 int channels)
3245{
3246 unsigned int chanmask;
3247 int chan = channels ? (channels - 1) : 1;
3248
3249 switch (channels) {
3250 default:
3251 case 0:
3252 case 2:
3253 chanmask = 0x00;
3254 break;
3255 case 4:
3256 chanmask = 0x08;
3257 break;
3258 case 6:
3259 chanmask = 0x0b;
3260 break;
3261 case 8:
3262 chanmask = 0x13;
3263 break;
3264 }
3265
3266 /* Set the audio infoframe channel allocation and checksum fields. The
3267 * channel count is computed implicitly by the hardware. */
3268 snd_hda_codec_write(codec, 0x1, 0,
3269 Nv_VERB_SET_Channel_Allocation, chanmask);
3270
3271 snd_hda_codec_write(codec, 0x1, 0,
3272 Nv_VERB_SET_Info_Frame_Checksum,
3273 (0x71 - chan - chanmask));
3274}
3275
84eb01be
TI		 3276static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3277 struct hda_codec *codec,
3278 struct snd_pcm_substream *substream)
3279{
3280 struct hdmi_spec *spec = codec->spec;
3281 int i;
3282
3283 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3284 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3285 for (i = 0; i < 4; i++) {
3286 /* set the stream id */
3287 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3288 AC_VERB_SET_CHANNEL_STREAMID, 0);
3289 /* set the stream format */
3290 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3291 AC_VERB_SET_STREAM_FORMAT, 0);
3292 }
3293
1f348522
AP		 3294 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3295 * streams are disabled. */
3296 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3297
84eb01be
TI		 3298 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3299}
3300
3301static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3302 struct hda_codec *codec,
3303 unsigned int stream_tag,
3304 unsigned int format,
3305 struct snd_pcm_substream *substream)
3306{
3307 int chs;
112daa7a 3308 unsigned int dataDCC2, channel_id;
84eb01be 3309 int i;
7c935976 3310 struct hdmi_spec *spec = codec->spec;
e3245cdd 3311 struct hda_spdif_out *spdif;
bce0d2a8 3312 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3313
3314 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3315 per_cvt = get_cvt(spec, 0);
3316 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3317
3318 chs = substream->runtime->channels;
84eb01be 3319
84eb01be
TI		 3320 dataDCC2 = 0x2;
3321
84eb01be 3322 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3323 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3324 snd_hda_codec_write(codec,
3325 nvhdmi_master_con_nid_7x,
3326 0,
3327 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3328 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3329
3330 /* set the stream id */
3331 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3332 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3333
3334 /* set the stream format */
3335 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3336 AC_VERB_SET_STREAM_FORMAT, format);
3337
3338 /* turn on again (if needed) */
3339 /* enable and set the channel status audio/data flag */
7c935976 3340 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3341 snd_hda_codec_write(codec,
3342 nvhdmi_master_con_nid_7x,
3343 0,
3344 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3345 spdif->ctls & 0xff);
84eb01be
TI		 3346 snd_hda_codec_write(codec,
3347 nvhdmi_master_con_nid_7x,
3348 0,
3349 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3350 }
3351
3352 for (i = 0; i < 4; i++) {
3353 if (chs == 2)
3354 channel_id = 0;
3355 else
3356 channel_id = i * 2;
3357
3358 /* turn off SPDIF once;
3359 *otherwise the IEC958 bits won't be updated
3360 */
3361 if (codec->spdif_status_reset &&
7c935976 3362 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3363 snd_hda_codec_write(codec,
3364 nvhdmi_con_nids_7x[i],
3365 0,
3366 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3367 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3368 /* set the stream id */
3369 snd_hda_codec_write(codec,
3370 nvhdmi_con_nids_7x[i],
3371 0,
3372 AC_VERB_SET_CHANNEL_STREAMID,
3373 (stream_tag << 4) | channel_id);
3374 /* set the stream format */
3375 snd_hda_codec_write(codec,
3376 nvhdmi_con_nids_7x[i],
3377 0,
3378 AC_VERB_SET_STREAM_FORMAT,
3379 format);
3380 /* turn on again (if needed) */
3381 /* enable and set the channel status audio/data flag */
3382 if (codec->spdif_status_reset &&
7c935976 3383 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3384 snd_hda_codec_write(codec,
3385 nvhdmi_con_nids_7x[i],
3386 0,
3387 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3388 spdif->ctls & 0xff);
84eb01be
TI		 3389 snd_hda_codec_write(codec,
3390 nvhdmi_con_nids_7x[i],
3391 0,
3392 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3393 }
3394 }
3395
1f348522 3396 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3397
3398 mutex_unlock(&codec->spdif_mutex);
3399 return 0;
3400}
3401
fb79e1e0 3402static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3403 .substreams = 1,
3404 .channels_min = 2,
3405 .channels_max = 8,
3406 .nid = nvhdmi_master_con_nid_7x,
3407 .rates = SUPPORTED_RATES,
3408 .maxbps = SUPPORTED_MAXBPS,
3409 .formats = SUPPORTED_FORMATS,
3410 .ops = {
3411 .open = simple_playback_pcm_open,
3412 .close = nvhdmi_8ch_7x_pcm_close,
3413 .prepare = nvhdmi_8ch_7x_pcm_prepare
3414 },
3415};
3416
84eb01be
TI		 3417static int patch_nvhdmi_2ch(struct hda_codec *codec)
3418{
3419 struct hdmi_spec *spec;
d0b1252d
TI		 3420 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3421 nvhdmi_master_pin_nid_7x);
3422 if (err < 0)
3423 return err;
84eb01be 3424
ceaa86ba 3425 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3426 /* override the PCM rates, etc, as the codec doesn't give full list */
3427 spec = codec->spec;
3428 spec->pcm_playback.rates = SUPPORTED_RATES;
3429 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3430 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3431 return 0;
3432}
3433
53775b0d
TI		 3434static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3435{
3436 struct hdmi_spec *spec = codec->spec;
3437 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3438 if (!err) {
3439 struct hda_pcm *info = get_pcm_rec(spec, 0);
3440 info->own_chmap = true;
3441 }
53775b0d
TI		 3442 return err;
3443}
3444
3445static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3446{
3447 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3448 struct hda_pcm *info;
53775b0d
TI		 3449 struct snd_pcm_chmap *chmap;
3450 int err;
3451
3452 err = simple_playback_build_controls(codec);
3453 if (err < 0)
3454 return err;
3455
3456 /* add channel maps */
bce0d2a8
TI		 3457 info = get_pcm_rec(spec, 0);
3458 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3459 SNDRV_PCM_STREAM_PLAYBACK,
3460 snd_pcm_alt_chmaps, 8, 0, &chmap);
3461 if (err < 0)
3462 return err;
b9a94a9c 3463 switch (codec->preset->vendor_id) {
53775b0d
TI		 3464 case 0x10de0002:
3465 case 0x10de0003:
3466 case 0x10de0005:
3467 case 0x10de0006:
3468 chmap->channel_mask = (1U << 2) | (1U << 8);
3469 break;
3470 case 0x10de0007:
3471 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3472 }
3473 return 0;
3474}
3475
84eb01be
TI		 3476static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3477{
3478 struct hdmi_spec *spec;
3479 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3480 if (err < 0)
3481 return err;
3482 spec = codec->spec;
3483 spec->multiout.max_channels = 8;
d0b1252d 3484 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3485 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3486 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3487 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3488
3489 /* Initialize the audio infoframe channel mask and checksum to something
3490 * valid */
3491 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3492
84eb01be
TI		 3493 return 0;
3494}
3495
611885bc
AH		 3496/*
3497 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3498 * - 0x10de0015
3499 * - 0x10de0040
3500 */
67b90cb8
SP		 3501static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3502 struct cea_channel_speaker_allocation *cap, int channels)
611885bc
AH		 3503{
3504 if (cap->ca_index == 0x00 && channels == 2)
3505 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3506
67b90cb8
SP		 3507 return chmap->ops.chmap_cea_alloc_validate_get_type(
3508 chmap, cap, channels);
611885bc
AH		 3509}
3510
3511static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
3512{
3513 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3514 return -EINVAL;
3515
3516 return 0;
3517}
3518
3519static int patch_nvhdmi(struct hda_codec *codec)
3520{
3521 struct hdmi_spec *spec;
3522 int err;
3523
3524 err = patch_generic_hdmi(codec);
3525 if (err)
3526 return err;
3527
3528 spec = codec->spec;
75fae117 3529 spec->dyn_pin_out = true;
611885bc 3530
67b90cb8 3531 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
611885bc 3532 nvhdmi_chmap_cea_alloc_validate_get_type;
67b90cb8 3533 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
611885bc
AH		 3534
3535 return 0;
3536}
3537
26e9a960
TR		 3538/*
3539 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3540 * accessed using vendor-defined verbs. These registers can be used for
3541 * interoperability between the HDA and HDMI drivers.
3542 */
3543
3544/* Audio Function Group node */
3545#define NVIDIA_AFG_NID 0x01
3546
3547/*
3548 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3549 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3550 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3551 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3552 * additional bit (at position 30) to signal the validity of the format.
3553 *
3554 * | 31 | 30 | 29 16 | 15 0 |
3555 * +---------+-------+--------+--------+
3556 * | TRIGGER | VALID | UNUSED | FORMAT |
3557 * +-----------------------------------|
3558 *
3559 * Note that for the trigger bit to take effect it needs to change value
3560 * (i.e. it needs to be toggled).
3561 */
3562#define NVIDIA_GET_SCRATCH0 0xfa6
3563#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3564#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3565#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3566#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3567#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3568#define NVIDIA_SCRATCH_VALID (1 << 6)
3569
3570#define NVIDIA_GET_SCRATCH1 0xfab
3571#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3572#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3573#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3574#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3575
3576/*
3577 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3578 * the format is invalidated so that the HDMI codec can be disabled.
3579 */
3580static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3581{
3582 unsigned int value;
3583
3584 /* bits [31:30] contain the trigger and valid bits */
3585 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3586 NVIDIA_GET_SCRATCH0, 0);
3587 value = (value >> 24) & 0xff;
3588
3589 /* bits [15:0] are used to store the HDA format */
3590 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3591 NVIDIA_SET_SCRATCH0_BYTE0,
3592 (format >> 0) & 0xff);
3593 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3594 NVIDIA_SET_SCRATCH0_BYTE1,
3595 (format >> 8) & 0xff);
3596
3597 /* bits [16:24] are unused */
3598 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3599 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3600
3601 /*
3602 * Bit 30 signals that the data is valid and hence that HDMI audio can
3603 * be enabled.
3604 */
3605 if (format == 0)
3606 value &= ~NVIDIA_SCRATCH_VALID;
3607 else
3608 value |= NVIDIA_SCRATCH_VALID;
3609
3610 /*
3611 * Whenever the trigger bit is toggled, an interrupt is raised in the
3612 * HDMI codec. The HDMI driver will use that as trigger to update its
3613 * configuration.
3614 */
3615 value ^= NVIDIA_SCRATCH_TRIGGER;
3616
3617 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3618 NVIDIA_SET_SCRATCH0_BYTE3, value);
3619}
3620
3621static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3622 struct hda_codec *codec,
3623 unsigned int stream_tag,
3624 unsigned int format,
3625 struct snd_pcm_substream *substream)
3626{
3627 int err;
3628
3629 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3630 format, substream);
3631 if (err < 0)
3632 return err;
3633
3634 /* notify the HDMI codec of the format change */
3635 tegra_hdmi_set_format(codec, format);
3636
3637 return 0;
3638}
3639
3640static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3641 struct hda_codec *codec,
3642 struct snd_pcm_substream *substream)
3643{
3644 /* invalidate the format in the HDMI codec */
3645 tegra_hdmi_set_format(codec, 0);
3646
3647 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3648}
3649
3650static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3651{
3652 struct hdmi_spec *spec = codec->spec;
3653 unsigned int i;
3654
3655 for (i = 0; i < spec->num_pins; i++) {
3656 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3657
3658 if (pcm->pcm_type == type)
3659 return pcm;
3660 }
3661
3662 return NULL;
3663}
3664
3665static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3666{
3667 struct hda_pcm_stream *stream;
3668 struct hda_pcm *pcm;
3669 int err;
3670
3671 err = generic_hdmi_build_pcms(codec);
3672 if (err < 0)
3673 return err;
3674
3675 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3676 if (!pcm)
3677 return -ENODEV;
3678
3679 /*
3680 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3681 * codec about format changes.
3682 */
3683 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3684 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3685 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3686
3687 return 0;
3688}
3689
3690static int patch_tegra_hdmi(struct hda_codec *codec)
3691{
3692 int err;
3693
3694 err = patch_generic_hdmi(codec);
3695 if (err)
3696 return err;
3697
3698 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3699
3700 return 0;
3701}
3702
84eb01be 3703/*
5a613584 3704 * ATI/AMD-specific implementations
84eb01be
TI		 3705 */
3706
5a613584 3707#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3708 ((codec)->core.vendor_id == 0x1002aa01 && \
3709 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3710#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3711
3712/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3713#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3714#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3715#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3716#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3717#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3718#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3719#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3720#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3721#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3722#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3723#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3724#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3725#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3726#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3727#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3728#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3729#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3730#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3731#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3732#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3733#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3734#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3735#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3736#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3737
84d69e79
AH		 3738/* AMD specific HDA cvt verbs */
3739#define ATI_VERB_SET_RAMP_RATE 0x770
3740#define ATI_VERB_GET_RAMP_RATE 0xf70
3741
5a613584
AH		 3742#define ATI_OUT_ENABLE 0x1
3743
3744#define ATI_MULTICHANNEL_MODE_PAIRED 0
3745#define ATI_MULTICHANNEL_MODE_SINGLE 1
3746
461cf6b3
AH		 3747#define ATI_HBR_CAPABLE 0x01
3748#define ATI_HBR_ENABLE 0x10
3749
89250f84
AH		 3750static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3751 unsigned char *buf, int *eld_size)
3752{
3753 /* call hda_eld.c ATI/AMD-specific function */
3754 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3755 is_amdhdmi_rev3_or_later(codec));
3756}
3757
5a613584
AH		 3758static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3759 int active_channels, int conn_type)
3760{
3761 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3762}
3763
3764static int atihdmi_paired_swap_fc_lfe(int pos)
3765{
3766 /*
3767 * ATI/AMD have automatic FC/LFE swap built-in
3768 * when in pairwise mapping mode.
3769 */
3770
3771 switch (pos) {
3772 /* see channel_allocations[].speakers[] */
3773 case 2: return 3;
3774 case 3: return 2;
3775 default: break;
3776 }
3777
3778 return pos;
3779}
3780
3781static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3782{
3783 struct cea_channel_speaker_allocation *cap;
3784 int i, j;
3785
3786 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3787
3788 cap = &channel_allocations[get_channel_allocation_order(ca)];
3789 for (i = 0; i < chs; ++i) {
3790 int mask = to_spk_mask(map[i]);
3791 bool ok = false;
3792 bool companion_ok = false;
3793
3794 if (!mask)
3795 continue;
3796
3797 for (j = 0 + i % 2; j < 8; j += 2) {
3798 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3799 if (cap->speakers[chan_idx] == mask) {
3800 /* channel is in a supported position */
3801 ok = true;
3802
3803 if (i % 2 == 0 && i + 1 < chs) {
3804 /* even channel, check the odd companion */
3805 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3806 int comp_mask_req = to_spk_mask(map[i+1]);
3807 int comp_mask_act = cap->speakers[comp_chan_idx];
3808
3809 if (comp_mask_req == comp_mask_act)
3810 companion_ok = true;
3811 else
3812 return -EINVAL;
3813 }
3814 break;
3815 }
3816 }
3817
3818 if (!ok)
3819 return -EINVAL;
3820
3821 if (companion_ok)
3822 i++; /* companion channel already checked */
3823 }
3824
3825 return 0;
3826}
3827
3828static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3829 int hdmi_slot, int stream_channel)
3830{
3831 int verb;
3832 int ati_channel_setup = 0;
3833
3834 if (hdmi_slot > 7)
3835 return -EINVAL;
3836
3837 if (!has_amd_full_remap_support(codec)) {
3838 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3839
3840 /* In case this is an odd slot but without stream channel, do not
3841 * disable the slot since the corresponding even slot could have a
3842 * channel. In case neither have a channel, the slot pair will be
3843 * disabled when this function is called for the even slot. */
3844 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3845 return 0;
3846
3847 hdmi_slot -= hdmi_slot % 2;
3848
3849 if (stream_channel != 0xf)
3850 stream_channel -= stream_channel % 2;
3851 }
3852
3853 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3854
3855 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3856
3857 if (stream_channel != 0xf)
3858 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3859
3860 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3861}
3862
3863static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3864 int asp_slot)
3865{
3866 bool was_odd = false;
3867 int ati_asp_slot = asp_slot;
3868 int verb;
3869 int ati_channel_setup;
3870
3871 if (asp_slot > 7)
3872 return -EINVAL;
3873
3874 if (!has_amd_full_remap_support(codec)) {
3875 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3876 if (ati_asp_slot % 2 != 0) {
3877 ati_asp_slot -= 1;
3878 was_odd = true;
3879 }
3880 }
3881
3882 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3883
3884 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3885
3886 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3887 return 0xf;
3888
3889 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3890}
84eb01be 3891
67b90cb8
SP		 3892static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3893 struct hdac_chmap *chmap,
3894 struct cea_channel_speaker_allocation *cap,
3895 int channels)
5a613584
AH		 3896{
3897 int c;
3898
3899 /*
3900 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3901 * we need to take that into account (a single channel may take 2
3902 * channel slots if we need to carry a silent channel next to it).
3903 * On Rev3+ AMD codecs this function is not used.
3904 */
3905 int chanpairs = 0;
3906
3907 /* We only produce even-numbered channel count TLVs */
3908 if ((channels % 2) != 0)
3909 return -1;
3910
3911 for (c = 0; c < 7; c += 2) {
3912 if (cap->speakers[c] || cap->speakers[c+1])
3913 chanpairs++;
3914 }
3915
3916 if (chanpairs * 2 != channels)
3917 return -1;
3918
3919 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3920}
3921
3922static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3923 unsigned int *chmap, int channels)
3924{
3925 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3926 int count = 0;
3927 int c;
3928
3929 for (c = 7; c >= 0; c--) {
3930 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3931 int spk = cap->speakers[chan];
3932 if (!spk) {
3933 /* add N/A channel if the companion channel is occupied */
3934 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3935 chmap[count++] = SNDRV_CHMAP_NA;
3936
3937 continue;
3938 }
3939
3940 chmap[count++] = spk_to_chmap(spk);
3941 }
3942
3943 WARN_ON(count != channels);
3944}
3945
461cf6b3
AH		 3946static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3947 bool hbr)
3948{
3949 int hbr_ctl, hbr_ctl_new;
3950
3951 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3952 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3953 if (hbr)
3954 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3955 else
3956 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3957
4e76a883
TI		 3958 codec_dbg(codec,
3959 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3960 pin_nid,
3961 hbr_ctl == hbr_ctl_new ? "" : "new-",
3962 hbr_ctl_new);
3963
3964 if (hbr_ctl != hbr_ctl_new)
3965 snd_hda_codec_write(codec, pin_nid, 0,
3966 ATI_VERB_SET_HBR_CONTROL,
3967 hbr_ctl_new);
3968
3969 } else if (hbr)
3970 return -EINVAL;
3971
3972 return 0;
3973}
3974
84d69e79
AH		 3975static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3976 hda_nid_t pin_nid, u32 stream_tag, int format)
3977{
3978
3979 if (is_amdhdmi_rev3_or_later(codec)) {
3980 int ramp_rate = 180; /* default as per AMD spec */
3981 /* disable ramp-up/down for non-pcm as per AMD spec */
3982 if (format & AC_FMT_TYPE_NON_PCM)
3983 ramp_rate = 0;
3984
3985 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3986 }
3987
3988 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3989}
3990
3991
5a613584 3992static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3993{
3994 struct hdmi_spec *spec = codec->spec;
5a613584 3995 int pin_idx, err;
84eb01be 3996
5a613584
AH		 3997 err = generic_hdmi_init(codec);
3998
3999 if (err)
84eb01be 4000 return err;
5a613584
AH		 4001
4002 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4003 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4004
4005 /* make sure downmix information in infoframe is zero */
4006 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4007
4008 /* enable channel-wise remap mode if supported */
4009 if (has_amd_full_remap_support(codec))
4010 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4011 ATI_VERB_SET_MULTICHANNEL_MODE,
4012 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 4013 }
5a613584 4014
84eb01be
TI		 4015 return 0;
4016}
4017
84eb01be
TI		 4018static int patch_atihdmi(struct hda_codec *codec)
4019{
4020 struct hdmi_spec *spec;
5a613584
AH		 4021 struct hdmi_spec_per_cvt *per_cvt;
4022 int err, cvt_idx;
4023
4024 err = patch_generic_hdmi(codec);
4025
4026 if (err)
d0b1252d 4027 return err;
5a613584
AH		 4028
4029 codec->patch_ops.init = atihdmi_init;
4030
d0b1252d 4031 spec = codec->spec;
5a613584 4032
89250f84 4033 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 4034 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4035 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4036 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 4037 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 4038 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 4039
4040 if (!has_amd_full_remap_support(codec)) {
4041 /* override to ATI/AMD-specific versions with pairwise mapping */
67b90cb8 4042 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
5a613584 4043 atihdmi_paired_chmap_cea_alloc_validate_get_type;
67b90cb8
SP		 4044 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4045 atihdmi_paired_cea_alloc_to_tlv_chmap;
4046 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
5a613584
AH		 4047 }
4048
4049 /* ATI/AMD converters do not advertise all of their capabilities */
4050 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4051 per_cvt = get_cvt(spec, cvt_idx);
4052 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4053 per_cvt->rates |= SUPPORTED_RATES;
4054 per_cvt->formats |= SUPPORTED_FORMATS;
4055 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4056 }
4057
67b90cb8 4058 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
5a613584 4059
84eb01be
TI		 4060 return 0;
4061}
4062
3de5ff88
AL		 4063/* VIA HDMI Implementation */
4064#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4065#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4066
3de5ff88
AL		 4067static int patch_via_hdmi(struct hda_codec *codec)
4068{
250e41ac 4069 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 4070}
84eb01be
TI		 4071
4072/*
4073 * patch entries
4074 */
b9a94a9c
TI		 4075static const struct hda_device_id snd_hda_id_hdmi[] = {
4076HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4077HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4078HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4079HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4080HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4081HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4082HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4083HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4084HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4085HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4086HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4087HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4088HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
4089HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
4090HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
4091HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
4092HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
4093HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
4094HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
4095HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
4096HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
4097HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
4098HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 4099/* 17 is known to be absent */
b9a94a9c
TI		 4100HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
4101HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
4102HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
4103HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
4104HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
4105HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4106HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4107HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4108HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4109HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4110HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4111HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4112HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4113HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4114HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4115HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4116HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4117HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4118HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4119HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4120HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3ec622f4 4121HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 4122HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4123HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4124HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4125HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4126HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4127HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
4128HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4129HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4130HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4131HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
4132HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
4133HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
4134HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
4135HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
4136HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
4137HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
91815d8a 4138HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
b9a94a9c
TI		 4139HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4140HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
4141HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
4142HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 4143/* special ID for generic HDMI */
b9a94a9c 4144HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 4145{} /* terminator */
4146};
b9a94a9c 4147MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 4148
4149MODULE_LICENSE("GPL");
4150MODULE_DESCRIPTION("HDMI HD-audio codec");
4151MODULE_ALIAS("snd-hda-codec-intelhdmi");
4152MODULE_ALIAS("snd-hda-codec-nvhdmi");
4153MODULE_ALIAS("snd-hda-codec-atihdmi");
4154
d8a766a1 4155static struct hda_codec_driver hdmi_driver = {
b9a94a9c 4156 .id = snd_hda_id_hdmi,
84eb01be
TI		 4157};
4158
d8a766a1 4159module_hda_codec_driver(hdmi_driver);
Linux kernel - Deliverables
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