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ALSA: jack: Allow building the jack layer without input device
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
84eb01be
TI		 42#include "hda_codec.h"
43#include "hda_local.h"
1835a0f9 44#include "hda_jack.h"
84eb01be 45
0ebaa24c
TI		 46static bool static_hdmi_pcm;
47module_param(static_hdmi_pcm, bool, 0644);
48MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
7639a06c
TI		 50#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 53#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 54#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
432ac1a2 55#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a
LY		 56 || is_skylake(codec) || is_broxton(codec) \
57 || is_kabylake(codec))
75dcbe4d 58
7639a06c
TI		 59#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
60#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 61#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 62
384a48d7
SW		 63struct hdmi_spec_per_cvt {
64 hda_nid_t cvt_nid;
65 int assigned;
66 unsigned int channels_min;
67 unsigned int channels_max;
68 u32 rates;
69 u64 formats;
70 unsigned int maxbps;
71};
079d88cc 72
4eea3091
TI		 73/* max. connections to a widget */
74#define HDA_MAX_CONNECTIONS 32
75
384a48d7
SW		 76struct hdmi_spec_per_pin {
77 hda_nid_t pin_nid;
a76056f2
LY		 78 /* pin idx, different device entries on the same pin use the same idx */
79 int pin_nid_idx;
384a48d7
SW		 80 int num_mux_nids;
81 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 82 int mux_idx;
1df5a06a 83 hda_nid_t cvt_nid;
744626da
WF		 84
85 struct hda_codec *codec;
384a48d7 86 struct hdmi_eld sink_eld;
a4e9a38b 87 struct mutex lock;
744626da 88 struct delayed_work work;
92c69e79 89 struct snd_kcontrol *eld_ctl;
2bea241a 90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 92 int repoll_count;
b054087d
TI		 93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
1a6003b5 95 bool non_pcm;
d45e6889
TI		 96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 98#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 99 struct snd_info_entry *proc_entry;
100#endif
384a48d7 101};
079d88cc 102
307229d2
AH		 103struct cea_channel_speaker_allocation;
104
105/* operations used by generic code that can be overridden by patches */
106struct hdmi_ops {
107 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
108 unsigned char *buf, int *eld_size);
109
110 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
111 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int asp_slot);
113 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int asp_slot, int channel);
115
116 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
117 int ca, int active_channels, int conn_type);
118
119 /* enable/disable HBR (HD passthrough) */
120 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
121
122 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
123 hda_nid_t pin_nid, u32 stream_tag, int format);
124
125 /* Helpers for producing the channel map TLVs. These can be overridden
126 * for devices that have non-standard mapping requirements. */
127 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
128 int channels);
129 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
130 unsigned int *chmap, int channels);
131
132 /* check that the user-given chmap is supported */
133 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
134};
135
2bea241a
LY		 136struct hdmi_pcm {
137 struct hda_pcm *pcm;
138 struct snd_jack *jack;
139};
140
384a48d7
SW		 141struct hdmi_spec {
142 int num_cvts;
bce0d2a8
TI		 143 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
144 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 145
384a48d7 146 int num_pins;
bce0d2a8 147 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 148 struct hdmi_pcm pcm_rec[16];
42b29870 149 struct mutex pcm_lock;
a76056f2
LY		 150 /* pcm_bitmap means which pcms have been assigned to pins*/
151 unsigned long pcm_bitmap;
2bf3c85a 152 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 153 /* bitmap shows whether the pcm is opened in user space
154 * bit 0 means the first playback PCM (PCM3);
155 * bit 1 means the second playback PCM, and so on.
156 */
157 unsigned long pcm_in_use;
d45e6889 158 unsigned int channels_max; /* max over all cvts */
079d88cc 159
4bd038f9 160 struct hdmi_eld temp_eld;
307229d2 161 struct hdmi_ops ops;
75fae117
SW		 162
163 bool dyn_pin_out;
6590faab 164 bool dyn_pcm_assign;
079d88cc 165 /*
5a613584 166 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 167 */
168 struct hda_multi_out multiout;
d0b1252d 169 struct hda_pcm_stream pcm_playback;
25adc137
DH		 170
171 /* i915/powerwell (Haswell+/Valleyview+) specific */
172 struct i915_audio_component_audio_ops i915_audio_ops;
55913110 173 bool i915_bound; /* was i915 bound in this driver? */
079d88cc
WF		 174};
175
f4e3040b 176#ifdef CONFIG_SND_HDA_I915
6603249d
TI		 177#define codec_has_acomp(codec) \
178 ((codec)->bus->core.audio_component != NULL)
f4e3040b
TI		 179#else
180#define codec_has_acomp(codec) false
181#endif
079d88cc
WF		 182
183struct hdmi_audio_infoframe {
184 u8 type; /* 0x84 */
185 u8 ver; /* 0x01 */
186 u8 len; /* 0x0a */
187
53d7d69d
WF		 188 u8 checksum;
189
079d88cc
WF		 190 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
191 u8 SS01_SF24;
192 u8 CXT04;
193 u8 CA;
194 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 195};
196
197struct dp_audio_infoframe {
198 u8 type; /* 0x84 */
199 u8 len; /* 0x1b */
200 u8 ver; /* 0x11 << 2 */
201
202 u8 CC02_CT47; /* match with HDMI infoframe from this on */
203 u8 SS01_SF24;
204 u8 CXT04;
205 u8 CA;
206 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 207};
208
2b203dbb
TI		 209union audio_infoframe {
210 struct hdmi_audio_infoframe hdmi;
211 struct dp_audio_infoframe dp;
212 u8 bytes[0];
213};
214
079d88cc
WF		 215/*
216 * CEA speaker placement:
217 *
218 * FLH FCH FRH
219 * FLW FL FLC FC FRC FR FRW
220 *
221 * LFE
222 * TC
223 *
224 * RL RLC RC RRC RR
225 *
226 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
227 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
228 */
229enum cea_speaker_placement {
230 FL = (1 << 0), /* Front Left */
231 FC = (1 << 1), /* Front Center */
232 FR = (1 << 2), /* Front Right */
233 FLC = (1 << 3), /* Front Left Center */
234 FRC = (1 << 4), /* Front Right Center */
235 RL = (1 << 5), /* Rear Left */
236 RC = (1 << 6), /* Rear Center */
237 RR = (1 << 7), /* Rear Right */
238 RLC = (1 << 8), /* Rear Left Center */
239 RRC = (1 << 9), /* Rear Right Center */
240 LFE = (1 << 10), /* Low Frequency Effect */
241 FLW = (1 << 11), /* Front Left Wide */
242 FRW = (1 << 12), /* Front Right Wide */
243 FLH = (1 << 13), /* Front Left High */
244 FCH = (1 << 14), /* Front Center High */
245 FRH = (1 << 15), /* Front Right High */
246 TC = (1 << 16), /* Top Center */
247};
248
249/*
250 * ELD SA bits in the CEA Speaker Allocation data block
251 */
252static int eld_speaker_allocation_bits[] = {
253 [0] = FL | FR,
254 [1] = LFE,
255 [2] = FC,
256 [3] = RL | RR,
257 [4] = RC,
258 [5] = FLC | FRC,
259 [6] = RLC | RRC,
260 /* the following are not defined in ELD yet */
261 [7] = FLW | FRW,
262 [8] = FLH | FRH,
263 [9] = TC,
264 [10] = FCH,
265};
266
267struct cea_channel_speaker_allocation {
268 int ca_index;
269 int speakers[8];
270
271 /* derived values, just for convenience */
272 int channels;
273 int spk_mask;
274};
275
276/*
277 * ALSA sequence is:
278 *
279 * surround40 surround41 surround50 surround51 surround71
280 * ch0 front left = = = =
281 * ch1 front right = = = =
282 * ch2 rear left = = = =
283 * ch3 rear right = = = =
284 * ch4 LFE center center center
285 * ch5 LFE LFE
286 * ch6 side left
287 * ch7 side right
288 *
289 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
290 */
291static int hdmi_channel_mapping[0x32][8] = {
292 /* stereo */
293 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
294 /* 2.1 */
295 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
296 /* Dolby Surround */
297 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
298 /* surround40 */
299 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
300 /* 4ch */
301 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
302 /* surround41 */
9396d317 303 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 304 /* surround50 */
305 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
306 /* surround51 */
307 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
308 /* 7.1 */
309 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
310};
311
312/*
313 * This is an ordered list!
314 *
315 * The preceding ones have better chances to be selected by
53d7d69d 316 * hdmi_channel_allocation().
079d88cc
WF		 317 */
318static struct cea_channel_speaker_allocation channel_allocations[] = {
319/* channel: 7 6 5 4 3 2 1 0 */
320{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
321 /* 2.1 */
322{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
323 /* Dolby Surround */
324{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
325 /* surround40 */
326{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
327 /* surround41 */
328{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
329 /* surround50 */
330{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
331 /* surround51 */
332{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
333 /* 6.1 */
334{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
335 /* surround71 */
336{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
337
338{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
339{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
340{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
341{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
342{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
343{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
344{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
345{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
346{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
347{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
348{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
349{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
350{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
351{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
352{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
353{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
354{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
355{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
356{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
357{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
358{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
359{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
360{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
361{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
362{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
363{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
364{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
365{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
366{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
367{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
368{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
369{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
370{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
371{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
372{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
373{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
374{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
375{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
376{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
377{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
378{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
379};
380
381
382/*
383 * HDMI routines
384 */
385
bce0d2a8
TI		 386#define get_pin(spec, idx) \
387 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
388#define get_cvt(spec, idx) \
389 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 390/* obtain hdmi_pcm object assigned to idx */
391#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
392/* obtain hda_pcm object assigned to idx */
393#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 394
4e76a883 395static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 396{
4e76a883 397 struct hdmi_spec *spec = codec->spec;
384a48d7 398 int pin_idx;
079d88cc 399
384a48d7 400 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 401 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 402 return pin_idx;
079d88cc 403
4e76a883 404 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 405 return -EINVAL;
406}
407
2bf3c85a
LY		 408static int hinfo_to_pcm_index(struct hda_codec *codec,
409 struct hda_pcm_stream *hinfo)
410{
411 struct hdmi_spec *spec = codec->spec;
412 int pcm_idx;
413
414 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
415 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
416 return pcm_idx;
417
418 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
419 return -EINVAL;
420}
421
4e76a883 422static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 423 struct hda_pcm_stream *hinfo)
424{
4e76a883 425 struct hdmi_spec *spec = codec->spec;
6590faab 426 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 427 int pin_idx;
428
6590faab
LY		 429 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
430 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 431 if (per_pin->pcm &&
432 per_pin->pcm->pcm->stream == hinfo)
384a48d7 433 return pin_idx;
6590faab 434 }
384a48d7 435
6590faab 436 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 437 return -EINVAL;
438}
439
022f344b
LY		 440static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
441 int pcm_idx)
442{
443 int i;
444 struct hdmi_spec_per_pin *per_pin;
445
446 for (i = 0; i < spec->num_pins; i++) {
447 per_pin = get_pin(spec, i);
448 if (per_pin->pcm_idx == pcm_idx)
449 return per_pin;
450 }
451 return NULL;
452}
453
4e76a883 454static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 455{
4e76a883 456 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 457 int cvt_idx;
458
459 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 460 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 461 return cvt_idx;
462
4e76a883 463 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 464 return -EINVAL;
465}
466
14bc52b8
PLB		 467static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_info *uinfo)
469{
470 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 471 struct hdmi_spec *spec = codec->spec;
a4e9a38b 472 struct hdmi_spec_per_pin *per_pin;
68e03de9 473 struct hdmi_eld *eld;
14bc52b8
PLB		 474 int pin_idx;
475
14bc52b8
PLB		 476 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
477
478 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 479 per_pin = get_pin(spec, pin_idx);
480 eld = &per_pin->sink_eld;
68e03de9 481
a4e9a38b 482 mutex_lock(&per_pin->lock);
68e03de9 483 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 484 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 485
486 return 0;
487}
488
489static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
490 struct snd_ctl_elem_value *ucontrol)
491{
492 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 493 struct hdmi_spec *spec = codec->spec;
a4e9a38b 494 struct hdmi_spec_per_pin *per_pin;
68e03de9 495 struct hdmi_eld *eld;
14bc52b8
PLB		 496 int pin_idx;
497
14bc52b8 498 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 499 per_pin = get_pin(spec, pin_idx);
500 eld = &per_pin->sink_eld;
68e03de9 501
a4e9a38b 502 mutex_lock(&per_pin->lock);
360a8245
DH		 503 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
504 eld->eld_size > ELD_MAX_SIZE) {
a4e9a38b 505 mutex_unlock(&per_pin->lock);
68e03de9
DH		 506 snd_BUG();
507 return -EINVAL;
508 }
509
510 memset(ucontrol->value.bytes.data, 0,
511 ARRAY_SIZE(ucontrol->value.bytes.data));
512 if (eld->eld_valid)
513 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
514 eld->eld_size);
a4e9a38b 515 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 516
517 return 0;
518}
519
520static struct snd_kcontrol_new eld_bytes_ctl = {
521 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
522 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
523 .name = "ELD",
524 .info = hdmi_eld_ctl_info,
525 .get = hdmi_eld_ctl_get,
526};
527
528static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
529 int device)
530{
531 struct snd_kcontrol *kctl;
532 struct hdmi_spec *spec = codec->spec;
533 int err;
534
535 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
536 if (!kctl)
537 return -ENOMEM;
538 kctl->private_value = pin_idx;
539 kctl->id.device = device;
540
bce0d2a8 541 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 542 if (err < 0)
543 return err;
544
bce0d2a8 545 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 546 return 0;
547}
548
079d88cc
WF		 549#ifdef BE_PARANOID
550static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
551 int *packet_index, int *byte_index)
552{
553 int val;
554
555 val = snd_hda_codec_read(codec, pin_nid, 0,
556 AC_VERB_GET_HDMI_DIP_INDEX, 0);
557
558 *packet_index = val >> 5;
559 *byte_index = val & 0x1f;
560}
561#endif
562
563static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
564 int packet_index, int byte_index)
565{
566 int val;
567
568 val = (packet_index << 5) | (byte_index & 0x1f);
569
570 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
571}
572
573static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
574 unsigned char val)
575{
576 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
577}
578
384a48d7 579static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 580{
75fae117
SW		 581 struct hdmi_spec *spec = codec->spec;
582 int pin_out;
583
079d88cc
WF		 584 /* Unmute */
585 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
586 snd_hda_codec_write(codec, pin_nid, 0,
587 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 588
589 if (spec->dyn_pin_out)
590 /* Disable pin out until stream is active */
591 pin_out = 0;
592 else
593 /* Enable pin out: some machines with GM965 gets broken output
594 * when the pin is disabled or changed while using with HDMI
595 */
596 pin_out = PIN_OUT;
597
079d88cc 598 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 599 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 600}
601
384a48d7 602static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 603{
384a48d7 604 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 605 AC_VERB_GET_CVT_CHAN_COUNT, 0);
606}
607
608static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 609 hda_nid_t cvt_nid, int chs)
079d88cc 610{
384a48d7
SW		 611 if (chs != hdmi_get_channel_count(codec, cvt_nid))
612 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 613 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
614}
615
a4e9a38b
TI		 616/*
617 * ELD proc files
618 */
619
cd6a6503 620#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 621static void print_eld_info(struct snd_info_entry *entry,
622 struct snd_info_buffer *buffer)
623{
624 struct hdmi_spec_per_pin *per_pin = entry->private_data;
625
626 mutex_lock(&per_pin->lock);
627 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
628 mutex_unlock(&per_pin->lock);
629}
630
631static void write_eld_info(struct snd_info_entry *entry,
632 struct snd_info_buffer *buffer)
633{
634 struct hdmi_spec_per_pin *per_pin = entry->private_data;
635
636 mutex_lock(&per_pin->lock);
637 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
638 mutex_unlock(&per_pin->lock);
639}
640
641static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
642{
643 char name[32];
644 struct hda_codec *codec = per_pin->codec;
645 struct snd_info_entry *entry;
646 int err;
647
648 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 649 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 650 if (err < 0)
651 return err;
652
653 snd_info_set_text_ops(entry, per_pin, print_eld_info);
654 entry->c.text.write = write_eld_info;
655 entry->mode |= S_IWUSR;
656 per_pin->proc_entry = entry;
657
658 return 0;
659}
660
661static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
662{
1947a114 663 if (!per_pin->codec->bus->shutdown) {
c560a679 664 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 665 per_pin->proc_entry = NULL;
666 }
667}
668#else
b55447a7
TI		 669static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
670 int index)
a4e9a38b
TI		 671{
672 return 0;
673}
b55447a7 674static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 675{
676}
677#endif
079d88cc
WF		 678
679/*
680 * Channel mapping routines
681 */
682
683/*
684 * Compute derived values in channel_allocations[].
685 */
686static void init_channel_allocations(void)
687{
688 int i, j;
689 struct cea_channel_speaker_allocation *p;
690
691 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
692 p = channel_allocations + i;
693 p->channels = 0;
694 p->spk_mask = 0;
695 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
696 if (p->speakers[j]) {
697 p->channels++;
698 p->spk_mask |= p->speakers[j];
699 }
700 }
701}
702
72357c78
WX		 703static int get_channel_allocation_order(int ca)
704{
705 int i;
706
707 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
708 if (channel_allocations[i].ca_index == ca)
709 break;
710 }
711 return i;
712}
713
079d88cc
WF		 714/*
715 * The transformation takes two steps:
716 *
717 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
718 * spk_mask => (channel_allocations[]) => ai->CA
719 *
720 * TODO: it could select the wrong CA from multiple candidates.
721*/
79514d47
TI		 722static int hdmi_channel_allocation(struct hda_codec *codec,
723 struct hdmi_eld *eld, int channels)
079d88cc 724{
079d88cc 725 int i;
53d7d69d 726 int ca = 0;
079d88cc 727 int spk_mask = 0;
079d88cc
WF		 728 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
729
730 /*
731 * CA defaults to 0 for basic stereo audio
732 */
733 if (channels <= 2)
734 return 0;
735
079d88cc
WF		 736 /*
737 * expand ELD's speaker allocation mask
738 *
739 * ELD tells the speaker mask in a compact(paired) form,
740 * expand ELD's notions to match the ones used by Audio InfoFrame.
741 */
742 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 743 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 744 spk_mask |= eld_speaker_allocation_bits[i];
745 }
746
747 /* search for the first working match in the CA table */
748 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
749 if (channels == channel_allocations[i].channels &&
750 (spk_mask & channel_allocations[i].spk_mask) ==
751 channel_allocations[i].spk_mask) {
53d7d69d 752 ca = channel_allocations[i].ca_index;
079d88cc
WF		 753 break;
754 }
755 }
756
18e39186
AH		 757 if (!ca) {
758 /* if there was no match, select the regular ALSA channel
759 * allocation with the matching number of channels */
760 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
761 if (channels == channel_allocations[i].channels) {
762 ca = channel_allocations[i].ca_index;
763 break;
764 }
765 }
766 }
767
1613d6b4 768 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
79514d47 769 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 770 ca, channels, buf);
079d88cc 771
53d7d69d 772 return ca;
079d88cc
WF		 773}
774
775static void hdmi_debug_channel_mapping(struct hda_codec *codec,
776 hda_nid_t pin_nid)
777{
778#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 779 struct hdmi_spec *spec = codec->spec;
079d88cc 780 int i;
307229d2 781 int channel;
079d88cc
WF		 782
783 for (i = 0; i < 8; i++) {
307229d2 784 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 785 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 786 channel, i);
079d88cc
WF		 787 }
788#endif
789}
790
d45e6889 791static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 792 hda_nid_t pin_nid,
433968da 793 bool non_pcm,
53d7d69d 794 int ca)
079d88cc 795{
307229d2 796 struct hdmi_spec *spec = codec->spec;
90f28002 797 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 798 int i;
079d88cc 799 int err;
72357c78 800 int order;
433968da 801 int non_pcm_mapping[8];
079d88cc 802
72357c78 803 order = get_channel_allocation_order(ca);
90f28002 804 ch_alloc = &channel_allocations[order];
433968da 805
079d88cc 806 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 807 int hdmi_slot = 0;
808 /* fill actual channel mappings in ALSA channel (i) order */
809 for (i = 0; i < ch_alloc->channels; i++) {
810 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
811 hdmi_slot++; /* skip zero slots */
812
813 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
814 }
815 /* fill the rest of the slots with ALSA channel 0xf */
816 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
817 if (!ch_alloc->speakers[7 - hdmi_slot])
818 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 819 }
820
433968da 821 if (non_pcm) {
90f28002 822 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 823 non_pcm_mapping[i] = (i << 4) | i;
433968da 824 for (; i < 8; i++)
11f7c52d 825 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 826 }
827
079d88cc 828 for (i = 0; i < 8; i++) {
307229d2
AH		 829 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
830 int hdmi_slot = slotsetup & 0x0f;
831 int channel = (slotsetup & 0xf0) >> 4;
832 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 833 if (err) {
4e76a883 834 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 835 break;
836 }
837 }
079d88cc
WF		 838}
839
d45e6889
TI		 840struct channel_map_table {
841 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 842 int spk_mask; /* speaker position bit mask */
843};
844
845static struct channel_map_table map_tables[] = {
a5b7d510
AH		 846 { SNDRV_CHMAP_FL, FL },
847 { SNDRV_CHMAP_FR, FR },
848 { SNDRV_CHMAP_RL, RL },
849 { SNDRV_CHMAP_RR, RR },
850 { SNDRV_CHMAP_LFE, LFE },
851 { SNDRV_CHMAP_FC, FC },
852 { SNDRV_CHMAP_RLC, RLC },
853 { SNDRV_CHMAP_RRC, RRC },
854 { SNDRV_CHMAP_RC, RC },
855 { SNDRV_CHMAP_FLC, FLC },
856 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 857 { SNDRV_CHMAP_TFL, FLH },
858 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 859 { SNDRV_CHMAP_FLW, FLW },
860 { SNDRV_CHMAP_FRW, FRW },
861 { SNDRV_CHMAP_TC, TC },
94908a39 862 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 863 {} /* terminator */
864};
865
866/* from ALSA API channel position to speaker bit mask */
867static int to_spk_mask(unsigned char c)
868{
869 struct channel_map_table *t = map_tables;
870 for (; t->map; t++) {
871 if (t->map == c)
872 return t->spk_mask;
873 }
874 return 0;
875}
876
877/* from ALSA API channel position to CEA slot */
a5b7d510 878static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 879{
a5b7d510
AH		 880 int mask = to_spk_mask(pos);
881 int i;
d45e6889 882
a5b7d510
AH		 883 if (mask) {
884 for (i = 0; i < 8; i++) {
885 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
886 return i;
887 }
d45e6889 888 }
a5b7d510
AH		 889
890 return -1;
d45e6889
TI		 891}
892
893/* from speaker bit mask to ALSA API channel position */
894static int spk_to_chmap(int spk)
895{
896 struct channel_map_table *t = map_tables;
897 for (; t->map; t++) {
898 if (t->spk_mask == spk)
899 return t->map;
900 }
901 return 0;
902}
903
a5b7d510
AH		 904/* from CEA slot to ALSA API channel position */
905static int from_cea_slot(int ordered_ca, unsigned char slot)
906{
907 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
908
909 return spk_to_chmap(mask);
910}
911
d45e6889
TI		 912/* get the CA index corresponding to the given ALSA API channel map */
913static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
914{
915 int i, spks = 0, spk_mask = 0;
916
917 for (i = 0; i < chs; i++) {
918 int mask = to_spk_mask(map[i]);
919 if (mask) {
920 spk_mask |= mask;
921 spks++;
922 }
923 }
924
925 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
926 if ((chs == channel_allocations[i].channels ||
927 spks == channel_allocations[i].channels) &&
928 (spk_mask & channel_allocations[i].spk_mask) ==
929 channel_allocations[i].spk_mask)
930 return channel_allocations[i].ca_index;
931 }
932 return -1;
933}
934
935/* set up the channel slots for the given ALSA API channel map */
936static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
937 hda_nid_t pin_nid,
a5b7d510
AH		 938 int chs, unsigned char *map,
939 int ca)
d45e6889 940{
307229d2 941 struct hdmi_spec *spec = codec->spec;
a5b7d510 942 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 943 int alsa_pos, hdmi_slot;
944 int assignments[8] = {[0 ... 7] = 0xf};
945
946 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
947
a5b7d510 948 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 949
950 if (hdmi_slot < 0)
951 continue; /* unassigned channel */
952
953 assignments[hdmi_slot] = alsa_pos;
954 }
955
956 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 957 int err;
11f7c52d 958
307229d2
AH		 959 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
960 assignments[hdmi_slot]);
d45e6889
TI		 961 if (err)
962 return -EINVAL;
963 }
964 return 0;
965}
966
967/* store ALSA API channel map from the current default map */
968static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
969{
970 int i;
56cac413 971 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 972 for (i = 0; i < 8; i++) {
56cac413 973 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 974 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 975 else
976 map[i] = 0;
977 }
978}
979
980static void hdmi_setup_channel_mapping(struct hda_codec *codec,
981 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 982 int channels, unsigned char *map,
983 bool chmap_set)
d45e6889 984{
20608731 985 if (!non_pcm && chmap_set) {
d45e6889 986 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 987 channels, map, ca);
d45e6889
TI		 988 } else {
989 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
990 hdmi_setup_fake_chmap(map, ca);
991 }
980b2495
AH		 992
993 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 994}
079d88cc 995
307229d2
AH		 996static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
997 int asp_slot, int channel)
998{
999 return snd_hda_codec_write(codec, pin_nid, 0,
1000 AC_VERB_SET_HDMI_CHAN_SLOT,
1001 (channel << 4) | asp_slot);
1002}
1003
1004static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
1005 int asp_slot)
1006{
1007 return (snd_hda_codec_read(codec, pin_nid, 0,
1008 AC_VERB_GET_HDMI_CHAN_SLOT,
1009 asp_slot) & 0xf0) >> 4;
1010}
1011
079d88cc
WF		 1012/*
1013 * Audio InfoFrame routines
1014 */
1015
1016/*
1017 * Enable Audio InfoFrame Transmission
1018 */
1019static void hdmi_start_infoframe_trans(struct hda_codec *codec,
1020 hda_nid_t pin_nid)
1021{
1022 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1023 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
1024 AC_DIPXMIT_BEST);
1025}
1026
1027/*
1028 * Disable Audio InfoFrame Transmission
1029 */
1030static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
1031 hda_nid_t pin_nid)
1032{
1033 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1034 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
1035 AC_DIPXMIT_DISABLE);
1036}
1037
1038static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
1039{
1040#ifdef CONFIG_SND_DEBUG_VERBOSE
1041 int i;
1042 int size;
1043
1044 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 1045 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 1046
1047 for (i = 0; i < 8; i++) {
1048 size = snd_hda_codec_read(codec, pin_nid, 0,
1049 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 1050 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 1051 }
1052#endif
1053}
1054
1055static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
1056{
1057#ifdef BE_PARANOID
1058 int i, j;
1059 int size;
1060 int pi, bi;
1061 for (i = 0; i < 8; i++) {
1062 size = snd_hda_codec_read(codec, pin_nid, 0,
1063 AC_VERB_GET_HDMI_DIP_SIZE, i);
1064 if (size == 0)
1065 continue;
1066
1067 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1068 for (j = 1; j < 1000; j++) {
1069 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1070 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1071 if (pi != i)
4e76a883 1072 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1073 bi, pi, i);
1074 if (bi == 0) /* byte index wrapped around */
1075 break;
1076 }
4e76a883 1077 codec_dbg(codec,
079d88cc
WF		 1078 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1079 i, size, j);
1080 }
1081#endif
1082}
1083
53d7d69d 1084static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1085{
53d7d69d 1086 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1087 u8 sum = 0;
1088 int i;
1089
53d7d69d 1090 hdmi_ai->checksum = 0;
079d88cc 1091
53d7d69d 1092 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1093 sum += bytes[i];
1094
53d7d69d 1095 hdmi_ai->checksum = -sum;
079d88cc
WF		 1096}
1097
1098static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1099 hda_nid_t pin_nid,
53d7d69d 1100 u8 *dip, int size)
079d88cc 1101{
079d88cc
WF		 1102 int i;
1103
1104 hdmi_debug_dip_size(codec, pin_nid);
1105 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1106
079d88cc 1107 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1108 for (i = 0; i < size; i++)
1109 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1110}
1111
1112static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1113 u8 *dip, int size)
079d88cc 1114{
079d88cc
WF		 1115 u8 val;
1116 int i;
1117
1118 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1119 != AC_DIPXMIT_BEST)
1120 return false;
1121
1122 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1123 for (i = 0; i < size; i++) {
079d88cc
WF		 1124 val = snd_hda_codec_read(codec, pin_nid, 0,
1125 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1126 if (val != dip[i])
079d88cc
WF		 1127 return false;
1128 }
1129
1130 return true;
1131}
1132
307229d2
AH		 1133static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1134 hda_nid_t pin_nid,
1135 int ca, int active_channels,
1136 int conn_type)
1137{
1138 union audio_infoframe ai;
1139
caaf5ef9 1140 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1141 if (conn_type == 0) { /* HDMI */
1142 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1143
1144 hdmi_ai->type = 0x84;
1145 hdmi_ai->ver = 0x01;
1146 hdmi_ai->len = 0x0a;
1147 hdmi_ai->CC02_CT47 = active_channels - 1;
1148 hdmi_ai->CA = ca;
1149 hdmi_checksum_audio_infoframe(hdmi_ai);
1150 } else if (conn_type == 1) { /* DisplayPort */
1151 struct dp_audio_infoframe *dp_ai = &ai.dp;
1152
1153 dp_ai->type = 0x84;
1154 dp_ai->len = 0x1b;
1155 dp_ai->ver = 0x11 << 2;
1156 dp_ai->CC02_CT47 = active_channels - 1;
1157 dp_ai->CA = ca;
1158 } else {
4e76a883 1159 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1160 pin_nid);
1161 return;
1162 }
1163
1164 /*
1165 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1166 * sizeof(*dp_ai) to avoid partial match/update problems when
1167 * the user switches between HDMI/DP monitors.
1168 */
1169 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1170 sizeof(ai))) {
4e76a883
TI		 1171 codec_dbg(codec,
1172 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1173 pin_nid,
1174 active_channels, ca);
1175 hdmi_stop_infoframe_trans(codec, pin_nid);
1176 hdmi_fill_audio_infoframe(codec, pin_nid,
1177 ai.bytes, sizeof(ai));
1178 hdmi_start_infoframe_trans(codec, pin_nid);
1179 }
1180}
1181
b054087d
TI		 1182static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1183 struct hdmi_spec_per_pin *per_pin,
1184 bool non_pcm)
079d88cc 1185{
307229d2 1186 struct hdmi_spec *spec = codec->spec;
384a48d7 1187 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1188 int channels = per_pin->channels;
1df5a06a 1189 int active_channels;
384a48d7 1190 struct hdmi_eld *eld;
1df5a06a 1191 int ca, ordered_ca;
079d88cc 1192
b054087d
TI		 1193 if (!channels)
1194 return;
1195
75dcbe4d 1196 if (is_haswell_plus(codec))
58f7d28d
ML		 1197 snd_hda_codec_write(codec, pin_nid, 0,
1198 AC_VERB_SET_AMP_GAIN_MUTE,
1199 AMP_OUT_UNMUTE);
1200
bce0d2a8 1201 eld = &per_pin->sink_eld;
079d88cc 1202
d45e6889
TI		 1203 if (!non_pcm && per_pin->chmap_set)
1204 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1205 else
79514d47 1206 ca = hdmi_channel_allocation(codec, eld, channels);
d45e6889
TI		 1207 if (ca < 0)
1208 ca = 0;
384a48d7 1209
1df5a06a
AH		 1210 ordered_ca = get_channel_allocation_order(ca);
1211 active_channels = channel_allocations[ordered_ca].channels;
1212
1213 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1214
39edac70
AH		 1215 /*
1216 * always configure channel mapping, it may have been changed by the
1217 * user in the meantime
1218 */
1219 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1220 channels, per_pin->chmap,
1221 per_pin->chmap_set);
1222
307229d2
AH		 1223 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1224 eld->info.conn_type);
433968da 1225
1a6003b5 1226 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1227}
1228
079d88cc
WF		 1229/*
1230 * Unsolicited events
1231 */
1232
efe47108 1233static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1234
1a4f69d5 1235static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 1236{
1237 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 1238 int pin_idx = pin_nid_to_pin_index(codec, nid);
1239
20ce9029
DH		 1240 if (pin_idx < 0)
1241 return;
20ce9029
DH		 1242 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1243 snd_hda_jack_report_sync(codec);
1244}
1245
1a4f69d5
TI		 1246static void jack_callback(struct hda_codec *codec,
1247 struct hda_jack_callback *jack)
1248{
2ebab40e 1249 check_presence_and_report(codec, jack->nid);
1a4f69d5
TI		 1250}
1251
20ce9029
DH		 1252static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1253{
3a93897e 1254 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1255 struct hda_jack_tbl *jack;
2e59e5ab 1256 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1257
1258 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1259 if (!jack)
1260 return;
3a93897e 1261 jack->jack_dirty = 1;
079d88cc 1262
4e76a883 1263 codec_dbg(codec,
2e59e5ab 1264 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1265 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1266 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1267
1a4f69d5 1268 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 1269}
1270
1271static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1272{
1273 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1274 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1275 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1276 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1277
4e76a883 1278 codec_info(codec,
e9ea8e8f 1279 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1280 codec->addr,
079d88cc
WF		 1281 tag,
1282 subtag,
1283 cp_state,
1284 cp_ready);
1285
1286 /* TODO */
1287 if (cp_state)
1288 ;
1289 if (cp_ready)
1290 ;
1291}
1292
1293
1294static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1295{
079d88cc
WF		 1296 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1297 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1298
3a93897e 1299 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1300 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1301 return;
1302 }
1303
1304 if (subtag == 0)
1305 hdmi_intrinsic_event(codec, res);
1306 else
1307 hdmi_non_intrinsic_event(codec, res);
1308}
1309
58f7d28d 1310static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1311 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1312{
58f7d28d 1313 int pwr;
83f26ad2 1314
53b434f0
WX		 1315 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1316 * thus pins could only choose converter 0 for use. Make sure the
1317 * converters are in correct power state */
fd678cac 1318 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1319 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1320
fd678cac 1321 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1322 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1323 AC_PWRST_D0);
1324 msleep(40);
1325 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1326 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1327 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1328 }
83f26ad2
DH		 1329}
1330
079d88cc
WF		 1331/*
1332 * Callbacks
1333 */
1334
92f10b3f
TI		 1335/* HBR should be Non-PCM, 8 channels */
1336#define is_hbr_format(format) \
1337 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1338
307229d2
AH		 1339static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1340 bool hbr)
079d88cc 1341{
307229d2 1342 int pinctl, new_pinctl;
83f26ad2 1343
384a48d7
SW		 1344 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1345 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1346 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1347
13122e6e
AH		 1348 if (pinctl < 0)
1349 return hbr ? -EINVAL : 0;
1350
ea87d1c4 1351 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1352 if (hbr)
ea87d1c4
AH		 1353 new_pinctl |= AC_PINCTL_EPT_HBR;
1354 else
1355 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1356
4e76a883
TI		 1357 codec_dbg(codec,
1358 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1359 pin_nid,
ea87d1c4
AH		 1360 pinctl == new_pinctl ? "" : "new-",
1361 new_pinctl);
1362
1363 if (pinctl != new_pinctl)
384a48d7 1364 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1365 AC_VERB_SET_PIN_WIDGET_CONTROL,
1366 new_pinctl);
307229d2
AH		 1367 } else if (hbr)
1368 return -EINVAL;
ea87d1c4 1369
307229d2
AH		 1370 return 0;
1371}
1372
1373static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1374 hda_nid_t pin_nid, u32 stream_tag, int format)
1375{
1376 struct hdmi_spec *spec = codec->spec;
1377 int err;
1378
75dcbe4d 1379 if (is_haswell_plus(codec))
307229d2
AH		 1380 haswell_verify_D0(codec, cvt_nid, pin_nid);
1381
1382 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1383
1384 if (err) {
4e76a883 1385 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1386 return err;
ea87d1c4 1387 }
079d88cc 1388
384a48d7 1389 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1390 return 0;
079d88cc
WF		 1391}
1392
42b29870
LY		 1393/* Try to find an available converter
1394 * If pin_idx is less then zero, just try to find an available converter.
1395 * Otherwise, try to find an available converter and get the cvt mux index
1396 * of the pin.
1397 */
7ef166b8
WX		 1398static int hdmi_choose_cvt(struct hda_codec *codec,
1399 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1400{
1401 struct hdmi_spec *spec = codec->spec;
384a48d7 1402 struct hdmi_spec_per_pin *per_pin;
384a48d7 1403 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1404 int cvt_idx, mux_idx = 0;
bbbe3390 1405
42b29870
LY		 1406 /* pin_idx < 0 means no pin will be bound to the converter */
1407 if (pin_idx < 0)
1408 per_pin = NULL;
1409 else
1410 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1411
1412 /* Dynamically assign converter to stream */
1413 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1414 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1415
384a48d7
SW		 1416 /* Must not already be assigned */
1417 if (per_cvt->assigned)
1418 continue;
42b29870
LY		 1419 if (per_pin == NULL)
1420 break;
384a48d7
SW		 1421 /* Must be in pin's mux's list of converters */
1422 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1423 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1424 break;
1425 /* Not in mux list */
1426 if (mux_idx == per_pin->num_mux_nids)
1427 continue;
1428 break;
1429 }
7ef166b8 1430
384a48d7
SW		 1431 /* No free converters */
1432 if (cvt_idx == spec->num_cvts)
42b29870 1433 return -EBUSY;
384a48d7 1434
42b29870
LY		 1435 if (per_pin != NULL)
1436 per_pin->mux_idx = mux_idx;
2df6742f 1437
7ef166b8
WX		 1438 if (cvt_id)
1439 *cvt_id = cvt_idx;
1440 if (mux_id)
1441 *mux_id = mux_idx;
1442
1443 return 0;
1444}
1445
2df6742f
ML		 1446/* Assure the pin select the right convetor */
1447static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1448 struct hdmi_spec_per_pin *per_pin)
1449{
1450 hda_nid_t pin_nid = per_pin->pin_nid;
1451 int mux_idx, curr;
1452
1453 mux_idx = per_pin->mux_idx;
1454 curr = snd_hda_codec_read(codec, pin_nid, 0,
1455 AC_VERB_GET_CONNECT_SEL, 0);
1456 if (curr != mux_idx)
1457 snd_hda_codec_write_cache(codec, pin_nid, 0,
1458 AC_VERB_SET_CONNECT_SEL,
1459 mux_idx);
1460}
1461
42b29870
LY		 1462/* get the mux index for the converter of the pins
1463 * converter's mux index is the same for all pins on Intel platform
1464 */
1465static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1466 hda_nid_t cvt_nid)
1467{
1468 int i;
1469
1470 for (i = 0; i < spec->num_cvts; i++)
1471 if (spec->cvt_nids[i] == cvt_nid)
1472 return i;
1473 return -EINVAL;
1474}
1475
300016b9
ML		 1476/* Intel HDMI workaround to fix audio routing issue:
1477 * For some Intel display codecs, pins share the same connection list.
1478 * So a conveter can be selected by multiple pins and playback on any of these
1479 * pins will generate sound on the external display, because audio flows from
1480 * the same converter to the display pipeline. Also muting one pin may make
1481 * other pins have no sound output.
1482 * So this function assures that an assigned converter for a pin is not selected
1483 * by any other pins.
1484 */
1485static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1486 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1487{
1488 struct hdmi_spec *spec = codec->spec;
7639a06c 1489 hda_nid_t nid;
f82d7d16
ML		 1490 int cvt_idx, curr;
1491 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1492
f82d7d16 1493 /* configure all pins, including "no physical connection" ones */
7639a06c 1494 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 1495 unsigned int wid_caps = get_wcaps(codec, nid);
1496 unsigned int wid_type = get_wcaps_type(wid_caps);
1497
1498 if (wid_type != AC_WID_PIN)
1499 continue;
7ef166b8 1500
f82d7d16 1501 if (nid == pin_nid)
7ef166b8
WX		 1502 continue;
1503
f82d7d16 1504 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1505 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1506 if (curr != mux_idx)
1507 continue;
7ef166b8 1508
f82d7d16
ML		 1509 /* choose an unassigned converter. The conveters in the
1510 * connection list are in the same order as in the codec.
1511 */
1512 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1513 per_cvt = get_cvt(spec, cvt_idx);
1514 if (!per_cvt->assigned) {
4e76a883
TI		 1515 codec_dbg(codec,
1516 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1517 cvt_idx, nid);
1518 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1519 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1520 cvt_idx);
1521 break;
1522 }
7ef166b8
WX		 1523 }
1524 }
1525}
1526
42b29870
LY		 1527/* A wrapper of intel_not_share_asigned_cvt() */
1528static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1529 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1530{
1531 int mux_idx;
1532 struct hdmi_spec *spec = codec->spec;
1533
1534 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1535 return;
1536
1537 /* On Intel platform, the mapping of converter nid to
1538 * mux index of the pins are always the same.
1539 * The pin nid may be 0, this means all pins will not
1540 * share the converter.
1541 */
1542 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1543 if (mux_idx >= 0)
1544 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1545}
1546
1547/* called in hdmi_pcm_open when no pin is assigned to the PCM
1548 * in dyn_pcm_assign mode.
1549 */
1550static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1551 struct hda_codec *codec,
1552 struct snd_pcm_substream *substream)
1553{
1554 struct hdmi_spec *spec = codec->spec;
1555 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1556 int cvt_idx, pcm_idx;
42b29870
LY		 1557 struct hdmi_spec_per_cvt *per_cvt = NULL;
1558 int err;
1559
ac98379a
LY		 1560 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1561 if (pcm_idx < 0)
1562 return -EINVAL;
1563
42b29870
LY		 1564 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1565 if (err)
1566 return err;
1567
1568 per_cvt = get_cvt(spec, cvt_idx);
1569 per_cvt->assigned = 1;
1570 hinfo->nid = per_cvt->cvt_nid;
1571
1572 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1573
ac98379a 1574 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1575 /* todo: setup spdif ctls assign */
1576
1577 /* Initially set the converter's capabilities */
1578 hinfo->channels_min = per_cvt->channels_min;
1579 hinfo->channels_max = per_cvt->channels_max;
1580 hinfo->rates = per_cvt->rates;
1581 hinfo->formats = per_cvt->formats;
1582 hinfo->maxbps = per_cvt->maxbps;
1583
1584 /* Store the updated parameters */
1585 runtime->hw.channels_min = hinfo->channels_min;
1586 runtime->hw.channels_max = hinfo->channels_max;
1587 runtime->hw.formats = hinfo->formats;
1588 runtime->hw.rates = hinfo->rates;
1589
1590 snd_pcm_hw_constraint_step(substream->runtime, 0,
1591 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1592 return 0;
1593}
1594
7ef166b8
WX		 1595/*
1596 * HDA PCM callbacks
1597 */
1598static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1599 struct hda_codec *codec,
1600 struct snd_pcm_substream *substream)
1601{
1602 struct hdmi_spec *spec = codec->spec;
1603 struct snd_pcm_runtime *runtime = substream->runtime;
2bf3c85a 1604 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
7ef166b8
WX		 1605 struct hdmi_spec_per_pin *per_pin;
1606 struct hdmi_eld *eld;
1607 struct hdmi_spec_per_cvt *per_cvt = NULL;
1608 int err;
1609
1610 /* Validate hinfo */
2bf3c85a
LY		 1611 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1612 if (pcm_idx < 0)
7ef166b8 1613 return -EINVAL;
2bf3c85a 1614
42b29870 1615 mutex_lock(&spec->pcm_lock);
4e76a883 1616 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1617 if (!spec->dyn_pcm_assign) {
1618 if (snd_BUG_ON(pin_idx < 0)) {
1619 mutex_unlock(&spec->pcm_lock);
1620 return -EINVAL;
1621 }
1622 } else {
1623 /* no pin is assigned to the PCM
1624 * PA need pcm open successfully when probe
1625 */
1626 if (pin_idx < 0) {
1627 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1628 mutex_unlock(&spec->pcm_lock);
1629 return err;
1630 }
1631 }
7ef166b8
WX		 1632
1633 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
42b29870
LY		 1634 if (err < 0) {
1635 mutex_unlock(&spec->pcm_lock);
7ef166b8 1636 return err;
42b29870 1637 }
7ef166b8
WX		 1638
1639 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1640 /* Claim converter */
1641 per_cvt->assigned = 1;
42b29870 1642
ac98379a 1643 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1644 per_pin = get_pin(spec, pin_idx);
1df5a06a 1645 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1646 hinfo->nid = per_cvt->cvt_nid;
1647
bddee96b 1648 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1649 AC_VERB_SET_CONNECT_SEL,
1650 mux_idx);
7ef166b8
WX		 1651
1652 /* configure unused pins to choose other converters */
ca2e7224 1653 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
300016b9 1654 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1655
2bf3c85a 1656 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1657
2def8172 1658 /* Initially set the converter's capabilities */
384a48d7
SW		 1659 hinfo->channels_min = per_cvt->channels_min;
1660 hinfo->channels_max = per_cvt->channels_max;
1661 hinfo->rates = per_cvt->rates;
1662 hinfo->formats = per_cvt->formats;
1663 hinfo->maxbps = per_cvt->maxbps;
2def8172 1664
42b29870 1665 eld = &per_pin->sink_eld;
384a48d7 1666 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1667 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1668 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1669 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1670 !hinfo->rates || !hinfo->formats) {
1671 per_cvt->assigned = 0;
1672 hinfo->nid = 0;
2bf3c85a 1673 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
42b29870 1674 mutex_unlock(&spec->pcm_lock);
bbbe3390 1675 return -ENODEV;
2ad779b7 1676 }
bbbe3390 1677 }
2def8172 1678
42b29870 1679 mutex_unlock(&spec->pcm_lock);
2def8172 1680 /* Store the updated parameters */
639cef0e
TI		 1681 runtime->hw.channels_min = hinfo->channels_min;
1682 runtime->hw.channels_max = hinfo->channels_max;
1683 runtime->hw.formats = hinfo->formats;
1684 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1685
1686 snd_pcm_hw_constraint_step(substream->runtime, 0,
1687 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1688 return 0;
1689}
1690
079d88cc
WF		 1691/*
1692 * HDA/HDMI auto parsing
1693 */
384a48d7 1694static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1695{
1696 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1697 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1698 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1699
1700 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1701 codec_warn(codec,
1702 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1703 pin_nid, get_wcaps(codec, pin_nid));
1704 return -EINVAL;
1705 }
1706
384a48d7
SW		 1707 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1708 per_pin->mux_nids,
1709 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1710
1711 return 0;
1712}
1713
a76056f2
LY		 1714static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1715 struct hdmi_spec_per_pin *per_pin)
1716{
1717 int i;
1718
1719 /* try the prefer PCM */
1720 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1721 return per_pin->pin_nid_idx;
1722
1723 /* have a second try; check the "reserved area" over num_pins */
1724 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1725 if (!test_bit(i, &spec->pcm_bitmap))
1726 return i;
1727 }
1728
1729 /* the last try; check the empty slots in pins */
1730 for (i = 0; i < spec->num_pins; i++) {
1731 if (!test_bit(i, &spec->pcm_bitmap))
1732 return i;
1733 }
1734 return -EBUSY;
1735}
1736
1737static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1738 struct hdmi_spec_per_pin *per_pin)
1739{
1740 int idx;
1741
1742 /* pcm already be attached to the pin */
1743 if (per_pin->pcm)
1744 return;
1745 idx = hdmi_find_pcm_slot(spec, per_pin);
1746 if (idx == -ENODEV)
1747 return;
1748 per_pin->pcm_idx = idx;
2bea241a 1749 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1750 set_bit(idx, &spec->pcm_bitmap);
1751}
1752
1753static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1754 struct hdmi_spec_per_pin *per_pin)
1755{
1756 int idx;
1757
1758 /* pcm already be detached from the pin */
1759 if (!per_pin->pcm)
1760 return;
1761 idx = per_pin->pcm_idx;
1762 per_pin->pcm_idx = -1;
1763 per_pin->pcm = NULL;
1764 if (idx >= 0 && idx < spec->pcm_used)
1765 clear_bit(idx, &spec->pcm_bitmap);
1766}
1767
ac98379a
LY		 1768static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1769 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1770{
1771 int mux_idx;
1772
1773 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1774 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1775 break;
1776 return mux_idx;
1777}
1778
1779static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1780
1781static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1782 struct hdmi_spec_per_pin *per_pin)
1783{
1784 struct hda_codec *codec = per_pin->codec;
1785 struct hda_pcm *pcm;
1786 struct hda_pcm_stream *hinfo;
1787 struct snd_pcm_substream *substream;
1788 int mux_idx;
1789 bool non_pcm;
1790
1791 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1792 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1793 else
1794 return;
1795 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1796 return;
1797
1798 /* hdmi audio only uses playback and one substream */
1799 hinfo = pcm->stream;
1800 substream = pcm->pcm->streams[0].substream;
1801
1802 per_pin->cvt_nid = hinfo->nid;
1803
1804 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1805 if (mux_idx < per_pin->num_mux_nids)
1806 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1807 AC_VERB_SET_CONNECT_SEL,
1808 mux_idx);
1809 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1810
1811 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1812 if (substream->runtime)
1813 per_pin->channels = substream->runtime->channels;
1814 per_pin->setup = true;
1815 per_pin->mux_idx = mux_idx;
1816
1817 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1818}
1819
1820static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1821 struct hdmi_spec_per_pin *per_pin)
1822{
1823 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1824 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1825
1826 per_pin->chmap_set = false;
1827 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1828
1829 per_pin->setup = false;
1830 per_pin->channels = 0;
1831}
1832
e90247f9
TI		 1833/* update per_pin ELD from the given new ELD;
1834 * setup info frame and notification accordingly
1835 */
1836static void update_eld(struct hda_codec *codec,
1837 struct hdmi_spec_per_pin *per_pin,
1838 struct hdmi_eld *eld)
1839{
1840 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1841 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1842 bool old_eld_valid = pin_eld->eld_valid;
1843 bool eld_changed;
1844
a76056f2 1845 if (spec->dyn_pcm_assign) {
ac98379a 1846 if (eld->eld_valid) {
a76056f2 1847 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1848 hdmi_pcm_setup_pin(spec, per_pin);
1849 } else {
1850 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1851 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1852 }
a76056f2
LY		 1853 }
1854
e90247f9
TI		 1855 if (eld->eld_valid)
1856 snd_hdmi_show_eld(codec, &eld->info);
1857
1858 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1859 if (eld->eld_valid && pin_eld->eld_valid)
1860 if (pin_eld->eld_size != eld->eld_size ||
1861 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1862 eld->eld_size) != 0)
1863 eld_changed = true;
1864
1865 pin_eld->eld_valid = eld->eld_valid;
1866 pin_eld->eld_size = eld->eld_size;
1867 if (eld->eld_valid)
1868 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1869 pin_eld->info = eld->info;
1870
1871 /*
1872 * Re-setup pin and infoframe. This is needed e.g. when
1873 * - sink is first plugged-in
1874 * - transcoder can change during stream playback on Haswell
1875 * and this can make HW reset converter selection on a pin.
1876 */
1877 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1878 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1879 intel_verify_pin_cvt_connect(codec, per_pin);
1880 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1881 per_pin->mux_idx);
1882 }
1883
1884 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1885 }
1886
1887 if (eld_changed)
1888 snd_ctl_notify(codec->card,
1889 SNDRV_CTL_EVENT_MASK_VALUE |
1890 SNDRV_CTL_EVENT_MASK_INFO,
1891 &per_pin->eld_ctl->id);
1892}
1893
788d441a
TI		 1894/* update ELD and jack state via HD-audio verbs */
1895static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1896 int repoll)
079d88cc 1897{
464837a7 1898 struct hda_jack_tbl *jack;
744626da 1899 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1900 struct hdmi_spec *spec = codec->spec;
1901 struct hdmi_eld *eld = &spec->temp_eld;
1902 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1903 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1904 /*
1905 * Always execute a GetPinSense verb here, even when called from
1906 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1907 * response's PD bit is not the real PD value, but indicates that
1908 * the real PD value changed. An older version of the HD-audio
1909 * specification worked this way. Hence, we just ignore the data in
1910 * the unsolicited response to avoid custom WARs.
1911 */
da4a7a39 1912 int present;
efe47108 1913 bool ret;
9a5e5234 1914 bool do_repoll = false;
079d88cc 1915
664c7155 1916 snd_hda_power_up_pm(codec);
da4a7a39
DH		 1917 present = snd_hda_pin_sense(codec, pin_nid);
1918
a4e9a38b 1919 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1920 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1921 if (pin_eld->monitor_present)
1922 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1923 else
1924 eld->eld_valid = false;
079d88cc 1925
4e76a883 1926 codec_dbg(codec,
384a48d7 1927 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1928 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1929
4bd038f9 1930 if (eld->eld_valid) {
307229d2 1931 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1932 &eld->eld_size) < 0)
4bd038f9 1933 eld->eld_valid = false;
1613d6b4 1934 else {
79514d47 1935 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1936 eld->eld_size) < 0)
4bd038f9 1937 eld->eld_valid = false;
1613d6b4 1938 }
9a5e5234
TI		 1939 if (!eld->eld_valid && repoll)
1940 do_repoll = true;
744626da 1941 }
4bd038f9 1942
9a5e5234 1943 if (do_repoll)
e90247f9
TI		 1944 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1945 else
1946 update_eld(codec, per_pin, eld);
92c69e79 1947
aff747eb 1948 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1949
1950 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1951 if (jack)
1952 jack->block_report = !ret;
1953
a4e9a38b 1954 mutex_unlock(&per_pin->lock);
664c7155 1955 snd_hda_power_down_pm(codec);
efe47108 1956 return ret;
079d88cc
WF		 1957}
1958
3184270e
LY		 1959static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1960 struct hdmi_spec_per_pin *per_pin)
1961{
1962 struct hdmi_spec *spec = codec->spec;
1963 struct snd_jack *jack = NULL;
1964 struct hda_jack_tbl *jack_tbl;
1965
1966 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1967 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1968 * NULL even after snd_hda_jack_tbl_clear() is called to
1969 * free snd_jack. This may cause access invalid memory
1970 * when calling snd_jack_report
1971 */
1972 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1973 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1974 else if (!spec->dyn_pcm_assign) {
1975 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1976 if (jack_tbl)
1977 jack = jack_tbl->jack;
1978 }
1979 return jack;
1980}
1981
788d441a
TI		 1982/* update ELD and jack state via audio component */
1983static void sync_eld_via_acomp(struct hda_codec *codec,
1984 struct hdmi_spec_per_pin *per_pin)
1985{
788d441a
TI		 1986 struct hdmi_spec *spec = codec->spec;
1987 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1988 struct snd_jack *jack = NULL;
788d441a
TI		 1989 int size;
1990
e2dc7d7d
TI		 1991 mutex_lock(&per_pin->lock);
1992 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1993 &eld->monitor_present, eld->eld_buffer,
1994 ELD_MAX_SIZE);
1995 if (size < 0)
1996 goto unlock;
1997 if (size > 0) {
1998 size = min(size, ELD_MAX_SIZE);
1999 if (snd_hdmi_parse_eld(codec, &eld->info,
2000 eld->eld_buffer, size) < 0)
2001 size = -EINVAL;
2002 }
788d441a 2003
e2dc7d7d
TI		 2004 if (size > 0) {
2005 eld->eld_valid = true;
2006 eld->eld_size = size;
2007 } else {
2008 eld->eld_valid = false;
2009 eld->eld_size = 0;
788d441a 2010 }
e2dc7d7d 2011
25e4abb3
LY		 2012 /* pcm_idx >=0 before update_eld() means it is in monitor
2013 * disconnected event. Jack must be fetched before update_eld()
2014 */
3184270e 2015 jack = pin_idx_to_jack(codec, per_pin);
e2dc7d7d 2016 update_eld(codec, per_pin, eld);
3184270e
LY		 2017 if (jack == NULL)
2018 jack = pin_idx_to_jack(codec, per_pin);
25e4abb3
LY		 2019 if (jack == NULL)
2020 goto unlock;
2021 snd_jack_report(jack,
e2dc7d7d
TI		 2022 eld->monitor_present ? SND_JACK_AVOUT : 0);
2023 unlock:
2024 mutex_unlock(&per_pin->lock);
788d441a
TI		 2025}
2026
2027static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
2028{
2029 struct hda_codec *codec = per_pin->codec;
a76056f2
LY		 2030 struct hdmi_spec *spec = codec->spec;
2031 int ret;
788d441a 2032
a76056f2 2033 mutex_lock(&spec->pcm_lock);
788d441a
TI		 2034 if (codec_has_acomp(codec)) {
2035 sync_eld_via_acomp(codec, per_pin);
a76056f2 2036 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 2037 } else {
a76056f2 2038 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
788d441a 2039 }
a76056f2
LY		 2040 mutex_unlock(&spec->pcm_lock);
2041
2042 return ret;
788d441a
TI		 2043}
2044
744626da
WF		 2045static void hdmi_repoll_eld(struct work_struct *work)
2046{
2047 struct hdmi_spec_per_pin *per_pin =
2048 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
2049
c6e8453e
WF		 2050 if (per_pin->repoll_count++ > 6)
2051 per_pin->repoll_count = 0;
2052
efe47108
TI		 2053 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
2054 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 2055}
2056
c88d4e84
TI		 2057static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2058 hda_nid_t nid);
2059
079d88cc
WF		 2060static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
2061{
2062 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2063 unsigned int caps, config;
2064 int pin_idx;
2065 struct hdmi_spec_per_pin *per_pin;
07acecc1 2066 int err;
079d88cc 2067
efc2f8de 2068 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 2069 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
2070 return 0;
2071
efc2f8de 2072 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 2073 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
2074 return 0;
2075
75dcbe4d 2076 if (is_haswell_plus(codec))
c88d4e84
TI		 2077 intel_haswell_fixup_connect_list(codec, pin_nid);
2078
384a48d7 2079 pin_idx = spec->num_pins;
bce0d2a8
TI		 2080 per_pin = snd_array_new(&spec->pins);
2081 if (!per_pin)
2082 return -ENOMEM;
384a48d7
SW		 2083
2084 per_pin->pin_nid = pin_nid;
1a6003b5 2085 per_pin->non_pcm = false;
a76056f2
LY		 2086 if (spec->dyn_pcm_assign)
2087 per_pin->pcm_idx = -1;
2bea241a
LY		 2088 else {
2089 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
a76056f2 2090 per_pin->pcm_idx = pin_idx;
2bea241a 2091 }
a76056f2 2092 per_pin->pin_nid_idx = pin_idx;
079d88cc 2093
384a48d7
SW		 2094 err = hdmi_read_pin_conn(codec, pin_idx);
2095 if (err < 0)
2096 return err;
079d88cc 2097
079d88cc
WF		 2098 spec->num_pins++;
2099
384a48d7 2100 return 0;
079d88cc
WF		 2101}
2102
384a48d7 2103static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 2104{
2105 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2106 struct hdmi_spec_per_cvt *per_cvt;
2107 unsigned int chans;
2108 int err;
079d88cc 2109
384a48d7
SW		 2110 chans = get_wcaps(codec, cvt_nid);
2111 chans = get_wcaps_channels(chans);
2112
bce0d2a8
TI		 2113 per_cvt = snd_array_new(&spec->cvts);
2114 if (!per_cvt)
2115 return -ENOMEM;
384a48d7
SW		 2116
2117 per_cvt->cvt_nid = cvt_nid;
2118 per_cvt->channels_min = 2;
d45e6889 2119 if (chans <= 16) {
384a48d7 2120 per_cvt->channels_max = chans;
d45e6889
TI		 2121 if (chans > spec->channels_max)
2122 spec->channels_max = chans;
2123 }
384a48d7
SW		 2124
2125 err = snd_hda_query_supported_pcm(codec, cvt_nid,
2126 &per_cvt->rates,
2127 &per_cvt->formats,
2128 &per_cvt->maxbps);
2129 if (err < 0)
2130 return err;
2131
bce0d2a8
TI		 2132 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
2133 spec->cvt_nids[spec->num_cvts] = cvt_nid;
2134 spec->num_cvts++;
079d88cc
WF		 2135
2136 return 0;
2137}
2138
2139static int hdmi_parse_codec(struct hda_codec *codec)
2140{
2141 hda_nid_t nid;
2142 int i, nodes;
2143
7639a06c 2144 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 2145 if (!nid || nodes < 0) {
4e76a883 2146 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 2147 return -EINVAL;
2148 }
2149
2150 for (i = 0; i < nodes; i++, nid++) {
2151 unsigned int caps;
2152 unsigned int type;
2153
efc2f8de 2154 caps = get_wcaps(codec, nid);
079d88cc
WF		 2155 type = get_wcaps_type(caps);
2156
2157 if (!(caps & AC_WCAP_DIGITAL))
2158 continue;
2159
2160 switch (type) {
2161 case AC_WID_AUD_OUT:
384a48d7 2162 hdmi_add_cvt(codec, nid);
079d88cc
WF		 2163 break;
2164 case AC_WID_PIN:
3eaead57 2165 hdmi_add_pin(codec, nid);
079d88cc
WF		 2166 break;
2167 }
2168 }
2169
079d88cc
WF		 2170 return 0;
2171}
2172
84eb01be
TI		 2173/*
2174 */
1a6003b5
TI		 2175static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2176{
2177 struct hda_spdif_out *spdif;
2178 bool non_pcm;
2179
2180 mutex_lock(&codec->spdif_mutex);
2181 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2182 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2183 mutex_unlock(&codec->spdif_mutex);
2184 return non_pcm;
2185}
2186
84eb01be
TI		 2187/*
2188 * HDMI callbacks
2189 */
2190
2191static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2192 struct hda_codec *codec,
2193 unsigned int stream_tag,
2194 unsigned int format,
2195 struct snd_pcm_substream *substream)
2196{
384a48d7
SW		 2197 hda_nid_t cvt_nid = hinfo->nid;
2198 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 2199 int pin_idx;
2200 struct hdmi_spec_per_pin *per_pin;
2201 hda_nid_t pin_nid;
ddd621fb 2202 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 2203 bool non_pcm;
75fae117 2204 int pinctl;
42b29870 2205 int err;
1a6003b5 2206
42b29870
LY		 2207 mutex_lock(&spec->pcm_lock);
2208 pin_idx = hinfo_to_pin_index(codec, hinfo);
2209 if (spec->dyn_pcm_assign && pin_idx < 0) {
2210 /* when dyn_pcm_assign and pcm is not bound to a pin
2211 * skip pin setup and return 0 to make audio playback
2212 * be ongoing
2213 */
2214 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2215 snd_hda_codec_setup_stream(codec, cvt_nid,
2216 stream_tag, 0, format);
2217 mutex_unlock(&spec->pcm_lock);
2218 return 0;
2219 }
1a6003b5 2220
42b29870
LY		 2221 if (snd_BUG_ON(pin_idx < 0)) {
2222 mutex_unlock(&spec->pcm_lock);
2223 return -EINVAL;
2224 }
2225 per_pin = get_pin(spec, pin_idx);
2226 pin_nid = per_pin->pin_nid;
ca2e7224 2227 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2df6742f
ML		 2228 /* Verify pin:cvt selections to avoid silent audio after S3.
2229 * After S3, the audio driver restores pin:cvt selections
2230 * but this can happen before gfx is ready and such selection
2231 * is overlooked by HW. Thus multiple pins can share a same
2232 * default convertor and mute control will affect each other,
2233 * which can cause a resumed audio playback become silent
2234 * after S3.
2235 */
2236 intel_verify_pin_cvt_connect(codec, per_pin);
2237 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
2238 }
2239
ddd621fb
LY		 2240 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2241 /* Todo: add DP1.2 MST audio support later */
e2dc7d7d 2242 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
ddd621fb 2243
1a6003b5 2244 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 2245 mutex_lock(&per_pin->lock);
b054087d
TI		 2246 per_pin->channels = substream->runtime->channels;
2247 per_pin->setup = true;
384a48d7 2248
b054087d 2249 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 2250 mutex_unlock(&per_pin->lock);
75fae117
SW		 2251 if (spec->dyn_pin_out) {
2252 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
2253 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2254 snd_hda_codec_write(codec, pin_nid, 0,
2255 AC_VERB_SET_PIN_WIDGET_CONTROL,
2256 pinctl | PIN_OUT);
2257 }
2258
42b29870
LY		 2259 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
2260 stream_tag, format);
2261 mutex_unlock(&spec->pcm_lock);
2262 return err;
84eb01be
TI		 2263}
2264
8dfaa573
TI		 2265static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2266 struct hda_codec *codec,
2267 struct snd_pcm_substream *substream)
2268{
2269 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2270 return 0;
2271}
2272
f2ad24fa
TI		 2273static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2274 struct hda_codec *codec,
2275 struct snd_pcm_substream *substream)
384a48d7
SW		 2276{
2277 struct hdmi_spec *spec = codec->spec;
2bf3c85a 2278 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 2279 struct hdmi_spec_per_cvt *per_cvt;
2280 struct hdmi_spec_per_pin *per_pin;
75fae117 2281 int pinctl;
384a48d7 2282
384a48d7 2283 if (hinfo->nid) {
2bf3c85a
LY		 2284 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2285 if (snd_BUG_ON(pcm_idx < 0))
2286 return -EINVAL;
4e76a883 2287 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 2288 if (snd_BUG_ON(cvt_idx < 0))
2289 return -EINVAL;
bce0d2a8 2290 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 2291
2292 snd_BUG_ON(!per_cvt->assigned);
2293 per_cvt->assigned = 0;
2294 hinfo->nid = 0;
2295
42b29870 2296 mutex_lock(&spec->pcm_lock);
b09887f8 2297 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 2298 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 2299 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 2300 if (spec->dyn_pcm_assign && pin_idx < 0) {
2301 mutex_unlock(&spec->pcm_lock);
2302 return 0;
2303 }
2304
2305 if (snd_BUG_ON(pin_idx < 0)) {
2306 mutex_unlock(&spec->pcm_lock);
384a48d7 2307 return -EINVAL;
42b29870 2308 }
bce0d2a8 2309 per_pin = get_pin(spec, pin_idx);
384a48d7 2310
75fae117
SW		 2311 if (spec->dyn_pin_out) {
2312 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2313 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2314 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2315 AC_VERB_SET_PIN_WIDGET_CONTROL,
2316 pinctl & ~PIN_OUT);
2317 }
2318
a4e9a38b 2319 mutex_lock(&per_pin->lock);
d45e6889
TI		 2320 per_pin->chmap_set = false;
2321 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 2322
2323 per_pin->setup = false;
2324 per_pin->channels = 0;
a4e9a38b 2325 mutex_unlock(&per_pin->lock);
42b29870 2326 mutex_unlock(&spec->pcm_lock);
384a48d7 2327 }
d45e6889 2328
384a48d7
SW		 2329 return 0;
2330}
2331
2332static const struct hda_pcm_ops generic_ops = {
2333 .open = hdmi_pcm_open,
f2ad24fa 2334 .close = hdmi_pcm_close,
384a48d7 2335 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2336 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2337};
2338
d45e6889
TI		 2339/*
2340 * ALSA API channel-map control callbacks
2341 */
2342static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
2343 struct snd_ctl_elem_info *uinfo)
2344{
2345 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2346 struct hda_codec *codec = info->private_data;
2347 struct hdmi_spec *spec = codec->spec;
2348 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2349 uinfo->count = spec->channels_max;
2350 uinfo->value.integer.min = 0;
2351 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
2352 return 0;
2353}
2354
307229d2
AH		 2355static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2356 int channels)
2357{
2358 /* If the speaker allocation matches the channel count, it is OK.*/
2359 if (cap->channels != channels)
2360 return -1;
2361
2362 /* all channels are remappable freely */
2363 return SNDRV_CTL_TLVT_CHMAP_VAR;
2364}
2365
2366static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
2367 unsigned int *chmap, int channels)
2368{
2369 int count = 0;
2370 int c;
2371
2372 for (c = 7; c >= 0; c--) {
2373 int spk = cap->speakers[c];
2374 if (!spk)
2375 continue;
2376
2377 chmap[count++] = spk_to_chmap(spk);
2378 }
2379
2380 WARN_ON(count != channels);
2381}
2382
d45e6889
TI		 2383static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
2384 unsigned int size, unsigned int __user *tlv)
2385{
2386 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2387 struct hda_codec *codec = info->private_data;
2388 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 2389 unsigned int __user *dst;
2390 int chs, count = 0;
2391
2392 if (size < 8)
2393 return -ENOMEM;
2394 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
2395 return -EFAULT;
2396 size -= 8;
2397 dst = tlv + 2;
498dab3a 2398 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 2399 int i;
d45e6889
TI		 2400 struct cea_channel_speaker_allocation *cap;
2401 cap = channel_allocations;
2402 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
2403 int chs_bytes = chs * 4;
307229d2
AH		 2404 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
2405 unsigned int tlv_chmap[8];
2406
2407 if (type < 0)
d45e6889 2408 continue;
d45e6889
TI		 2409 if (size < 8)
2410 return -ENOMEM;
307229d2 2411 if (put_user(type, dst) ||
d45e6889
TI		 2412 put_user(chs_bytes, dst + 1))
2413 return -EFAULT;
2414 dst += 2;
2415 size -= 8;
2416 count += 8;
2417 if (size < chs_bytes)
2418 return -ENOMEM;
2419 size -= chs_bytes;
2420 count += chs_bytes;
307229d2
AH		 2421 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
2422 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2423 return -EFAULT;
2424 dst += chs;
d45e6889
TI		 2425 }
2426 }
2427 if (put_user(count, tlv + 1))
2428 return -EFAULT;
2429 return 0;
2430}
2431
2432static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2433 struct snd_ctl_elem_value *ucontrol)
2434{
2435 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2436 struct hda_codec *codec = info->private_data;
2437 struct hdmi_spec *spec = codec->spec;
022f344b
LY		 2438 int pcm_idx = kcontrol->private_value;
2439 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
d45e6889
TI		 2440 int i;
2441
022f344b
LY		 2442 if (!per_pin) {
2443 for (i = 0; i < spec->channels_max; i++)
2444 ucontrol->value.integer.value[i] = 0;
2445 return 0;
2446 }
2447
d45e6889
TI		 2448 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2449 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2450 return 0;
2451}
2452
2453static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2454 struct snd_ctl_elem_value *ucontrol)
2455{
2456 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2457 struct hda_codec *codec = info->private_data;
2458 struct hdmi_spec *spec = codec->spec;
022f344b
LY		 2459 int pcm_idx = kcontrol->private_value;
2460 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
d45e6889
TI		 2461 unsigned int ctl_idx;
2462 struct snd_pcm_substream *substream;
2463 unsigned char chmap[8];
307229d2 2464 int i, err, ca, prepared = 0;
d45e6889 2465
022f344b
LY		 2466 /* No monitor is connected in dyn_pcm_assign.
2467 * It's invalid to setup the chmap
2468 */
2469 if (!per_pin)
2470 return 0;
2471
d45e6889
TI		 2472 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2473 substream = snd_pcm_chmap_substream(info, ctl_idx);
2474 if (!substream || !substream->runtime)
6f54c361 2475 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 2476 switch (substream->runtime->status->state) {
2477 case SNDRV_PCM_STATE_OPEN:
2478 case SNDRV_PCM_STATE_SETUP:
2479 break;
2480 case SNDRV_PCM_STATE_PREPARED:
2481 prepared = 1;
2482 break;
2483 default:
2484 return -EBUSY;
2485 }
2486 memset(chmap, 0, sizeof(chmap));
2487 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2488 chmap[i] = ucontrol->value.integer.value[i];
2489 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2490 return 0;
2491 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2492 if (ca < 0)
2493 return -EINVAL;
307229d2
AH		 2494 if (spec->ops.chmap_validate) {
2495 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2496 if (err)
2497 return err;
2498 }
a4e9a38b 2499 mutex_lock(&per_pin->lock);
d45e6889
TI		 2500 per_pin->chmap_set = true;
2501 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2502 if (prepared)
b054087d 2503 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2504 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2505
2506 return 0;
2507}
2508
84eb01be
TI		 2509static int generic_hdmi_build_pcms(struct hda_codec *codec)
2510{
2511 struct hdmi_spec *spec = codec->spec;
384a48d7 2512 int pin_idx;
84eb01be 2513
384a48d7
SW		 2514 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2515 struct hda_pcm *info;
84eb01be 2516 struct hda_pcm_stream *pstr;
bce0d2a8 2517
bbbc7e85 2518 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 2519 if (!info)
2520 return -ENOMEM;
2bea241a
LY		 2521
2522 spec->pcm_rec[pin_idx].pcm = info;
2bf3c85a 2523 spec->pcm_used++;
84eb01be 2524 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2525 info->own_chmap = true;
384a48d7 2526
84eb01be 2527 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2528 pstr->substreams = 1;
2529 pstr->ops = generic_ops;
2530 /* other pstr fields are set in open */
84eb01be
TI		 2531 }
2532
2533 return 0;
2534}
2535
25e4abb3 2536static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 2537{
25e4abb3 2538 struct hdmi_pcm *pcm = jack->private_data;
788d441a 2539
25e4abb3 2540 pcm->jack = NULL;
788d441a
TI		 2541}
2542
25e4abb3
LY		 2543static int add_hdmi_jack_kctl(struct hda_codec *codec,
2544 struct hdmi_spec *spec,
2545 int pcm_idx,
788d441a
TI		 2546 const char *name)
2547{
2548 struct snd_jack *jack;
2549 int err;
2550
2551 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2552 true, false);
2553 if (err < 0)
2554 return err;
25e4abb3
LY		 2555
2556 spec->pcm_rec[pcm_idx].jack = jack;
2557 jack->private_data = &spec->pcm_rec[pcm_idx];
2558 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 2559 return 0;
2560}
2561
25e4abb3 2562static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 2563{
31ef2257 2564 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2565 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 2566 struct hdmi_spec_per_pin *per_pin;
2567 struct hda_jack_tbl *jack;
2568 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 2569 bool phantom_jack;
25e4abb3 2570 int ret;
0b6c49b5 2571
31ef2257
TI		 2572 if (pcmdev > 0)
2573 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 2574
2575 if (spec->dyn_pcm_assign)
2576 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2577
2578 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2579 /* if !dyn_pcm_assign, it must be non-MST mode.
2580 * This means pcms and pins are statically mapped.
2581 * And pcm_idx is pin_idx.
2582 */
2583 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 2584 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2585 if (phantom_jack)
30efd8de
DH		 2586 strncat(hdmi_str, " Phantom",
2587 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3
LY		 2588 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2589 phantom_jack);
2590 if (ret < 0)
2591 return ret;
2592 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2593 if (jack == NULL)
2594 return 0;
2595 /* assign jack->jack to pcm_rec[].jack to
2596 * align with dyn_pcm_assign mode
2597 */
2598 spec->pcm_rec[pcm_idx].jack = jack->jack;
2599 return 0;
0b6c49b5
DH		 2600}
2601
84eb01be
TI		 2602static int generic_hdmi_build_controls(struct hda_codec *codec)
2603{
2604 struct hdmi_spec *spec = codec->spec;
2605 int err;
25e4abb3 2606 int pin_idx, pcm_idx;
84eb01be 2607
0b6c49b5 2608
25e4abb3
LY		 2609 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2610 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 2611 if (err < 0)
2612 return err;
2613
b09887f8
LY		 2614 /* create the spdif for each pcm
2615 * pin will be bound when monitor is connected
2616 */
2617 if (spec->dyn_pcm_assign)
2618 err = snd_hda_create_dig_out_ctls(codec,
2619 0, spec->cvt_nids[0],
2620 HDA_PCM_TYPE_HDMI);
2621 else {
2622 struct hdmi_spec_per_pin *per_pin =
2623 get_pin(spec, pcm_idx);
2624 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2625 per_pin->pin_nid,
2626 per_pin->mux_nids[0],
2627 HDA_PCM_TYPE_HDMI);
b09887f8 2628 }
84eb01be
TI		 2629 if (err < 0)
2630 return err;
b09887f8
LY		 2631 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2632 }
2633
2634 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2635 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
14bc52b8
PLB		 2636
2637 /* add control for ELD Bytes */
bce0d2a8 2638 err = hdmi_create_eld_ctl(codec, pin_idx,
2bea241a 2639 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2640
2641 if (err < 0)
2642 return err;
31ef2257 2643
82b1d73f 2644 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2645 }
2646
d45e6889 2647 /* add channel maps */
022f344b 2648 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2649 struct hda_pcm *pcm;
d45e6889
TI		 2650 struct snd_pcm_chmap *chmap;
2651 struct snd_kcontrol *kctl;
2652 int i;
2ca320e2 2653
022f344b 2654 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2655 if (!pcm || !pcm->pcm)
2ca320e2 2656 break;
bbbc7e85 2657 err = snd_pcm_add_chmap_ctls(pcm->pcm,
d45e6889 2658 SNDRV_PCM_STREAM_PLAYBACK,
022f344b 2659 NULL, 0, pcm_idx, &chmap);
d45e6889
TI		 2660 if (err < 0)
2661 return err;
2662 /* override handlers */
2663 chmap->private_data = codec;
2664 kctl = chmap->kctl;
2665 for (i = 0; i < kctl->count; i++)
2666 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2667 kctl->info = hdmi_chmap_ctl_info;
2668 kctl->get = hdmi_chmap_ctl_get;
2669 kctl->put = hdmi_chmap_ctl_put;
2670 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2671 }
2672
84eb01be
TI		 2673 return 0;
2674}
2675
8b8d654b 2676static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2677{
2678 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2679 int pin_idx;
2680
2681 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2682 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2683
744626da 2684 per_pin->codec = codec;
a4e9a38b 2685 mutex_init(&per_pin->lock);
744626da 2686 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2687 eld_proc_new(per_pin, pin_idx);
84eb01be 2688 }
8b8d654b
TI		 2689 return 0;
2690}
2691
2692static int generic_hdmi_init(struct hda_codec *codec)
2693{
2694 struct hdmi_spec *spec = codec->spec;
2695 int pin_idx;
2696
2697 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2698 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2699 hda_nid_t pin_nid = per_pin->pin_nid;
2700
2701 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2702 if (!codec_has_acomp(codec))
2703 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2704 codec->jackpoll_interval > 0 ?
2705 jack_callback : NULL);
8b8d654b 2706 }
84eb01be
TI		 2707 return 0;
2708}
2709
bce0d2a8
TI		 2710static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2711{
2712 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2713 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2714}
2715
2716static void hdmi_array_free(struct hdmi_spec *spec)
2717{
2718 snd_array_free(&spec->pins);
2719 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2720}
2721
84eb01be
TI		 2722static void generic_hdmi_free(struct hda_codec *codec)
2723{
2724 struct hdmi_spec *spec = codec->spec;
25e4abb3 2725 int pin_idx, pcm_idx;
384a48d7 2726
6603249d 2727 if (codec_has_acomp(codec))
25adc137
DH		 2728 snd_hdac_i915_register_notifier(NULL);
2729
384a48d7 2730 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2731 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2732 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2733 eld_proc_free(per_pin);
25e4abb3
LY		 2734 }
2735
2736 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2737 if (spec->pcm_rec[pcm_idx].jack == NULL)
2738 continue;
2739 if (spec->dyn_pcm_assign)
2740 snd_device_free(codec->card,
2741 spec->pcm_rec[pcm_idx].jack);
2742 else
2743 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2744 }
84eb01be 2745
55913110
TI		 2746 if (spec->i915_bound)
2747 snd_hdac_i915_exit(&codec->bus->core);
bce0d2a8 2748 hdmi_array_free(spec);
84eb01be
TI		 2749 kfree(spec);
2750}
2751
28cb72e5
WX		 2752#ifdef CONFIG_PM
2753static int generic_hdmi_resume(struct hda_codec *codec)
2754{
2755 struct hdmi_spec *spec = codec->spec;
2756 int pin_idx;
2757
a2833683 2758 codec->patch_ops.init(codec);
eeecd9d1 2759 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2760
2761 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2762 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2763 hdmi_present_sense(per_pin, 1);
2764 }
2765 return 0;
2766}
2767#endif
2768
fb79e1e0 2769static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2770 .init = generic_hdmi_init,
2771 .free = generic_hdmi_free,
2772 .build_pcms = generic_hdmi_build_pcms,
2773 .build_controls = generic_hdmi_build_controls,
2774 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2775#ifdef CONFIG_PM
2776 .resume = generic_hdmi_resume,
2777#endif
84eb01be
TI		 2778};
2779
307229d2
AH		 2780static const struct hdmi_ops generic_standard_hdmi_ops = {
2781 .pin_get_eld = snd_hdmi_get_eld,
2782 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2783 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2784 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2785 .pin_hbr_setup = hdmi_pin_hbr_setup,
2786 .setup_stream = hdmi_setup_stream,
2787 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2788 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2789};
2790
6ffe168f 2791
c88d4e84
TI		 2792static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2793 hda_nid_t nid)
2794{
2795 struct hdmi_spec *spec = codec->spec;
2796 hda_nid_t conns[4];
2797 int nconns;
6ffe168f 2798
c88d4e84
TI		 2799 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2800 if (nconns == spec->num_cvts &&
2801 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2802 return;
2803
c88d4e84 2804 /* override pins connection list */
4e76a883 2805 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2806 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2807}
2808
1611a9c9
ML		 2809#define INTEL_VENDOR_NID 0x08
2810#define INTEL_GET_VENDOR_VERB 0xf81
2811#define INTEL_SET_VENDOR_VERB 0x781
2812#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2813#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2814
2815static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2816 bool update_tree)
1611a9c9
ML		 2817{
2818 unsigned int vendor_param;
2819
1611a9c9
ML		 2820 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2821 INTEL_GET_VENDOR_VERB, 0);
2822 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2823 return;
2824
2825 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2826 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2827 INTEL_SET_VENDOR_VERB, vendor_param);
2828 if (vendor_param == -1)
2829 return;
2830
17df3f55
TI		 2831 if (update_tree)
2832 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2833}
2834
c88d4e84
TI		 2835static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2836{
2837 unsigned int vendor_param;
2838
2839 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2840 INTEL_GET_VENDOR_VERB, 0);
2841 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2842 return;
2843
2844 /* enable DP1.2 mode */
2845 vendor_param |= INTEL_EN_DP12;
a551d914 2846 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2847 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2848 INTEL_SET_VENDOR_VERB, vendor_param);
2849}
2850
17df3f55
TI		 2851/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2852 * Otherwise you may get severe h/w communication errors.
2853 */
2854static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2855 unsigned int power_state)
2856{
2857 if (power_state == AC_PWRST_D0) {
2858 intel_haswell_enable_all_pins(codec, false);
2859 intel_haswell_fixup_enable_dp12(codec);
2860 }
c88d4e84 2861
17df3f55
TI		 2862 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2863 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2864}
6ffe168f 2865
f0675d4a 2866static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2867{
2868 struct hda_codec *codec = audio_ptr;
2869 int pin_nid = port + 0x04;
2870
8ae743e8
TI		 2871 /* skip notification during system suspend (but not in runtime PM);
2872 * the state will be updated at resume
2873 */
2874 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2875 return;
eb399d3c
TI		 2876 /* ditto during suspend/resume process itself */
2877 if (atomic_read(&(codec)->core.in_pm))
2878 return;
8ae743e8 2879
25adc137
DH		 2880 check_presence_and_report(codec, pin_nid);
2881}
2882
84eb01be
TI		 2883static int patch_generic_hdmi(struct hda_codec *codec)
2884{
2885 struct hdmi_spec *spec;
84eb01be
TI		 2886
2887 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2888 if (spec == NULL)
2889 return -ENOMEM;
2890
307229d2 2891 spec->ops = generic_standard_hdmi_ops;
42b29870 2892 mutex_init(&spec->pcm_lock);
84eb01be 2893 codec->spec = spec;
bce0d2a8 2894 hdmi_array_init(spec, 4);
6ffe168f 2895
55913110
TI		 2896 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2897 if (!codec_has_acomp(codec) &&
2898 (codec->core.vendor_id >> 16) == 0x8086)
2899 if (!snd_hdac_i915_init(&codec->bus->core))
2900 spec->i915_bound = true;
2901
75dcbe4d 2902 if (is_haswell_plus(codec)) {
17df3f55 2903 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2904 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2905 }
6ffe168f 2906
2bd1f73f
ML		 2907 /* For Valleyview/Cherryview, only the display codec is in the display
2908 * power well and can use link_power ops to request/release the power.
2909 * For Haswell/Broadwell, the controller is also in the power well and
2910 * can cover the codec power request, and so need not set this flag.
2911 * For previous platforms, there is no such power well feature.
2912 */
ff9d8859
LH		 2913 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2914 is_broxton(codec))
2bd1f73f
ML		 2915 codec->core.link_power_control = 1;
2916
6603249d 2917 if (codec_has_acomp(codec)) {
5b8620bb 2918 codec->depop_delay = 0;
25adc137
DH		 2919 spec->i915_audio_ops.audio_ptr = codec;
2920 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2921 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2922 }
5b8620bb 2923
84eb01be 2924 if (hdmi_parse_codec(codec) < 0) {
55913110
TI		 2925 if (spec->i915_bound)
2926 snd_hdac_i915_exit(&codec->bus->core);
84eb01be
TI		 2927 codec->spec = NULL;
2928 kfree(spec);
2929 return -EINVAL;
2930 }
2931 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2932 if (is_haswell_plus(codec)) {
17df3f55 2933 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2934 codec->dp_mst = true;
2935 }
17df3f55 2936
2377c3c3
LH		 2937 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2938 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2939 codec->auto_runtime_pm = 1;
2940
8b8d654b 2941 generic_hdmi_init_per_pins(codec);
84eb01be 2942
84eb01be
TI		 2943 init_channel_allocations();
2944
25e4abb3 2945 WARN_ON(spec->dyn_pcm_assign && !codec_has_acomp(codec));
84eb01be
TI		 2946 return 0;
2947}
2948
3aaf8980
SW		 2949/*
2950 * Shared non-generic implementations
2951 */
2952
2953static int simple_playback_build_pcms(struct hda_codec *codec)
2954{
2955 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2956 struct hda_pcm *info;
8ceb332d
TI		 2957 unsigned int chans;
2958 struct hda_pcm_stream *pstr;
bce0d2a8 2959 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2960
bce0d2a8
TI		 2961 per_cvt = get_cvt(spec, 0);
2962 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2963 chans = get_wcaps_channels(chans);
3aaf8980 2964
bbbc7e85 2965 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2966 if (!info)
2967 return -ENOMEM;
2bea241a 2968 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2969 info->pcm_type = HDA_PCM_TYPE_HDMI;
2970 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2971 *pstr = spec->pcm_playback;
bce0d2a8 2972 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2973 if (pstr->channels_max <= 2 && chans && chans <= 16)
2974 pstr->channels_max = chans;
3aaf8980
SW		 2975
2976 return 0;
2977}
2978
4b6ace9e
TI		 2979/* unsolicited event for jack sensing */
2980static void simple_hdmi_unsol_event(struct hda_codec *codec,
2981 unsigned int res)
2982{
9dd8cf12 2983 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2984 snd_hda_jack_report_sync(codec);
2985}
2986
2987/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2988 * as long as spec->pins[] is set correctly
2989 */
2990#define simple_hdmi_build_jack generic_hdmi_build_jack
2991
3aaf8980
SW		 2992static int simple_playback_build_controls(struct hda_codec *codec)
2993{
2994 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2995 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2996 int err;
3aaf8980 2997
bce0d2a8 2998 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2999 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3000 per_cvt->cvt_nid,
3001 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 3002 if (err < 0)
3003 return err;
3004 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 3005}
3006
4f0110ce
TI		 3007static int simple_playback_init(struct hda_codec *codec)
3008{
3009 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 3010 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3011 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 3012
3013 snd_hda_codec_write(codec, pin, 0,
3014 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3015 /* some codecs require to unmute the pin */
3016 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3017 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3018 AMP_OUT_UNMUTE);
62f949bf 3019 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 3020 return 0;
3021}
3022
3aaf8980
SW		 3023static void simple_playback_free(struct hda_codec *codec)
3024{
3025 struct hdmi_spec *spec = codec->spec;
3026
bce0d2a8 3027 hdmi_array_free(spec);
3aaf8980
SW		 3028 kfree(spec);
3029}
3030
84eb01be
TI		 3031/*
3032 * Nvidia specific implementations
3033 */
3034
3035#define Nv_VERB_SET_Channel_Allocation 0xF79
3036#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3037#define Nv_VERB_SET_Audio_Protection_On 0xF98
3038#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3039
3040#define nvhdmi_master_con_nid_7x 0x04
3041#define nvhdmi_master_pin_nid_7x 0x05
3042
fb79e1e0 3043static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 3044 /*front, rear, clfe, rear_surr */
3045 0x6, 0x8, 0xa, 0xc,
3046};
3047
ceaa86ba
TI		 3048static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3049 /* set audio protect on */
3050 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3051 /* enable digital output on pin widget */
3052 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3053 {} /* terminator */
3054};
3055
3056static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 3057 /* set audio protect on */
3058 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3059 /* enable digital output on pin widget */
3060 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3061 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3062 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3063 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3064 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3065 {} /* terminator */
3066};
3067
3068#ifdef LIMITED_RATE_FMT_SUPPORT
3069/* support only the safe format and rate */
3070#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3071#define SUPPORTED_MAXBPS 16
3072#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3073#else
3074/* support all rates and formats */
3075#define SUPPORTED_RATES \
3076 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3077 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3078 SNDRV_PCM_RATE_192000)
3079#define SUPPORTED_MAXBPS 24
3080#define SUPPORTED_FORMATS \
3081 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3082#endif
3083
ceaa86ba
TI		 3084static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3085{
3086 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3087 return 0;
3088}
3089
3090static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 3091{
ceaa86ba 3092 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 3093 return 0;
3094}
3095
393004b2
ND		 3096static unsigned int channels_2_6_8[] = {
3097 2, 6, 8
3098};
3099
3100static unsigned int channels_2_8[] = {
3101 2, 8
3102};
3103
3104static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3105 .count = ARRAY_SIZE(channels_2_6_8),
3106 .list = channels_2_6_8,
3107 .mask = 0,
3108};
3109
3110static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3111 .count = ARRAY_SIZE(channels_2_8),
3112 .list = channels_2_8,
3113 .mask = 0,
3114};
3115
84eb01be
TI		 3116static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3117 struct hda_codec *codec,
3118 struct snd_pcm_substream *substream)
3119{
3120 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 3121 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3122
b9a94a9c 3123 switch (codec->preset->vendor_id) {
393004b2
ND		 3124 case 0x10de0002:
3125 case 0x10de0003:
3126 case 0x10de0005:
3127 case 0x10de0006:
3128 hw_constraints_channels = &hw_constraints_2_8_channels;
3129 break;
3130 case 0x10de0007:
3131 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3132 break;
3133 default:
3134 break;
3135 }
3136
3137 if (hw_constraints_channels != NULL) {
3138 snd_pcm_hw_constraint_list(substream->runtime, 0,
3139 SNDRV_PCM_HW_PARAM_CHANNELS,
3140 hw_constraints_channels);
ad09fc9d
TI		 3141 } else {
3142 snd_pcm_hw_constraint_step(substream->runtime, 0,
3143 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 3144 }
3145
84eb01be
TI		 3146 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3147}
3148
3149static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3150 struct hda_codec *codec,
3151 struct snd_pcm_substream *substream)
3152{
3153 struct hdmi_spec *spec = codec->spec;
3154 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3155}
3156
3157static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3158 struct hda_codec *codec,
3159 unsigned int stream_tag,
3160 unsigned int format,
3161 struct snd_pcm_substream *substream)
3162{
3163 struct hdmi_spec *spec = codec->spec;
3164 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3165 stream_tag, format, substream);
3166}
3167
d0b1252d
TI		 3168static const struct hda_pcm_stream simple_pcm_playback = {
3169 .substreams = 1,
3170 .channels_min = 2,
3171 .channels_max = 2,
3172 .ops = {
3173 .open = simple_playback_pcm_open,
3174 .close = simple_playback_pcm_close,
3175 .prepare = simple_playback_pcm_prepare
3176 },
3177};
3178
3179static const struct hda_codec_ops simple_hdmi_patch_ops = {
3180 .build_controls = simple_playback_build_controls,
3181 .build_pcms = simple_playback_build_pcms,
3182 .init = simple_playback_init,
3183 .free = simple_playback_free,
250e41ac 3184 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 3185};
3186
3187static int patch_simple_hdmi(struct hda_codec *codec,
3188 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3189{
3190 struct hdmi_spec *spec;
bce0d2a8
TI		 3191 struct hdmi_spec_per_cvt *per_cvt;
3192 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 3193
3194 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3195 if (!spec)
3196 return -ENOMEM;
3197
3198 codec->spec = spec;
bce0d2a8 3199 hdmi_array_init(spec, 1);
d0b1252d
TI		 3200
3201 spec->multiout.num_dacs = 0; /* no analog */
3202 spec->multiout.max_channels = 2;
3203 spec->multiout.dig_out_nid = cvt_nid;
3204 spec->num_cvts = 1;
3205 spec->num_pins = 1;
bce0d2a8
TI		 3206 per_pin = snd_array_new(&spec->pins);
3207 per_cvt = snd_array_new(&spec->cvts);
3208 if (!per_pin || !per_cvt) {
3209 simple_playback_free(codec);
3210 return -ENOMEM;
3211 }
3212 per_cvt->cvt_nid = cvt_nid;
3213 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 3214 spec->pcm_playback = simple_pcm_playback;
3215
3216 codec->patch_ops = simple_hdmi_patch_ops;
3217
3218 return 0;
3219}
3220
1f348522
AP		 3221static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3222 int channels)
3223{
3224 unsigned int chanmask;
3225 int chan = channels ? (channels - 1) : 1;
3226
3227 switch (channels) {
3228 default:
3229 case 0:
3230 case 2:
3231 chanmask = 0x00;
3232 break;
3233 case 4:
3234 chanmask = 0x08;
3235 break;
3236 case 6:
3237 chanmask = 0x0b;
3238 break;
3239 case 8:
3240 chanmask = 0x13;
3241 break;
3242 }
3243
3244 /* Set the audio infoframe channel allocation and checksum fields. The
3245 * channel count is computed implicitly by the hardware. */
3246 snd_hda_codec_write(codec, 0x1, 0,
3247 Nv_VERB_SET_Channel_Allocation, chanmask);
3248
3249 snd_hda_codec_write(codec, 0x1, 0,
3250 Nv_VERB_SET_Info_Frame_Checksum,
3251 (0x71 - chan - chanmask));
3252}
3253
84eb01be
TI		 3254static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3255 struct hda_codec *codec,
3256 struct snd_pcm_substream *substream)
3257{
3258 struct hdmi_spec *spec = codec->spec;
3259 int i;
3260
3261 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3262 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3263 for (i = 0; i < 4; i++) {
3264 /* set the stream id */
3265 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3266 AC_VERB_SET_CHANNEL_STREAMID, 0);
3267 /* set the stream format */
3268 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3269 AC_VERB_SET_STREAM_FORMAT, 0);
3270 }
3271
1f348522
AP		 3272 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3273 * streams are disabled. */
3274 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3275
84eb01be
TI		 3276 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3277}
3278
3279static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3280 struct hda_codec *codec,
3281 unsigned int stream_tag,
3282 unsigned int format,
3283 struct snd_pcm_substream *substream)
3284{
3285 int chs;
112daa7a 3286 unsigned int dataDCC2, channel_id;
84eb01be 3287 int i;
7c935976 3288 struct hdmi_spec *spec = codec->spec;
e3245cdd 3289 struct hda_spdif_out *spdif;
bce0d2a8 3290 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3291
3292 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3293 per_cvt = get_cvt(spec, 0);
3294 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3295
3296 chs = substream->runtime->channels;
84eb01be 3297
84eb01be
TI		 3298 dataDCC2 = 0x2;
3299
84eb01be 3300 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3301 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3302 snd_hda_codec_write(codec,
3303 nvhdmi_master_con_nid_7x,
3304 0,
3305 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3306 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3307
3308 /* set the stream id */
3309 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3310 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3311
3312 /* set the stream format */
3313 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3314 AC_VERB_SET_STREAM_FORMAT, format);
3315
3316 /* turn on again (if needed) */
3317 /* enable and set the channel status audio/data flag */
7c935976 3318 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3319 snd_hda_codec_write(codec,
3320 nvhdmi_master_con_nid_7x,
3321 0,
3322 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3323 spdif->ctls & 0xff);
84eb01be
TI		 3324 snd_hda_codec_write(codec,
3325 nvhdmi_master_con_nid_7x,
3326 0,
3327 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3328 }
3329
3330 for (i = 0; i < 4; i++) {
3331 if (chs == 2)
3332 channel_id = 0;
3333 else
3334 channel_id = i * 2;
3335
3336 /* turn off SPDIF once;
3337 *otherwise the IEC958 bits won't be updated
3338 */
3339 if (codec->spdif_status_reset &&
7c935976 3340 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3341 snd_hda_codec_write(codec,
3342 nvhdmi_con_nids_7x[i],
3343 0,
3344 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3345 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3346 /* set the stream id */
3347 snd_hda_codec_write(codec,
3348 nvhdmi_con_nids_7x[i],
3349 0,
3350 AC_VERB_SET_CHANNEL_STREAMID,
3351 (stream_tag << 4) | channel_id);
3352 /* set the stream format */
3353 snd_hda_codec_write(codec,
3354 nvhdmi_con_nids_7x[i],
3355 0,
3356 AC_VERB_SET_STREAM_FORMAT,
3357 format);
3358 /* turn on again (if needed) */
3359 /* enable and set the channel status audio/data flag */
3360 if (codec->spdif_status_reset &&
7c935976 3361 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3362 snd_hda_codec_write(codec,
3363 nvhdmi_con_nids_7x[i],
3364 0,
3365 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3366 spdif->ctls & 0xff);
84eb01be
TI		 3367 snd_hda_codec_write(codec,
3368 nvhdmi_con_nids_7x[i],
3369 0,
3370 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3371 }
3372 }
3373
1f348522 3374 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3375
3376 mutex_unlock(&codec->spdif_mutex);
3377 return 0;
3378}
3379
fb79e1e0 3380static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3381 .substreams = 1,
3382 .channels_min = 2,
3383 .channels_max = 8,
3384 .nid = nvhdmi_master_con_nid_7x,
3385 .rates = SUPPORTED_RATES,
3386 .maxbps = SUPPORTED_MAXBPS,
3387 .formats = SUPPORTED_FORMATS,
3388 .ops = {
3389 .open = simple_playback_pcm_open,
3390 .close = nvhdmi_8ch_7x_pcm_close,
3391 .prepare = nvhdmi_8ch_7x_pcm_prepare
3392 },
3393};
3394
84eb01be
TI		 3395static int patch_nvhdmi_2ch(struct hda_codec *codec)
3396{
3397 struct hdmi_spec *spec;
d0b1252d
TI		 3398 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3399 nvhdmi_master_pin_nid_7x);
3400 if (err < 0)
3401 return err;
84eb01be 3402
ceaa86ba 3403 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3404 /* override the PCM rates, etc, as the codec doesn't give full list */
3405 spec = codec->spec;
3406 spec->pcm_playback.rates = SUPPORTED_RATES;
3407 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3408 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3409 return 0;
3410}
3411
53775b0d
TI		 3412static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3413{
3414 struct hdmi_spec *spec = codec->spec;
3415 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3416 if (!err) {
3417 struct hda_pcm *info = get_pcm_rec(spec, 0);
3418 info->own_chmap = true;
3419 }
53775b0d
TI		 3420 return err;
3421}
3422
3423static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3424{
3425 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3426 struct hda_pcm *info;
53775b0d
TI		 3427 struct snd_pcm_chmap *chmap;
3428 int err;
3429
3430 err = simple_playback_build_controls(codec);
3431 if (err < 0)
3432 return err;
3433
3434 /* add channel maps */
bce0d2a8
TI		 3435 info = get_pcm_rec(spec, 0);
3436 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3437 SNDRV_PCM_STREAM_PLAYBACK,
3438 snd_pcm_alt_chmaps, 8, 0, &chmap);
3439 if (err < 0)
3440 return err;
b9a94a9c 3441 switch (codec->preset->vendor_id) {
53775b0d
TI		 3442 case 0x10de0002:
3443 case 0x10de0003:
3444 case 0x10de0005:
3445 case 0x10de0006:
3446 chmap->channel_mask = (1U << 2) | (1U << 8);
3447 break;
3448 case 0x10de0007:
3449 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3450 }
3451 return 0;
3452}
3453
84eb01be
TI		 3454static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3455{
3456 struct hdmi_spec *spec;
3457 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3458 if (err < 0)
3459 return err;
3460 spec = codec->spec;
3461 spec->multiout.max_channels = 8;
d0b1252d 3462 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3463 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3464 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3465 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3466
3467 /* Initialize the audio infoframe channel mask and checksum to something
3468 * valid */
3469 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3470
84eb01be
TI		 3471 return 0;
3472}
3473
611885bc
AH		 3474/*
3475 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3476 * - 0x10de0015
3477 * - 0x10de0040
3478 */
3479static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3480 int channels)
3481{
3482 if (cap->ca_index == 0x00 && channels == 2)
3483 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3484
3485 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
3486}
3487
3488static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
3489{
3490 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3491 return -EINVAL;
3492
3493 return 0;
3494}
3495
3496static int patch_nvhdmi(struct hda_codec *codec)
3497{
3498 struct hdmi_spec *spec;
3499 int err;
3500
3501 err = patch_generic_hdmi(codec);
3502 if (err)
3503 return err;
3504
3505 spec = codec->spec;
75fae117 3506 spec->dyn_pin_out = true;
611885bc
AH		 3507
3508 spec->ops.chmap_cea_alloc_validate_get_type =
3509 nvhdmi_chmap_cea_alloc_validate_get_type;
3510 spec->ops.chmap_validate = nvhdmi_chmap_validate;
3511
3512 return 0;
3513}
3514
26e9a960
TR		 3515/*
3516 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3517 * accessed using vendor-defined verbs. These registers can be used for
3518 * interoperability between the HDA and HDMI drivers.
3519 */
3520
3521/* Audio Function Group node */
3522#define NVIDIA_AFG_NID 0x01
3523
3524/*
3525 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3526 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3527 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3528 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3529 * additional bit (at position 30) to signal the validity of the format.
3530 *
3531 * | 31 | 30 | 29 16 | 15 0 |
3532 * +---------+-------+--------+--------+
3533 * | TRIGGER | VALID | UNUSED | FORMAT |
3534 * +-----------------------------------|
3535 *
3536 * Note that for the trigger bit to take effect it needs to change value
3537 * (i.e. it needs to be toggled).
3538 */
3539#define NVIDIA_GET_SCRATCH0 0xfa6
3540#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3541#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3542#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3543#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3544#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3545#define NVIDIA_SCRATCH_VALID (1 << 6)
3546
3547#define NVIDIA_GET_SCRATCH1 0xfab
3548#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3549#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3550#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3551#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3552
3553/*
3554 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3555 * the format is invalidated so that the HDMI codec can be disabled.
3556 */
3557static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3558{
3559 unsigned int value;
3560
3561 /* bits [31:30] contain the trigger and valid bits */
3562 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3563 NVIDIA_GET_SCRATCH0, 0);
3564 value = (value >> 24) & 0xff;
3565
3566 /* bits [15:0] are used to store the HDA format */
3567 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3568 NVIDIA_SET_SCRATCH0_BYTE0,
3569 (format >> 0) & 0xff);
3570 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3571 NVIDIA_SET_SCRATCH0_BYTE1,
3572 (format >> 8) & 0xff);
3573
3574 /* bits [16:24] are unused */
3575 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3576 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3577
3578 /*
3579 * Bit 30 signals that the data is valid and hence that HDMI audio can
3580 * be enabled.
3581 */
3582 if (format == 0)
3583 value &= ~NVIDIA_SCRATCH_VALID;
3584 else
3585 value |= NVIDIA_SCRATCH_VALID;
3586
3587 /*
3588 * Whenever the trigger bit is toggled, an interrupt is raised in the
3589 * HDMI codec. The HDMI driver will use that as trigger to update its
3590 * configuration.
3591 */
3592 value ^= NVIDIA_SCRATCH_TRIGGER;
3593
3594 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3595 NVIDIA_SET_SCRATCH0_BYTE3, value);
3596}
3597
3598static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3599 struct hda_codec *codec,
3600 unsigned int stream_tag,
3601 unsigned int format,
3602 struct snd_pcm_substream *substream)
3603{
3604 int err;
3605
3606 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3607 format, substream);
3608 if (err < 0)
3609 return err;
3610
3611 /* notify the HDMI codec of the format change */
3612 tegra_hdmi_set_format(codec, format);
3613
3614 return 0;
3615}
3616
3617static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3618 struct hda_codec *codec,
3619 struct snd_pcm_substream *substream)
3620{
3621 /* invalidate the format in the HDMI codec */
3622 tegra_hdmi_set_format(codec, 0);
3623
3624 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3625}
3626
3627static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3628{
3629 struct hdmi_spec *spec = codec->spec;
3630 unsigned int i;
3631
3632 for (i = 0; i < spec->num_pins; i++) {
3633 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3634
3635 if (pcm->pcm_type == type)
3636 return pcm;
3637 }
3638
3639 return NULL;
3640}
3641
3642static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3643{
3644 struct hda_pcm_stream *stream;
3645 struct hda_pcm *pcm;
3646 int err;
3647
3648 err = generic_hdmi_build_pcms(codec);
3649 if (err < 0)
3650 return err;
3651
3652 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3653 if (!pcm)
3654 return -ENODEV;
3655
3656 /*
3657 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3658 * codec about format changes.
3659 */
3660 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3661 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3662 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3663
3664 return 0;
3665}
3666
3667static int patch_tegra_hdmi(struct hda_codec *codec)
3668{
3669 int err;
3670
3671 err = patch_generic_hdmi(codec);
3672 if (err)
3673 return err;
3674
3675 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3676
3677 return 0;
3678}
3679
84eb01be 3680/*
5a613584 3681 * ATI/AMD-specific implementations
84eb01be
TI		 3682 */
3683
5a613584 3684#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3685 ((codec)->core.vendor_id == 0x1002aa01 && \
3686 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3687#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3688
3689/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3690#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3691#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3692#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3693#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3694#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3695#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3696#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3697#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3698#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3699#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3700#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3701#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3702#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3703#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3704#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3705#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3706#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3707#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3708#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3709#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3710#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3711#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3712#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3713#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3714
84d69e79
AH		 3715/* AMD specific HDA cvt verbs */
3716#define ATI_VERB_SET_RAMP_RATE 0x770
3717#define ATI_VERB_GET_RAMP_RATE 0xf70
3718
5a613584
AH		 3719#define ATI_OUT_ENABLE 0x1
3720
3721#define ATI_MULTICHANNEL_MODE_PAIRED 0
3722#define ATI_MULTICHANNEL_MODE_SINGLE 1
3723
461cf6b3
AH		 3724#define ATI_HBR_CAPABLE 0x01
3725#define ATI_HBR_ENABLE 0x10
3726
89250f84
AH		 3727static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3728 unsigned char *buf, int *eld_size)
3729{
3730 /* call hda_eld.c ATI/AMD-specific function */
3731 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3732 is_amdhdmi_rev3_or_later(codec));
3733}
3734
5a613584
AH		 3735static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3736 int active_channels, int conn_type)
3737{
3738 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3739}
3740
3741static int atihdmi_paired_swap_fc_lfe(int pos)
3742{
3743 /*
3744 * ATI/AMD have automatic FC/LFE swap built-in
3745 * when in pairwise mapping mode.
3746 */
3747
3748 switch (pos) {
3749 /* see channel_allocations[].speakers[] */
3750 case 2: return 3;
3751 case 3: return 2;
3752 default: break;
3753 }
3754
3755 return pos;
3756}
3757
3758static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3759{
3760 struct cea_channel_speaker_allocation *cap;
3761 int i, j;
3762
3763 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3764
3765 cap = &channel_allocations[get_channel_allocation_order(ca)];
3766 for (i = 0; i < chs; ++i) {
3767 int mask = to_spk_mask(map[i]);
3768 bool ok = false;
3769 bool companion_ok = false;
3770
3771 if (!mask)
3772 continue;
3773
3774 for (j = 0 + i % 2; j < 8; j += 2) {
3775 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3776 if (cap->speakers[chan_idx] == mask) {
3777 /* channel is in a supported position */
3778 ok = true;
3779
3780 if (i % 2 == 0 && i + 1 < chs) {
3781 /* even channel, check the odd companion */
3782 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3783 int comp_mask_req = to_spk_mask(map[i+1]);
3784 int comp_mask_act = cap->speakers[comp_chan_idx];
3785
3786 if (comp_mask_req == comp_mask_act)
3787 companion_ok = true;
3788 else
3789 return -EINVAL;
3790 }
3791 break;
3792 }
3793 }
3794
3795 if (!ok)
3796 return -EINVAL;
3797
3798 if (companion_ok)
3799 i++; /* companion channel already checked */
3800 }
3801
3802 return 0;
3803}
3804
3805static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3806 int hdmi_slot, int stream_channel)
3807{
3808 int verb;
3809 int ati_channel_setup = 0;
3810
3811 if (hdmi_slot > 7)
3812 return -EINVAL;
3813
3814 if (!has_amd_full_remap_support(codec)) {
3815 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3816
3817 /* In case this is an odd slot but without stream channel, do not
3818 * disable the slot since the corresponding even slot could have a
3819 * channel. In case neither have a channel, the slot pair will be
3820 * disabled when this function is called for the even slot. */
3821 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3822 return 0;
3823
3824 hdmi_slot -= hdmi_slot % 2;
3825
3826 if (stream_channel != 0xf)
3827 stream_channel -= stream_channel % 2;
3828 }
3829
3830 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3831
3832 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3833
3834 if (stream_channel != 0xf)
3835 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3836
3837 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3838}
3839
3840static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3841 int asp_slot)
3842{
3843 bool was_odd = false;
3844 int ati_asp_slot = asp_slot;
3845 int verb;
3846 int ati_channel_setup;
3847
3848 if (asp_slot > 7)
3849 return -EINVAL;
3850
3851 if (!has_amd_full_remap_support(codec)) {
3852 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3853 if (ati_asp_slot % 2 != 0) {
3854 ati_asp_slot -= 1;
3855 was_odd = true;
3856 }
3857 }
3858
3859 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3860
3861 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3862
3863 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3864 return 0xf;
3865
3866 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3867}
84eb01be 3868
5a613584
AH		 3869static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3870 int channels)
3871{
3872 int c;
3873
3874 /*
3875 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3876 * we need to take that into account (a single channel may take 2
3877 * channel slots if we need to carry a silent channel next to it).
3878 * On Rev3+ AMD codecs this function is not used.
3879 */
3880 int chanpairs = 0;
3881
3882 /* We only produce even-numbered channel count TLVs */
3883 if ((channels % 2) != 0)
3884 return -1;
3885
3886 for (c = 0; c < 7; c += 2) {
3887 if (cap->speakers[c] || cap->speakers[c+1])
3888 chanpairs++;
3889 }
3890
3891 if (chanpairs * 2 != channels)
3892 return -1;
3893
3894 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3895}
3896
3897static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3898 unsigned int *chmap, int channels)
3899{
3900 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3901 int count = 0;
3902 int c;
3903
3904 for (c = 7; c >= 0; c--) {
3905 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3906 int spk = cap->speakers[chan];
3907 if (!spk) {
3908 /* add N/A channel if the companion channel is occupied */
3909 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3910 chmap[count++] = SNDRV_CHMAP_NA;
3911
3912 continue;
3913 }
3914
3915 chmap[count++] = spk_to_chmap(spk);
3916 }
3917
3918 WARN_ON(count != channels);
3919}
3920
461cf6b3
AH		 3921static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3922 bool hbr)
3923{
3924 int hbr_ctl, hbr_ctl_new;
3925
3926 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3927 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3928 if (hbr)
3929 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3930 else
3931 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3932
4e76a883
TI		 3933 codec_dbg(codec,
3934 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3935 pin_nid,
3936 hbr_ctl == hbr_ctl_new ? "" : "new-",
3937 hbr_ctl_new);
3938
3939 if (hbr_ctl != hbr_ctl_new)
3940 snd_hda_codec_write(codec, pin_nid, 0,
3941 ATI_VERB_SET_HBR_CONTROL,
3942 hbr_ctl_new);
3943
3944 } else if (hbr)
3945 return -EINVAL;
3946
3947 return 0;
3948}
3949
84d69e79
AH		 3950static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3951 hda_nid_t pin_nid, u32 stream_tag, int format)
3952{
3953
3954 if (is_amdhdmi_rev3_or_later(codec)) {
3955 int ramp_rate = 180; /* default as per AMD spec */
3956 /* disable ramp-up/down for non-pcm as per AMD spec */
3957 if (format & AC_FMT_TYPE_NON_PCM)
3958 ramp_rate = 0;
3959
3960 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3961 }
3962
3963 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3964}
3965
3966
5a613584 3967static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3968{
3969 struct hdmi_spec *spec = codec->spec;
5a613584 3970 int pin_idx, err;
84eb01be 3971
5a613584
AH		 3972 err = generic_hdmi_init(codec);
3973
3974 if (err)
84eb01be 3975 return err;
5a613584
AH		 3976
3977 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3978 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3979
3980 /* make sure downmix information in infoframe is zero */
3981 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3982
3983 /* enable channel-wise remap mode if supported */
3984 if (has_amd_full_remap_support(codec))
3985 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3986 ATI_VERB_SET_MULTICHANNEL_MODE,
3987 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3988 }
5a613584 3989
84eb01be
TI		 3990 return 0;
3991}
3992
84eb01be
TI		 3993static int patch_atihdmi(struct hda_codec *codec)
3994{
3995 struct hdmi_spec *spec;
5a613584
AH		 3996 struct hdmi_spec_per_cvt *per_cvt;
3997 int err, cvt_idx;
3998
3999 err = patch_generic_hdmi(codec);
4000
4001 if (err)
d0b1252d 4002 return err;
5a613584
AH		 4003
4004 codec->patch_ops.init = atihdmi_init;
4005
d0b1252d 4006 spec = codec->spec;
5a613584 4007
89250f84 4008 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 4009 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4010 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4011 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 4012 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 4013 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 4014
4015 if (!has_amd_full_remap_support(codec)) {
4016 /* override to ATI/AMD-specific versions with pairwise mapping */
4017 spec->ops.chmap_cea_alloc_validate_get_type =
4018 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4019 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
4020 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
4021 }
4022
4023 /* ATI/AMD converters do not advertise all of their capabilities */
4024 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4025 per_cvt = get_cvt(spec, cvt_idx);
4026 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4027 per_cvt->rates |= SUPPORTED_RATES;
4028 per_cvt->formats |= SUPPORTED_FORMATS;
4029 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4030 }
4031
4032 spec->channels_max = max(spec->channels_max, 8u);
4033
84eb01be
TI		 4034 return 0;
4035}
4036
3de5ff88
AL		 4037/* VIA HDMI Implementation */
4038#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4039#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4040
3de5ff88
AL		 4041static int patch_via_hdmi(struct hda_codec *codec)
4042{
250e41ac 4043 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 4044}
84eb01be
TI		 4045
4046/*
4047 * patch entries
4048 */
b9a94a9c
TI		 4049static const struct hda_device_id snd_hda_id_hdmi[] = {
4050HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4051HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4052HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4053HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4054HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4055HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4056HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4057HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4058HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4059HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4060HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4061HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4062HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
4063HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
4064HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
4065HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
4066HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
4067HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
4068HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
4069HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
4070HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
4071HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
4072HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 4073/* 17 is known to be absent */
b9a94a9c
TI		 4074HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
4075HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
4076HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
4077HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
4078HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
4079HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4080HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4081HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4082HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4083HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4084HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4085HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4086HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4087HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4088HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4089HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4090HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4091HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4092HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4093HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4094HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3ec622f4 4095HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 4096HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4097HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4098HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4099HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4100HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4101HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
4102HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4103HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4104HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4105HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
4106HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
4107HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
4108HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
4109HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
4110HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
4111HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
91815d8a 4112HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
b9a94a9c
TI		 4113HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4114HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
4115HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
4116HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 4117/* special ID for generic HDMI */
b9a94a9c 4118HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 4119{} /* terminator */
4120};
b9a94a9c 4121MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 4122
4123MODULE_LICENSE("GPL");
4124MODULE_DESCRIPTION("HDMI HD-audio codec");
4125MODULE_ALIAS("snd-hda-codec-intelhdmi");
4126MODULE_ALIAS("snd-hda-codec-nvhdmi");
4127MODULE_ALIAS("snd-hda-codec-atihdmi");
4128
d8a766a1 4129static struct hda_codec_driver hdmi_driver = {
b9a94a9c 4130 .id = snd_hda_id_hdmi,
84eb01be
TI		 4131};
4132
d8a766a1 4133module_hda_codec_driver(hdmi_driver);
Linux kernel - Deliverables
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