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[ALSA] hda-intel - Fix PCM device number assignment
[deliverable/linux.git] / sound / pci / hda / patch_si3054.c
CommitLineData
b65f824c
SK		 1/*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * HD audio interface patch for Silicon Labs 3054/5 modem codec
5 *
f01cc521 6 * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
b65f824c
SK		 7 * Takashi Iwai <tiwai@suse.de>
8 *
9 *
10 * This driver is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This driver is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
b65f824c
SK		 25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
b65f824c
SK		 28#include <sound/core.h>
29#include "hda_codec.h"
30#include "hda_local.h"
31
32
33/* si3054 verbs */
34#define SI3054_VERB_READ_NODE 0x900
35#define SI3054_VERB_WRITE_NODE 0x100
36
37/* si3054 nodes (registers) */
38#define SI3054_EXTENDED_MID 2
39#define SI3054_LINE_RATE 3
40#define SI3054_LINE_LEVEL 4
41#define SI3054_GPIO_CFG 5
42#define SI3054_GPIO_POLARITY 6
43#define SI3054_GPIO_STICKY 7
44#define SI3054_GPIO_WAKEUP 8
45#define SI3054_GPIO_STATUS 9
46#define SI3054_GPIO_CONTROL 10
47#define SI3054_MISC_AFE 11
48#define SI3054_CHIPID 12
49#define SI3054_LINE_CFG1 13
50#define SI3054_LINE_STATUS 14
51#define SI3054_DC_TERMINATION 15
52#define SI3054_LINE_CONFIG 16
53#define SI3054_CALLPROG_ATT 17
54#define SI3054_SQ_CONTROL 18
55#define SI3054_MISC_CONTROL 19
56#define SI3054_RING_CTRL1 20
57#define SI3054_RING_CTRL2 21
58
59/* extended MID */
60#define SI3054_MEI_READY 0xf
61
62/* line level */
63#define SI3054_ATAG_MASK 0x00f0
64#define SI3054_DTAG_MASK 0xf000
65
66/* GPIO bits */
67#define SI3054_GPIO_OH 0x0001
68#define SI3054_GPIO_CID 0x0002
69
70/* chipid and revisions */
71#define SI3054_CHIPID_CODEC_REV_MASK 0x000f
72#define SI3054_CHIPID_DAA_REV_MASK 0x00f0
73#define SI3054_CHIPID_INTERNATIONAL 0x0100
74#define SI3054_CHIPID_DAA_ID 0x0f00
75#define SI3054_CHIPID_CODEC_ID (1<<12)
76
77/* si3054 codec registers (nodes) access macros */
78#define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
79#define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
82beb8fd
TI		 80#define SET_REG_CACHE(codec,reg,val) \
81 snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val)
b65f824c
SK		 82
83
84struct si3054_spec {
85 unsigned international;
86 struct hda_pcm pcm;
87};
88
89
90/*
91 * Modem mixer
92 */
93
94#define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
95#define PRIVATE_REG(val) ((val>>16)&0xffff)
96#define PRIVATE_MASK(val) (val&0xffff)
97
a5ce8890 98#define si3054_switch_info snd_ctl_boolean_mono_info
b65f824c 99
c8b6bf9b
TI		 100static int si3054_switch_get(struct snd_kcontrol *kcontrol,
101 struct snd_ctl_elem_value *uvalue)
b65f824c
SK		 102{
103 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
104 u16 reg = PRIVATE_REG(kcontrol->private_value);
105 u16 mask = PRIVATE_MASK(kcontrol->private_value);
106 uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
107 return 0;
108}
109
c8b6bf9b
TI		 110static int si3054_switch_put(struct snd_kcontrol *kcontrol,
111 struct snd_ctl_elem_value *uvalue)
b65f824c
SK		 112{
113 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
114 u16 reg = PRIVATE_REG(kcontrol->private_value);
115 u16 mask = PRIVATE_MASK(kcontrol->private_value);
116 if (uvalue->value.integer.value[0])
82beb8fd 117 SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask);
b65f824c 118 else
82beb8fd 119 SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask);
b65f824c
SK		 120 return 0;
121}
122
123#define SI3054_KCONTROL(kname,reg,mask) { \
124 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
125 .name = kname, \
126 .info = si3054_switch_info, \
127 .get = si3054_switch_get, \
128 .put = si3054_switch_put, \
129 .private_value = PRIVATE_VALUE(reg,mask), \
130}
131
132
c8b6bf9b 133static struct snd_kcontrol_new si3054_modem_mixer[] = {
b65f824c
SK		 134 SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
135 SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
136 {}
137};
138
139static int si3054_build_controls(struct hda_codec *codec)
140{
141 return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
142}
143
144
145/*
146 * PCM callbacks
147 */
148
149static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
150 struct hda_codec *codec,
151 unsigned int stream_tag,
152 unsigned int format,
c8b6bf9b 153 struct snd_pcm_substream *substream)
b65f824c
SK		 154{
155 u16 val;
156
157 SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
158 val = GET_REG(codec, SI3054_LINE_LEVEL);
159 val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
160 val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
161 SET_REG(codec, SI3054_LINE_LEVEL, val);
162
163 snd_hda_codec_setup_stream(codec, hinfo->nid,
164 stream_tag, 0, format);
165 return 0;
166}
167
168static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
169 struct hda_codec *codec,
c8b6bf9b 170 struct snd_pcm_substream *substream)
b65f824c
SK		 171{
172 static unsigned int rates[] = { 8000, 9600, 16000 };
c8b6bf9b 173 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
b65f824c
SK		 174 .count = ARRAY_SIZE(rates),
175 .list = rates,
176 .mask = 0,
177 };
178 substream->runtime->hw.period_bytes_min = 80;
179 return snd_pcm_hw_constraint_list(substream->runtime, 0,
180 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
181}
182
183
184static struct hda_pcm_stream si3054_pcm = {
185 .substreams = 1,
186 .channels_min = 1,
187 .channels_max = 1,
188 .nid = 0x1,
189 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
190 .formats = SNDRV_PCM_FMTBIT_S16_LE,
191 .maxbps = 16,
192 .ops = {
193 .open = si3054_pcm_open,
194 .prepare = si3054_pcm_prepare,
195 },
196};
197
198
199static int si3054_build_pcms(struct hda_codec *codec)
200{
201 struct si3054_spec *spec = codec->spec;
202 struct hda_pcm *info = &spec->pcm;
203 si3054_pcm.nid = codec->mfg;
204 codec->num_pcms = 1;
205 codec->pcm_info = info;
206 info->name = "Si3054 Modem";
207 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
208 info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm;
7ba72ba1 209 info->pcm_type = HDA_PCM_TYPE_MODEM;
b65f824c
SK		 210 return 0;
211}
212
213
214/*
215 * Init part
216 */
217
218static int si3054_init(struct hda_codec *codec)
219{
220 struct si3054_spec *spec = codec->spec;
221 unsigned wait_count;
222 u16 val;
223
224 snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
225 snd_hda_codec_write(codec, codec->mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
226 SET_REG(codec, SI3054_LINE_RATE, 9600);
227 SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
228 SET_REG(codec, SI3054_EXTENDED_MID, 0);
229
230 wait_count = 10;
231 do {
232 msleep(2);
233 val = GET_REG(codec, SI3054_EXTENDED_MID);
234 } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
235
236 if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
237 snd_printk(KERN_ERR "si3054: cannot initialize. EXT MID = %04x\n", val);
83af036d
TI		 238 /* let's pray that this is no fatal error */
239 /* return -EACCES; */
b65f824c
SK		 240 }
241
242 SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
243 SET_REG(codec, SI3054_GPIO_CFG, 0x0);
244 SET_REG(codec, SI3054_MISC_AFE, 0);
245 SET_REG(codec, SI3054_LINE_CFG1,0x200);
246
247 if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
248 snd_printd("Link Frame Detect(FDT) is not ready (line status: %04x)\n",
249 GET_REG(codec,SI3054_LINE_STATUS));
250 }
251
252 spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
253
254 return 0;
255}
256
257static void si3054_free(struct hda_codec *codec)
258{
259 kfree(codec->spec);
260}
261
262
263/*
264 */
265
266static struct hda_codec_ops si3054_patch_ops = {
267 .build_controls = si3054_build_controls,
268 .build_pcms = si3054_build_pcms,
269 .init = si3054_init,
270 .free = si3054_free,
b65f824c
SK		 271};
272
273static int patch_si3054(struct hda_codec *codec)
274{
e560d8d8 275 struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
b65f824c
SK		 276 if (spec == NULL)
277 return -ENOMEM;
278 codec->spec = spec;
279 codec->patch_ops = si3054_patch_ops;
280 return 0;
281}
282
283/*
284 * patch entries
285 */
286struct hda_codec_preset snd_hda_preset_si3054[] = {
26741b55 287 { .id = 0x163c3055, .name = "Si3054", .patch = patch_si3054 },
b65f824c 288 { .id = 0x163c3155, .name = "Si3054", .patch = patch_si3054 },
e061bf1a 289 { .id = 0x11c13026, .name = "Si3054", .patch = patch_si3054 },
476d1205
SK		 290 { .id = 0x11c13055, .name = "Si3054", .patch = patch_si3054 },
291 { .id = 0x11c13155, .name = "Si3054", .patch = patch_si3054 },
292 { .id = 0x10573055, .name = "Si3054", .patch = patch_si3054 },
5720fddd 293 { .id = 0x10573057, .name = "Si3054", .patch = patch_si3054 },
476d1205 294 { .id = 0x10573155, .name = "Si3054", .patch = patch_si3054 },
be38114a
CM		 295 /* VIA HDA on Clevo m540 */
296 { .id = 0x11063288, .name = "Si3054", .patch = patch_si3054 },
3b542985
CR		 297 /* Asus A8J Modem (SM56) */
298 { .id = 0x15433155, .name = "Si3054", .patch = patch_si3054 },
ef2ec0dd
CM		 299 /* LG LW20 modem */
300 { .id = 0x18540018, .name = "Si3054", .patch = patch_si3054 },
b65f824c
SK		 301 {}
302};
303
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