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Merge branch 'irq-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
c1017a4c 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
1da177e4
LT		 29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/moduleparam.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
c1017a4c 45MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 46MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49 "{Intel,82901AB-ICH0},"
50 "{Intel,82801BA-ICH2},"
51 "{Intel,82801CA-ICH3},"
52 "{Intel,82801DB-ICH4},"
53 "{Intel,ICH5},"
54 "{Intel,ICH6},"
55 "{Intel,ICH7},"
56 "{Intel,6300ESB},"
c4c8ea94 57 "{Intel,ESB2},"
1da177e4
LT		 58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
a2854dc5
AB		 62 "{NVidia,nForce3 Audio},"
63 "{NVidia,MCP04},"
64 "{NVidia,MCP501},"
65 "{NVidia,CK804},"
66 "{NVidia,CK8},"
67 "{NVidia,CK8S},"
1da177e4
LT		 68 "{AMD,AMD768},"
69 "{AMD,AMD8111},"
70 "{ALI,M5455}}");
71
b7fe4622
CL		 72static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
73static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
6581f4e7 74static int ac97_clock;
b7fe4622
CL		 75static char *ac97_quirk;
76static int buggy_semaphore;
beef08a5 77static int buggy_irq = -1; /* auto-check */
b7fe4622 78static int xbox;
a9e99660 79static int spdif_aclink = -1;
b7fe4622
CL		 80
81module_param(index, int, 0444);
1da177e4 82MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
b7fe4622 83module_param(id, charp, 0444);
1da177e4 84MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
b7fe4622 85module_param(ac97_clock, int, 0444);
2b3b5485 86MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
b7fe4622 87module_param(ac97_quirk, charp, 0444);
1da177e4 88MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 89module_param(buggy_semaphore, bool, 0444);
a06147d2 90MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
b7fe4622 91module_param(buggy_irq, bool, 0444);
1da177e4 92MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
b7fe4622 93module_param(xbox, bool, 0444);
1da177e4 94MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
a9e99660
TI		 95module_param(spdif_aclink, int, 0444);
96MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
1da177e4 97
2b3e584b
TI		 98/* just for backward compatibility */
99static int enable;
698444f3 100module_param(enable, bool, 0444);
2b3e584b
TI		 101static int joystick;
102module_param(joystick, int, 0444);
103
1da177e4
LT		 104/*
105 * Direct registers
106 */
1da177e4
LT		 107enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
108
109#define ICHREG(x) ICH_REG_##x
110
111#define DEFINE_REGSET(name,base) \
112enum { \
113 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
114 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
115 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
116 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
117 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
118 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
119 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
120};
121
122/* busmaster blocks */
123DEFINE_REGSET(OFF, 0); /* offset */
124DEFINE_REGSET(PI, 0x00); /* PCM in */
125DEFINE_REGSET(PO, 0x10); /* PCM out */
126DEFINE_REGSET(MC, 0x20); /* Mic in */
127
128/* ICH4 busmaster blocks */
129DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
130DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
131DEFINE_REGSET(SP, 0x60); /* SPDIF out */
132
133/* values for each busmaster block */
134
135/* LVI */
136#define ICH_REG_LVI_MASK 0x1f
137
138/* SR */
139#define ICH_FIFOE 0x10 /* FIFO error */
140#define ICH_BCIS 0x08 /* buffer completion interrupt status */
141#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
142#define ICH_CELV 0x02 /* current equals last valid */
143#define ICH_DCH 0x01 /* DMA controller halted */
144
145/* PIV */
146#define ICH_REG_PIV_MASK 0x1f /* mask */
147
148/* CR */
149#define ICH_IOCE 0x10 /* interrupt on completion enable */
150#define ICH_FEIE 0x08 /* fifo error interrupt enable */
151#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
152#define ICH_RESETREGS 0x02 /* reset busmaster registers */
153#define ICH_STARTBM 0x01 /* start busmaster operation */
154
155
156/* global block */
157#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
158#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
159#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
160#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
161#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
162#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
163#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
4235a317
TI		 164#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
165#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
1da177e4
LT		 166#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
167#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
168#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
169#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
170#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
171#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
172#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
173#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
174#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
175#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
176#define ICH_ACLINK 0x00000008 /* AClink shut off */
177#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
178#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
179#define ICH_GIE 0x00000001 /* GPI interrupt enable */
180#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
181#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
182#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
183#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
184#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
185#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
186#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
187#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
188#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
189#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
84a43bd5
TI		 190#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
191#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
1da177e4
LT		 192#define ICH_MD3 0x00020000 /* modem power down semaphore */
193#define ICH_AD3 0x00010000 /* audio power down semaphore */
194#define ICH_RCS 0x00008000 /* read completion status */
195#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
196#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
197#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
198#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
199#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
200#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
201#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
202#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
203#define ICH_POINT 0x00000040 /* playback interrupt */
204#define ICH_PIINT 0x00000020 /* capture interrupt */
205#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
206#define ICH_MOINT 0x00000004 /* modem playback interrupt */
207#define ICH_MIINT 0x00000002 /* modem capture interrupt */
208#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
209#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
210#define ICH_CAS 0x01 /* codec access semaphore */
211#define ICH_REG_SDM 0x80
212#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
213#define ICH_DI2L_SHIFT 6
214#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
215#define ICH_DI1L_SHIFT 4
216#define ICH_SE 0x00000008 /* steer enable */
217#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
218
219#define ICH_MAX_FRAGS 32 /* max hw frags */
220
221
222/*
223 * registers for Ali5455
224 */
225
226/* ALi 5455 busmaster blocks */
227DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
228DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
229DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
230DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
231DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
232DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
233DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
234DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
235DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
236DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
237DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
238
239enum {
240 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
241 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
242 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
243 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
244 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
245 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
246 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
247 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
248 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
249 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
250 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
251 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
252 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
253 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
254 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
255 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
256 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
257 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
258 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
259 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
260 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
261};
262
263#define ALI_CAS_SEM_BUSY 0x80000000
264#define ALI_CPR_ADDR_SECONDARY 0x100
265#define ALI_CPR_ADDR_READ 0x80
266#define ALI_CSPSR_CODEC_READY 0x08
267#define ALI_CSPSR_READ_OK 0x02
268#define ALI_CSPSR_WRITE_OK 0x01
269
270/* interrupts for the whole chip by interrupt status register finish */
271
272#define ALI_INT_MICIN2 (1<<26)
273#define ALI_INT_PCMIN2 (1<<25)
274#define ALI_INT_I2SIN (1<<24)
275#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
276#define ALI_INT_SPDIFIN (1<<22)
277#define ALI_INT_LFEOUT (1<<21)
278#define ALI_INT_CENTEROUT (1<<20)
279#define ALI_INT_CODECSPDIFOUT (1<<19)
280#define ALI_INT_MICIN (1<<18)
281#define ALI_INT_PCMOUT (1<<17)
282#define ALI_INT_PCMIN (1<<16)
283#define ALI_INT_CPRAIS (1<<7) /* command port available */
284#define ALI_INT_SPRAIS (1<<5) /* status port available */
285#define ALI_INT_GPIO (1<<1)
6b75a9d8
TI		 286#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
287 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
1da177e4
LT		 288
289#define ICH_ALI_SC_RESET (1<<31) /* master reset */
290#define ICH_ALI_SC_AC97_DBL (1<<30)
291#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
292#define ICH_ALI_SC_IN_BITS (3<<18)
293#define ICH_ALI_SC_OUT_BITS (3<<16)
294#define ICH_ALI_SC_6CH_CFG (3<<14)
295#define ICH_ALI_SC_PCM_4 (1<<8)
296#define ICH_ALI_SC_PCM_6 (2<<8)
297#define ICH_ALI_SC_PCM_246_MASK (3<<8)
298
299#define ICH_ALI_SS_SEC_ID (3<<5)
300#define ICH_ALI_SS_PRI_ID (3<<3)
301
302#define ICH_ALI_IF_AC97SP (1<<21)
303#define ICH_ALI_IF_MC (1<<20)
304#define ICH_ALI_IF_PI (1<<19)
305#define ICH_ALI_IF_MC2 (1<<18)
306#define ICH_ALI_IF_PI2 (1<<17)
307#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
308#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
309#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
310#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
311#define ICH_ALI_IF_PO_SPDF (1<<3)
312#define ICH_ALI_IF_PO (1<<1)
313
314/*
315 *
316 */
317
6b75a9d8
TI		 318enum {
319 ICHD_PCMIN,
320 ICHD_PCMOUT,
321 ICHD_MIC,
322 ICHD_MIC2,
323 ICHD_PCM2IN,
324 ICHD_SPBAR,
325 ICHD_LAST = ICHD_SPBAR
326};
327enum {
328 NVD_PCMIN,
329 NVD_PCMOUT,
330 NVD_MIC,
331 NVD_SPBAR,
332 NVD_LAST = NVD_SPBAR
333};
334enum {
335 ALID_PCMIN,
336 ALID_PCMOUT,
337 ALID_MIC,
338 ALID_AC97SPDIFOUT,
339 ALID_SPDIFIN,
340 ALID_SPDIFOUT,
341 ALID_LAST = ALID_SPDIFOUT
342};
1da177e4 343
6b75a9d8 344#define get_ichdev(substream) (substream->runtime->private_data)
1da177e4 345
6b75a9d8 346struct ichdev {
1da177e4
LT		 347 unsigned int ichd; /* ich device number */
348 unsigned long reg_offset; /* offset to bmaddr */
349 u32 *bdbar; /* CPU address (32bit) */
350 unsigned int bdbar_addr; /* PCI bus address (32bit) */
6b75a9d8 351 struct snd_pcm_substream *substream;
1da177e4
LT		 352 unsigned int physbuf; /* physical address (32bit) */
353 unsigned int size;
354 unsigned int fragsize;
355 unsigned int fragsize1;
356 unsigned int position;
357 unsigned int pos_shift;
da2436a2 358 unsigned int last_pos;
1da177e4
LT		 359 int frags;
360 int lvi;
361 int lvi_frag;
362 int civ;
363 int ack;
364 int ack_reload;
365 unsigned int ack_bit;
366 unsigned int roff_sr;
367 unsigned int roff_picb;
368 unsigned int int_sta_mask; /* interrupt status mask */
369 unsigned int ali_slot; /* ALI DMA slot */
370 struct ac97_pcm *pcm;
371 int pcm_open_flag;
372 unsigned int page_attr_changed: 1;
1cfe43d2 373 unsigned int suspended: 1;
6b75a9d8 374};
1da177e4 375
6b75a9d8 376struct intel8x0 {
1da177e4
LT		 377 unsigned int device_type;
378
379 int irq;
380
3388c37e
TI		 381 void __iomem *addr;
382 void __iomem *bmaddr;
1da177e4
LT		 383
384 struct pci_dev *pci;
6b75a9d8 385 struct snd_card *card;
1da177e4
LT		 386
387 int pcm_devs;
6b75a9d8
TI		 388 struct snd_pcm *pcm[6];
389 struct ichdev ichd[6];
1da177e4
LT		 390
391 unsigned multi4: 1,
392 multi6: 1,
4235a317 393 multi8 :1,
1da177e4
LT		 394 dra: 1,
395 smp20bit: 1;
396 unsigned in_ac97_init: 1,
397 in_sdin_init: 1;
398 unsigned in_measurement: 1; /* during ac97 clock measurement */
399 unsigned fix_nocache: 1; /* workaround for 440MX */
400 unsigned buggy_irq: 1; /* workaround for buggy mobos */
401 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 402 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
1da177e4
LT		 403
404 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 405 unsigned int sdm_saved; /* SDM reg value */
1da177e4 406
6b75a9d8
TI		 407 struct snd_ac97_bus *ac97_bus;
408 struct snd_ac97 *ac97[3];
1da177e4 409 unsigned int ac97_sdin[3];
84a43bd5
TI		 410 unsigned int max_codecs, ncodecs;
411 unsigned int *codec_bit;
412 unsigned int codec_isr_bits;
413 unsigned int codec_ready_bits;
1da177e4
LT		 414
415 spinlock_t reg_lock;
416
417 u32 bdbars_count;
418 struct snd_dma_buffer bdbars;
419 u32 int_sta_reg; /* interrupt status register */
420 u32 int_sta_mask; /* interrupt status mask */
421};
422
cebe41d4 423static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
28d27aae
JP		 424 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
425 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
426 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
427 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
428 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
429 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
430 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
431 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
432 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
433 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
434 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
435 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
436 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
437 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
438 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
439 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
440 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
441 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
442 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
443 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
444 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
445 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
446 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
1da177e4
LT		 447 { 0, }
448};
449
450MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
451
452/*
453 * Lowlevel I/O - busmaster
454 */
455
3388c37e 456static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
1da177e4 457{
3388c37e 458 return ioread8(chip->bmaddr + offset);
1da177e4
LT		 459}
460
3388c37e 461static inline u16 igetword(struct intel8x0 *chip, u32 offset)
1da177e4 462{
3388c37e 463 return ioread16(chip->bmaddr + offset);
1da177e4
LT		 464}
465
3388c37e 466static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
1da177e4 467{
3388c37e 468 return ioread32(chip->bmaddr + offset);
1da177e4
LT		 469}
470
3388c37e 471static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
1da177e4 472{
3388c37e 473 iowrite8(val, chip->bmaddr + offset);
1da177e4
LT		 474}
475
3388c37e 476static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 477{
3388c37e 478 iowrite16(val, chip->bmaddr + offset);
1da177e4
LT		 479}
480
3388c37e 481static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
1da177e4 482{
3388c37e 483 iowrite32(val, chip->bmaddr + offset);
1da177e4
LT		 484}
485
486/*
487 * Lowlevel I/O - AC'97 registers
488 */
489
3388c37e 490static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
1da177e4 491{
3388c37e 492 return ioread16(chip->addr + offset);
1da177e4
LT		 493}
494
3388c37e 495static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 496{
3388c37e 497 iowrite16(val, chip->addr + offset);
1da177e4
LT		 498}
499
500/*
501 * Basic I/O
502 */
503
504/*
505 * access to AC97 codec via normal i/o (for ICH and SIS7012)
506 */
507
6b75a9d8 508static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 509{
510 int time;
511
512 if (codec > 2)
513 return -EIO;
514 if (chip->in_sdin_init) {
515 /* we don't know the ready bit assignment at the moment */
516 /* so we check any */
84a43bd5 517 codec = chip->codec_isr_bits;
1da177e4 518 } else {
84a43bd5 519 codec = chip->codec_bit[chip->ac97_sdin[codec]];
1da177e4
LT		 520 }
521
522 /* codec ready ? */
523 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
524 return -EIO;
525
a06147d2
TI		 526 if (chip->buggy_semaphore)
527 return 0; /* just ignore ... */
528
1da177e4
LT		 529 /* Anyone holding a semaphore for 1 msec should be shot... */
530 time = 100;
531 do {
532 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
533 return 0;
534 udelay(10);
535 } while (time--);
536
537 /* access to some forbidden (non existant) ac97 registers will not
538 * reset the semaphore. So even if you don't get the semaphore, still
539 * continue the access. We don't need the semaphore anyway. */
99b359ba 540 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 541 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
542 iagetword(chip, 0); /* clear semaphore flag */
543 /* I don't care about the semaphore */
544 return -EBUSY;
545}
546
6b75a9d8 547static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 548 unsigned short reg,
549 unsigned short val)
550{
6b75a9d8 551 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 552
553 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
554 if (! chip->in_ac97_init)
99b359ba 555 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 556 }
557 iaputword(chip, reg + ac97->num * 0x80, val);
558}
559
6b75a9d8 560static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 561 unsigned short reg)
562{
6b75a9d8 563 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 564 unsigned short res;
565 unsigned int tmp;
566
567 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
568 if (! chip->in_ac97_init)
99b359ba 569 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 570 res = 0xffff;
571 } else {
572 res = iagetword(chip, reg + ac97->num * 0x80);
573 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
574 /* reset RCS and preserve other R/WC bits */
6b75a9d8 575 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 576 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4 577 if (! chip->in_ac97_init)
99b359ba 578 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 579 res = 0xffff;
580 }
581 }
582 return res;
583}
584
84a43bd5
TI		 585static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
586 unsigned int codec)
1da177e4
LT		 587{
588 unsigned int tmp;
589
590 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
591 iagetword(chip, codec * 0x80);
592 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
593 /* reset RCS and preserve other R/WC bits */
6b75a9d8 594 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 595 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4
LT		 596 }
597 }
598}
599
600/*
601 * access to AC97 for Ali5455
602 */
6b75a9d8 603static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
1da177e4
LT		 604{
605 int count = 0;
606 for (count = 0; count < 0x7f; count++) {
607 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
608 if (val & mask)
609 return 0;
610 }
79ba34b9
TI		 611 if (! chip->in_ac97_init)
612 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
1da177e4
LT		 613 return -EBUSY;
614}
615
6b75a9d8 616static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
1da177e4
LT		 617{
618 int time = 100;
79ba34b9
TI		 619 if (chip->buggy_semaphore)
620 return 0; /* just ignore ... */
67d8a3c1 621 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
1da177e4 622 udelay(1);
79ba34b9 623 if (! time && ! chip->in_ac97_init)
1da177e4
LT		 624 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
625 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
626}
627
6b75a9d8 628static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 629{
6b75a9d8 630 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 631 unsigned short data = 0xffff;
632
633 if (snd_intel8x0_ali_codec_semaphore(chip))
634 goto __err;
635 reg |= ALI_CPR_ADDR_READ;
636 if (ac97->num)
637 reg |= ALI_CPR_ADDR_SECONDARY;
638 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
639 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
640 goto __err;
641 data = igetword(chip, ICHREG(ALI_SPR));
642 __err:
643 return data;
644}
645
6b75a9d8
TI		 646static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
647 unsigned short val)
1da177e4 648{
6b75a9d8 649 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 650
651 if (snd_intel8x0_ali_codec_semaphore(chip))
652 return;
653 iputword(chip, ICHREG(ALI_CPR), val);
654 if (ac97->num)
655 reg |= ALI_CPR_ADDR_SECONDARY;
656 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
657 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
658}
659
660
661/*
662 * DMA I/O
663 */
6b75a9d8 664static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 665{
666 int idx;
667 u32 *bdbar = ichdev->bdbar;
668 unsigned long port = ichdev->reg_offset;
669
670 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
671 if (ichdev->size == ichdev->fragsize) {
672 ichdev->ack_reload = ichdev->ack = 2;
673 ichdev->fragsize1 = ichdev->fragsize >> 1;
674 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
675 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
676 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
677 ichdev->fragsize1 >> ichdev->pos_shift);
678 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
679 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
680 ichdev->fragsize1 >> ichdev->pos_shift);
681 }
682 ichdev->frags = 2;
683 } else {
684 ichdev->ack_reload = ichdev->ack = 1;
685 ichdev->fragsize1 = ichdev->fragsize;
686 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
6b75a9d8
TI		 687 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
688 (((idx >> 1) * ichdev->fragsize) %
689 ichdev->size));
1da177e4
LT		 690 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
691 ichdev->fragsize >> ichdev->pos_shift);
6b75a9d8 692#if 0
14ab0861 693 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
6b75a9d8
TI		 694 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
695#endif
1da177e4
LT		 696 }
697 ichdev->frags = ichdev->size / ichdev->fragsize;
698 }
699 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
700 ichdev->civ = 0;
701 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
702 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
703 ichdev->position = 0;
704#if 0
14ab0861
TI		 705 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
706 "period_size1 = 0x%x\n",
707 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
708 ichdev->fragsize1);
1da177e4
LT		 709#endif
710 /* clear interrupts */
711 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
712}
713
714#ifdef __i386__
715/*
716 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
717 * which aborts PCI busmaster for audio transfer. A workaround is to set
718 * the pages as non-cached. For details, see the errata in
631dd1a8 719 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
1da177e4
LT		 720 */
721static void fill_nocache(void *buf, int size, int nocache)
722{
723 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
6d238cc4
AV		 724 if (nocache)
725 set_pages_uc(virt_to_page(buf), size);
726 else
727 set_pages_wb(virt_to_page(buf), size);
1da177e4
LT		 728}
729#else
6d238cc4 730#define fill_nocache(buf, size, nocache) do { ; } while (0)
1da177e4
LT		 731#endif
732
733/*
734 * Interrupt handler
735 */
736
6b75a9d8 737static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 738{
739 unsigned long port = ichdev->reg_offset;
883be793 740 unsigned long flags;
1da177e4
LT		 741 int status, civ, i, step;
742 int ack = 0;
743
883be793 744 spin_lock_irqsave(&chip->reg_lock, flags);
1da177e4
LT		 745 status = igetbyte(chip, port + ichdev->roff_sr);
746 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
747 if (!(status & ICH_BCIS)) {
748 step = 0;
749 } else if (civ == ichdev->civ) {
750 // snd_printd("civ same %d\n", civ);
751 step = 1;
752 ichdev->civ++;
753 ichdev->civ &= ICH_REG_LVI_MASK;
754 } else {
755 step = civ - ichdev->civ;
756 if (step < 0)
757 step += ICH_REG_LVI_MASK + 1;
758 // if (step != 1)
759 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
760 ichdev->civ = civ;
761 }
762
763 ichdev->position += step * ichdev->fragsize1;
764 if (! chip->in_measurement)
765 ichdev->position %= ichdev->size;
766 ichdev->lvi += step;
767 ichdev->lvi &= ICH_REG_LVI_MASK;
768 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
769 for (i = 0; i < step; i++) {
770 ichdev->lvi_frag++;
771 ichdev->lvi_frag %= ichdev->frags;
772 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
6b75a9d8 773#if 0
14ab0861
TI		 774 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
775 "all = 0x%x, 0x%x\n",
6b75a9d8
TI		 776 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
777 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
778 inl(port + 4), inb(port + ICH_REG_OFF_CR));
779#endif
1da177e4
LT		 780 if (--ichdev->ack == 0) {
781 ichdev->ack = ichdev->ack_reload;
782 ack = 1;
783 }
784 }
883be793 785 spin_unlock_irqrestore(&chip->reg_lock, flags);
1da177e4
LT		 786 if (ack && ichdev->substream) {
787 snd_pcm_period_elapsed(ichdev->substream);
788 }
789 iputbyte(chip, port + ichdev->roff_sr,
790 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
791}
792
7d12e780 793static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
1da177e4 794{
6b75a9d8
TI		 795 struct intel8x0 *chip = dev_id;
796 struct ichdev *ichdev;
1da177e4
LT		 797 unsigned int status;
798 unsigned int i;
799
800 status = igetdword(chip, chip->int_sta_reg);
801 if (status == 0xffffffff) /* we are not yet resumed */
802 return IRQ_NONE;
803
804 if ((status & chip->int_sta_mask) == 0) {
805 if (status) {
806 /* ack */
807 iputdword(chip, chip->int_sta_reg, status);
808 if (! chip->buggy_irq)
809 status = 0;
810 }
811 return IRQ_RETVAL(status);
812 }
813
814 for (i = 0; i < chip->bdbars_count; i++) {
815 ichdev = &chip->ichd[i];
816 if (status & ichdev->int_sta_mask)
817 snd_intel8x0_update(chip, ichdev);
818 }
819
820 /* ack them */
821 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
822
823 return IRQ_HANDLED;
824}
825
826/*
827 * PCM part
828 */
829
6b75a9d8 830static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 831{
6b75a9d8
TI		 832 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
833 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 834 unsigned char val = 0;
835 unsigned long port = ichdev->reg_offset;
836
837 switch (cmd) {
1da177e4 838 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 839 ichdev->suspended = 0;
840 /* fallthru */
841 case SNDRV_PCM_TRIGGER_START:
da2436a2 842 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4 843 val = ICH_IOCE | ICH_STARTBM;
da2436a2 844 ichdev->last_pos = ichdev->position;
1da177e4 845 break;
1da177e4 846 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 847 ichdev->suspended = 1;
848 /* fallthru */
849 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 850 val = 0;
851 break;
852 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
853 val = ICH_IOCE;
854 break;
1da177e4
LT		 855 default:
856 return -EINVAL;
857 }
858 iputbyte(chip, port + ICH_REG_OFF_CR, val);
859 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
860 /* wait until DMA stopped */
861 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
862 /* reset whole DMA things */
863 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
864 }
865 return 0;
866}
867
6b75a9d8 868static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 869{
6b75a9d8
TI		 870 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
871 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 872 unsigned long port = ichdev->reg_offset;
6b75a9d8
TI		 873 static int fiforeg[] = {
874 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
875 };
1da177e4
LT		 876 unsigned int val, fifo;
877
878 val = igetdword(chip, ICHREG(ALI_DMACR));
879 switch (cmd) {
1cfe43d2
TI		 880 case SNDRV_PCM_TRIGGER_RESUME:
881 ichdev->suspended = 0;
882 /* fallthru */
1da177e4
LT		 883 case SNDRV_PCM_TRIGGER_START:
884 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 885 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
886 /* clear FIFO for synchronization of channels */
887 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
888 fifo &= ~(0xff << (ichdev->ali_slot % 4));
889 fifo |= 0x83 << (ichdev->ali_slot % 4);
890 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
891 }
892 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
893 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
6b75a9d8
TI		 894 /* start DMA */
895 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
1da177e4 896 break;
1cfe43d2
TI		 897 case SNDRV_PCM_TRIGGER_SUSPEND:
898 ichdev->suspended = 1;
899 /* fallthru */
1da177e4
LT		 900 case SNDRV_PCM_TRIGGER_STOP:
901 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
6b75a9d8
TI		 902 /* pause */
903 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
1da177e4
LT		 904 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
905 while (igetbyte(chip, port + ICH_REG_OFF_CR))
906 ;
907 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
908 break;
909 /* reset whole DMA things */
910 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
911 /* clear interrupts */
6b75a9d8
TI		 912 iputbyte(chip, port + ICH_REG_OFF_SR,
913 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
1da177e4
LT		 914 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
915 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
916 break;
917 default:
918 return -EINVAL;
919 }
920 return 0;
921}
922
6b75a9d8
TI		 923static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
924 struct snd_pcm_hw_params *hw_params)
1da177e4 925{
6b75a9d8
TI		 926 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
927 struct ichdev *ichdev = get_ichdev(substream);
928 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 929 int dbl = params_rate(hw_params) > 48000;
930 int err;
931
932 if (chip->fix_nocache && ichdev->page_attr_changed) {
933 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
934 ichdev->page_attr_changed = 0;
935 }
936 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
937 if (err < 0)
938 return err;
939 if (chip->fix_nocache) {
940 if (runtime->dma_area && ! ichdev->page_attr_changed) {
941 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
942 ichdev->page_attr_changed = 1;
943 }
944 }
945 if (ichdev->pcm_open_flag) {
946 snd_ac97_pcm_close(ichdev->pcm);
947 ichdev->pcm_open_flag = 0;
948 }
949 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
950 params_channels(hw_params),
951 ichdev->pcm->r[dbl].slots);
952 if (err >= 0) {
953 ichdev->pcm_open_flag = 1;
954 /* Force SPDIF setting */
955 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
6b75a9d8
TI		 956 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
957 params_rate(hw_params));
1da177e4
LT		 958 }
959 return err;
960}
961
6b75a9d8 962static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
1da177e4 963{
6b75a9d8
TI		 964 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
965 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 966
967 if (ichdev->pcm_open_flag) {
968 snd_ac97_pcm_close(ichdev->pcm);
969 ichdev->pcm_open_flag = 0;
970 }
971 if (chip->fix_nocache && ichdev->page_attr_changed) {
972 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
973 ichdev->page_attr_changed = 0;
974 }
975 return snd_pcm_lib_free_pages(substream);
976}
977
6b75a9d8
TI		 978static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
979 struct snd_pcm_runtime *runtime)
1da177e4
LT		 980{
981 unsigned int cnt;
982 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 983
984 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 985 switch (chip->device_type) {
986 case DEVICE_ALI:
987 cnt = igetdword(chip, ICHREG(ALI_SCR));
988 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
989 if (runtime->channels == 4 || dbl)
990 cnt |= ICH_ALI_SC_PCM_4;
991 else if (runtime->channels == 6)
992 cnt |= ICH_ALI_SC_PCM_6;
993 iputdword(chip, ICHREG(ALI_SCR), cnt);
994 break;
995 case DEVICE_SIS:
996 cnt = igetdword(chip, ICHREG(GLOB_CNT));
997 cnt &= ~ICH_SIS_PCM_246_MASK;
998 if (runtime->channels == 4 || dbl)
999 cnt |= ICH_SIS_PCM_4;
1000 else if (runtime->channels == 6)
1001 cnt |= ICH_SIS_PCM_6;
1002 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1003 break;
1004 default:
1005 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1006 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1007 if (runtime->channels == 4 || dbl)
1008 cnt |= ICH_PCM_4;
1009 else if (runtime->channels == 6)
1010 cnt |= ICH_PCM_6;
4235a317
TI		 1011 else if (runtime->channels == 8)
1012 cnt |= ICH_PCM_8;
1da177e4
LT		 1013 if (chip->device_type == DEVICE_NFORCE) {
1014 /* reset to 2ch once to keep the 6 channel data in alignment,
1015 * to start from Front Left always
1016 */
1017 if (cnt & ICH_PCM_246_MASK) {
1018 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1019 spin_unlock_irq(&chip->reg_lock);
1020 msleep(50); /* grrr... */
1021 spin_lock_irq(&chip->reg_lock);
1022 }
1023 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1024 if (runtime->sample_bits > 16)
1025 cnt |= ICH_PCM_20BIT;
1026 }
1027 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1028 break;
1029 }
1cfe43d2 1030 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1031}
1032
6b75a9d8 1033static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 1034{
6b75a9d8
TI		 1035 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1036 struct snd_pcm_runtime *runtime = substream->runtime;
1037 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1038
1039 ichdev->physbuf = runtime->dma_addr;
1040 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1041 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1042 if (ichdev->ichd == ICHD_PCMOUT) {
1043 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1044 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1045 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1046 }
1047 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1048 return 0;
1049}
1050
6b75a9d8 1051static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1052{
6b75a9d8
TI		 1053 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1054 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 1055 size_t ptr1, ptr;
da2436a2 1056 int civ, timeout = 10;
1da177e4
LT		 1057 unsigned int position;
1058
1059 spin_lock(&chip->reg_lock);
1060 do {
1061 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1062 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1063 position = ichdev->position;
1064 if (ptr1 == 0) {
1065 udelay(10);
1066 continue;
1067 }
1068 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1069 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1070 break;
1071 } while (timeout--);
f708eb1d 1072 ptr = ichdev->last_pos;
da2436a2
JK		 1073 if (ptr1 != 0) {
1074 ptr1 <<= ichdev->pos_shift;
1075 ptr = ichdev->fragsize1 - ptr1;
1076 ptr += position;
f708eb1d
TI		 1077 if (ptr < ichdev->last_pos) {
1078 unsigned int pos_base, last_base;
1079 pos_base = position / ichdev->fragsize1;
1080 last_base = ichdev->last_pos / ichdev->fragsize1;
1081 /* another sanity check; ptr1 can go back to full
1082 * before the base position is updated
1083 */
1084 if (pos_base == last_base)
1085 ptr = ichdev->last_pos;
1086 }
da2436a2 1087 }
f708eb1d 1088 ichdev->last_pos = ptr;
1da177e4
LT		 1089 spin_unlock(&chip->reg_lock);
1090 if (ptr >= ichdev->size)
1091 return 0;
1092 return bytes_to_frames(substream->runtime, ptr);
1093}
1094
6b75a9d8 1095static struct snd_pcm_hardware snd_intel8x0_stream =
1da177e4
LT		 1096{
1097 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE |
1101 SNDRV_PCM_INFO_RESUME),
1102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1103 .rates = SNDRV_PCM_RATE_48000,
1104 .rate_min = 48000,
1105 .rate_max = 48000,
1106 .channels_min = 2,
1107 .channels_max = 2,
1108 .buffer_bytes_max = 128 * 1024,
1109 .period_bytes_min = 32,
1110 .period_bytes_max = 128 * 1024,
1111 .periods_min = 1,
1112 .periods_max = 1024,
1113 .fifo_size = 0,
1114};
1115
1116static unsigned int channels4[] = {
1117 2, 4,
1118};
1119
6b75a9d8 1120static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1da177e4
LT		 1121 .count = ARRAY_SIZE(channels4),
1122 .list = channels4,
1123 .mask = 0,
1124};
1125
1126static unsigned int channels6[] = {
1127 2, 4, 6,
1128};
1129
6b75a9d8 1130static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1da177e4
LT		 1131 .count = ARRAY_SIZE(channels6),
1132 .list = channels6,
1133 .mask = 0,
1134};
1135
4235a317
TI		 1136static unsigned int channels8[] = {
1137 2, 4, 6, 8,
1138};
1139
1140static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1141 .count = ARRAY_SIZE(channels8),
1142 .list = channels8,
1143 .mask = 0,
1144};
1145
6b75a9d8 1146static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1da177e4 1147{
6b75a9d8
TI		 1148 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1149 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1150 int err;
1151
1152 ichdev->substream = substream;
1153 runtime->hw = snd_intel8x0_stream;
1154 runtime->hw.rates = ichdev->pcm->rates;
1155 snd_pcm_limit_hw_rates(runtime);
1156 if (chip->device_type == DEVICE_SIS) {
1157 runtime->hw.buffer_bytes_max = 64*1024;
1158 runtime->hw.period_bytes_max = 64*1024;
1159 }
1160 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1161 return err;
1162 runtime->private_data = ichdev;
1163 return 0;
1164}
1165
6b75a9d8 1166static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1da177e4 1167{
6b75a9d8
TI		 1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1170 int err;
1171
1172 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1173 if (err < 0)
1174 return err;
1175
4235a317
TI		 1176 if (chip->multi8) {
1177 runtime->hw.channels_max = 8;
1178 snd_pcm_hw_constraint_list(runtime, 0,
1179 SNDRV_PCM_HW_PARAM_CHANNELS,
1180 &hw_constraints_channels8);
1181 } else if (chip->multi6) {
1da177e4 1182 runtime->hw.channels_max = 6;
6b75a9d8
TI		 1183 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1184 &hw_constraints_channels6);
1da177e4
LT		 1185 } else if (chip->multi4) {
1186 runtime->hw.channels_max = 4;
6b75a9d8
TI		 1187 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1188 &hw_constraints_channels4);
1da177e4
LT		 1189 }
1190 if (chip->dra) {
1191 snd_ac97_pcm_double_rate_rules(runtime);
1192 }
1193 if (chip->smp20bit) {
1194 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1195 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1196 }
1197 return 0;
1198}
1199
6b75a9d8 1200static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1da177e4 1201{
6b75a9d8 1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1203
1204 chip->ichd[ICHD_PCMOUT].substream = NULL;
1205 return 0;
1206}
1207
6b75a9d8 1208static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1da177e4 1209{
6b75a9d8 1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1211
1212 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1213}
1214
6b75a9d8 1215static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1da177e4 1216{
6b75a9d8 1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1218
1219 chip->ichd[ICHD_PCMIN].substream = NULL;
1220 return 0;
1221}
1222
6b75a9d8 1223static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1da177e4 1224{
6b75a9d8 1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1228}
1229
6b75a9d8 1230static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1da177e4 1231{
6b75a9d8 1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1233
1234 chip->ichd[ICHD_MIC].substream = NULL;
1235 return 0;
1236}
1237
6b75a9d8 1238static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1da177e4 1239{
6b75a9d8 1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1241
1242 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1243}
1244
6b75a9d8 1245static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1da177e4 1246{
6b75a9d8 1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1248
1249 chip->ichd[ICHD_MIC2].substream = NULL;
1250 return 0;
1251}
1252
6b75a9d8 1253static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1da177e4 1254{
6b75a9d8 1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1256
1257 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1258}
1259
6b75a9d8 1260static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1da177e4 1261{
6b75a9d8 1262 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1263
1264 chip->ichd[ICHD_PCM2IN].substream = NULL;
1265 return 0;
1266}
1267
6b75a9d8 1268static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1269{
6b75a9d8 1270 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1271 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1272
1273 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1274}
1275
6b75a9d8 1276static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1277{
6b75a9d8 1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1279 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1280
1281 chip->ichd[idx].substream = NULL;
1282 return 0;
1283}
1284
6b75a9d8 1285static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1286{
6b75a9d8 1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1288 unsigned int val;
1289
1290 spin_lock_irq(&chip->reg_lock);
1291 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1292 val |= ICH_ALI_IF_AC97SP;
1293 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1294 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1295 spin_unlock_irq(&chip->reg_lock);
1296
1297 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1298}
1299
6b75a9d8 1300static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1301{
6b75a9d8 1302 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1303 unsigned int val;
1304
1305 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1306 spin_lock_irq(&chip->reg_lock);
1307 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1308 val &= ~ICH_ALI_IF_AC97SP;
1309 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1310 spin_unlock_irq(&chip->reg_lock);
1311
1312 return 0;
1313}
1314
1a183131 1315#if 0 // NYI
6b75a9d8 1316static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1da177e4 1317{
6b75a9d8 1318 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1321}
1322
6b75a9d8 1323static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1da177e4 1324{
6b75a9d8 1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1326
1327 chip->ichd[ALID_SPDIFIN].substream = NULL;
1328 return 0;
1329}
1330
6b75a9d8 1331static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1332{
6b75a9d8 1333 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1334
1335 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1336}
1337
6b75a9d8 1338static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1339{
6b75a9d8 1340 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1341
1342 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1343 return 0;
1344}
1345#endif
1346
6b75a9d8 1347static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1da177e4
LT		 1348 .open = snd_intel8x0_playback_open,
1349 .close = snd_intel8x0_playback_close,
1350 .ioctl = snd_pcm_lib_ioctl,
1351 .hw_params = snd_intel8x0_hw_params,
1352 .hw_free = snd_intel8x0_hw_free,
1353 .prepare = snd_intel8x0_pcm_prepare,
1354 .trigger = snd_intel8x0_pcm_trigger,
1355 .pointer = snd_intel8x0_pcm_pointer,
1356};
1357
6b75a9d8 1358static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1da177e4
LT		 1359 .open = snd_intel8x0_capture_open,
1360 .close = snd_intel8x0_capture_close,
1361 .ioctl = snd_pcm_lib_ioctl,
1362 .hw_params = snd_intel8x0_hw_params,
1363 .hw_free = snd_intel8x0_hw_free,
1364 .prepare = snd_intel8x0_pcm_prepare,
1365 .trigger = snd_intel8x0_pcm_trigger,
1366 .pointer = snd_intel8x0_pcm_pointer,
1367};
1368
6b75a9d8 1369static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1da177e4
LT		 1370 .open = snd_intel8x0_mic_open,
1371 .close = snd_intel8x0_mic_close,
1372 .ioctl = snd_pcm_lib_ioctl,
1373 .hw_params = snd_intel8x0_hw_params,
1374 .hw_free = snd_intel8x0_hw_free,
1375 .prepare = snd_intel8x0_pcm_prepare,
1376 .trigger = snd_intel8x0_pcm_trigger,
1377 .pointer = snd_intel8x0_pcm_pointer,
1378};
1379
6b75a9d8 1380static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1da177e4
LT		 1381 .open = snd_intel8x0_mic2_open,
1382 .close = snd_intel8x0_mic2_close,
1383 .ioctl = snd_pcm_lib_ioctl,
1384 .hw_params = snd_intel8x0_hw_params,
1385 .hw_free = snd_intel8x0_hw_free,
1386 .prepare = snd_intel8x0_pcm_prepare,
1387 .trigger = snd_intel8x0_pcm_trigger,
1388 .pointer = snd_intel8x0_pcm_pointer,
1389};
1390
6b75a9d8 1391static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1da177e4
LT		 1392 .open = snd_intel8x0_capture2_open,
1393 .close = snd_intel8x0_capture2_close,
1394 .ioctl = snd_pcm_lib_ioctl,
1395 .hw_params = snd_intel8x0_hw_params,
1396 .hw_free = snd_intel8x0_hw_free,
1397 .prepare = snd_intel8x0_pcm_prepare,
1398 .trigger = snd_intel8x0_pcm_trigger,
1399 .pointer = snd_intel8x0_pcm_pointer,
1400};
1401
6b75a9d8 1402static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1da177e4
LT		 1403 .open = snd_intel8x0_spdif_open,
1404 .close = snd_intel8x0_spdif_close,
1405 .ioctl = snd_pcm_lib_ioctl,
1406 .hw_params = snd_intel8x0_hw_params,
1407 .hw_free = snd_intel8x0_hw_free,
1408 .prepare = snd_intel8x0_pcm_prepare,
1409 .trigger = snd_intel8x0_pcm_trigger,
1410 .pointer = snd_intel8x0_pcm_pointer,
1411};
1412
6b75a9d8 1413static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1da177e4
LT		 1414 .open = snd_intel8x0_playback_open,
1415 .close = snd_intel8x0_playback_close,
1416 .ioctl = snd_pcm_lib_ioctl,
1417 .hw_params = snd_intel8x0_hw_params,
1418 .hw_free = snd_intel8x0_hw_free,
1419 .prepare = snd_intel8x0_pcm_prepare,
1420 .trigger = snd_intel8x0_ali_trigger,
1421 .pointer = snd_intel8x0_pcm_pointer,
1422};
1423
6b75a9d8 1424static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1da177e4
LT		 1425 .open = snd_intel8x0_capture_open,
1426 .close = snd_intel8x0_capture_close,
1427 .ioctl = snd_pcm_lib_ioctl,
1428 .hw_params = snd_intel8x0_hw_params,
1429 .hw_free = snd_intel8x0_hw_free,
1430 .prepare = snd_intel8x0_pcm_prepare,
1431 .trigger = snd_intel8x0_ali_trigger,
1432 .pointer = snd_intel8x0_pcm_pointer,
1433};
1434
6b75a9d8 1435static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1da177e4
LT		 1436 .open = snd_intel8x0_mic_open,
1437 .close = snd_intel8x0_mic_close,
1438 .ioctl = snd_pcm_lib_ioctl,
1439 .hw_params = snd_intel8x0_hw_params,
1440 .hw_free = snd_intel8x0_hw_free,
1441 .prepare = snd_intel8x0_pcm_prepare,
1442 .trigger = snd_intel8x0_ali_trigger,
1443 .pointer = snd_intel8x0_pcm_pointer,
1444};
1445
6b75a9d8 1446static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1da177e4
LT		 1447 .open = snd_intel8x0_ali_ac97spdifout_open,
1448 .close = snd_intel8x0_ali_ac97spdifout_close,
1449 .ioctl = snd_pcm_lib_ioctl,
1450 .hw_params = snd_intel8x0_hw_params,
1451 .hw_free = snd_intel8x0_hw_free,
1452 .prepare = snd_intel8x0_pcm_prepare,
1453 .trigger = snd_intel8x0_ali_trigger,
1454 .pointer = snd_intel8x0_pcm_pointer,
1455};
1456
1a183131 1457#if 0 // NYI
6b75a9d8 1458static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1da177e4
LT		 1459 .open = snd_intel8x0_ali_spdifin_open,
1460 .close = snd_intel8x0_ali_spdifin_close,
1461 .ioctl = snd_pcm_lib_ioctl,
1462 .hw_params = snd_intel8x0_hw_params,
1463 .hw_free = snd_intel8x0_hw_free,
1464 .prepare = snd_intel8x0_pcm_prepare,
1465 .trigger = snd_intel8x0_pcm_trigger,
1466 .pointer = snd_intel8x0_pcm_pointer,
1467};
1468
6b75a9d8 1469static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1da177e4
LT		 1470 .open = snd_intel8x0_ali_spdifout_open,
1471 .close = snd_intel8x0_ali_spdifout_close,
1472 .ioctl = snd_pcm_lib_ioctl,
1473 .hw_params = snd_intel8x0_hw_params,
1474 .hw_free = snd_intel8x0_hw_free,
1475 .prepare = snd_intel8x0_pcm_prepare,
1476 .trigger = snd_intel8x0_pcm_trigger,
1477 .pointer = snd_intel8x0_pcm_pointer,
1478};
1479#endif // NYI
1480
1481struct ich_pcm_table {
1482 char *suffix;
6b75a9d8
TI		 1483 struct snd_pcm_ops *playback_ops;
1484 struct snd_pcm_ops *capture_ops;
1da177e4
LT		 1485 size_t prealloc_size;
1486 size_t prealloc_max_size;
1487 int ac97_idx;
1488};
1489
6b75a9d8
TI		 1490static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1491 struct ich_pcm_table *rec)
1da177e4 1492{
6b75a9d8 1493 struct snd_pcm *pcm;
1da177e4
LT		 1494 int err;
1495 char name[32];
1496
1497 if (rec->suffix)
1498 sprintf(name, "Intel ICH - %s", rec->suffix);
1499 else
1500 strcpy(name, "Intel ICH");
1501 err = snd_pcm_new(chip->card, name, device,
1502 rec->playback_ops ? 1 : 0,
1503 rec->capture_ops ? 1 : 0, &pcm);
1504 if (err < 0)
1505 return err;
1506
1507 if (rec->playback_ops)
1508 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1509 if (rec->capture_ops)
1510 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1511
1512 pcm->private_data = chip;
1513 pcm->info_flags = 0;
1514 if (rec->suffix)
1515 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1516 else
1517 strcpy(pcm->name, chip->card->shortname);
1518 chip->pcm[device] = pcm;
1519
6b75a9d8
TI		 1520 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1521 snd_dma_pci_data(chip->pci),
1da177e4
LT		 1522 rec->prealloc_size, rec->prealloc_max_size);
1523
1524 return 0;
1525}
1526
1527static struct ich_pcm_table intel_pcms[] __devinitdata = {
1528 {
1529 .playback_ops = &snd_intel8x0_playback_ops,
1530 .capture_ops = &snd_intel8x0_capture_ops,
1531 .prealloc_size = 64 * 1024,
1532 .prealloc_max_size = 128 * 1024,
1533 },
1534 {
1535 .suffix = "MIC ADC",
1536 .capture_ops = &snd_intel8x0_capture_mic_ops,
1537 .prealloc_size = 0,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = ICHD_MIC,
1540 },
1541 {
1542 .suffix = "MIC2 ADC",
1543 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1544 .prealloc_size = 0,
1545 .prealloc_max_size = 128 * 1024,
1546 .ac97_idx = ICHD_MIC2,
1547 },
1548 {
1549 .suffix = "ADC2",
1550 .capture_ops = &snd_intel8x0_capture2_ops,
1551 .prealloc_size = 0,
1552 .prealloc_max_size = 128 * 1024,
1553 .ac97_idx = ICHD_PCM2IN,
1554 },
1555 {
1556 .suffix = "IEC958",
1557 .playback_ops = &snd_intel8x0_spdif_ops,
1558 .prealloc_size = 64 * 1024,
1559 .prealloc_max_size = 128 * 1024,
1560 .ac97_idx = ICHD_SPBAR,
1561 },
1562};
1563
1564static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1565 {
1566 .playback_ops = &snd_intel8x0_playback_ops,
1567 .capture_ops = &snd_intel8x0_capture_ops,
1568 .prealloc_size = 64 * 1024,
1569 .prealloc_max_size = 128 * 1024,
1570 },
1571 {
1572 .suffix = "MIC ADC",
1573 .capture_ops = &snd_intel8x0_capture_mic_ops,
1574 .prealloc_size = 0,
1575 .prealloc_max_size = 128 * 1024,
1576 .ac97_idx = NVD_MIC,
1577 },
1578 {
1579 .suffix = "IEC958",
1580 .playback_ops = &snd_intel8x0_spdif_ops,
1581 .prealloc_size = 64 * 1024,
1582 .prealloc_max_size = 128 * 1024,
1583 .ac97_idx = NVD_SPBAR,
1584 },
1585};
1586
1587static struct ich_pcm_table ali_pcms[] __devinitdata = {
1588 {
1589 .playback_ops = &snd_intel8x0_ali_playback_ops,
1590 .capture_ops = &snd_intel8x0_ali_capture_ops,
1591 .prealloc_size = 64 * 1024,
1592 .prealloc_max_size = 128 * 1024,
1593 },
1594 {
1595 .suffix = "MIC ADC",
1596 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1597 .prealloc_size = 0,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ALID_MIC,
1600 },
1601 {
1602 .suffix = "IEC958",
1603 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1a183131 1604 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1da177e4
LT		 1605 .prealloc_size = 64 * 1024,
1606 .prealloc_max_size = 128 * 1024,
1607 .ac97_idx = ALID_AC97SPDIFOUT,
1608 },
1609#if 0 // NYI
1610 {
1611 .suffix = "HW IEC958",
1612 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1613 .prealloc_size = 64 * 1024,
1614 .prealloc_max_size = 128 * 1024,
1615 },
1616#endif
1617};
1618
6b75a9d8 1619static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1da177e4
LT		 1620{
1621 int i, tblsize, device, err;
1622 struct ich_pcm_table *tbl, *rec;
1623
1624 switch (chip->device_type) {
1625 case DEVICE_INTEL_ICH4:
1626 tbl = intel_pcms;
1627 tblsize = ARRAY_SIZE(intel_pcms);
a9e99660
TI		 1628 if (spdif_aclink)
1629 tblsize--;
1da177e4
LT		 1630 break;
1631 case DEVICE_NFORCE:
1632 tbl = nforce_pcms;
1633 tblsize = ARRAY_SIZE(nforce_pcms);
a9e99660
TI		 1634 if (spdif_aclink)
1635 tblsize--;
1da177e4
LT		 1636 break;
1637 case DEVICE_ALI:
1638 tbl = ali_pcms;
1639 tblsize = ARRAY_SIZE(ali_pcms);
1640 break;
1641 default:
1642 tbl = intel_pcms;
1643 tblsize = 2;
1644 break;
1645 }
1646
1647 device = 0;
1648 for (i = 0; i < tblsize; i++) {
1649 rec = tbl + i;
1650 if (i > 0 && rec->ac97_idx) {
1651 /* activate PCM only when associated AC'97 codec */
1652 if (! chip->ichd[rec->ac97_idx].pcm)
1653 continue;
1654 }
1655 err = snd_intel8x0_pcm1(chip, device, rec);
1656 if (err < 0)
1657 return err;
1658 device++;
1659 }
1660
1661 chip->pcm_devs = device;
1662 return 0;
1663}
1664
1665
1666/*
1667 * Mixer part
1668 */
1669
6b75a9d8 1670static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1671{
6b75a9d8 1672 struct intel8x0 *chip = bus->private_data;
1da177e4
LT		 1673 chip->ac97_bus = NULL;
1674}
1675
6b75a9d8 1676static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1677{
6b75a9d8 1678 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 1679 chip->ac97[ac97->num] = NULL;
1680}
1681
1682static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1683 /* front PCM */
1684 {
1685 .exclusive = 1,
1686 .r = { {
1687 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1688 (1 << AC97_SLOT_PCM_RIGHT) |
1689 (1 << AC97_SLOT_PCM_CENTER) |
1690 (1 << AC97_SLOT_PCM_SLEFT) |
1691 (1 << AC97_SLOT_PCM_SRIGHT) |
1692 (1 << AC97_SLOT_LFE)
1693 },
1694 {
1695 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1696 (1 << AC97_SLOT_PCM_RIGHT) |
1697 (1 << AC97_SLOT_PCM_LEFT_0) |
1698 (1 << AC97_SLOT_PCM_RIGHT_0)
1699 }
1700 }
1701 },
1702 /* PCM IN #1 */
1703 {
1704 .stream = 1,
1705 .exclusive = 1,
1706 .r = { {
1707 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1708 (1 << AC97_SLOT_PCM_RIGHT)
1709 }
1710 }
1711 },
1712 /* MIC IN #1 */
1713 {
1714 .stream = 1,
1715 .exclusive = 1,
1716 .r = { {
1717 .slots = (1 << AC97_SLOT_MIC)
1718 }
1719 }
1720 },
1721 /* S/PDIF PCM */
1722 {
1723 .exclusive = 1,
1724 .spdif = 1,
1725 .r = { {
1726 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1727 (1 << AC97_SLOT_SPDIF_RIGHT2)
1728 }
1729 }
1730 },
1731 /* PCM IN #2 */
1732 {
1733 .stream = 1,
1734 .exclusive = 1,
1735 .r = { {
1736 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1737 (1 << AC97_SLOT_PCM_RIGHT)
1738 }
1739 }
1740 },
1741 /* MIC IN #2 */
1742 {
1743 .stream = 1,
1744 .exclusive = 1,
1745 .r = { {
1746 .slots = (1 << AC97_SLOT_MIC)
1747 }
1748 }
1749 },
1750};
1751
1752static struct ac97_quirk ac97_quirks[] __devinitdata = {
0d9ac27a
TI		 1753 {
1754 .subvendor = 0x0e11,
1755 .subdevice = 0x000e,
1756 .name = "Compaq Deskpro EN", /* AD1885 */
1757 .type = AC97_TUNE_HP_ONLY
1758 },
1da177e4 1759 {
6fd8b87f
JCD		 1760 .subvendor = 0x0e11,
1761 .subdevice = 0x008a,
1da177e4
LT		 1762 .name = "Compaq Evo W4000", /* AD1885 */
1763 .type = AC97_TUNE_HP_ONLY
1764 },
1765 {
6fd8b87f
JCD		 1766 .subvendor = 0x0e11,
1767 .subdevice = 0x00b8,
1da177e4
LT		 1768 .name = "Compaq Evo D510C",
1769 .type = AC97_TUNE_HP_ONLY
1770 },
1771 {
6fd8b87f
JCD		 1772 .subvendor = 0x0e11,
1773 .subdevice = 0x0860,
1da177e4
LT		 1774 .name = "HP/Compaq nx7010",
1775 .type = AC97_TUNE_MUTE_LED
1776 },
9c77b846
DC		 1777 {
1778 .subvendor = 0x1014,
1779 .subdevice = 0x0534,
1780 .name = "ThinkPad X31",
1781 .type = AC97_TUNE_INV_EAPD
1782 },
1da177e4 1783 {
6fd8b87f
JCD		 1784 .subvendor = 0x1014,
1785 .subdevice = 0x1f00,
1da177e4
LT		 1786 .name = "MS-9128",
1787 .type = AC97_TUNE_ALC_JACK
1788 },
5d529390
TI		 1789 {
1790 .subvendor = 0x1014,
1791 .subdevice = 0x0267,
1792 .name = "IBM NetVista A30p", /* AD1981B */
1793 .type = AC97_TUNE_HP_ONLY
b6a370b6
TI		 1794 },
1795 {
1796 .subvendor = 0x1025,
1797 .subdevice = 0x0082,
1798 .name = "Acer Travelmate 2310",
1799 .type = AC97_TUNE_HP_ONLY
5d529390 1800 },
72c8986c
DS		 1801 {
1802 .subvendor = 0x1025,
1803 .subdevice = 0x0083,
1804 .name = "Acer Aspire 3003LCi",
1805 .type = AC97_TUNE_HP_ONLY
1806 },
1da177e4 1807 {
6fd8b87f
JCD		 1808 .subvendor = 0x1028,
1809 .subdevice = 0x00d8,
1da177e4
LT		 1810 .name = "Dell Precision 530", /* AD1885 */
1811 .type = AC97_TUNE_HP_ONLY
1812 },
1813 {
6fd8b87f
JCD		 1814 .subvendor = 0x1028,
1815 .subdevice = 0x010d,
1da177e4
LT		 1816 .name = "Dell", /* which model? AD1885 */
1817 .type = AC97_TUNE_HP_ONLY
1818 },
1819 {
6fd8b87f
JCD		 1820 .subvendor = 0x1028,
1821 .subdevice = 0x0126,
1da177e4
LT		 1822 .name = "Dell Optiplex GX260", /* AD1981A */
1823 .type = AC97_TUNE_HP_ONLY
1824 },
1825 {
6fd8b87f
JCD		 1826 .subvendor = 0x1028,
1827 .subdevice = 0x012c,
1da177e4
LT		 1828 .name = "Dell Precision 650", /* AD1981A */
1829 .type = AC97_TUNE_HP_ONLY
1830 },
1831 {
6fd8b87f
JCD		 1832 .subvendor = 0x1028,
1833 .subdevice = 0x012d,
1da177e4
LT		 1834 .name = "Dell Precision 450", /* AD1981B*/
1835 .type = AC97_TUNE_HP_ONLY
1836 },
1837 {
6fd8b87f
JCD		 1838 .subvendor = 0x1028,
1839 .subdevice = 0x0147,
1da177e4
LT		 1840 .name = "Dell", /* which model? AD1981B*/
1841 .type = AC97_TUNE_HP_ONLY
1842 },
c9fe51c4
CB		 1843 {
1844 .subvendor = 0x1028,
1845 .subdevice = 0x0151,
1846 .name = "Dell Optiplex GX270", /* AD1981B */
1847 .type = AC97_TUNE_HP_ONLY
1848 },
1781a9af
DC		 1849 {
1850 .subvendor = 0x1028,
1851 .subdevice = 0x014e,
1852 .name = "Dell D800", /* STAC9750/51 */
1853 .type = AC97_TUNE_HP_ONLY
1854 },
1da177e4 1855 {
6fd8b87f
JCD		 1856 .subvendor = 0x1028,
1857 .subdevice = 0x0163,
1da177e4
LT		 1858 .name = "Dell Unknown", /* STAC9750/51 */
1859 .type = AC97_TUNE_HP_ONLY
1860 },
c8283425
DC		 1861 {
1862 .subvendor = 0x1028,
1863 .subdevice = 0x016a,
1864 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1865 .type = AC97_TUNE_HP_ONLY
0613a594
DC		 1866 },
1867 {
1868 .subvendor = 0x1028,
1869 .subdevice = 0x0182,
1870 .name = "Dell Latitude D610", /* STAC9750/51 */
1871 .type = AC97_TUNE_HP_ONLY
c8283425 1872 },
8286c53e
DC		 1873 {
1874 .subvendor = 0x1028,
1875 .subdevice = 0x0186,
1876 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1877 .type = AC97_TUNE_HP_MUTE_LED
1878 },
1879 {
1880 .subvendor = 0x1028,
1881 .subdevice = 0x0188,
1882 .name = "Dell Inspiron 6000",
1883 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1884 },
6d6f9156
KL		 1885 {
1886 .subvendor = 0x1028,
1887 .subdevice = 0x0191,
1888 .name = "Dell Inspiron 8600",
1889 .type = AC97_TUNE_HP_ONLY
1890 },
1da177e4 1891 {
6fd8b87f
JCD		 1892 .subvendor = 0x103c,
1893 .subdevice = 0x006d,
1da177e4
LT		 1894 .name = "HP zv5000",
1895 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1896 },
1897 { /* FIXME: which codec? */
6fd8b87f
JCD		 1898 .subvendor = 0x103c,
1899 .subdevice = 0x00c3,
1da177e4
LT		 1900 .name = "HP xw6000",
1901 .type = AC97_TUNE_HP_ONLY
1902 },
1903 {
6fd8b87f
JCD		 1904 .subvendor = 0x103c,
1905 .subdevice = 0x088c,
1da177e4 1906 .name = "HP nc8000",
8286c53e 1907 .type = AC97_TUNE_HP_MUTE_LED
1da177e4
LT		 1908 },
1909 {
6fd8b87f
JCD		 1910 .subvendor = 0x103c,
1911 .subdevice = 0x0890,
1da177e4
LT		 1912 .name = "HP nc6000",
1913 .type = AC97_TUNE_MUTE_LED
1914 },
1915 {
6fd8b87f
JCD		 1916 .subvendor = 0x103c,
1917 .subdevice = 0x129d,
1da177e4
LT		 1918 .name = "HP xw8000",
1919 .type = AC97_TUNE_HP_ONLY
1920 },
a0faefed
MG		 1921 {
1922 .subvendor = 0x103c,
1923 .subdevice = 0x0938,
1924 .name = "HP nc4200",
1925 .type = AC97_TUNE_HP_MUTE_LED
1926 },
1927 {
1928 .subvendor = 0x103c,
1929 .subdevice = 0x099c,
d82ed2ff 1930 .name = "HP nx6110/nc6120",
a0faefed
MG		 1931 .type = AC97_TUNE_HP_MUTE_LED
1932 },
1933 {
1934 .subvendor = 0x103c,
1935 .subdevice = 0x0944,
1936 .name = "HP nc6220",
1937 .type = AC97_TUNE_HP_MUTE_LED
1938 },
1939 {
1940 .subvendor = 0x103c,
1941 .subdevice = 0x0934,
1942 .name = "HP nc8220",
1943 .type = AC97_TUNE_HP_MUTE_LED
1944 },
1da177e4 1945 {
6fd8b87f
JCD		 1946 .subvendor = 0x103c,
1947 .subdevice = 0x12f1,
1da177e4
LT		 1948 .name = "HP xw8200", /* AD1981B*/
1949 .type = AC97_TUNE_HP_ONLY
1950 },
1951 {
6fd8b87f
JCD		 1952 .subvendor = 0x103c,
1953 .subdevice = 0x12f2,
1da177e4
LT		 1954 .name = "HP xw6200",
1955 .type = AC97_TUNE_HP_ONLY
1956 },
1957 {
6fd8b87f
JCD		 1958 .subvendor = 0x103c,
1959 .subdevice = 0x3008,
1da177e4
LT		 1960 .name = "HP xw4200", /* AD1981B*/
1961 .type = AC97_TUNE_HP_ONLY
1962 },
7e6c3989
DC		 1963 {
1964 .subvendor = 0x104d,
1965 .subdevice = 0x8144,
1966 .name = "Sony",
1967 .type = AC97_TUNE_INV_EAPD
1968 },
1da177e4 1969 {
6fd8b87f
JCD		 1970 .subvendor = 0x104d,
1971 .subdevice = 0x8197,
1da177e4
LT		 1972 .name = "Sony S1XP",
1973 .type = AC97_TUNE_INV_EAPD
1974 },
5da5b6f9
DC		 1975 {
1976 .subvendor = 0x104d,
1977 .subdevice = 0x81c0,
1978 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1979 .type = AC97_TUNE_INV_EAPD
1980 },
ebb6f6ac
DC		 1981 {
1982 .subvendor = 0x104d,
1983 .subdevice = 0x81c5,
1984 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1985 .type = AC97_TUNE_INV_EAPD
1986 },
1da177e4 1987 {
6fd8b87f
JCD		 1988 .subvendor = 0x1043,
1989 .subdevice = 0x80f3,
1da177e4
LT		 1990 .name = "ASUS ICH5/AD1985",
1991 .type = AC97_TUNE_AD_SHARING
1992 },
1993 {
6fd8b87f
JCD		 1994 .subvendor = 0x10cf,
1995 .subdevice = 0x11c3,
1da177e4
LT		 1996 .name = "Fujitsu-Siemens E4010",
1997 .type = AC97_TUNE_HP_ONLY
1998 },
98c7f212
TI		 1999 {
2000 .subvendor = 0x10cf,
2001 .subdevice = 0x1225,
2002 .name = "Fujitsu-Siemens T3010",
2003 .type = AC97_TUNE_HP_ONLY
2004 },
1da177e4 2005 {
6fd8b87f
JCD		 2006 .subvendor = 0x10cf,
2007 .subdevice = 0x1253,
1da177e4
LT		 2008 .name = "Fujitsu S6210", /* STAC9750/51 */
2009 .type = AC97_TUNE_HP_ONLY
2010 },
37c34ffb
TI		 2011 {
2012 .subvendor = 0x10cf,
2013 .subdevice = 0x127d,
2014 .name = "Fujitsu Lifebook P7010",
2015 .type = AC97_TUNE_HP_ONLY
2016 },
8286c53e
DC		 2017 {
2018 .subvendor = 0x10cf,
2019 .subdevice = 0x127e,
2020 .name = "Fujitsu Lifebook C1211D",
2021 .type = AC97_TUNE_HP_ONLY
2022 },
9970dce5
TI		 2023 {
2024 .subvendor = 0x10cf,
2025 .subdevice = 0x12ec,
2026 .name = "Fujitsu-Siemens 4010",
2027 .type = AC97_TUNE_HP_ONLY
2028 },
2eb061f4
JK		 2029 {
2030 .subvendor = 0x10cf,
2031 .subdevice = 0x12f2,
2032 .name = "Fujitsu-Siemens Celsius H320",
2033 .type = AC97_TUNE_SWAP_HP
2034 },
1da177e4 2035 {
6fd8b87f
JCD		 2036 .subvendor = 0x10f1,
2037 .subdevice = 0x2665,
1da177e4
LT		 2038 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2039 .type = AC97_TUNE_HP_ONLY
2040 },
2041 {
6fd8b87f
JCD		 2042 .subvendor = 0x10f1,
2043 .subdevice = 0x2885,
1da177e4
LT		 2044 .name = "AMD64 Mobo", /* ALC650 */
2045 .type = AC97_TUNE_HP_ONLY
2046 },
4f42bcc1
TI		 2047 {
2048 .subvendor = 0x10f1,
2049 .subdevice = 0x2895,
2050 .name = "Tyan Thunder K8WE",
2051 .type = AC97_TUNE_HP_ONLY
2052 },
6c504447
KP		 2053 {
2054 .subvendor = 0x10f7,
2055 .subdevice = 0x834c,
2056 .name = "Panasonic CF-R4",
2057 .type = AC97_TUNE_HP_ONLY,
2058 },
1da177e4 2059 {
6fd8b87f
JCD		 2060 .subvendor = 0x110a,
2061 .subdevice = 0x0056,
1da177e4
LT		 2062 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2063 .type = AC97_TUNE_HP_ONLY
2064 },
2065 {
6fd8b87f
JCD		 2066 .subvendor = 0x11d4,
2067 .subdevice = 0x5375,
1da177e4
LT		 2068 .name = "ADI AD1985 (discrete)",
2069 .type = AC97_TUNE_HP_ONLY
2070 },
2071 {
6fd8b87f
JCD		 2072 .subvendor = 0x1462,
2073 .subdevice = 0x5470,
1da177e4
LT		 2074 .name = "MSI P4 ATX 645 Ultra",
2075 .type = AC97_TUNE_HP_ONLY
2076 },
bbb3c644
DC		 2077 {
2078 .subvendor = 0x161f,
2079 .subdevice = 0x203a,
2080 .name = "Gateway 4525GZ", /* AD1981B */
2081 .type = AC97_TUNE_INV_EAPD
2082 },
1da177e4 2083 {
6fd8b87f
JCD		 2084 .subvendor = 0x1734,
2085 .subdevice = 0x0088,
1da177e4
LT		 2086 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2087 .type = AC97_TUNE_HP_ONLY
2088 },
2089 {
6fd8b87f
JCD		 2090 .subvendor = 0x8086,
2091 .subdevice = 0x2000,
1da177e4
LT		 2092 .mask = 0xfff0,
2093 .name = "Intel ICH5/AD1985",
2094 .type = AC97_TUNE_AD_SHARING
2095 },
2096 {
6fd8b87f
JCD		 2097 .subvendor = 0x8086,
2098 .subdevice = 0x4000,
1da177e4
LT		 2099 .mask = 0xfff0,
2100 .name = "Intel ICH5/AD1985",
2101 .type = AC97_TUNE_AD_SHARING
2102 },
2103 {
6fd8b87f
JCD		 2104 .subvendor = 0x8086,
2105 .subdevice = 0x4856,
1da177e4
LT		 2106 .name = "Intel D845WN (82801BA)",
2107 .type = AC97_TUNE_SWAP_HP
2108 },
2109 {
6fd8b87f
JCD		 2110 .subvendor = 0x8086,
2111 .subdevice = 0x4d44,
1da177e4
LT		 2112 .name = "Intel D850EMV2", /* AD1885 */
2113 .type = AC97_TUNE_HP_ONLY
2114 },
2115 {
6fd8b87f
JCD		 2116 .subvendor = 0x8086,
2117 .subdevice = 0x4d56,
1da177e4
LT		 2118 .name = "Intel ICH/AD1885",
2119 .type = AC97_TUNE_HP_ONLY
2120 },
2121 {
6fd8b87f
JCD		 2122 .subvendor = 0x8086,
2123 .subdevice = 0x6000,
1da177e4
LT		 2124 .mask = 0xfff0,
2125 .name = "Intel ICH5/AD1985",
2126 .type = AC97_TUNE_AD_SHARING
2127 },
2128 {
6fd8b87f
JCD		 2129 .subvendor = 0x8086,
2130 .subdevice = 0xe000,
1da177e4
LT		 2131 .mask = 0xfff0,
2132 .name = "Intel ICH5/AD1985",
2133 .type = AC97_TUNE_AD_SHARING
2134 },
2135#if 0 /* FIXME: this seems wrong on most boards */
2136 {
6fd8b87f
JCD		 2137 .subvendor = 0x8086,
2138 .subdevice = 0xa000,
1da177e4
LT		 2139 .mask = 0xfff0,
2140 .name = "Intel ICH5/AD1985",
2141 .type = AC97_TUNE_HP_ONLY
2142 },
2143#endif
2144 { } /* terminator */
2145};
2146
6b75a9d8
TI		 2147static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2148 const char *quirk_override)
1da177e4 2149{
6b75a9d8
TI		 2150 struct snd_ac97_bus *pbus;
2151 struct snd_ac97_template ac97;
1da177e4
LT		 2152 int err;
2153 unsigned int i, codecs;
2154 unsigned int glob_sta = 0;
6b75a9d8
TI		 2155 struct snd_ac97_bus_ops *ops;
2156 static struct snd_ac97_bus_ops standard_bus_ops = {
1da177e4
LT		 2157 .write = snd_intel8x0_codec_write,
2158 .read = snd_intel8x0_codec_read,
2159 };
6b75a9d8 2160 static struct snd_ac97_bus_ops ali_bus_ops = {
1da177e4
LT		 2161 .write = snd_intel8x0_ali_codec_write,
2162 .read = snd_intel8x0_ali_codec_read,
2163 };
2164
2165 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
a9e99660
TI		 2166 if (!spdif_aclink) {
2167 switch (chip->device_type) {
2168 case DEVICE_NFORCE:
2169 chip->spdif_idx = NVD_SPBAR;
2170 break;
2171 case DEVICE_ALI:
2172 chip->spdif_idx = ALID_AC97SPDIFOUT;
2173 break;
2174 case DEVICE_INTEL_ICH4:
2175 chip->spdif_idx = ICHD_SPBAR;
2176 break;
2177 };
2178 }
1da177e4
LT		 2179
2180 chip->in_ac97_init = 1;
2181
2182 memset(&ac97, 0, sizeof(ac97));
2183 ac97.private_data = chip;
2184 ac97.private_free = snd_intel8x0_mixer_free_ac97;
f1a63a38 2185 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 2186 if (chip->xbox)
2187 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2188 if (chip->device_type != DEVICE_ALI) {
2189 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2190 ops = &standard_bus_ops;
84a43bd5
TI		 2191 chip->in_sdin_init = 1;
2192 codecs = 0;
2193 for (i = 0; i < chip->max_codecs; i++) {
2194 if (! (glob_sta & chip->codec_bit[i]))
2195 continue;
2196 if (chip->device_type == DEVICE_INTEL_ICH4) {
2197 snd_intel8x0_codec_read_test(chip, codecs);
2198 chip->ac97_sdin[codecs] =
2199 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
da3cec35
TI		 2200 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2201 chip->ac97_sdin[codecs] = 0;
84a43bd5
TI		 2202 } else
2203 chip->ac97_sdin[codecs] = i;
2204 codecs++;
1da177e4 2205 }
84a43bd5
TI		 2206 chip->in_sdin_init = 0;
2207 if (! codecs)
2208 codecs = 1;
1da177e4
LT		 2209 } else {
2210 ops = &ali_bus_ops;
2211 codecs = 1;
2212 /* detect the secondary codec */
2213 for (i = 0; i < 100; i++) {
2214 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2215 if (reg & 0x40) {
2216 codecs = 2;
2217 break;
2218 }
2219 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2220 udelay(1);
2221 }
2222 }
2223 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2224 goto __err;
2225 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2226 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2227 pbus->clock = ac97_clock;
2228 /* FIXME: my test board doesn't work well with VRA... */
2229 if (chip->device_type == DEVICE_ALI)
2230 pbus->no_vra = 1;
2231 else
2232 pbus->dra = 1;
2233 chip->ac97_bus = pbus;
84a43bd5 2234 chip->ncodecs = codecs;
1da177e4
LT		 2235
2236 ac97.pci = chip->pci;
2237 for (i = 0; i < codecs; i++) {
2238 ac97.num = i;
2239 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2240 if (err != -EACCES)
2241 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2242 if (i == 0)
2243 goto __err;
1da177e4
LT		 2244 }
2245 }
2246 /* tune up the primary codec */
2247 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2248 /* enable separate SDINs for ICH4 */
2249 if (chip->device_type == DEVICE_INTEL_ICH4)
2250 pbus->isdin = 1;
2251 /* find the available PCM streams */
2252 i = ARRAY_SIZE(ac97_pcm_defs);
2253 if (chip->device_type != DEVICE_INTEL_ICH4)
2254 i -= 2; /* do not allocate PCM2IN and MIC2 */
2255 if (chip->spdif_idx < 0)
2256 i--; /* do not allocate S/PDIF */
2257 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2258 if (err < 0)
2259 goto __err;
2260 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2261 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2262 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2263 if (chip->spdif_idx >= 0)
2264 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2265 if (chip->device_type == DEVICE_INTEL_ICH4) {
2266 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2267 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2268 }
2269 /* enable separate SDINs for ICH4 */
2270 if (chip->device_type == DEVICE_INTEL_ICH4) {
2271 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2272 u8 tmp = igetbyte(chip, ICHREG(SDM));
2273 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2274 if (pcm) {
2275 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2276 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2277 for (i = 1; i < 4; i++) {
2278 if (pcm->r[0].codec[i]) {
2279 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2280 break;
2281 }
2282 }
2283 } else {
2284 tmp &= ~ICH_SE; /* steer disable */
2285 }
2286 iputbyte(chip, ICHREG(SDM), tmp);
2287 }
2288 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2289 chip->multi4 = 1;
4235a317 2290 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
1da177e4 2291 chip->multi6 = 1;
4235a317
TI		 2292 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2293 chip->multi8 = 1;
2294 }
1da177e4
LT		 2295 }
2296 if (pbus->pcms[0].r[1].rslots[0]) {
2297 chip->dra = 1;
2298 }
2299 if (chip->device_type == DEVICE_INTEL_ICH4) {
2300 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2301 chip->smp20bit = 1;
2302 }
a9e99660 2303 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2304 /* 48kHz only */
2305 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2306 }
a9e99660 2307 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
1da177e4
LT		 2308 /* use slot 10/11 for SPDIF */
2309 u32 val;
2310 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2311 val |= ICH_PCM_SPDIF_1011;
2312 iputdword(chip, ICHREG(GLOB_CNT), val);
2313 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2314 }
2315 chip->in_ac97_init = 0;
2316 return 0;
2317
2318 __err:
2319 /* clear the cold-reset bit for the next chance */
2320 if (chip->device_type != DEVICE_ALI)
6b75a9d8
TI		 2321 iputdword(chip, ICHREG(GLOB_CNT),
2322 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1da177e4
LT		 2323 return err;
2324}
2325
2326
2327/*
2328 *
2329 */
2330
6b75a9d8 2331static void do_ali_reset(struct intel8x0 *chip)
1da177e4
LT		 2332{
2333 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2334 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2335 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2336 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2337 iputdword(chip, ICHREG(ALI_INTERFACECR),
d78bec21 2338 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1da177e4
LT		 2339 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2340 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2341}
2342
e3e9c5e7
TLSC		 2343#ifdef CONFIG_SND_AC97_POWER_SAVE
2344static struct snd_pci_quirk ich_chip_reset_mode[] = {
2345 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2346 { } /* end */
2347};
1da177e4 2348
e3e9c5e7
TLSC		 2349static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2350{
2351 unsigned int cnt;
1da177e4 2352 /* ACLink on, 2 channels */
e3e9c5e7
TLSC		 2353
2354 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2355 return -EIO;
2356
1da177e4
LT		 2357 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2358 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
e3e9c5e7 2359
6dbe6628
TI		 2360 /* do cold reset - the full ac97 powerdown may leave the controller
2361 * in a warm state but actually it cannot communicate with the codec.
2362 */
2363 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2364 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2365 udelay(10);
2366 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2367 msleep(1);
e3e9c5e7
TLSC		 2368 return 0;
2369}
2370#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2371 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
6dbe6628 2372#else
e1672800 2373#define snd_intel8x0_ich_chip_cold_reset(chip) 0
e3e9c5e7
TLSC		 2374#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2375#endif
2376
2377static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2378{
2379 unsigned long end_time;
2380 unsigned int cnt;
2381 /* ACLink on, 2 channels */
2382 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2383 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
1da177e4
LT		 2384 /* finish cold or do warm reset */
2385 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2386 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2387 end_time = (jiffies + (HZ / 4)) + 1;
2388 do {
2389 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
e3e9c5e7 2390 return 0;
954bea35 2391 schedule_timeout_uninterruptible(1);
1da177e4 2392 } while (time_after_eq(end_time, jiffies));
6b75a9d8
TI		 2393 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2394 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4 2395 return -EIO;
e3e9c5e7
TLSC		 2396}
2397
2398static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2399{
2400 unsigned long end_time;
2401 unsigned int status, nstatus;
2402 unsigned int cnt;
2403 int err;
2404
2405 /* put logic to right state */
2406 /* first clear status bits */
2407 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2408 if (chip->device_type == DEVICE_NFORCE)
2409 status |= ICH_NVSPINT;
2410 cnt = igetdword(chip, ICHREG(GLOB_STA));
2411 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2412
2413 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2414 err = snd_intel8x0_ich_chip_cold_reset(chip);
2415 else
2416 err = snd_intel8x0_ich_chip_reset(chip);
2417 if (err < 0)
2418 return err;
1da177e4 2419
1da177e4
LT		 2420 if (probing) {
2421 /* wait for any codec ready status.
2422 * Once it becomes ready it should remain ready
2423 * as long as we do not disable the ac97 link.
2424 */
2425 end_time = jiffies + HZ;
2426 do {
6b75a9d8 2427 status = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2428 chip->codec_isr_bits;
1da177e4
LT		 2429 if (status)
2430 break;
954bea35 2431 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2432 } while (time_after_eq(end_time, jiffies));
2433 if (! status) {
2434 /* no codec is found */
6b75a9d8
TI		 2435 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2436 igetdword(chip, ICHREG(GLOB_STA)));
1da177e4
LT		 2437 return -EIO;
2438 }
2439
1da177e4
LT		 2440 /* wait for other codecs ready status. */
2441 end_time = jiffies + HZ / 4;
84a43bd5
TI		 2442 while (status != chip->codec_isr_bits &&
2443 time_after_eq(end_time, jiffies)) {
954bea35 2444 schedule_timeout_uninterruptible(1);
84a43bd5
TI		 2445 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2446 chip->codec_isr_bits;
1da177e4
LT		 2447 }
2448
2449 } else {
2450 /* resume phase */
2451 int i;
2452 status = 0;
84a43bd5 2453 for (i = 0; i < chip->ncodecs; i++)
1da177e4 2454 if (chip->ac97[i])
84a43bd5 2455 status |= chip->codec_bit[chip->ac97_sdin[i]];
1da177e4
LT		 2456 /* wait until all the probed codecs are ready */
2457 end_time = jiffies + HZ;
2458 do {
6b75a9d8 2459 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2460 chip->codec_isr_bits;
1da177e4
LT		 2461 if (status == nstatus)
2462 break;
954bea35 2463 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2464 } while (time_after_eq(end_time, jiffies));
2465 }
2466
2467 if (chip->device_type == DEVICE_SIS) {
2468 /* unmute the output on SIS7012 */
2469 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2470 }
a9e99660 2471 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2472 /* enable SPDIF interrupt */
2473 unsigned int val;
2474 pci_read_config_dword(chip->pci, 0x4c, &val);
2475 val |= 0x1000000;
2476 pci_write_config_dword(chip->pci, 0x4c, val);
2477 }
2478 return 0;
2479}
2480
6b75a9d8 2481static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2482{
2483 u32 reg;
2484 int i = 0;
2485
2486 reg = igetdword(chip, ICHREG(ALI_SCR));
2487 if ((reg & 2) == 0) /* Cold required */
2488 reg |= 2;
2489 else
2490 reg |= 1; /* Warm */
2491 reg &= ~0x80000000; /* ACLink on */
2492 iputdword(chip, ICHREG(ALI_SCR), reg);
2493
2494 for (i = 0; i < HZ / 2; i++) {
2495 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2496 goto __ok;
954bea35 2497 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2498 }
2499 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2500 if (probing)
2501 return -EIO;
2502
2503 __ok:
2504 for (i = 0; i < HZ / 2; i++) {
2505 reg = igetdword(chip, ICHREG(ALI_RTSR));
2506 if (reg & 0x80) /* primary codec */
2507 break;
2508 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
954bea35 2509 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2510 }
2511
2512 do_ali_reset(chip);
2513 return 0;
2514}
2515
6b75a9d8 2516static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
1da177e4 2517{
253b999f 2518 unsigned int i, timeout;
1da177e4
LT		 2519 int err;
2520
2521 if (chip->device_type != DEVICE_ALI) {
2522 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2523 return err;
2524 iagetword(chip, 0); /* clear semaphore flag */
2525 } else {
2526 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2527 return err;
2528 }
2529
2530 /* disable interrupts */
2531 for (i = 0; i < chip->bdbars_count; i++)
2532 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2533 /* reset channels */
2534 for (i = 0; i < chip->bdbars_count; i++)
2535 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
253b999f
JK		 2536 for (i = 0; i < chip->bdbars_count; i++) {
2537 timeout = 100000;
2538 while (--timeout != 0) {
2539 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2540 break;
2541 }
2542 if (timeout == 0)
2543 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2544 }
1da177e4
LT		 2545 /* initialize Buffer Descriptor Lists */
2546 for (i = 0; i < chip->bdbars_count; i++)
6b75a9d8
TI		 2547 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2548 chip->ichd[i].bdbar_addr);
1da177e4
LT		 2549 return 0;
2550}
2551
6b75a9d8 2552static int snd_intel8x0_free(struct intel8x0 *chip)
1da177e4
LT		 2553{
2554 unsigned int i;
2555
2556 if (chip->irq < 0)
2557 goto __hw_end;
2558 /* disable interrupts */
2559 for (i = 0; i < chip->bdbars_count; i++)
2560 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2561 /* reset channels */
2562 for (i = 0; i < chip->bdbars_count; i++)
2563 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
a9e99660 2564 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2565 /* stop the spdif interrupt */
2566 unsigned int val;
2567 pci_read_config_dword(chip->pci, 0x4c, &val);
2568 val &= ~0x1000000;
2569 pci_write_config_dword(chip->pci, 0x4c, val);
2570 }
2571 /* --- */
f000fd80 2572
1da177e4
LT		 2573 __hw_end:
2574 if (chip->irq >= 0)
6b75a9d8 2575 free_irq(chip->irq, chip);
1da177e4
LT		 2576 if (chip->bdbars.area) {
2577 if (chip->fix_nocache)
2578 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2579 snd_dma_free_pages(&chip->bdbars);
2580 }
3388c37e
TI		 2581 if (chip->addr)
2582 pci_iounmap(chip->pci, chip->addr);
2583 if (chip->bmaddr)
2584 pci_iounmap(chip->pci, chip->bmaddr);
1da177e4
LT		 2585 pci_release_regions(chip->pci);
2586 pci_disable_device(chip->pci);
2587 kfree(chip);
2588 return 0;
2589}
2590
2591#ifdef CONFIG_PM
2592/*
2593 * power management
2594 */
5809c6c4 2595static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2596{
5809c6c4
TI		 2597 struct snd_card *card = pci_get_drvdata(pci);
2598 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2599 int i;
2600
5809c6c4 2601 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 2602 for (i = 0; i < chip->pcm_devs; i++)
2603 snd_pcm_suspend_all(chip->pcm[i]);
2604 /* clear nocache */
2605 if (chip->fix_nocache) {
2606 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2607 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2608 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2609 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2610 if (runtime->dma_area)
2611 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2612 }
2613 }
2614 }
84a43bd5 2615 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2616 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2617 if (chip->device_type == DEVICE_INTEL_ICH4)
2618 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2619
30b35399 2620 if (chip->irq >= 0) {
6b75a9d8 2621 free_irq(chip->irq, chip);
30b35399
TI		 2622 chip->irq = -1;
2623 }
5809c6c4
TI		 2624 pci_disable_device(pci);
2625 pci_save_state(pci);
19bfafb2
TK		 2626 /* The call below may disable built-in speaker on some laptops
2627 * after S2RAM. So, don't touch it.
2628 */
2629 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
1da177e4
LT		 2630 return 0;
2631}
2632
5809c6c4 2633static int intel8x0_resume(struct pci_dev *pci)
1da177e4 2634{
5809c6c4
TI		 2635 struct snd_card *card = pci_get_drvdata(pci);
2636 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2637 int i;
2638
30b35399 2639 pci_set_power_state(pci, PCI_D0);
5809c6c4 2640 pci_restore_state(pci);
30b35399
TI		 2641 if (pci_enable_device(pci) < 0) {
2642 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2643 "disabling device\n");
2644 snd_card_disconnect(card);
2645 return -EIO;
2646 }
5809c6c4 2647 pci_set_master(pci);
2078f38c 2648 snd_intel8x0_chip_init(chip, 0);
30b35399 2649 if (request_irq(pci->irq, snd_intel8x0_interrupt,
437a5a46 2650 IRQF_SHARED, card->shortname, chip)) {
30b35399
TI		 2651 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2652 "disabling device\n", pci->irq);
2653 snd_card_disconnect(card);
2654 return -EIO;
2655 }
5809c6c4 2656 chip->irq = pci->irq;
90158b83 2657 synchronize_irq(chip->irq);
1da177e4 2658
52b72388 2659 /* re-initialize mixer stuff */
a9e99660 2660 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
52b72388
TI		 2661 /* enable separate SDINs for ICH4 */
2662 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2663 /* use slot 10/11 for SPDIF */
2664 iputdword(chip, ICHREG(GLOB_CNT),
2665 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2666 ICH_PCM_SPDIF_1011);
2667 }
2668
1da177e4
LT		 2669 /* refill nocache */
2670 if (chip->fix_nocache)
2671 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2672
84a43bd5 2673 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2674 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 2675
2676 /* refill nocache */
2677 if (chip->fix_nocache) {
2678 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2679 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2680 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2681 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2682 if (runtime->dma_area)
2683 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2684 }
2685 }
2686 }
2687
1cfe43d2
TI		 2688 /* resume status */
2689 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2690 struct ichdev *ichdev = &chip->ichd[i];
1cfe43d2
TI		 2691 unsigned long port = ichdev->reg_offset;
2692 if (! ichdev->substream || ! ichdev->suspended)
2693 continue;
2694 if (ichdev->ichd == ICHD_PCMOUT)
2695 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2696 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2697 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2698 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2699 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2700 }
2701
5809c6c4 2702 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2703 return 0;
2704}
2705#endif /* CONFIG_PM */
2706
2707#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2708
6b75a9d8 2709static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
1da177e4 2710{
6b75a9d8
TI		 2711 struct snd_pcm_substream *subs;
2712 struct ichdev *ichdev;
1da177e4 2713 unsigned long port;
920e4ae3 2714 unsigned long pos, pos1, t;
2ec775e7 2715 int civ, timeout = 1000, attempt = 1;
920e4ae3 2716 struct timespec start_time, stop_time;
1da177e4
LT		 2717
2718 if (chip->ac97_bus->clock != 48000)
2719 return; /* specified in module option */
2720
2ec775e7 2721 __again:
1da177e4
LT		 2722 subs = chip->pcm[0]->streams[0].substream;
2723 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
99b359ba 2724 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
1da177e4
LT		 2725 return;
2726 }
2727 ichdev = &chip->ichd[ICHD_PCMOUT];
2728 ichdev->physbuf = subs->dma_buffer.addr;
29dab4fd 2729 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
1da177e4
LT		 2730 ichdev->substream = NULL; /* don't process interrupts */
2731
2732 /* set rate */
2733 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2734 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2735 return;
2736 }
2737 snd_intel8x0_setup_periods(chip, ichdev);
2738 port = ichdev->reg_offset;
2739 spin_lock_irq(&chip->reg_lock);
2740 chip->in_measurement = 1;
2741 /* trigger */
2742 if (chip->device_type != DEVICE_ALI)
2743 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2744 else {
2745 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2746 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2747 }
920e4ae3 2748 do_posix_clock_monotonic_gettime(&start_time);
1da177e4 2749 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2750 msleep(50);
1da177e4
LT		 2751 spin_lock_irq(&chip->reg_lock);
2752 /* check the position */
920e4ae3
JK		 2753 do {
2754 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2755 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2756 if (pos1 == 0) {
2757 udelay(10);
2758 continue;
2759 }
2760 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2761 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2762 break;
2763 } while (timeout--);
da2436a2
JK		 2764 if (pos1 == 0) { /* oops, this value is not reliable */
2765 pos = 0;
2766 } else {
2767 pos = ichdev->fragsize1;
2768 pos -= pos1 << ichdev->pos_shift;
2769 pos += ichdev->position;
2770 }
1da177e4 2771 chip->in_measurement = 0;
920e4ae3 2772 do_posix_clock_monotonic_gettime(&stop_time);
1da177e4
LT		 2773 /* stop */
2774 if (chip->device_type == DEVICE_ALI) {
d78bec21 2775 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
1da177e4
LT		 2776 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2777 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2778 ;
2779 } else {
2780 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2781 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2782 ;
2783 }
2784 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2785 spin_unlock_irq(&chip->reg_lock);
2786
da2436a2
JK		 2787 if (pos == 0) {
2788 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2ec775e7 2789 __retry:
30fd9940
JK		 2790 if (attempt < 3) {
2791 msleep(300);
2ec775e7
JK		 2792 attempt++;
2793 goto __again;
2794 }
30fd9940 2795 goto __end;
da2436a2
JK		 2796 }
2797
920e4ae3 2798 pos /= 4;
1da177e4
LT		 2799 t = stop_time.tv_sec - start_time.tv_sec;
2800 t *= 1000000;
920e4ae3
JK		 2801 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2802 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
1da177e4 2803 if (t == 0) {
920e4ae3 2804 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2ec775e7 2805 goto __retry;
1da177e4 2806 }
920e4ae3 2807 pos *= 1000;
1da177e4 2808 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2ec775e7 2809 if (pos < 40000 || pos >= 60000) {
1da177e4
LT		 2810 /* abnormal value. hw problem? */
2811 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2ec775e7
JK		 2812 goto __retry;
2813 } else if (pos > 40500 && pos < 41500)
920e4ae3
JK		 2814 /* first exception - 41000Hz reference clock */
2815 chip->ac97_bus->clock = 41000;
29dab4fd 2816 else if (pos > 43600 && pos < 44600)
920e4ae3
JK		 2817 /* second exception - 44100HZ reference clock */
2818 chip->ac97_bus->clock = 44100;
1da177e4
LT		 2819 else if (pos < 47500 || pos > 48500)
2820 /* not 48000Hz, tuning the clock.. */
2821 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
30fd9940 2822 __end:
1da177e4 2823 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
6dbe6628 2824 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
1da177e4
LT		 2825}
2826
d695e4ea
TI		 2827static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2828 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2829 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2830 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
78fad343 2831 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
d695e4ea
TI		 2832 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2833 { } /* terminator */
2b3b5485
JK		 2834};
2835
2836static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2837{
2838 struct pci_dev *pci = chip->pci;
d695e4ea
TI		 2839 const struct snd_pci_quirk *wl;
2840
2841 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2842 if (!wl)
2843 return 0;
2844 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2845 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2846 chip->ac97_bus->clock = wl->value;
2847 return 1;
2b3b5485
JK		 2848}
2849
adf1b3d2 2850#ifdef CONFIG_PROC_FS
6b75a9d8
TI		 2851static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2852 struct snd_info_buffer *buffer)
1da177e4 2853{
6b75a9d8 2854 struct intel8x0 *chip = entry->private_data;
1da177e4
LT		 2855 unsigned int tmp;
2856
2857 snd_iprintf(buffer, "Intel8x0\n\n");
2858 if (chip->device_type == DEVICE_ALI)
2859 return;
2860 tmp = igetdword(chip, ICHREG(GLOB_STA));
2861 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2862 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2863 if (chip->device_type == DEVICE_INTEL_ICH4)
2864 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
84a43bd5
TI		 2865 snd_iprintf(buffer, "AC'97 codecs ready :");
2866 if (tmp & chip->codec_isr_bits) {
2867 int i;
2868 static const char *codecs[3] = {
2869 "primary", "secondary", "tertiary"
2870 };
2871 for (i = 0; i < chip->max_codecs; i++)
2872 if (tmp & chip->codec_bit[i])
2873 snd_iprintf(buffer, " %s", codecs[i]);
2874 } else
2875 snd_iprintf(buffer, " none");
2876 snd_iprintf(buffer, "\n");
2877 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2878 chip->device_type == DEVICE_SIS)
1da177e4
LT		 2879 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2880 chip->ac97_sdin[0],
2881 chip->ac97_sdin[1],
2882 chip->ac97_sdin[2]);
2883}
2884
6b75a9d8 2885static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
1da177e4 2886{
6b75a9d8 2887 struct snd_info_entry *entry;
1da177e4
LT		 2888
2889 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
bf850204 2890 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
1da177e4 2891}
adf1b3d2
TI		 2892#else
2893#define snd_intel8x0_proc_init(x)
2894#endif
1da177e4 2895
6b75a9d8 2896static int snd_intel8x0_dev_free(struct snd_device *device)
1da177e4 2897{
6b75a9d8 2898 struct intel8x0 *chip = device->device_data;
1da177e4
LT		 2899 return snd_intel8x0_free(chip);
2900}
2901
2902struct ich_reg_info {
2903 unsigned int int_sta_mask;
2904 unsigned int offset;
2905};
2906
84a43bd5
TI		 2907static unsigned int ich_codec_bits[3] = {
2908 ICH_PCR, ICH_SCR, ICH_TCR
2909};
2910static unsigned int sis_codec_bits[3] = {
2911 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2912};
2913
6b75a9d8 2914static int __devinit snd_intel8x0_create(struct snd_card *card,
1da177e4
LT		 2915 struct pci_dev *pci,
2916 unsigned long device_type,
6b75a9d8 2917 struct intel8x0 ** r_intel8x0)
1da177e4 2918{
6b75a9d8 2919 struct intel8x0 *chip;
1da177e4
LT		 2920 int err;
2921 unsigned int i;
2922 unsigned int int_sta_masks;
6b75a9d8
TI		 2923 struct ichdev *ichdev;
2924 static struct snd_device_ops ops = {
1da177e4
LT		 2925 .dev_free = snd_intel8x0_dev_free,
2926 };
2927
2928 static unsigned int bdbars[] = {
2929 3, /* DEVICE_INTEL */
2930 6, /* DEVICE_INTEL_ICH4 */
2931 3, /* DEVICE_SIS */
2932 6, /* DEVICE_ALI */
2933 4, /* DEVICE_NFORCE */
2934 };
2935 static struct ich_reg_info intel_regs[6] = {
2936 { ICH_PIINT, 0 },
2937 { ICH_POINT, 0x10 },
2938 { ICH_MCINT, 0x20 },
2939 { ICH_M2INT, 0x40 },
2940 { ICH_P2INT, 0x50 },
2941 { ICH_SPINT, 0x60 },
2942 };
2943 static struct ich_reg_info nforce_regs[4] = {
2944 { ICH_PIINT, 0 },
2945 { ICH_POINT, 0x10 },
2946 { ICH_MCINT, 0x20 },
2947 { ICH_NVSPINT, 0x70 },
2948 };
2949 static struct ich_reg_info ali_regs[6] = {
2950 { ALI_INT_PCMIN, 0x40 },
2951 { ALI_INT_PCMOUT, 0x50 },
2952 { ALI_INT_MICIN, 0x60 },
2953 { ALI_INT_CODECSPDIFOUT, 0x70 },
2954 { ALI_INT_SPDIFIN, 0xa0 },
2955 { ALI_INT_SPDIFOUT, 0xb0 },
2956 };
2957 struct ich_reg_info *tbl;
2958
2959 *r_intel8x0 = NULL;
2960
2961 if ((err = pci_enable_device(pci)) < 0)
2962 return err;
2963
e560d8d8 2964 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2965 if (chip == NULL) {
2966 pci_disable_device(pci);
2967 return -ENOMEM;
2968 }
2969 spin_lock_init(&chip->reg_lock);
2970 chip->device_type = device_type;
2971 chip->card = card;
2972 chip->pci = pci;
2973 chip->irq = -1;
c829b052
TI		 2974
2975 /* module parameters */
2976 chip->buggy_irq = buggy_irq;
2977 chip->buggy_semaphore = buggy_semaphore;
2978 if (xbox)
2979 chip->xbox = 1;
1da177e4
LT		 2980
2981 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2982 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2983 chip->fix_nocache = 1; /* enable workaround */
2984
1da177e4
LT		 2985 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2986 kfree(chip);
2987 pci_disable_device(pci);
2988 return err;
2989 }
2990
2991 if (device_type == DEVICE_ALI) {
2992 /* ALI5455 has no ac97 region */
3388c37e 2993 chip->bmaddr = pci_iomap(pci, 0, 0);
1da177e4
LT		 2994 goto port_inited;
2995 }
2996
3388c37e
TI		 2997 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2998 chip->addr = pci_iomap(pci, 2, 0);
2999 else
3000 chip->addr = pci_iomap(pci, 0, 0);
3001 if (!chip->addr) {
3002 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
3003 snd_intel8x0_free(chip);
3004 return -EIO;
3005 }
3006 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3007 chip->bmaddr = pci_iomap(pci, 3, 0);
3008 else
3009 chip->bmaddr = pci_iomap(pci, 1, 0);
3010 if (!chip->bmaddr) {
3011 snd_printk(KERN_ERR "Controller space ioremap problem\n");
3012 snd_intel8x0_free(chip);
3013 return -EIO;
1da177e4
LT		 3014 }
3015
3016 port_inited:
1da177e4
LT		 3017 chip->bdbars_count = bdbars[device_type];
3018
3019 /* initialize offsets */
3020 switch (device_type) {
3021 case DEVICE_NFORCE:
3022 tbl = nforce_regs;
3023 break;
3024 case DEVICE_ALI:
3025 tbl = ali_regs;
3026 break;
3027 default:
3028 tbl = intel_regs;
3029 break;
3030 }
3031 for (i = 0; i < chip->bdbars_count; i++) {
3032 ichdev = &chip->ichd[i];
3033 ichdev->ichd = i;
3034 ichdev->reg_offset = tbl[i].offset;
3035 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3036 if (device_type == DEVICE_SIS) {
3037 /* SiS 7012 swaps the registers */
3038 ichdev->roff_sr = ICH_REG_OFF_PICB;
3039 ichdev->roff_picb = ICH_REG_OFF_SR;
3040 } else {
3041 ichdev->roff_sr = ICH_REG_OFF_SR;
3042 ichdev->roff_picb = ICH_REG_OFF_PICB;
3043 }
3044 if (device_type == DEVICE_ALI)
3045 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3046 /* SIS7012 handles the pcm data in bytes, others are in samples */
3047 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3048 }
3049
3050 /* allocate buffer descriptor lists */
3051 /* the start of each lists must be aligned to 8 bytes */
3052 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3053 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3054 &chip->bdbars) < 0) {
3055 snd_intel8x0_free(chip);
3056 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3057 return -ENOMEM;
3058 }
3059 /* tables must be aligned to 8 bytes here, but the kernel pages
3060 are much bigger, so we don't care (on i386) */
3061 /* workaround for 440MX */
3062 if (chip->fix_nocache)
3063 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3064 int_sta_masks = 0;
3065 for (i = 0; i < chip->bdbars_count; i++) {
3066 ichdev = &chip->ichd[i];
beef08a5
TI		 3067 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3068 (i * ICH_MAX_FRAGS * 2);
3069 ichdev->bdbar_addr = chip->bdbars.addr +
3070 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1da177e4
LT		 3071 int_sta_masks |= ichdev->int_sta_mask;
3072 }
beef08a5
TI		 3073 chip->int_sta_reg = device_type == DEVICE_ALI ?
3074 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
1da177e4
LT		 3075 chip->int_sta_mask = int_sta_masks;
3076
beef08a5 3077 pci_set_master(pci);
beef08a5 3078
84a43bd5
TI		 3079 switch(chip->device_type) {
3080 case DEVICE_INTEL_ICH4:
3081 /* ICH4 can have three codecs */
3082 chip->max_codecs = 3;
3083 chip->codec_bit = ich_codec_bits;
3084 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3085 break;
3086 case DEVICE_SIS:
3087 /* recent SIS7012 can have three codecs */
3088 chip->max_codecs = 3;
3089 chip->codec_bit = sis_codec_bits;
3090 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3091 break;
3092 default:
3093 /* others up to two codecs */
3094 chip->max_codecs = 2;
3095 chip->codec_bit = ich_codec_bits;
3096 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3097 break;
3098 }
3099 for (i = 0; i < chip->max_codecs; i++)
3100 chip->codec_isr_bits |= chip->codec_bit[i];
3101
1da177e4
LT		 3102 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3103 snd_intel8x0_free(chip);
3104 return err;
3105 }
3106
2078f38c
TI		 3107 /* request irq after initializaing int_sta_mask, etc */
3108 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3109 IRQF_SHARED, card->shortname, chip)) {
3110 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3111 snd_intel8x0_free(chip);
3112 return -EBUSY;
3113 }
3114 chip->irq = pci->irq;
3115
1da177e4
LT		 3116 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3117 snd_intel8x0_free(chip);
3118 return err;
3119 }
3120
3121 snd_card_set_dev(card, &pci->dev);
3122
3123 *r_intel8x0 = chip;
3124 return 0;
3125}
3126
3127static struct shortname_table {
3128 unsigned int id;
3129 const char *s;
3130} shortnames[] __devinitdata = {
8cdfd251
TI		 3131 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3132 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3133 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 3134 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 3135 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3136 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3137 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 3138 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3139 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3140 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 3141 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 3142 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 3143 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 3144 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3145 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3146 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3147 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3148 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3149 { 0x003a, "NVidia MCP04" },
3150 { 0x746d, "AMD AMD8111" },
3151 { 0x7445, "AMD AMD768" },
3152 { 0x5455, "ALi M5455" },
3153 { 0, NULL },
3154};
3155
a9e99660
TI		 3156static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3157 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3158 { } /* end */
3159};
3160
3161/* look up white/black list for SPDIF over ac-link */
3162static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3163{
3164 const struct snd_pci_quirk *w;
3165
3166 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3167 if (w) {
3168 if (w->value)
3169 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3170 "AC-Link for %s\n", w->name);
3171 else
3172 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3173 "SPDIF DMA for %s\n", w->name);
3174 return w->value;
3175 }
3176 return 0;
3177}
3178
1da177e4
LT		 3179static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3180 const struct pci_device_id *pci_id)
3181{
6b75a9d8
TI		 3182 struct snd_card *card;
3183 struct intel8x0 *chip;
1da177e4
LT		 3184 int err;
3185 struct shortname_table *name;
3186
e58de7ba
TI		 3187 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3188 if (err < 0)
3189 return err;
1da177e4 3190
a9e99660
TI		 3191 if (spdif_aclink < 0)
3192 spdif_aclink = check_default_spdif_aclink(pci);
3193
3194 strcpy(card->driver, "ICH");
3195 if (!spdif_aclink) {
3196 switch (pci_id->driver_data) {
3197 case DEVICE_NFORCE:
3198 strcpy(card->driver, "NFORCE");
3199 break;
3200 case DEVICE_INTEL_ICH4:
3201 strcpy(card->driver, "ICH4");
3202 }
1da177e4
LT		 3203 }
3204
3205 strcpy(card->shortname, "Intel ICH");
3206 for (name = shortnames; name->id; name++) {
3207 if (pci->device == name->id) {
3208 strcpy(card->shortname, name->s);
3209 break;
3210 }
3211 }
3212
beef08a5
TI		 3213 if (buggy_irq < 0) {
3214 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3215 * Needs to return IRQ_HANDLED for unknown irqs.
3216 */
3217 if (pci_id->driver_data == DEVICE_NFORCE)
3218 buggy_irq = 1;
3219 else
3220 buggy_irq = 0;
3221 }
3222
a06147d2 3223 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
c829b052 3224 &chip)) < 0) {
1da177e4
LT		 3225 snd_card_free(card);
3226 return err;
3227 }
5809c6c4 3228 card->private_data = chip;
1da177e4 3229
b7fe4622 3230 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
1da177e4
LT		 3231 snd_card_free(card);
3232 return err;
3233 }
3234 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3235 snd_card_free(card);
3236 return err;
3237 }
3238
3239 snd_intel8x0_proc_init(chip);
3240
3241 snprintf(card->longname, sizeof(card->longname),
3388c37e
TI		 3242 "%s with %s at irq %i", card->shortname,
3243 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
1da177e4 3244
2b3b5485
JK		 3245 if (ac97_clock == 0 || ac97_clock == 1) {
3246 if (ac97_clock == 0) {
3247 if (intel8x0_in_clock_list(chip) == 0)
3248 intel8x0_measure_ac97_clock(chip);
3249 } else {
3250 intel8x0_measure_ac97_clock(chip);
3251 }
3252 }
1da177e4
LT		 3253
3254 if ((err = snd_card_register(card)) < 0) {
3255 snd_card_free(card);
3256 return err;
3257 }
3258 pci_set_drvdata(pci, card);
1da177e4
LT		 3259 return 0;
3260}
3261
3262static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3263{
3264 snd_card_free(pci_get_drvdata(pci));
3265 pci_set_drvdata(pci, NULL);
3266}
3267
3268static struct pci_driver driver = {
3269 .name = "Intel ICH",
3270 .id_table = snd_intel8x0_ids,
3271 .probe = snd_intel8x0_probe,
3272 .remove = __devexit_p(snd_intel8x0_remove),
5809c6c4
TI		 3273#ifdef CONFIG_PM
3274 .suspend = intel8x0_suspend,
3275 .resume = intel8x0_resume,
3276#endif
1da177e4
LT		 3277};
3278
3279
3280static int __init alsa_card_intel8x0_init(void)
3281{
01d25d46 3282 return pci_register_driver(&driver);
1da177e4
LT		 3283}
3284
3285static void __exit alsa_card_intel8x0_exit(void)
3286{
3287 pci_unregister_driver(&driver);
3288}
3289
3290module_init(alsa_card_intel8x0_init)
3291module_exit(alsa_card_intel8x0_exit)
Linux kernel - Deliverables
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