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ALSA: Convert to new pm_ops for PCI drivers
[deliverable/linux.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
c1017a4c 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
1da177e4
LT		 29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
1da177e4
LT		 36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
228cf793 45#ifdef CONFIG_KVM_GUEST
700cc5c9 46#include <linux/kvm_para.h>
228cf793
KO		 47#else
48#define kvm_para_available() (0)
49#endif
50
c1017a4c 51MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 52MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
53MODULE_LICENSE("GPL");
54MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
55 "{Intel,82901AB-ICH0},"
56 "{Intel,82801BA-ICH2},"
57 "{Intel,82801CA-ICH3},"
58 "{Intel,82801DB-ICH4},"
59 "{Intel,ICH5},"
60 "{Intel,ICH6},"
61 "{Intel,ICH7},"
62 "{Intel,6300ESB},"
c4c8ea94 63 "{Intel,ESB2},"
1da177e4
LT		 64 "{Intel,MX440},"
65 "{SiS,SI7012},"
66 "{NVidia,nForce Audio},"
67 "{NVidia,nForce2 Audio},"
a2854dc5
AB		 68 "{NVidia,nForce3 Audio},"
69 "{NVidia,MCP04},"
70 "{NVidia,MCP501},"
71 "{NVidia,CK804},"
72 "{NVidia,CK8},"
73 "{NVidia,CK8S},"
1da177e4
LT		 74 "{AMD,AMD768},"
75 "{AMD,AMD8111},"
76 "{ALI,M5455}}");
77
b7fe4622
CL		 78static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
79static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
6581f4e7 80static int ac97_clock;
b7fe4622 81static char *ac97_quirk;
a67ff6a5 82static bool buggy_semaphore;
beef08a5 83static int buggy_irq = -1; /* auto-check */
a67ff6a5 84static bool xbox;
a9e99660 85static int spdif_aclink = -1;
228cf793 86static int inside_vm = -1;
b7fe4622
CL		 87
88module_param(index, int, 0444);
1da177e4 89MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
b7fe4622 90module_param(id, charp, 0444);
1da177e4 91MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
b7fe4622 92module_param(ac97_clock, int, 0444);
2b3b5485 93MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
b7fe4622 94module_param(ac97_quirk, charp, 0444);
1da177e4 95MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 96module_param(buggy_semaphore, bool, 0444);
a06147d2 97MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
69116f27 98module_param(buggy_irq, bint, 0444);
1da177e4 99MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
b7fe4622 100module_param(xbox, bool, 0444);
1da177e4 101MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
a9e99660
TI		 102module_param(spdif_aclink, int, 0444);
103MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
69116f27 104module_param(inside_vm, bint, 0444);
228cf793 105MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
1da177e4 106
2b3e584b 107/* just for backward compatibility */
a67ff6a5 108static bool enable;
698444f3 109module_param(enable, bool, 0444);
2b3e584b
TI		 110static int joystick;
111module_param(joystick, int, 0444);
112
1da177e4
LT		 113/*
114 * Direct registers
115 */
1da177e4
LT		 116enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
117
118#define ICHREG(x) ICH_REG_##x
119
120#define DEFINE_REGSET(name,base) \
121enum { \
122 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
123 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
124 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
125 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
126 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
127 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
128 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
129};
130
131/* busmaster blocks */
132DEFINE_REGSET(OFF, 0); /* offset */
133DEFINE_REGSET(PI, 0x00); /* PCM in */
134DEFINE_REGSET(PO, 0x10); /* PCM out */
135DEFINE_REGSET(MC, 0x20); /* Mic in */
136
137/* ICH4 busmaster blocks */
138DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
139DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
140DEFINE_REGSET(SP, 0x60); /* SPDIF out */
141
142/* values for each busmaster block */
143
144/* LVI */
145#define ICH_REG_LVI_MASK 0x1f
146
147/* SR */
148#define ICH_FIFOE 0x10 /* FIFO error */
149#define ICH_BCIS 0x08 /* buffer completion interrupt status */
150#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
151#define ICH_CELV 0x02 /* current equals last valid */
152#define ICH_DCH 0x01 /* DMA controller halted */
153
154/* PIV */
155#define ICH_REG_PIV_MASK 0x1f /* mask */
156
157/* CR */
158#define ICH_IOCE 0x10 /* interrupt on completion enable */
159#define ICH_FEIE 0x08 /* fifo error interrupt enable */
160#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
161#define ICH_RESETREGS 0x02 /* reset busmaster registers */
162#define ICH_STARTBM 0x01 /* start busmaster operation */
163
164
165/* global block */
166#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
167#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
168#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
169#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
170#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
171#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
172#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
4235a317
TI		 173#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
174#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
1da177e4
LT		 175#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
176#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
177#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
178#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
179#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
180#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
181#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
182#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
183#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
184#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
185#define ICH_ACLINK 0x00000008 /* AClink shut off */
186#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
187#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
188#define ICH_GIE 0x00000001 /* GPI interrupt enable */
189#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
190#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
191#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
192#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
193#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
194#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
195#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
196#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
197#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
198#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
84a43bd5
TI		 199#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
200#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
1da177e4
LT		 201#define ICH_MD3 0x00020000 /* modem power down semaphore */
202#define ICH_AD3 0x00010000 /* audio power down semaphore */
203#define ICH_RCS 0x00008000 /* read completion status */
204#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
205#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
206#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
207#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
208#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
209#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
210#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
211#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
212#define ICH_POINT 0x00000040 /* playback interrupt */
213#define ICH_PIINT 0x00000020 /* capture interrupt */
214#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
215#define ICH_MOINT 0x00000004 /* modem playback interrupt */
216#define ICH_MIINT 0x00000002 /* modem capture interrupt */
217#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
218#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
219#define ICH_CAS 0x01 /* codec access semaphore */
220#define ICH_REG_SDM 0x80
221#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
222#define ICH_DI2L_SHIFT 6
223#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
224#define ICH_DI1L_SHIFT 4
225#define ICH_SE 0x00000008 /* steer enable */
226#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
227
228#define ICH_MAX_FRAGS 32 /* max hw frags */
229
230
231/*
232 * registers for Ali5455
233 */
234
235/* ALi 5455 busmaster blocks */
236DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
237DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
238DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
239DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
240DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
241DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
242DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
243DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
244DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
245DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
246DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
247
248enum {
249 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
250 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
251 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
252 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
253 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
254 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
255 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
256 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
257 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
258 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
259 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
260 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
261 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
262 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
263 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
264 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
265 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
266 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
267 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
268 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
269 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
270};
271
272#define ALI_CAS_SEM_BUSY 0x80000000
273#define ALI_CPR_ADDR_SECONDARY 0x100
274#define ALI_CPR_ADDR_READ 0x80
275#define ALI_CSPSR_CODEC_READY 0x08
276#define ALI_CSPSR_READ_OK 0x02
277#define ALI_CSPSR_WRITE_OK 0x01
278
279/* interrupts for the whole chip by interrupt status register finish */
280
281#define ALI_INT_MICIN2 (1<<26)
282#define ALI_INT_PCMIN2 (1<<25)
283#define ALI_INT_I2SIN (1<<24)
284#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
285#define ALI_INT_SPDIFIN (1<<22)
286#define ALI_INT_LFEOUT (1<<21)
287#define ALI_INT_CENTEROUT (1<<20)
288#define ALI_INT_CODECSPDIFOUT (1<<19)
289#define ALI_INT_MICIN (1<<18)
290#define ALI_INT_PCMOUT (1<<17)
291#define ALI_INT_PCMIN (1<<16)
292#define ALI_INT_CPRAIS (1<<7) /* command port available */
293#define ALI_INT_SPRAIS (1<<5) /* status port available */
294#define ALI_INT_GPIO (1<<1)
6b75a9d8
TI		 295#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
296 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
1da177e4
LT		 297
298#define ICH_ALI_SC_RESET (1<<31) /* master reset */
299#define ICH_ALI_SC_AC97_DBL (1<<30)
300#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
301#define ICH_ALI_SC_IN_BITS (3<<18)
302#define ICH_ALI_SC_OUT_BITS (3<<16)
303#define ICH_ALI_SC_6CH_CFG (3<<14)
304#define ICH_ALI_SC_PCM_4 (1<<8)
305#define ICH_ALI_SC_PCM_6 (2<<8)
306#define ICH_ALI_SC_PCM_246_MASK (3<<8)
307
308#define ICH_ALI_SS_SEC_ID (3<<5)
309#define ICH_ALI_SS_PRI_ID (3<<3)
310
311#define ICH_ALI_IF_AC97SP (1<<21)
312#define ICH_ALI_IF_MC (1<<20)
313#define ICH_ALI_IF_PI (1<<19)
314#define ICH_ALI_IF_MC2 (1<<18)
315#define ICH_ALI_IF_PI2 (1<<17)
316#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
317#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
318#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
319#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
320#define ICH_ALI_IF_PO_SPDF (1<<3)
321#define ICH_ALI_IF_PO (1<<1)
322
323/*
324 *
325 */
326
6b75a9d8
TI		 327enum {
328 ICHD_PCMIN,
329 ICHD_PCMOUT,
330 ICHD_MIC,
331 ICHD_MIC2,
332 ICHD_PCM2IN,
333 ICHD_SPBAR,
334 ICHD_LAST = ICHD_SPBAR
335};
336enum {
337 NVD_PCMIN,
338 NVD_PCMOUT,
339 NVD_MIC,
340 NVD_SPBAR,
341 NVD_LAST = NVD_SPBAR
342};
343enum {
344 ALID_PCMIN,
345 ALID_PCMOUT,
346 ALID_MIC,
347 ALID_AC97SPDIFOUT,
348 ALID_SPDIFIN,
349 ALID_SPDIFOUT,
350 ALID_LAST = ALID_SPDIFOUT
351};
1da177e4 352
6b75a9d8 353#define get_ichdev(substream) (substream->runtime->private_data)
1da177e4 354
6b75a9d8 355struct ichdev {
1da177e4
LT		 356 unsigned int ichd; /* ich device number */
357 unsigned long reg_offset; /* offset to bmaddr */
358 u32 *bdbar; /* CPU address (32bit) */
359 unsigned int bdbar_addr; /* PCI bus address (32bit) */
6b75a9d8 360 struct snd_pcm_substream *substream;
1da177e4
LT		 361 unsigned int physbuf; /* physical address (32bit) */
362 unsigned int size;
363 unsigned int fragsize;
364 unsigned int fragsize1;
365 unsigned int position;
366 unsigned int pos_shift;
da2436a2 367 unsigned int last_pos;
1da177e4
LT		 368 int frags;
369 int lvi;
370 int lvi_frag;
371 int civ;
372 int ack;
373 int ack_reload;
374 unsigned int ack_bit;
375 unsigned int roff_sr;
376 unsigned int roff_picb;
377 unsigned int int_sta_mask; /* interrupt status mask */
378 unsigned int ali_slot; /* ALI DMA slot */
379 struct ac97_pcm *pcm;
380 int pcm_open_flag;
381 unsigned int page_attr_changed: 1;
1cfe43d2 382 unsigned int suspended: 1;
6b75a9d8 383};
1da177e4 384
6b75a9d8 385struct intel8x0 {
1da177e4
LT		 386 unsigned int device_type;
387
388 int irq;
389
3388c37e
TI		 390 void __iomem *addr;
391 void __iomem *bmaddr;
1da177e4
LT		 392
393 struct pci_dev *pci;
6b75a9d8 394 struct snd_card *card;
1da177e4
LT		 395
396 int pcm_devs;
6b75a9d8
TI		 397 struct snd_pcm *pcm[6];
398 struct ichdev ichd[6];
1da177e4
LT		 399
400 unsigned multi4: 1,
401 multi6: 1,
4235a317 402 multi8 :1,
1da177e4
LT		 403 dra: 1,
404 smp20bit: 1;
405 unsigned in_ac97_init: 1,
406 in_sdin_init: 1;
407 unsigned in_measurement: 1; /* during ac97 clock measurement */
408 unsigned fix_nocache: 1; /* workaround for 440MX */
409 unsigned buggy_irq: 1; /* workaround for buggy mobos */
410 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 411 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
228cf793 412 unsigned inside_vm: 1; /* enable VM optimization */
1da177e4
LT		 413
414 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 415 unsigned int sdm_saved; /* SDM reg value */
1da177e4 416
6b75a9d8
TI		 417 struct snd_ac97_bus *ac97_bus;
418 struct snd_ac97 *ac97[3];
1da177e4 419 unsigned int ac97_sdin[3];
84a43bd5
TI		 420 unsigned int max_codecs, ncodecs;
421 unsigned int *codec_bit;
422 unsigned int codec_isr_bits;
423 unsigned int codec_ready_bits;
1da177e4
LT		 424
425 spinlock_t reg_lock;
426
427 u32 bdbars_count;
428 struct snd_dma_buffer bdbars;
429 u32 int_sta_reg; /* interrupt status register */
430 u32 int_sta_mask; /* interrupt status mask */
431};
432
cebe41d4 433static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
28d27aae
JP		 434 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
435 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
436 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
437 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
438 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
439 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
440 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
441 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
442 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
443 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
444 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
445 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
446 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
447 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
448 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
449 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
450 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
451 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
452 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
453 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
454 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
455 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
456 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
1da177e4
LT		 457 { 0, }
458};
459
460MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
461
462/*
463 * Lowlevel I/O - busmaster
464 */
465
3388c37e 466static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
1da177e4 467{
3388c37e 468 return ioread8(chip->bmaddr + offset);
1da177e4
LT		 469}
470
3388c37e 471static inline u16 igetword(struct intel8x0 *chip, u32 offset)
1da177e4 472{
3388c37e 473 return ioread16(chip->bmaddr + offset);
1da177e4
LT		 474}
475
3388c37e 476static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
1da177e4 477{
3388c37e 478 return ioread32(chip->bmaddr + offset);
1da177e4
LT		 479}
480
3388c37e 481static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
1da177e4 482{
3388c37e 483 iowrite8(val, chip->bmaddr + offset);
1da177e4
LT		 484}
485
3388c37e 486static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 487{
3388c37e 488 iowrite16(val, chip->bmaddr + offset);
1da177e4
LT		 489}
490
3388c37e 491static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
1da177e4 492{
3388c37e 493 iowrite32(val, chip->bmaddr + offset);
1da177e4
LT		 494}
495
496/*
497 * Lowlevel I/O - AC'97 registers
498 */
499
3388c37e 500static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
1da177e4 501{
3388c37e 502 return ioread16(chip->addr + offset);
1da177e4
LT		 503}
504
3388c37e 505static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 506{
3388c37e 507 iowrite16(val, chip->addr + offset);
1da177e4
LT		 508}
509
510/*
511 * Basic I/O
512 */
513
514/*
515 * access to AC97 codec via normal i/o (for ICH and SIS7012)
516 */
517
6b75a9d8 518static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 519{
520 int time;
521
522 if (codec > 2)
523 return -EIO;
524 if (chip->in_sdin_init) {
525 /* we don't know the ready bit assignment at the moment */
526 /* so we check any */
84a43bd5 527 codec = chip->codec_isr_bits;
1da177e4 528 } else {
84a43bd5 529 codec = chip->codec_bit[chip->ac97_sdin[codec]];
1da177e4
LT		 530 }
531
532 /* codec ready ? */
533 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
534 return -EIO;
535
a06147d2
TI		 536 if (chip->buggy_semaphore)
537 return 0; /* just ignore ... */
538
1da177e4
LT		 539 /* Anyone holding a semaphore for 1 msec should be shot... */
540 time = 100;
541 do {
542 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
543 return 0;
544 udelay(10);
545 } while (time--);
546
25985edc 547 /* access to some forbidden (non existent) ac97 registers will not
1da177e4
LT		 548 * reset the semaphore. So even if you don't get the semaphore, still
549 * continue the access. We don't need the semaphore anyway. */
99b359ba 550 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 551 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
552 iagetword(chip, 0); /* clear semaphore flag */
553 /* I don't care about the semaphore */
554 return -EBUSY;
555}
556
6b75a9d8 557static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 558 unsigned short reg,
559 unsigned short val)
560{
6b75a9d8 561 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 562
563 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
564 if (! chip->in_ac97_init)
99b359ba 565 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 566 }
567 iaputword(chip, reg + ac97->num * 0x80, val);
568}
569
6b75a9d8 570static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 571 unsigned short reg)
572{
6b75a9d8 573 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 574 unsigned short res;
575 unsigned int tmp;
576
577 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
578 if (! chip->in_ac97_init)
99b359ba 579 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 580 res = 0xffff;
581 } else {
582 res = iagetword(chip, reg + ac97->num * 0x80);
583 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
584 /* reset RCS and preserve other R/WC bits */
6b75a9d8 585 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 586 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4 587 if (! chip->in_ac97_init)
99b359ba 588 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 589 res = 0xffff;
590 }
591 }
592 return res;
593}
594
84a43bd5
TI		 595static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
596 unsigned int codec)
1da177e4
LT		 597{
598 unsigned int tmp;
599
600 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
601 iagetword(chip, codec * 0x80);
602 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
603 /* reset RCS and preserve other R/WC bits */
6b75a9d8 604 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 605 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4
LT		 606 }
607 }
608}
609
610/*
611 * access to AC97 for Ali5455
612 */
6b75a9d8 613static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
1da177e4
LT		 614{
615 int count = 0;
616 for (count = 0; count < 0x7f; count++) {
617 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
618 if (val & mask)
619 return 0;
620 }
79ba34b9
TI		 621 if (! chip->in_ac97_init)
622 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
1da177e4
LT		 623 return -EBUSY;
624}
625
6b75a9d8 626static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
1da177e4
LT		 627{
628 int time = 100;
79ba34b9
TI		 629 if (chip->buggy_semaphore)
630 return 0; /* just ignore ... */
67d8a3c1 631 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
1da177e4 632 udelay(1);
79ba34b9 633 if (! time && ! chip->in_ac97_init)
1da177e4
LT		 634 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
635 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
636}
637
6b75a9d8 638static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 639{
6b75a9d8 640 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 641 unsigned short data = 0xffff;
642
643 if (snd_intel8x0_ali_codec_semaphore(chip))
644 goto __err;
645 reg |= ALI_CPR_ADDR_READ;
646 if (ac97->num)
647 reg |= ALI_CPR_ADDR_SECONDARY;
648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
649 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
650 goto __err;
651 data = igetword(chip, ICHREG(ALI_SPR));
652 __err:
653 return data;
654}
655
6b75a9d8
TI		 656static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
657 unsigned short val)
1da177e4 658{
6b75a9d8 659 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 660
661 if (snd_intel8x0_ali_codec_semaphore(chip))
662 return;
663 iputword(chip, ICHREG(ALI_CPR), val);
664 if (ac97->num)
665 reg |= ALI_CPR_ADDR_SECONDARY;
666 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
667 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
668}
669
670
671/*
672 * DMA I/O
673 */
6b75a9d8 674static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 675{
676 int idx;
677 u32 *bdbar = ichdev->bdbar;
678 unsigned long port = ichdev->reg_offset;
679
680 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
681 if (ichdev->size == ichdev->fragsize) {
682 ichdev->ack_reload = ichdev->ack = 2;
683 ichdev->fragsize1 = ichdev->fragsize >> 1;
684 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
685 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
686 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
687 ichdev->fragsize1 >> ichdev->pos_shift);
688 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
689 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690 ichdev->fragsize1 >> ichdev->pos_shift);
691 }
692 ichdev->frags = 2;
693 } else {
694 ichdev->ack_reload = ichdev->ack = 1;
695 ichdev->fragsize1 = ichdev->fragsize;
696 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
6b75a9d8
TI		 697 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
698 (((idx >> 1) * ichdev->fragsize) %
699 ichdev->size));
1da177e4
LT		 700 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
701 ichdev->fragsize >> ichdev->pos_shift);
6b75a9d8 702#if 0
14ab0861 703 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
6b75a9d8
TI		 704 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
705#endif
1da177e4
LT		 706 }
707 ichdev->frags = ichdev->size / ichdev->fragsize;
708 }
709 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
710 ichdev->civ = 0;
711 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
712 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
713 ichdev->position = 0;
714#if 0
14ab0861
TI		 715 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
716 "period_size1 = 0x%x\n",
717 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
718 ichdev->fragsize1);
1da177e4
LT		 719#endif
720 /* clear interrupts */
721 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
722}
723
724#ifdef __i386__
725/*
726 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
727 * which aborts PCI busmaster for audio transfer. A workaround is to set
728 * the pages as non-cached. For details, see the errata in
631dd1a8 729 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
1da177e4
LT		 730 */
731static void fill_nocache(void *buf, int size, int nocache)
732{
733 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
6d238cc4
AV		 734 if (nocache)
735 set_pages_uc(virt_to_page(buf), size);
736 else
737 set_pages_wb(virt_to_page(buf), size);
1da177e4
LT		 738}
739#else
6d238cc4 740#define fill_nocache(buf, size, nocache) do { ; } while (0)
1da177e4
LT		 741#endif
742
743/*
744 * Interrupt handler
745 */
746
6b75a9d8 747static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 748{
749 unsigned long port = ichdev->reg_offset;
883be793 750 unsigned long flags;
1da177e4
LT		 751 int status, civ, i, step;
752 int ack = 0;
753
883be793 754 spin_lock_irqsave(&chip->reg_lock, flags);
1da177e4
LT		 755 status = igetbyte(chip, port + ichdev->roff_sr);
756 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
757 if (!(status & ICH_BCIS)) {
758 step = 0;
759 } else if (civ == ichdev->civ) {
760 // snd_printd("civ same %d\n", civ);
761 step = 1;
762 ichdev->civ++;
763 ichdev->civ &= ICH_REG_LVI_MASK;
764 } else {
765 step = civ - ichdev->civ;
766 if (step < 0)
767 step += ICH_REG_LVI_MASK + 1;
768 // if (step != 1)
769 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
770 ichdev->civ = civ;
771 }
772
773 ichdev->position += step * ichdev->fragsize1;
774 if (! chip->in_measurement)
775 ichdev->position %= ichdev->size;
776 ichdev->lvi += step;
777 ichdev->lvi &= ICH_REG_LVI_MASK;
778 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
779 for (i = 0; i < step; i++) {
780 ichdev->lvi_frag++;
781 ichdev->lvi_frag %= ichdev->frags;
782 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
6b75a9d8 783#if 0
14ab0861
TI		 784 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
785 "all = 0x%x, 0x%x\n",
6b75a9d8
TI		 786 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
787 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
788 inl(port + 4), inb(port + ICH_REG_OFF_CR));
789#endif
1da177e4
LT		 790 if (--ichdev->ack == 0) {
791 ichdev->ack = ichdev->ack_reload;
792 ack = 1;
793 }
794 }
883be793 795 spin_unlock_irqrestore(&chip->reg_lock, flags);
1da177e4
LT		 796 if (ack && ichdev->substream) {
797 snd_pcm_period_elapsed(ichdev->substream);
798 }
799 iputbyte(chip, port + ichdev->roff_sr,
800 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
801}
802
7d12e780 803static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
1da177e4 804{
6b75a9d8
TI		 805 struct intel8x0 *chip = dev_id;
806 struct ichdev *ichdev;
1da177e4
LT		 807 unsigned int status;
808 unsigned int i;
809
810 status = igetdword(chip, chip->int_sta_reg);
811 if (status == 0xffffffff) /* we are not yet resumed */
812 return IRQ_NONE;
813
814 if ((status & chip->int_sta_mask) == 0) {
815 if (status) {
816 /* ack */
817 iputdword(chip, chip->int_sta_reg, status);
818 if (! chip->buggy_irq)
819 status = 0;
820 }
821 return IRQ_RETVAL(status);
822 }
823
824 for (i = 0; i < chip->bdbars_count; i++) {
825 ichdev = &chip->ichd[i];
826 if (status & ichdev->int_sta_mask)
827 snd_intel8x0_update(chip, ichdev);
828 }
829
830 /* ack them */
831 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
832
833 return IRQ_HANDLED;
834}
835
836/*
837 * PCM part
838 */
839
6b75a9d8 840static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 841{
6b75a9d8
TI		 842 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
843 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 844 unsigned char val = 0;
845 unsigned long port = ichdev->reg_offset;
846
847 switch (cmd) {
1da177e4 848 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 849 ichdev->suspended = 0;
850 /* fallthru */
851 case SNDRV_PCM_TRIGGER_START:
da2436a2 852 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4 853 val = ICH_IOCE | ICH_STARTBM;
da2436a2 854 ichdev->last_pos = ichdev->position;
1da177e4 855 break;
1da177e4 856 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 857 ichdev->suspended = 1;
858 /* fallthru */
859 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 860 val = 0;
861 break;
862 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
863 val = ICH_IOCE;
864 break;
1da177e4
LT		 865 default:
866 return -EINVAL;
867 }
868 iputbyte(chip, port + ICH_REG_OFF_CR, val);
869 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
870 /* wait until DMA stopped */
871 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
872 /* reset whole DMA things */
873 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
874 }
875 return 0;
876}
877
6b75a9d8 878static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 879{
6b75a9d8
TI		 880 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
881 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 882 unsigned long port = ichdev->reg_offset;
6b75a9d8
TI		 883 static int fiforeg[] = {
884 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
885 };
1da177e4
LT		 886 unsigned int val, fifo;
887
888 val = igetdword(chip, ICHREG(ALI_DMACR));
889 switch (cmd) {
1cfe43d2
TI		 890 case SNDRV_PCM_TRIGGER_RESUME:
891 ichdev->suspended = 0;
892 /* fallthru */
1da177e4
LT		 893 case SNDRV_PCM_TRIGGER_START:
894 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 895 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
896 /* clear FIFO for synchronization of channels */
897 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
898 fifo &= ~(0xff << (ichdev->ali_slot % 4));
899 fifo |= 0x83 << (ichdev->ali_slot % 4);
900 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
901 }
902 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
903 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
6b75a9d8
TI		 904 /* start DMA */
905 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
1da177e4 906 break;
1cfe43d2
TI		 907 case SNDRV_PCM_TRIGGER_SUSPEND:
908 ichdev->suspended = 1;
909 /* fallthru */
1da177e4
LT		 910 case SNDRV_PCM_TRIGGER_STOP:
911 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
6b75a9d8
TI		 912 /* pause */
913 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
1da177e4
LT		 914 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
915 while (igetbyte(chip, port + ICH_REG_OFF_CR))
916 ;
917 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
918 break;
919 /* reset whole DMA things */
920 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
921 /* clear interrupts */
6b75a9d8
TI		 922 iputbyte(chip, port + ICH_REG_OFF_SR,
923 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
1da177e4
LT		 924 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
925 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
926 break;
927 default:
928 return -EINVAL;
929 }
930 return 0;
931}
932
6b75a9d8
TI		 933static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
934 struct snd_pcm_hw_params *hw_params)
1da177e4 935{
6b75a9d8
TI		 936 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
937 struct ichdev *ichdev = get_ichdev(substream);
938 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 939 int dbl = params_rate(hw_params) > 48000;
940 int err;
941
942 if (chip->fix_nocache && ichdev->page_attr_changed) {
943 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
944 ichdev->page_attr_changed = 0;
945 }
946 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
947 if (err < 0)
948 return err;
949 if (chip->fix_nocache) {
950 if (runtime->dma_area && ! ichdev->page_attr_changed) {
951 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
952 ichdev->page_attr_changed = 1;
953 }
954 }
955 if (ichdev->pcm_open_flag) {
956 snd_ac97_pcm_close(ichdev->pcm);
957 ichdev->pcm_open_flag = 0;
958 }
959 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
960 params_channels(hw_params),
961 ichdev->pcm->r[dbl].slots);
962 if (err >= 0) {
963 ichdev->pcm_open_flag = 1;
964 /* Force SPDIF setting */
965 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
6b75a9d8
TI		 966 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
967 params_rate(hw_params));
1da177e4
LT		 968 }
969 return err;
970}
971
6b75a9d8 972static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
1da177e4 973{
6b75a9d8
TI		 974 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
975 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 976
977 if (ichdev->pcm_open_flag) {
978 snd_ac97_pcm_close(ichdev->pcm);
979 ichdev->pcm_open_flag = 0;
980 }
981 if (chip->fix_nocache && ichdev->page_attr_changed) {
982 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
983 ichdev->page_attr_changed = 0;
984 }
985 return snd_pcm_lib_free_pages(substream);
986}
987
6b75a9d8
TI		 988static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
989 struct snd_pcm_runtime *runtime)
1da177e4
LT		 990{
991 unsigned int cnt;
992 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 993
994 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 995 switch (chip->device_type) {
996 case DEVICE_ALI:
997 cnt = igetdword(chip, ICHREG(ALI_SCR));
998 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
999 if (runtime->channels == 4 || dbl)
1000 cnt |= ICH_ALI_SC_PCM_4;
1001 else if (runtime->channels == 6)
1002 cnt |= ICH_ALI_SC_PCM_6;
1003 iputdword(chip, ICHREG(ALI_SCR), cnt);
1004 break;
1005 case DEVICE_SIS:
1006 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1007 cnt &= ~ICH_SIS_PCM_246_MASK;
1008 if (runtime->channels == 4 || dbl)
1009 cnt |= ICH_SIS_PCM_4;
1010 else if (runtime->channels == 6)
1011 cnt |= ICH_SIS_PCM_6;
1012 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1013 break;
1014 default:
1015 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1016 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1017 if (runtime->channels == 4 || dbl)
1018 cnt |= ICH_PCM_4;
1019 else if (runtime->channels == 6)
1020 cnt |= ICH_PCM_6;
4235a317
TI		 1021 else if (runtime->channels == 8)
1022 cnt |= ICH_PCM_8;
1da177e4
LT		 1023 if (chip->device_type == DEVICE_NFORCE) {
1024 /* reset to 2ch once to keep the 6 channel data in alignment,
1025 * to start from Front Left always
1026 */
1027 if (cnt & ICH_PCM_246_MASK) {
1028 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1029 spin_unlock_irq(&chip->reg_lock);
1030 msleep(50); /* grrr... */
1031 spin_lock_irq(&chip->reg_lock);
1032 }
1033 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1034 if (runtime->sample_bits > 16)
1035 cnt |= ICH_PCM_20BIT;
1036 }
1037 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1038 break;
1039 }
1cfe43d2 1040 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1041}
1042
6b75a9d8 1043static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 1044{
6b75a9d8
TI		 1045 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1046 struct snd_pcm_runtime *runtime = substream->runtime;
1047 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1048
1049 ichdev->physbuf = runtime->dma_addr;
1050 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1051 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1052 if (ichdev->ichd == ICHD_PCMOUT) {
1053 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1054 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1055 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1056 }
1057 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1058 return 0;
1059}
1060
6b75a9d8 1061static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1062{
6b75a9d8
TI		 1063 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1064 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 1065 size_t ptr1, ptr;
da2436a2 1066 int civ, timeout = 10;
1da177e4
LT		 1067 unsigned int position;
1068
1069 spin_lock(&chip->reg_lock);
1070 do {
1071 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1072 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1073 position = ichdev->position;
1074 if (ptr1 == 0) {
1075 udelay(10);
1076 continue;
1077 }
228cf793
KO		 1078 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1079 continue;
5a9a5179
DL		 1080
1081 /* IO read operation is very expensive inside virtual machine
1082 * as it is emulated. The probability that subsequent PICB read
1083 * will return different result is high enough to loop till
1084 * timeout here.
1085 * Same CIV is strict enough condition to be sure that PICB
1086 * is valid inside VM on emulated card. */
228cf793
KO		 1087 if (chip->inside_vm)
1088 break;
1089 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1da177e4
LT		 1090 break;
1091 } while (timeout--);
f708eb1d 1092 ptr = ichdev->last_pos;
da2436a2
JK		 1093 if (ptr1 != 0) {
1094 ptr1 <<= ichdev->pos_shift;
1095 ptr = ichdev->fragsize1 - ptr1;
1096 ptr += position;
f708eb1d
TI		 1097 if (ptr < ichdev->last_pos) {
1098 unsigned int pos_base, last_base;
1099 pos_base = position / ichdev->fragsize1;
1100 last_base = ichdev->last_pos / ichdev->fragsize1;
1101 /* another sanity check; ptr1 can go back to full
1102 * before the base position is updated
1103 */
1104 if (pos_base == last_base)
1105 ptr = ichdev->last_pos;
1106 }
da2436a2 1107 }
f708eb1d 1108 ichdev->last_pos = ptr;
1da177e4
LT		 1109 spin_unlock(&chip->reg_lock);
1110 if (ptr >= ichdev->size)
1111 return 0;
1112 return bytes_to_frames(substream->runtime, ptr);
1113}
1114
6b75a9d8 1115static struct snd_pcm_hardware snd_intel8x0_stream =
1da177e4
LT		 1116{
1117 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1118 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1119 SNDRV_PCM_INFO_MMAP_VALID |
1120 SNDRV_PCM_INFO_PAUSE |
1121 SNDRV_PCM_INFO_RESUME),
1122 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1123 .rates = SNDRV_PCM_RATE_48000,
1124 .rate_min = 48000,
1125 .rate_max = 48000,
1126 .channels_min = 2,
1127 .channels_max = 2,
1128 .buffer_bytes_max = 128 * 1024,
1129 .period_bytes_min = 32,
1130 .period_bytes_max = 128 * 1024,
1131 .periods_min = 1,
1132 .periods_max = 1024,
1133 .fifo_size = 0,
1134};
1135
1136static unsigned int channels4[] = {
1137 2, 4,
1138};
1139
6b75a9d8 1140static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1da177e4
LT		 1141 .count = ARRAY_SIZE(channels4),
1142 .list = channels4,
1143 .mask = 0,
1144};
1145
1146static unsigned int channels6[] = {
1147 2, 4, 6,
1148};
1149
6b75a9d8 1150static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1da177e4
LT		 1151 .count = ARRAY_SIZE(channels6),
1152 .list = channels6,
1153 .mask = 0,
1154};
1155
4235a317
TI		 1156static unsigned int channels8[] = {
1157 2, 4, 6, 8,
1158};
1159
1160static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1161 .count = ARRAY_SIZE(channels8),
1162 .list = channels8,
1163 .mask = 0,
1164};
1165
6b75a9d8 1166static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1da177e4 1167{
6b75a9d8
TI		 1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1170 int err;
1171
1172 ichdev->substream = substream;
1173 runtime->hw = snd_intel8x0_stream;
1174 runtime->hw.rates = ichdev->pcm->rates;
1175 snd_pcm_limit_hw_rates(runtime);
1176 if (chip->device_type == DEVICE_SIS) {
1177 runtime->hw.buffer_bytes_max = 64*1024;
1178 runtime->hw.period_bytes_max = 64*1024;
1179 }
1180 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1181 return err;
1182 runtime->private_data = ichdev;
1183 return 0;
1184}
1185
6b75a9d8 1186static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1da177e4 1187{
6b75a9d8
TI		 1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1190 int err;
1191
1192 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1193 if (err < 0)
1194 return err;
1195
4235a317
TI		 1196 if (chip->multi8) {
1197 runtime->hw.channels_max = 8;
1198 snd_pcm_hw_constraint_list(runtime, 0,
1199 SNDRV_PCM_HW_PARAM_CHANNELS,
1200 &hw_constraints_channels8);
1201 } else if (chip->multi6) {
1da177e4 1202 runtime->hw.channels_max = 6;
6b75a9d8
TI		 1203 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1204 &hw_constraints_channels6);
1da177e4
LT		 1205 } else if (chip->multi4) {
1206 runtime->hw.channels_max = 4;
6b75a9d8
TI		 1207 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1208 &hw_constraints_channels4);
1da177e4
LT		 1209 }
1210 if (chip->dra) {
1211 snd_ac97_pcm_double_rate_rules(runtime);
1212 }
1213 if (chip->smp20bit) {
1214 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1215 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1216 }
1217 return 0;
1218}
1219
6b75a9d8 1220static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1da177e4 1221{
6b75a9d8 1222 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1223
1224 chip->ichd[ICHD_PCMOUT].substream = NULL;
1225 return 0;
1226}
1227
6b75a9d8 1228static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1da177e4 1229{
6b75a9d8 1230 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1231
1232 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1233}
1234
6b75a9d8 1235static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1da177e4 1236{
6b75a9d8 1237 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1238
1239 chip->ichd[ICHD_PCMIN].substream = NULL;
1240 return 0;
1241}
1242
6b75a9d8 1243static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1da177e4 1244{
6b75a9d8 1245 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1246
1247 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1248}
1249
6b75a9d8 1250static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1da177e4 1251{
6b75a9d8 1252 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1253
1254 chip->ichd[ICHD_MIC].substream = NULL;
1255 return 0;
1256}
1257
6b75a9d8 1258static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1da177e4 1259{
6b75a9d8 1260 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1261
1262 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1263}
1264
6b75a9d8 1265static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1da177e4 1266{
6b75a9d8 1267 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1268
1269 chip->ichd[ICHD_MIC2].substream = NULL;
1270 return 0;
1271}
1272
6b75a9d8 1273static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1da177e4 1274{
6b75a9d8 1275 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1276
1277 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1278}
1279
6b75a9d8 1280static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1da177e4 1281{
6b75a9d8 1282 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1283
1284 chip->ichd[ICHD_PCM2IN].substream = NULL;
1285 return 0;
1286}
1287
6b75a9d8 1288static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1289{
6b75a9d8 1290 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1291 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1292
1293 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1294}
1295
6b75a9d8 1296static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1297{
6b75a9d8 1298 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1299 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1300
1301 chip->ichd[idx].substream = NULL;
1302 return 0;
1303}
1304
6b75a9d8 1305static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1306{
6b75a9d8 1307 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1308 unsigned int val;
1309
1310 spin_lock_irq(&chip->reg_lock);
1311 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1312 val |= ICH_ALI_IF_AC97SP;
1313 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1314 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1315 spin_unlock_irq(&chip->reg_lock);
1316
1317 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1318}
1319
6b75a9d8 1320static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1321{
6b75a9d8 1322 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1323 unsigned int val;
1324
1325 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1326 spin_lock_irq(&chip->reg_lock);
1327 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1328 val &= ~ICH_ALI_IF_AC97SP;
1329 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1330 spin_unlock_irq(&chip->reg_lock);
1331
1332 return 0;
1333}
1334
1a183131 1335#if 0 // NYI
6b75a9d8 1336static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1da177e4 1337{
6b75a9d8 1338 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1339
1340 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1341}
1342
6b75a9d8 1343static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1da177e4 1344{
6b75a9d8 1345 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1346
1347 chip->ichd[ALID_SPDIFIN].substream = NULL;
1348 return 0;
1349}
1350
6b75a9d8 1351static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1352{
6b75a9d8 1353 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1354
1355 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1356}
1357
6b75a9d8 1358static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1359{
6b75a9d8 1360 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1361
1362 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1363 return 0;
1364}
1365#endif
1366
6b75a9d8 1367static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1da177e4
LT		 1368 .open = snd_intel8x0_playback_open,
1369 .close = snd_intel8x0_playback_close,
1370 .ioctl = snd_pcm_lib_ioctl,
1371 .hw_params = snd_intel8x0_hw_params,
1372 .hw_free = snd_intel8x0_hw_free,
1373 .prepare = snd_intel8x0_pcm_prepare,
1374 .trigger = snd_intel8x0_pcm_trigger,
1375 .pointer = snd_intel8x0_pcm_pointer,
1376};
1377
6b75a9d8 1378static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1da177e4
LT		 1379 .open = snd_intel8x0_capture_open,
1380 .close = snd_intel8x0_capture_close,
1381 .ioctl = snd_pcm_lib_ioctl,
1382 .hw_params = snd_intel8x0_hw_params,
1383 .hw_free = snd_intel8x0_hw_free,
1384 .prepare = snd_intel8x0_pcm_prepare,
1385 .trigger = snd_intel8x0_pcm_trigger,
1386 .pointer = snd_intel8x0_pcm_pointer,
1387};
1388
6b75a9d8 1389static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1da177e4
LT		 1390 .open = snd_intel8x0_mic_open,
1391 .close = snd_intel8x0_mic_close,
1392 .ioctl = snd_pcm_lib_ioctl,
1393 .hw_params = snd_intel8x0_hw_params,
1394 .hw_free = snd_intel8x0_hw_free,
1395 .prepare = snd_intel8x0_pcm_prepare,
1396 .trigger = snd_intel8x0_pcm_trigger,
1397 .pointer = snd_intel8x0_pcm_pointer,
1398};
1399
6b75a9d8 1400static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1da177e4
LT		 1401 .open = snd_intel8x0_mic2_open,
1402 .close = snd_intel8x0_mic2_close,
1403 .ioctl = snd_pcm_lib_ioctl,
1404 .hw_params = snd_intel8x0_hw_params,
1405 .hw_free = snd_intel8x0_hw_free,
1406 .prepare = snd_intel8x0_pcm_prepare,
1407 .trigger = snd_intel8x0_pcm_trigger,
1408 .pointer = snd_intel8x0_pcm_pointer,
1409};
1410
6b75a9d8 1411static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1da177e4
LT		 1412 .open = snd_intel8x0_capture2_open,
1413 .close = snd_intel8x0_capture2_close,
1414 .ioctl = snd_pcm_lib_ioctl,
1415 .hw_params = snd_intel8x0_hw_params,
1416 .hw_free = snd_intel8x0_hw_free,
1417 .prepare = snd_intel8x0_pcm_prepare,
1418 .trigger = snd_intel8x0_pcm_trigger,
1419 .pointer = snd_intel8x0_pcm_pointer,
1420};
1421
6b75a9d8 1422static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1da177e4
LT		 1423 .open = snd_intel8x0_spdif_open,
1424 .close = snd_intel8x0_spdif_close,
1425 .ioctl = snd_pcm_lib_ioctl,
1426 .hw_params = snd_intel8x0_hw_params,
1427 .hw_free = snd_intel8x0_hw_free,
1428 .prepare = snd_intel8x0_pcm_prepare,
1429 .trigger = snd_intel8x0_pcm_trigger,
1430 .pointer = snd_intel8x0_pcm_pointer,
1431};
1432
6b75a9d8 1433static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1da177e4
LT		 1434 .open = snd_intel8x0_playback_open,
1435 .close = snd_intel8x0_playback_close,
1436 .ioctl = snd_pcm_lib_ioctl,
1437 .hw_params = snd_intel8x0_hw_params,
1438 .hw_free = snd_intel8x0_hw_free,
1439 .prepare = snd_intel8x0_pcm_prepare,
1440 .trigger = snd_intel8x0_ali_trigger,
1441 .pointer = snd_intel8x0_pcm_pointer,
1442};
1443
6b75a9d8 1444static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1da177e4
LT		 1445 .open = snd_intel8x0_capture_open,
1446 .close = snd_intel8x0_capture_close,
1447 .ioctl = snd_pcm_lib_ioctl,
1448 .hw_params = snd_intel8x0_hw_params,
1449 .hw_free = snd_intel8x0_hw_free,
1450 .prepare = snd_intel8x0_pcm_prepare,
1451 .trigger = snd_intel8x0_ali_trigger,
1452 .pointer = snd_intel8x0_pcm_pointer,
1453};
1454
6b75a9d8 1455static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1da177e4
LT		 1456 .open = snd_intel8x0_mic_open,
1457 .close = snd_intel8x0_mic_close,
1458 .ioctl = snd_pcm_lib_ioctl,
1459 .hw_params = snd_intel8x0_hw_params,
1460 .hw_free = snd_intel8x0_hw_free,
1461 .prepare = snd_intel8x0_pcm_prepare,
1462 .trigger = snd_intel8x0_ali_trigger,
1463 .pointer = snd_intel8x0_pcm_pointer,
1464};
1465
6b75a9d8 1466static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1da177e4
LT		 1467 .open = snd_intel8x0_ali_ac97spdifout_open,
1468 .close = snd_intel8x0_ali_ac97spdifout_close,
1469 .ioctl = snd_pcm_lib_ioctl,
1470 .hw_params = snd_intel8x0_hw_params,
1471 .hw_free = snd_intel8x0_hw_free,
1472 .prepare = snd_intel8x0_pcm_prepare,
1473 .trigger = snd_intel8x0_ali_trigger,
1474 .pointer = snd_intel8x0_pcm_pointer,
1475};
1476
1a183131 1477#if 0 // NYI
6b75a9d8 1478static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1da177e4
LT		 1479 .open = snd_intel8x0_ali_spdifin_open,
1480 .close = snd_intel8x0_ali_spdifin_close,
1481 .ioctl = snd_pcm_lib_ioctl,
1482 .hw_params = snd_intel8x0_hw_params,
1483 .hw_free = snd_intel8x0_hw_free,
1484 .prepare = snd_intel8x0_pcm_prepare,
1485 .trigger = snd_intel8x0_pcm_trigger,
1486 .pointer = snd_intel8x0_pcm_pointer,
1487};
1488
6b75a9d8 1489static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1da177e4
LT		 1490 .open = snd_intel8x0_ali_spdifout_open,
1491 .close = snd_intel8x0_ali_spdifout_close,
1492 .ioctl = snd_pcm_lib_ioctl,
1493 .hw_params = snd_intel8x0_hw_params,
1494 .hw_free = snd_intel8x0_hw_free,
1495 .prepare = snd_intel8x0_pcm_prepare,
1496 .trigger = snd_intel8x0_pcm_trigger,
1497 .pointer = snd_intel8x0_pcm_pointer,
1498};
1499#endif // NYI
1500
1501struct ich_pcm_table {
1502 char *suffix;
6b75a9d8
TI		 1503 struct snd_pcm_ops *playback_ops;
1504 struct snd_pcm_ops *capture_ops;
1da177e4
LT		 1505 size_t prealloc_size;
1506 size_t prealloc_max_size;
1507 int ac97_idx;
1508};
1509
6b75a9d8
TI		 1510static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1511 struct ich_pcm_table *rec)
1da177e4 1512{
6b75a9d8 1513 struct snd_pcm *pcm;
1da177e4
LT		 1514 int err;
1515 char name[32];
1516
1517 if (rec->suffix)
1518 sprintf(name, "Intel ICH - %s", rec->suffix);
1519 else
1520 strcpy(name, "Intel ICH");
1521 err = snd_pcm_new(chip->card, name, device,
1522 rec->playback_ops ? 1 : 0,
1523 rec->capture_ops ? 1 : 0, &pcm);
1524 if (err < 0)
1525 return err;
1526
1527 if (rec->playback_ops)
1528 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1529 if (rec->capture_ops)
1530 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1531
1532 pcm->private_data = chip;
1533 pcm->info_flags = 0;
1534 if (rec->suffix)
1535 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1536 else
1537 strcpy(pcm->name, chip->card->shortname);
1538 chip->pcm[device] = pcm;
1539
6b75a9d8
TI		 1540 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1541 snd_dma_pci_data(chip->pci),
1da177e4
LT		 1542 rec->prealloc_size, rec->prealloc_max_size);
1543
1544 return 0;
1545}
1546
1547static struct ich_pcm_table intel_pcms[] __devinitdata = {
1548 {
1549 .playback_ops = &snd_intel8x0_playback_ops,
1550 .capture_ops = &snd_intel8x0_capture_ops,
1551 .prealloc_size = 64 * 1024,
1552 .prealloc_max_size = 128 * 1024,
1553 },
1554 {
1555 .suffix = "MIC ADC",
1556 .capture_ops = &snd_intel8x0_capture_mic_ops,
1557 .prealloc_size = 0,
1558 .prealloc_max_size = 128 * 1024,
1559 .ac97_idx = ICHD_MIC,
1560 },
1561 {
1562 .suffix = "MIC2 ADC",
1563 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1564 .prealloc_size = 0,
1565 .prealloc_max_size = 128 * 1024,
1566 .ac97_idx = ICHD_MIC2,
1567 },
1568 {
1569 .suffix = "ADC2",
1570 .capture_ops = &snd_intel8x0_capture2_ops,
1571 .prealloc_size = 0,
1572 .prealloc_max_size = 128 * 1024,
1573 .ac97_idx = ICHD_PCM2IN,
1574 },
1575 {
1576 .suffix = "IEC958",
1577 .playback_ops = &snd_intel8x0_spdif_ops,
1578 .prealloc_size = 64 * 1024,
1579 .prealloc_max_size = 128 * 1024,
1580 .ac97_idx = ICHD_SPBAR,
1581 },
1582};
1583
1584static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1585 {
1586 .playback_ops = &snd_intel8x0_playback_ops,
1587 .capture_ops = &snd_intel8x0_capture_ops,
1588 .prealloc_size = 64 * 1024,
1589 .prealloc_max_size = 128 * 1024,
1590 },
1591 {
1592 .suffix = "MIC ADC",
1593 .capture_ops = &snd_intel8x0_capture_mic_ops,
1594 .prealloc_size = 0,
1595 .prealloc_max_size = 128 * 1024,
1596 .ac97_idx = NVD_MIC,
1597 },
1598 {
1599 .suffix = "IEC958",
1600 .playback_ops = &snd_intel8x0_spdif_ops,
1601 .prealloc_size = 64 * 1024,
1602 .prealloc_max_size = 128 * 1024,
1603 .ac97_idx = NVD_SPBAR,
1604 },
1605};
1606
1607static struct ich_pcm_table ali_pcms[] __devinitdata = {
1608 {
1609 .playback_ops = &snd_intel8x0_ali_playback_ops,
1610 .capture_ops = &snd_intel8x0_ali_capture_ops,
1611 .prealloc_size = 64 * 1024,
1612 .prealloc_max_size = 128 * 1024,
1613 },
1614 {
1615 .suffix = "MIC ADC",
1616 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1617 .prealloc_size = 0,
1618 .prealloc_max_size = 128 * 1024,
1619 .ac97_idx = ALID_MIC,
1620 },
1621 {
1622 .suffix = "IEC958",
1623 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1a183131 1624 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1da177e4
LT		 1625 .prealloc_size = 64 * 1024,
1626 .prealloc_max_size = 128 * 1024,
1627 .ac97_idx = ALID_AC97SPDIFOUT,
1628 },
1629#if 0 // NYI
1630 {
1631 .suffix = "HW IEC958",
1632 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1633 .prealloc_size = 64 * 1024,
1634 .prealloc_max_size = 128 * 1024,
1635 },
1636#endif
1637};
1638
6b75a9d8 1639static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1da177e4
LT		 1640{
1641 int i, tblsize, device, err;
1642 struct ich_pcm_table *tbl, *rec;
1643
1644 switch (chip->device_type) {
1645 case DEVICE_INTEL_ICH4:
1646 tbl = intel_pcms;
1647 tblsize = ARRAY_SIZE(intel_pcms);
a9e99660
TI		 1648 if (spdif_aclink)
1649 tblsize--;
1da177e4
LT		 1650 break;
1651 case DEVICE_NFORCE:
1652 tbl = nforce_pcms;
1653 tblsize = ARRAY_SIZE(nforce_pcms);
a9e99660
TI		 1654 if (spdif_aclink)
1655 tblsize--;
1da177e4
LT		 1656 break;
1657 case DEVICE_ALI:
1658 tbl = ali_pcms;
1659 tblsize = ARRAY_SIZE(ali_pcms);
1660 break;
1661 default:
1662 tbl = intel_pcms;
1663 tblsize = 2;
1664 break;
1665 }
1666
1667 device = 0;
1668 for (i = 0; i < tblsize; i++) {
1669 rec = tbl + i;
1670 if (i > 0 && rec->ac97_idx) {
1671 /* activate PCM only when associated AC'97 codec */
1672 if (! chip->ichd[rec->ac97_idx].pcm)
1673 continue;
1674 }
1675 err = snd_intel8x0_pcm1(chip, device, rec);
1676 if (err < 0)
1677 return err;
1678 device++;
1679 }
1680
1681 chip->pcm_devs = device;
1682 return 0;
1683}
1684
1685
1686/*
1687 * Mixer part
1688 */
1689
6b75a9d8 1690static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1691{
6b75a9d8 1692 struct intel8x0 *chip = bus->private_data;
1da177e4
LT		 1693 chip->ac97_bus = NULL;
1694}
1695
6b75a9d8 1696static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1697{
6b75a9d8 1698 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 1699 chip->ac97[ac97->num] = NULL;
1700}
1701
1702static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1703 /* front PCM */
1704 {
1705 .exclusive = 1,
1706 .r = { {
1707 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1708 (1 << AC97_SLOT_PCM_RIGHT) |
1709 (1 << AC97_SLOT_PCM_CENTER) |
1710 (1 << AC97_SLOT_PCM_SLEFT) |
1711 (1 << AC97_SLOT_PCM_SRIGHT) |
1712 (1 << AC97_SLOT_LFE)
1713 },
1714 {
1715 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1716 (1 << AC97_SLOT_PCM_RIGHT) |
1717 (1 << AC97_SLOT_PCM_LEFT_0) |
1718 (1 << AC97_SLOT_PCM_RIGHT_0)
1719 }
1720 }
1721 },
1722 /* PCM IN #1 */
1723 {
1724 .stream = 1,
1725 .exclusive = 1,
1726 .r = { {
1727 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1728 (1 << AC97_SLOT_PCM_RIGHT)
1729 }
1730 }
1731 },
1732 /* MIC IN #1 */
1733 {
1734 .stream = 1,
1735 .exclusive = 1,
1736 .r = { {
1737 .slots = (1 << AC97_SLOT_MIC)
1738 }
1739 }
1740 },
1741 /* S/PDIF PCM */
1742 {
1743 .exclusive = 1,
1744 .spdif = 1,
1745 .r = { {
1746 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1747 (1 << AC97_SLOT_SPDIF_RIGHT2)
1748 }
1749 }
1750 },
1751 /* PCM IN #2 */
1752 {
1753 .stream = 1,
1754 .exclusive = 1,
1755 .r = { {
1756 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1757 (1 << AC97_SLOT_PCM_RIGHT)
1758 }
1759 }
1760 },
1761 /* MIC IN #2 */
1762 {
1763 .stream = 1,
1764 .exclusive = 1,
1765 .r = { {
1766 .slots = (1 << AC97_SLOT_MIC)
1767 }
1768 }
1769 },
1770};
1771
1772static struct ac97_quirk ac97_quirks[] __devinitdata = {
0d9ac27a
TI		 1773 {
1774 .subvendor = 0x0e11,
1775 .subdevice = 0x000e,
1776 .name = "Compaq Deskpro EN", /* AD1885 */
1777 .type = AC97_TUNE_HP_ONLY
1778 },
1da177e4 1779 {
6fd8b87f
JCD		 1780 .subvendor = 0x0e11,
1781 .subdevice = 0x008a,
1da177e4
LT		 1782 .name = "Compaq Evo W4000", /* AD1885 */
1783 .type = AC97_TUNE_HP_ONLY
1784 },
1785 {
6fd8b87f
JCD		 1786 .subvendor = 0x0e11,
1787 .subdevice = 0x00b8,
1da177e4
LT		 1788 .name = "Compaq Evo D510C",
1789 .type = AC97_TUNE_HP_ONLY
1790 },
1791 {
6fd8b87f
JCD		 1792 .subvendor = 0x0e11,
1793 .subdevice = 0x0860,
1da177e4
LT		 1794 .name = "HP/Compaq nx7010",
1795 .type = AC97_TUNE_MUTE_LED
1796 },
9c77b846
DC		 1797 {
1798 .subvendor = 0x1014,
1799 .subdevice = 0x0534,
1800 .name = "ThinkPad X31",
1801 .type = AC97_TUNE_INV_EAPD
1802 },
1da177e4 1803 {
6fd8b87f
JCD		 1804 .subvendor = 0x1014,
1805 .subdevice = 0x1f00,
1da177e4
LT		 1806 .name = "MS-9128",
1807 .type = AC97_TUNE_ALC_JACK
1808 },
5d529390
TI		 1809 {
1810 .subvendor = 0x1014,
1811 .subdevice = 0x0267,
1812 .name = "IBM NetVista A30p", /* AD1981B */
1813 .type = AC97_TUNE_HP_ONLY
b6a370b6
TI		 1814 },
1815 {
1816 .subvendor = 0x1025,
1817 .subdevice = 0x0082,
1818 .name = "Acer Travelmate 2310",
1819 .type = AC97_TUNE_HP_ONLY
5d529390 1820 },
72c8986c
DS		 1821 {
1822 .subvendor = 0x1025,
1823 .subdevice = 0x0083,
1824 .name = "Acer Aspire 3003LCi",
1825 .type = AC97_TUNE_HP_ONLY
1826 },
1da177e4 1827 {
6fd8b87f
JCD		 1828 .subvendor = 0x1028,
1829 .subdevice = 0x00d8,
1da177e4
LT		 1830 .name = "Dell Precision 530", /* AD1885 */
1831 .type = AC97_TUNE_HP_ONLY
1832 },
1833 {
6fd8b87f
JCD		 1834 .subvendor = 0x1028,
1835 .subdevice = 0x010d,
1da177e4
LT		 1836 .name = "Dell", /* which model? AD1885 */
1837 .type = AC97_TUNE_HP_ONLY
1838 },
1839 {
6fd8b87f
JCD		 1840 .subvendor = 0x1028,
1841 .subdevice = 0x0126,
1da177e4
LT		 1842 .name = "Dell Optiplex GX260", /* AD1981A */
1843 .type = AC97_TUNE_HP_ONLY
1844 },
1845 {
6fd8b87f
JCD		 1846 .subvendor = 0x1028,
1847 .subdevice = 0x012c,
1da177e4
LT		 1848 .name = "Dell Precision 650", /* AD1981A */
1849 .type = AC97_TUNE_HP_ONLY
1850 },
1851 {
6fd8b87f
JCD		 1852 .subvendor = 0x1028,
1853 .subdevice = 0x012d,
1da177e4
LT		 1854 .name = "Dell Precision 450", /* AD1981B*/
1855 .type = AC97_TUNE_HP_ONLY
1856 },
1857 {
6fd8b87f
JCD		 1858 .subvendor = 0x1028,
1859 .subdevice = 0x0147,
1da177e4
LT		 1860 .name = "Dell", /* which model? AD1981B*/
1861 .type = AC97_TUNE_HP_ONLY
1862 },
c9fe51c4
CB		 1863 {
1864 .subvendor = 0x1028,
1865 .subdevice = 0x0151,
1866 .name = "Dell Optiplex GX270", /* AD1981B */
1867 .type = AC97_TUNE_HP_ONLY
1868 },
1781a9af
DC		 1869 {
1870 .subvendor = 0x1028,
1871 .subdevice = 0x014e,
1872 .name = "Dell D800", /* STAC9750/51 */
1873 .type = AC97_TUNE_HP_ONLY
1874 },
1da177e4 1875 {
6fd8b87f
JCD		 1876 .subvendor = 0x1028,
1877 .subdevice = 0x0163,
1da177e4
LT		 1878 .name = "Dell Unknown", /* STAC9750/51 */
1879 .type = AC97_TUNE_HP_ONLY
1880 },
c8283425
DC		 1881 {
1882 .subvendor = 0x1028,
1883 .subdevice = 0x016a,
1884 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1885 .type = AC97_TUNE_HP_ONLY
0613a594
DC		 1886 },
1887 {
1888 .subvendor = 0x1028,
1889 .subdevice = 0x0182,
1890 .name = "Dell Latitude D610", /* STAC9750/51 */
1891 .type = AC97_TUNE_HP_ONLY
c8283425 1892 },
8286c53e
DC		 1893 {
1894 .subvendor = 0x1028,
1895 .subdevice = 0x0186,
1896 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1897 .type = AC97_TUNE_HP_MUTE_LED
1898 },
1899 {
1900 .subvendor = 0x1028,
1901 .subdevice = 0x0188,
1902 .name = "Dell Inspiron 6000",
1903 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1904 },
f21169aa
DC		 1905 {
1906 .subvendor = 0x1028,
1907 .subdevice = 0x0189,
1908 .name = "Dell Inspiron 9300",
1909 .type = AC97_TUNE_HP_MUTE_LED
1910 },
6d6f9156
KL		 1911 {
1912 .subvendor = 0x1028,
1913 .subdevice = 0x0191,
1914 .name = "Dell Inspiron 8600",
1915 .type = AC97_TUNE_HP_ONLY
1916 },
1da177e4 1917 {
6fd8b87f
JCD		 1918 .subvendor = 0x103c,
1919 .subdevice = 0x006d,
1da177e4
LT		 1920 .name = "HP zv5000",
1921 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1922 },
1923 { /* FIXME: which codec? */
6fd8b87f
JCD		 1924 .subvendor = 0x103c,
1925 .subdevice = 0x00c3,
1da177e4
LT		 1926 .name = "HP xw6000",
1927 .type = AC97_TUNE_HP_ONLY
1928 },
1929 {
6fd8b87f
JCD		 1930 .subvendor = 0x103c,
1931 .subdevice = 0x088c,
1da177e4 1932 .name = "HP nc8000",
8286c53e 1933 .type = AC97_TUNE_HP_MUTE_LED
1da177e4
LT		 1934 },
1935 {
6fd8b87f
JCD		 1936 .subvendor = 0x103c,
1937 .subdevice = 0x0890,
1da177e4
LT		 1938 .name = "HP nc6000",
1939 .type = AC97_TUNE_MUTE_LED
1940 },
1941 {
6fd8b87f
JCD		 1942 .subvendor = 0x103c,
1943 .subdevice = 0x129d,
1da177e4
LT		 1944 .name = "HP xw8000",
1945 .type = AC97_TUNE_HP_ONLY
1946 },
a0faefed
MG		 1947 {
1948 .subvendor = 0x103c,
1949 .subdevice = 0x0938,
1950 .name = "HP nc4200",
1951 .type = AC97_TUNE_HP_MUTE_LED
1952 },
1953 {
1954 .subvendor = 0x103c,
1955 .subdevice = 0x099c,
d82ed2ff 1956 .name = "HP nx6110/nc6120",
a0faefed
MG		 1957 .type = AC97_TUNE_HP_MUTE_LED
1958 },
1959 {
1960 .subvendor = 0x103c,
1961 .subdevice = 0x0944,
1962 .name = "HP nc6220",
1963 .type = AC97_TUNE_HP_MUTE_LED
1964 },
1965 {
1966 .subvendor = 0x103c,
1967 .subdevice = 0x0934,
1968 .name = "HP nc8220",
1969 .type = AC97_TUNE_HP_MUTE_LED
1970 },
1da177e4 1971 {
6fd8b87f
JCD		 1972 .subvendor = 0x103c,
1973 .subdevice = 0x12f1,
1da177e4
LT		 1974 .name = "HP xw8200", /* AD1981B*/
1975 .type = AC97_TUNE_HP_ONLY
1976 },
1977 {
6fd8b87f
JCD		 1978 .subvendor = 0x103c,
1979 .subdevice = 0x12f2,
1da177e4
LT		 1980 .name = "HP xw6200",
1981 .type = AC97_TUNE_HP_ONLY
1982 },
1983 {
6fd8b87f
JCD		 1984 .subvendor = 0x103c,
1985 .subdevice = 0x3008,
1da177e4
LT		 1986 .name = "HP xw4200", /* AD1981B*/
1987 .type = AC97_TUNE_HP_ONLY
1988 },
7e6c3989
DC		 1989 {
1990 .subvendor = 0x104d,
1991 .subdevice = 0x8144,
1992 .name = "Sony",
1993 .type = AC97_TUNE_INV_EAPD
1994 },
1da177e4 1995 {
6fd8b87f
JCD		 1996 .subvendor = 0x104d,
1997 .subdevice = 0x8197,
1da177e4
LT		 1998 .name = "Sony S1XP",
1999 .type = AC97_TUNE_INV_EAPD
2000 },
5da5b6f9
DC		 2001 {
2002 .subvendor = 0x104d,
2003 .subdevice = 0x81c0,
2004 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2005 .type = AC97_TUNE_INV_EAPD
2006 },
ebb6f6ac
DC		 2007 {
2008 .subvendor = 0x104d,
2009 .subdevice = 0x81c5,
2010 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2011 .type = AC97_TUNE_INV_EAPD
2012 },
1da177e4 2013 {
6fd8b87f
JCD		 2014 .subvendor = 0x1043,
2015 .subdevice = 0x80f3,
1da177e4
LT		 2016 .name = "ASUS ICH5/AD1985",
2017 .type = AC97_TUNE_AD_SHARING
2018 },
2019 {
6fd8b87f
JCD		 2020 .subvendor = 0x10cf,
2021 .subdevice = 0x11c3,
1da177e4
LT		 2022 .name = "Fujitsu-Siemens E4010",
2023 .type = AC97_TUNE_HP_ONLY
2024 },
98c7f212
TI		 2025 {
2026 .subvendor = 0x10cf,
2027 .subdevice = 0x1225,
2028 .name = "Fujitsu-Siemens T3010",
2029 .type = AC97_TUNE_HP_ONLY
2030 },
1da177e4 2031 {
6fd8b87f
JCD		 2032 .subvendor = 0x10cf,
2033 .subdevice = 0x1253,
1da177e4
LT		 2034 .name = "Fujitsu S6210", /* STAC9750/51 */
2035 .type = AC97_TUNE_HP_ONLY
2036 },
37c34ffb
TI		 2037 {
2038 .subvendor = 0x10cf,
2039 .subdevice = 0x127d,
2040 .name = "Fujitsu Lifebook P7010",
2041 .type = AC97_TUNE_HP_ONLY
2042 },
8286c53e
DC		 2043 {
2044 .subvendor = 0x10cf,
2045 .subdevice = 0x127e,
2046 .name = "Fujitsu Lifebook C1211D",
2047 .type = AC97_TUNE_HP_ONLY
2048 },
9970dce5
TI		 2049 {
2050 .subvendor = 0x10cf,
2051 .subdevice = 0x12ec,
2052 .name = "Fujitsu-Siemens 4010",
2053 .type = AC97_TUNE_HP_ONLY
2054 },
2eb061f4
JK		 2055 {
2056 .subvendor = 0x10cf,
2057 .subdevice = 0x12f2,
2058 .name = "Fujitsu-Siemens Celsius H320",
2059 .type = AC97_TUNE_SWAP_HP
2060 },
1da177e4 2061 {
6fd8b87f
JCD		 2062 .subvendor = 0x10f1,
2063 .subdevice = 0x2665,
1da177e4
LT		 2064 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2065 .type = AC97_TUNE_HP_ONLY
2066 },
2067 {
6fd8b87f
JCD		 2068 .subvendor = 0x10f1,
2069 .subdevice = 0x2885,
1da177e4
LT		 2070 .name = "AMD64 Mobo", /* ALC650 */
2071 .type = AC97_TUNE_HP_ONLY
2072 },
4f42bcc1
TI		 2073 {
2074 .subvendor = 0x10f1,
2075 .subdevice = 0x2895,
2076 .name = "Tyan Thunder K8WE",
2077 .type = AC97_TUNE_HP_ONLY
2078 },
6c504447
KP		 2079 {
2080 .subvendor = 0x10f7,
2081 .subdevice = 0x834c,
2082 .name = "Panasonic CF-R4",
2083 .type = AC97_TUNE_HP_ONLY,
2084 },
1da177e4 2085 {
6fd8b87f
JCD		 2086 .subvendor = 0x110a,
2087 .subdevice = 0x0056,
1da177e4
LT		 2088 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2089 .type = AC97_TUNE_HP_ONLY
2090 },
2091 {
6fd8b87f
JCD		 2092 .subvendor = 0x11d4,
2093 .subdevice = 0x5375,
1da177e4
LT		 2094 .name = "ADI AD1985 (discrete)",
2095 .type = AC97_TUNE_HP_ONLY
2096 },
2097 {
6fd8b87f
JCD		 2098 .subvendor = 0x1462,
2099 .subdevice = 0x5470,
1da177e4
LT		 2100 .name = "MSI P4 ATX 645 Ultra",
2101 .type = AC97_TUNE_HP_ONLY
2102 },
27c3afe6
DC		 2103 {
2104 .subvendor = 0x161f,
2105 .subdevice = 0x202f,
2106 .name = "Gateway M520",
2107 .type = AC97_TUNE_INV_EAPD
2108 },
bbb3c644
DC		 2109 {
2110 .subvendor = 0x161f,
2111 .subdevice = 0x203a,
2112 .name = "Gateway 4525GZ", /* AD1981B */
2113 .type = AC97_TUNE_INV_EAPD
2114 },
1da177e4 2115 {
6fd8b87f
JCD		 2116 .subvendor = 0x1734,
2117 .subdevice = 0x0088,
1da177e4
LT		 2118 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2119 .type = AC97_TUNE_HP_ONLY
2120 },
2121 {
6fd8b87f
JCD		 2122 .subvendor = 0x8086,
2123 .subdevice = 0x2000,
1da177e4
LT		 2124 .mask = 0xfff0,
2125 .name = "Intel ICH5/AD1985",
2126 .type = AC97_TUNE_AD_SHARING
2127 },
2128 {
6fd8b87f
JCD		 2129 .subvendor = 0x8086,
2130 .subdevice = 0x4000,
1da177e4
LT		 2131 .mask = 0xfff0,
2132 .name = "Intel ICH5/AD1985",
2133 .type = AC97_TUNE_AD_SHARING
2134 },
2135 {
6fd8b87f
JCD		 2136 .subvendor = 0x8086,
2137 .subdevice = 0x4856,
1da177e4
LT		 2138 .name = "Intel D845WN (82801BA)",
2139 .type = AC97_TUNE_SWAP_HP
2140 },
2141 {
6fd8b87f
JCD		 2142 .subvendor = 0x8086,
2143 .subdevice = 0x4d44,
1da177e4
LT		 2144 .name = "Intel D850EMV2", /* AD1885 */
2145 .type = AC97_TUNE_HP_ONLY
2146 },
2147 {
6fd8b87f
JCD		 2148 .subvendor = 0x8086,
2149 .subdevice = 0x4d56,
1da177e4
LT		 2150 .name = "Intel ICH/AD1885",
2151 .type = AC97_TUNE_HP_ONLY
2152 },
2153 {
6fd8b87f
JCD		 2154 .subvendor = 0x8086,
2155 .subdevice = 0x6000,
1da177e4
LT		 2156 .mask = 0xfff0,
2157 .name = "Intel ICH5/AD1985",
2158 .type = AC97_TUNE_AD_SHARING
2159 },
2160 {
6fd8b87f
JCD		 2161 .subvendor = 0x8086,
2162 .subdevice = 0xe000,
1da177e4
LT		 2163 .mask = 0xfff0,
2164 .name = "Intel ICH5/AD1985",
2165 .type = AC97_TUNE_AD_SHARING
2166 },
2167#if 0 /* FIXME: this seems wrong on most boards */
2168 {
6fd8b87f
JCD		 2169 .subvendor = 0x8086,
2170 .subdevice = 0xa000,
1da177e4
LT		 2171 .mask = 0xfff0,
2172 .name = "Intel ICH5/AD1985",
2173 .type = AC97_TUNE_HP_ONLY
2174 },
2175#endif
2176 { } /* terminator */
2177};
2178
6b75a9d8
TI		 2179static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2180 const char *quirk_override)
1da177e4 2181{
6b75a9d8
TI		 2182 struct snd_ac97_bus *pbus;
2183 struct snd_ac97_template ac97;
1da177e4
LT		 2184 int err;
2185 unsigned int i, codecs;
2186 unsigned int glob_sta = 0;
6b75a9d8
TI		 2187 struct snd_ac97_bus_ops *ops;
2188 static struct snd_ac97_bus_ops standard_bus_ops = {
1da177e4
LT		 2189 .write = snd_intel8x0_codec_write,
2190 .read = snd_intel8x0_codec_read,
2191 };
6b75a9d8 2192 static struct snd_ac97_bus_ops ali_bus_ops = {
1da177e4
LT		 2193 .write = snd_intel8x0_ali_codec_write,
2194 .read = snd_intel8x0_ali_codec_read,
2195 };
2196
2197 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
a9e99660
TI		 2198 if (!spdif_aclink) {
2199 switch (chip->device_type) {
2200 case DEVICE_NFORCE:
2201 chip->spdif_idx = NVD_SPBAR;
2202 break;
2203 case DEVICE_ALI:
2204 chip->spdif_idx = ALID_AC97SPDIFOUT;
2205 break;
2206 case DEVICE_INTEL_ICH4:
2207 chip->spdif_idx = ICHD_SPBAR;
2208 break;
2209 };
2210 }
1da177e4
LT		 2211
2212 chip->in_ac97_init = 1;
2213
2214 memset(&ac97, 0, sizeof(ac97));
2215 ac97.private_data = chip;
2216 ac97.private_free = snd_intel8x0_mixer_free_ac97;
f1a63a38 2217 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 2218 if (chip->xbox)
2219 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2220 if (chip->device_type != DEVICE_ALI) {
2221 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2222 ops = &standard_bus_ops;
84a43bd5
TI		 2223 chip->in_sdin_init = 1;
2224 codecs = 0;
2225 for (i = 0; i < chip->max_codecs; i++) {
2226 if (! (glob_sta & chip->codec_bit[i]))
2227 continue;
2228 if (chip->device_type == DEVICE_INTEL_ICH4) {
2229 snd_intel8x0_codec_read_test(chip, codecs);
2230 chip->ac97_sdin[codecs] =
2231 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
da3cec35
TI		 2232 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2233 chip->ac97_sdin[codecs] = 0;
84a43bd5
TI		 2234 } else
2235 chip->ac97_sdin[codecs] = i;
2236 codecs++;
1da177e4 2237 }
84a43bd5
TI		 2238 chip->in_sdin_init = 0;
2239 if (! codecs)
2240 codecs = 1;
1da177e4
LT		 2241 } else {
2242 ops = &ali_bus_ops;
2243 codecs = 1;
2244 /* detect the secondary codec */
2245 for (i = 0; i < 100; i++) {
2246 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2247 if (reg & 0x40) {
2248 codecs = 2;
2249 break;
2250 }
2251 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2252 udelay(1);
2253 }
2254 }
2255 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2256 goto __err;
2257 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2258 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2259 pbus->clock = ac97_clock;
2260 /* FIXME: my test board doesn't work well with VRA... */
2261 if (chip->device_type == DEVICE_ALI)
2262 pbus->no_vra = 1;
2263 else
2264 pbus->dra = 1;
2265 chip->ac97_bus = pbus;
84a43bd5 2266 chip->ncodecs = codecs;
1da177e4
LT		 2267
2268 ac97.pci = chip->pci;
2269 for (i = 0; i < codecs; i++) {
2270 ac97.num = i;
2271 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2272 if (err != -EACCES)
2273 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2274 if (i == 0)
2275 goto __err;
1da177e4
LT		 2276 }
2277 }
2278 /* tune up the primary codec */
2279 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2280 /* enable separate SDINs for ICH4 */
2281 if (chip->device_type == DEVICE_INTEL_ICH4)
2282 pbus->isdin = 1;
2283 /* find the available PCM streams */
2284 i = ARRAY_SIZE(ac97_pcm_defs);
2285 if (chip->device_type != DEVICE_INTEL_ICH4)
2286 i -= 2; /* do not allocate PCM2IN and MIC2 */
2287 if (chip->spdif_idx < 0)
2288 i--; /* do not allocate S/PDIF */
2289 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2290 if (err < 0)
2291 goto __err;
2292 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2293 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2294 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2295 if (chip->spdif_idx >= 0)
2296 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2297 if (chip->device_type == DEVICE_INTEL_ICH4) {
2298 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2299 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2300 }
2301 /* enable separate SDINs for ICH4 */
2302 if (chip->device_type == DEVICE_INTEL_ICH4) {
2303 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2304 u8 tmp = igetbyte(chip, ICHREG(SDM));
2305 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2306 if (pcm) {
2307 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2308 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2309 for (i = 1; i < 4; i++) {
2310 if (pcm->r[0].codec[i]) {
2311 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2312 break;
2313 }
2314 }
2315 } else {
2316 tmp &= ~ICH_SE; /* steer disable */
2317 }
2318 iputbyte(chip, ICHREG(SDM), tmp);
2319 }
2320 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2321 chip->multi4 = 1;
4235a317 2322 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
1da177e4 2323 chip->multi6 = 1;
4235a317
TI		 2324 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2325 chip->multi8 = 1;
2326 }
1da177e4
LT		 2327 }
2328 if (pbus->pcms[0].r[1].rslots[0]) {
2329 chip->dra = 1;
2330 }
2331 if (chip->device_type == DEVICE_INTEL_ICH4) {
2332 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2333 chip->smp20bit = 1;
2334 }
a9e99660 2335 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2336 /* 48kHz only */
2337 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2338 }
a9e99660 2339 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
1da177e4
LT		 2340 /* use slot 10/11 for SPDIF */
2341 u32 val;
2342 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2343 val |= ICH_PCM_SPDIF_1011;
2344 iputdword(chip, ICHREG(GLOB_CNT), val);
2345 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2346 }
2347 chip->in_ac97_init = 0;
2348 return 0;
2349
2350 __err:
2351 /* clear the cold-reset bit for the next chance */
2352 if (chip->device_type != DEVICE_ALI)
6b75a9d8
TI		 2353 iputdword(chip, ICHREG(GLOB_CNT),
2354 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1da177e4
LT		 2355 return err;
2356}
2357
2358
2359/*
2360 *
2361 */
2362
6b75a9d8 2363static void do_ali_reset(struct intel8x0 *chip)
1da177e4
LT		 2364{
2365 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2366 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2367 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2368 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2369 iputdword(chip, ICHREG(ALI_INTERFACECR),
d78bec21 2370 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1da177e4
LT		 2371 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2372 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2373}
2374
e3e9c5e7
TLSC		 2375#ifdef CONFIG_SND_AC97_POWER_SAVE
2376static struct snd_pci_quirk ich_chip_reset_mode[] = {
2377 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2378 { } /* end */
2379};
1da177e4 2380
e3e9c5e7
TLSC		 2381static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2382{
2383 unsigned int cnt;
1da177e4 2384 /* ACLink on, 2 channels */
e3e9c5e7
TLSC		 2385
2386 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2387 return -EIO;
2388
1da177e4
LT		 2389 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2390 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
e3e9c5e7 2391
6dbe6628
TI		 2392 /* do cold reset - the full ac97 powerdown may leave the controller
2393 * in a warm state but actually it cannot communicate with the codec.
2394 */
2395 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2396 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2397 udelay(10);
2398 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2399 msleep(1);
e3e9c5e7
TLSC		 2400 return 0;
2401}
2402#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2403 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
6dbe6628 2404#else
e1672800 2405#define snd_intel8x0_ich_chip_cold_reset(chip) 0
e3e9c5e7
TLSC		 2406#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2407#endif
2408
2409static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2410{
2411 unsigned long end_time;
2412 unsigned int cnt;
2413 /* ACLink on, 2 channels */
2414 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2415 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
1da177e4
LT		 2416 /* finish cold or do warm reset */
2417 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2418 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2419 end_time = (jiffies + (HZ / 4)) + 1;
2420 do {
2421 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
e3e9c5e7 2422 return 0;
954bea35 2423 schedule_timeout_uninterruptible(1);
1da177e4 2424 } while (time_after_eq(end_time, jiffies));
6b75a9d8
TI		 2425 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2426 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4 2427 return -EIO;
e3e9c5e7
TLSC		 2428}
2429
2430static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2431{
2432 unsigned long end_time;
2433 unsigned int status, nstatus;
2434 unsigned int cnt;
2435 int err;
2436
2437 /* put logic to right state */
2438 /* first clear status bits */
2439 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2440 if (chip->device_type == DEVICE_NFORCE)
2441 status |= ICH_NVSPINT;
2442 cnt = igetdword(chip, ICHREG(GLOB_STA));
2443 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2444
2445 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2446 err = snd_intel8x0_ich_chip_cold_reset(chip);
2447 else
2448 err = snd_intel8x0_ich_chip_reset(chip);
2449 if (err < 0)
2450 return err;
1da177e4 2451
1da177e4
LT		 2452 if (probing) {
2453 /* wait for any codec ready status.
2454 * Once it becomes ready it should remain ready
2455 * as long as we do not disable the ac97 link.
2456 */
2457 end_time = jiffies + HZ;
2458 do {
6b75a9d8 2459 status = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2460 chip->codec_isr_bits;
1da177e4
LT		 2461 if (status)
2462 break;
954bea35 2463 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2464 } while (time_after_eq(end_time, jiffies));
2465 if (! status) {
2466 /* no codec is found */
6b75a9d8
TI		 2467 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2468 igetdword(chip, ICHREG(GLOB_STA)));
1da177e4
LT		 2469 return -EIO;
2470 }
2471
1da177e4
LT		 2472 /* wait for other codecs ready status. */
2473 end_time = jiffies + HZ / 4;
84a43bd5
TI		 2474 while (status != chip->codec_isr_bits &&
2475 time_after_eq(end_time, jiffies)) {
954bea35 2476 schedule_timeout_uninterruptible(1);
84a43bd5
TI		 2477 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2478 chip->codec_isr_bits;
1da177e4
LT		 2479 }
2480
2481 } else {
2482 /* resume phase */
2483 int i;
2484 status = 0;
84a43bd5 2485 for (i = 0; i < chip->ncodecs; i++)
1da177e4 2486 if (chip->ac97[i])
84a43bd5 2487 status |= chip->codec_bit[chip->ac97_sdin[i]];
1da177e4
LT		 2488 /* wait until all the probed codecs are ready */
2489 end_time = jiffies + HZ;
2490 do {
6b75a9d8 2491 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2492 chip->codec_isr_bits;
1da177e4
LT		 2493 if (status == nstatus)
2494 break;
954bea35 2495 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2496 } while (time_after_eq(end_time, jiffies));
2497 }
2498
2499 if (chip->device_type == DEVICE_SIS) {
2500 /* unmute the output on SIS7012 */
2501 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2502 }
a9e99660 2503 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2504 /* enable SPDIF interrupt */
2505 unsigned int val;
2506 pci_read_config_dword(chip->pci, 0x4c, &val);
2507 val |= 0x1000000;
2508 pci_write_config_dword(chip->pci, 0x4c, val);
2509 }
2510 return 0;
2511}
2512
6b75a9d8 2513static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2514{
2515 u32 reg;
2516 int i = 0;
2517
2518 reg = igetdword(chip, ICHREG(ALI_SCR));
2519 if ((reg & 2) == 0) /* Cold required */
2520 reg |= 2;
2521 else
2522 reg |= 1; /* Warm */
2523 reg &= ~0x80000000; /* ACLink on */
2524 iputdword(chip, ICHREG(ALI_SCR), reg);
2525
2526 for (i = 0; i < HZ / 2; i++) {
2527 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2528 goto __ok;
954bea35 2529 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2530 }
2531 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2532 if (probing)
2533 return -EIO;
2534
2535 __ok:
2536 for (i = 0; i < HZ / 2; i++) {
2537 reg = igetdword(chip, ICHREG(ALI_RTSR));
2538 if (reg & 0x80) /* primary codec */
2539 break;
2540 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
954bea35 2541 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2542 }
2543
2544 do_ali_reset(chip);
2545 return 0;
2546}
2547
6b75a9d8 2548static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
1da177e4 2549{
253b999f 2550 unsigned int i, timeout;
1da177e4
LT		 2551 int err;
2552
2553 if (chip->device_type != DEVICE_ALI) {
2554 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2555 return err;
2556 iagetword(chip, 0); /* clear semaphore flag */
2557 } else {
2558 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2559 return err;
2560 }
2561
2562 /* disable interrupts */
2563 for (i = 0; i < chip->bdbars_count; i++)
2564 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2565 /* reset channels */
2566 for (i = 0; i < chip->bdbars_count; i++)
2567 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
253b999f
JK		 2568 for (i = 0; i < chip->bdbars_count; i++) {
2569 timeout = 100000;
2570 while (--timeout != 0) {
2571 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2572 break;
2573 }
2574 if (timeout == 0)
2575 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2576 }
1da177e4
LT		 2577 /* initialize Buffer Descriptor Lists */
2578 for (i = 0; i < chip->bdbars_count; i++)
6b75a9d8
TI		 2579 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2580 chip->ichd[i].bdbar_addr);
1da177e4
LT		 2581 return 0;
2582}
2583
6b75a9d8 2584static int snd_intel8x0_free(struct intel8x0 *chip)
1da177e4
LT		 2585{
2586 unsigned int i;
2587
2588 if (chip->irq < 0)
2589 goto __hw_end;
2590 /* disable interrupts */
2591 for (i = 0; i < chip->bdbars_count; i++)
2592 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2593 /* reset channels */
2594 for (i = 0; i < chip->bdbars_count; i++)
2595 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
a9e99660 2596 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2597 /* stop the spdif interrupt */
2598 unsigned int val;
2599 pci_read_config_dword(chip->pci, 0x4c, &val);
2600 val &= ~0x1000000;
2601 pci_write_config_dword(chip->pci, 0x4c, val);
2602 }
2603 /* --- */
f000fd80 2604
1da177e4
LT		 2605 __hw_end:
2606 if (chip->irq >= 0)
6b75a9d8 2607 free_irq(chip->irq, chip);
1da177e4
LT		 2608 if (chip->bdbars.area) {
2609 if (chip->fix_nocache)
2610 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2611 snd_dma_free_pages(&chip->bdbars);
2612 }
3388c37e
TI		 2613 if (chip->addr)
2614 pci_iounmap(chip->pci, chip->addr);
2615 if (chip->bmaddr)
2616 pci_iounmap(chip->pci, chip->bmaddr);
1da177e4
LT		 2617 pci_release_regions(chip->pci);
2618 pci_disable_device(chip->pci);
2619 kfree(chip);
2620 return 0;
2621}
2622
2623#ifdef CONFIG_PM
2624/*
2625 * power management
2626 */
68cb2b55 2627static int intel8x0_suspend(struct device *dev)
1da177e4 2628{
68cb2b55
TI		 2629 struct pci_dev *pci = to_pci_dev(dev);
2630 struct snd_card *card = dev_get_drvdata(dev);
5809c6c4 2631 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2632 int i;
2633
5809c6c4 2634 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 2635 for (i = 0; i < chip->pcm_devs; i++)
2636 snd_pcm_suspend_all(chip->pcm[i]);
2637 /* clear nocache */
2638 if (chip->fix_nocache) {
2639 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2640 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2641 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2642 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2643 if (runtime->dma_area)
2644 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2645 }
2646 }
2647 }
84a43bd5 2648 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2649 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2650 if (chip->device_type == DEVICE_INTEL_ICH4)
2651 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2652
30b35399 2653 if (chip->irq >= 0) {
6b75a9d8 2654 free_irq(chip->irq, chip);
30b35399
TI		 2655 chip->irq = -1;
2656 }
5809c6c4
TI		 2657 pci_disable_device(pci);
2658 pci_save_state(pci);
19bfafb2
TK		 2659 /* The call below may disable built-in speaker on some laptops
2660 * after S2RAM. So, don't touch it.
2661 */
68cb2b55 2662 /* pci_set_power_state(pci, PCI_D3hot); */
1da177e4
LT		 2663 return 0;
2664}
2665
68cb2b55 2666static int intel8x0_resume(struct device *dev)
1da177e4 2667{
68cb2b55
TI		 2668 struct pci_dev *pci = to_pci_dev(dev);
2669 struct snd_card *card = dev_get_drvdata(dev);
5809c6c4 2670 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2671 int i;
2672
30b35399 2673 pci_set_power_state(pci, PCI_D0);
5809c6c4 2674 pci_restore_state(pci);
30b35399
TI		 2675 if (pci_enable_device(pci) < 0) {
2676 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2677 "disabling device\n");
2678 snd_card_disconnect(card);
2679 return -EIO;
2680 }
5809c6c4 2681 pci_set_master(pci);
2078f38c 2682 snd_intel8x0_chip_init(chip, 0);
30b35399 2683 if (request_irq(pci->irq, snd_intel8x0_interrupt,
934c2b6d 2684 IRQF_SHARED, KBUILD_MODNAME, chip)) {
30b35399
TI		 2685 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2686 "disabling device\n", pci->irq);
2687 snd_card_disconnect(card);
2688 return -EIO;
2689 }
5809c6c4 2690 chip->irq = pci->irq;
90158b83 2691 synchronize_irq(chip->irq);
1da177e4 2692
52b72388 2693 /* re-initialize mixer stuff */
a9e99660 2694 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
52b72388
TI		 2695 /* enable separate SDINs for ICH4 */
2696 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2697 /* use slot 10/11 for SPDIF */
2698 iputdword(chip, ICHREG(GLOB_CNT),
2699 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2700 ICH_PCM_SPDIF_1011);
2701 }
2702
1da177e4
LT		 2703 /* refill nocache */
2704 if (chip->fix_nocache)
2705 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2706
84a43bd5 2707 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2708 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 2709
2710 /* refill nocache */
2711 if (chip->fix_nocache) {
2712 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2713 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2714 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2715 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2716 if (runtime->dma_area)
2717 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2718 }
2719 }
2720 }
2721
1cfe43d2
TI		 2722 /* resume status */
2723 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2724 struct ichdev *ichdev = &chip->ichd[i];
1cfe43d2
TI		 2725 unsigned long port = ichdev->reg_offset;
2726 if (! ichdev->substream || ! ichdev->suspended)
2727 continue;
2728 if (ichdev->ichd == ICHD_PCMOUT)
2729 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2730 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2731 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2732 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2733 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2734 }
2735
5809c6c4 2736 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2737 return 0;
2738}
68cb2b55
TI		 2739
2740static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2741#define INTEL8X0_PM_OPS &intel8x0_pm
2742#else
2743#define INTEL8X0_PM_OPS NULL
1da177e4
LT		 2744#endif /* CONFIG_PM */
2745
2746#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2747
6b75a9d8 2748static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
1da177e4 2749{
6b75a9d8
TI		 2750 struct snd_pcm_substream *subs;
2751 struct ichdev *ichdev;
1da177e4 2752 unsigned long port;
920e4ae3 2753 unsigned long pos, pos1, t;
2ec775e7 2754 int civ, timeout = 1000, attempt = 1;
920e4ae3 2755 struct timespec start_time, stop_time;
1da177e4
LT		 2756
2757 if (chip->ac97_bus->clock != 48000)
2758 return; /* specified in module option */
2759
2ec775e7 2760 __again:
1da177e4
LT		 2761 subs = chip->pcm[0]->streams[0].substream;
2762 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
99b359ba 2763 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
1da177e4
LT		 2764 return;
2765 }
2766 ichdev = &chip->ichd[ICHD_PCMOUT];
2767 ichdev->physbuf = subs->dma_buffer.addr;
29dab4fd 2768 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
1da177e4
LT		 2769 ichdev->substream = NULL; /* don't process interrupts */
2770
2771 /* set rate */
2772 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2773 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2774 return;
2775 }
2776 snd_intel8x0_setup_periods(chip, ichdev);
2777 port = ichdev->reg_offset;
2778 spin_lock_irq(&chip->reg_lock);
2779 chip->in_measurement = 1;
2780 /* trigger */
2781 if (chip->device_type != DEVICE_ALI)
2782 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2783 else {
2784 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2785 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2786 }
920e4ae3 2787 do_posix_clock_monotonic_gettime(&start_time);
1da177e4 2788 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2789 msleep(50);
1da177e4
LT		 2790 spin_lock_irq(&chip->reg_lock);
2791 /* check the position */
920e4ae3
JK		 2792 do {
2793 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2794 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2795 if (pos1 == 0) {
2796 udelay(10);
2797 continue;
2798 }
2799 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2800 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2801 break;
2802 } while (timeout--);
da2436a2
JK		 2803 if (pos1 == 0) { /* oops, this value is not reliable */
2804 pos = 0;
2805 } else {
2806 pos = ichdev->fragsize1;
2807 pos -= pos1 << ichdev->pos_shift;
2808 pos += ichdev->position;
2809 }
1da177e4 2810 chip->in_measurement = 0;
920e4ae3 2811 do_posix_clock_monotonic_gettime(&stop_time);
1da177e4
LT		 2812 /* stop */
2813 if (chip->device_type == DEVICE_ALI) {
d78bec21 2814 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
1da177e4
LT		 2815 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2816 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2817 ;
2818 } else {
2819 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2820 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2821 ;
2822 }
2823 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2824 spin_unlock_irq(&chip->reg_lock);
2825
da2436a2
JK		 2826 if (pos == 0) {
2827 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2ec775e7 2828 __retry:
30fd9940
JK		 2829 if (attempt < 3) {
2830 msleep(300);
2ec775e7
JK		 2831 attempt++;
2832 goto __again;
2833 }
30fd9940 2834 goto __end;
da2436a2
JK		 2835 }
2836
920e4ae3 2837 pos /= 4;
1da177e4
LT		 2838 t = stop_time.tv_sec - start_time.tv_sec;
2839 t *= 1000000;
920e4ae3
JK		 2840 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2841 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
1da177e4 2842 if (t == 0) {
920e4ae3 2843 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2ec775e7 2844 goto __retry;
1da177e4 2845 }
920e4ae3 2846 pos *= 1000;
1da177e4 2847 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2ec775e7 2848 if (pos < 40000 || pos >= 60000) {
1da177e4
LT		 2849 /* abnormal value. hw problem? */
2850 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2ec775e7
JK		 2851 goto __retry;
2852 } else if (pos > 40500 && pos < 41500)
920e4ae3
JK		 2853 /* first exception - 41000Hz reference clock */
2854 chip->ac97_bus->clock = 41000;
29dab4fd 2855 else if (pos > 43600 && pos < 44600)
920e4ae3
JK		 2856 /* second exception - 44100HZ reference clock */
2857 chip->ac97_bus->clock = 44100;
1da177e4
LT		 2858 else if (pos < 47500 || pos > 48500)
2859 /* not 48000Hz, tuning the clock.. */
2860 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
30fd9940 2861 __end:
1da177e4 2862 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
6dbe6628 2863 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
1da177e4
LT		 2864}
2865
d695e4ea
TI		 2866static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2867 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2868 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2869 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
78fad343 2870 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
d695e4ea
TI		 2871 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2872 { } /* terminator */
2b3b5485
JK		 2873};
2874
2875static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2876{
2877 struct pci_dev *pci = chip->pci;
d695e4ea
TI		 2878 const struct snd_pci_quirk *wl;
2879
2880 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2881 if (!wl)
2882 return 0;
2883 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2884 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2885 chip->ac97_bus->clock = wl->value;
2886 return 1;
2b3b5485
JK		 2887}
2888
adf1b3d2 2889#ifdef CONFIG_PROC_FS
6b75a9d8
TI		 2890static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2891 struct snd_info_buffer *buffer)
1da177e4 2892{
6b75a9d8 2893 struct intel8x0 *chip = entry->private_data;
1da177e4
LT		 2894 unsigned int tmp;
2895
2896 snd_iprintf(buffer, "Intel8x0\n\n");
2897 if (chip->device_type == DEVICE_ALI)
2898 return;
2899 tmp = igetdword(chip, ICHREG(GLOB_STA));
2900 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2901 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2902 if (chip->device_type == DEVICE_INTEL_ICH4)
2903 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
84a43bd5
TI		 2904 snd_iprintf(buffer, "AC'97 codecs ready :");
2905 if (tmp & chip->codec_isr_bits) {
2906 int i;
2907 static const char *codecs[3] = {
2908 "primary", "secondary", "tertiary"
2909 };
2910 for (i = 0; i < chip->max_codecs; i++)
2911 if (tmp & chip->codec_bit[i])
2912 snd_iprintf(buffer, " %s", codecs[i]);
2913 } else
2914 snd_iprintf(buffer, " none");
2915 snd_iprintf(buffer, "\n");
2916 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2917 chip->device_type == DEVICE_SIS)
1da177e4
LT		 2918 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2919 chip->ac97_sdin[0],
2920 chip->ac97_sdin[1],
2921 chip->ac97_sdin[2]);
2922}
2923
6b75a9d8 2924static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
1da177e4 2925{
6b75a9d8 2926 struct snd_info_entry *entry;
1da177e4
LT		 2927
2928 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
bf850204 2929 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
1da177e4 2930}
adf1b3d2
TI		 2931#else
2932#define snd_intel8x0_proc_init(x)
2933#endif
1da177e4 2934
6b75a9d8 2935static int snd_intel8x0_dev_free(struct snd_device *device)
1da177e4 2936{
6b75a9d8 2937 struct intel8x0 *chip = device->device_data;
1da177e4
LT		 2938 return snd_intel8x0_free(chip);
2939}
2940
2941struct ich_reg_info {
2942 unsigned int int_sta_mask;
2943 unsigned int offset;
2944};
2945
84a43bd5
TI		 2946static unsigned int ich_codec_bits[3] = {
2947 ICH_PCR, ICH_SCR, ICH_TCR
2948};
2949static unsigned int sis_codec_bits[3] = {
2950 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2951};
2952
7fb4f392 2953static int __devinit snd_intel8x0_inside_vm(struct pci_dev *pci)
65c397d6 2954{
7fb4f392
KO		 2955 int result = inside_vm;
2956 char *msg = NULL;
65c397d6 2957
7fb4f392
KO		 2958 /* check module parameter first (override detection) */
2959 if (result >= 0) {
2960 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2961 goto fini;
2962 }
2963
2964 /* detect KVM and Parallels virtual environments */
2965 result = kvm_para_available();
2966#ifdef X86_FEATURE_HYPERVISOR
2967 result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR);
65c397d6 2968#endif
7fb4f392
KO		 2969 if (!result)
2970 goto fini;
2971
2972 /* check for known (emulated) devices */
2973 if (pci->subsystem_vendor == 0x1af4 &&
2974 pci->subsystem_device == 0x1100) {
2975 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2976 msg = "enable KVM";
2977 } else if (pci->subsystem_vendor == 0x1ab8) {
2978 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2979 msg = "enable Parallels VM";
2980 } else {
2981 msg = "disable (unknown or VT-d) VM";
2982 result = 0;
65c397d6
KO		 2983 }
2984
7fb4f392
KO		 2985fini:
2986 if (msg != NULL)
2987 printk(KERN_INFO "intel8x0: %s optimization\n", msg);
65c397d6
KO		 2988
2989 return result;
2990}
2991
6b75a9d8 2992static int __devinit snd_intel8x0_create(struct snd_card *card,
1da177e4
LT		 2993 struct pci_dev *pci,
2994 unsigned long device_type,
6b75a9d8 2995 struct intel8x0 ** r_intel8x0)
1da177e4 2996{
6b75a9d8 2997 struct intel8x0 *chip;
1da177e4
LT		 2998 int err;
2999 unsigned int i;
3000 unsigned int int_sta_masks;
6b75a9d8
TI		 3001 struct ichdev *ichdev;
3002 static struct snd_device_ops ops = {
1da177e4
LT		 3003 .dev_free = snd_intel8x0_dev_free,
3004 };
3005
3006 static unsigned int bdbars[] = {
3007 3, /* DEVICE_INTEL */
3008 6, /* DEVICE_INTEL_ICH4 */
3009 3, /* DEVICE_SIS */
3010 6, /* DEVICE_ALI */
3011 4, /* DEVICE_NFORCE */
3012 };
3013 static struct ich_reg_info intel_regs[6] = {
3014 { ICH_PIINT, 0 },
3015 { ICH_POINT, 0x10 },
3016 { ICH_MCINT, 0x20 },
3017 { ICH_M2INT, 0x40 },
3018 { ICH_P2INT, 0x50 },
3019 { ICH_SPINT, 0x60 },
3020 };
3021 static struct ich_reg_info nforce_regs[4] = {
3022 { ICH_PIINT, 0 },
3023 { ICH_POINT, 0x10 },
3024 { ICH_MCINT, 0x20 },
3025 { ICH_NVSPINT, 0x70 },
3026 };
3027 static struct ich_reg_info ali_regs[6] = {
3028 { ALI_INT_PCMIN, 0x40 },
3029 { ALI_INT_PCMOUT, 0x50 },
3030 { ALI_INT_MICIN, 0x60 },
3031 { ALI_INT_CODECSPDIFOUT, 0x70 },
3032 { ALI_INT_SPDIFIN, 0xa0 },
3033 { ALI_INT_SPDIFOUT, 0xb0 },
3034 };
3035 struct ich_reg_info *tbl;
3036
3037 *r_intel8x0 = NULL;
3038
3039 if ((err = pci_enable_device(pci)) < 0)
3040 return err;
3041
e560d8d8 3042 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 3043 if (chip == NULL) {
3044 pci_disable_device(pci);
3045 return -ENOMEM;
3046 }
3047 spin_lock_init(&chip->reg_lock);
3048 chip->device_type = device_type;
3049 chip->card = card;
3050 chip->pci = pci;
3051 chip->irq = -1;
c829b052
TI		 3052
3053 /* module parameters */
3054 chip->buggy_irq = buggy_irq;
3055 chip->buggy_semaphore = buggy_semaphore;
3056 if (xbox)
3057 chip->xbox = 1;
1da177e4 3058
7fb4f392 3059 chip->inside_vm = snd_intel8x0_inside_vm(pci);
228cf793 3060
1da177e4
LT		 3061 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3062 pci->device == PCI_DEVICE_ID_INTEL_440MX)
3063 chip->fix_nocache = 1; /* enable workaround */
3064
1da177e4
LT		 3065 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3066 kfree(chip);
3067 pci_disable_device(pci);
3068 return err;
3069 }
3070
3071 if (device_type == DEVICE_ALI) {
3072 /* ALI5455 has no ac97 region */
3388c37e 3073 chip->bmaddr = pci_iomap(pci, 0, 0);
1da177e4
LT		 3074 goto port_inited;
3075 }
3076
3388c37e
TI		 3077 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3078 chip->addr = pci_iomap(pci, 2, 0);
3079 else
3080 chip->addr = pci_iomap(pci, 0, 0);
3081 if (!chip->addr) {
3082 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
3083 snd_intel8x0_free(chip);
3084 return -EIO;
3085 }
3086 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3087 chip->bmaddr = pci_iomap(pci, 3, 0);
3088 else
3089 chip->bmaddr = pci_iomap(pci, 1, 0);
3090 if (!chip->bmaddr) {
3091 snd_printk(KERN_ERR "Controller space ioremap problem\n");
3092 snd_intel8x0_free(chip);
3093 return -EIO;
1da177e4
LT		 3094 }
3095
3096 port_inited:
1da177e4
LT		 3097 chip->bdbars_count = bdbars[device_type];
3098
3099 /* initialize offsets */
3100 switch (device_type) {
3101 case DEVICE_NFORCE:
3102 tbl = nforce_regs;
3103 break;
3104 case DEVICE_ALI:
3105 tbl = ali_regs;
3106 break;
3107 default:
3108 tbl = intel_regs;
3109 break;
3110 }
3111 for (i = 0; i < chip->bdbars_count; i++) {
3112 ichdev = &chip->ichd[i];
3113 ichdev->ichd = i;
3114 ichdev->reg_offset = tbl[i].offset;
3115 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3116 if (device_type == DEVICE_SIS) {
3117 /* SiS 7012 swaps the registers */
3118 ichdev->roff_sr = ICH_REG_OFF_PICB;
3119 ichdev->roff_picb = ICH_REG_OFF_SR;
3120 } else {
3121 ichdev->roff_sr = ICH_REG_OFF_SR;
3122 ichdev->roff_picb = ICH_REG_OFF_PICB;
3123 }
3124 if (device_type == DEVICE_ALI)
3125 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3126 /* SIS7012 handles the pcm data in bytes, others are in samples */
3127 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3128 }
3129
3130 /* allocate buffer descriptor lists */
3131 /* the start of each lists must be aligned to 8 bytes */
3132 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3133 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3134 &chip->bdbars) < 0) {
3135 snd_intel8x0_free(chip);
3136 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3137 return -ENOMEM;
3138 }
3139 /* tables must be aligned to 8 bytes here, but the kernel pages
3140 are much bigger, so we don't care (on i386) */
3141 /* workaround for 440MX */
3142 if (chip->fix_nocache)
3143 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3144 int_sta_masks = 0;
3145 for (i = 0; i < chip->bdbars_count; i++) {
3146 ichdev = &chip->ichd[i];
beef08a5
TI		 3147 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3148 (i * ICH_MAX_FRAGS * 2);
3149 ichdev->bdbar_addr = chip->bdbars.addr +
3150 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1da177e4
LT		 3151 int_sta_masks |= ichdev->int_sta_mask;
3152 }
beef08a5
TI		 3153 chip->int_sta_reg = device_type == DEVICE_ALI ?
3154 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
1da177e4
LT		 3155 chip->int_sta_mask = int_sta_masks;
3156
beef08a5 3157 pci_set_master(pci);
beef08a5 3158
84a43bd5
TI		 3159 switch(chip->device_type) {
3160 case DEVICE_INTEL_ICH4:
3161 /* ICH4 can have three codecs */
3162 chip->max_codecs = 3;
3163 chip->codec_bit = ich_codec_bits;
3164 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3165 break;
3166 case DEVICE_SIS:
3167 /* recent SIS7012 can have three codecs */
3168 chip->max_codecs = 3;
3169 chip->codec_bit = sis_codec_bits;
3170 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3171 break;
3172 default:
3173 /* others up to two codecs */
3174 chip->max_codecs = 2;
3175 chip->codec_bit = ich_codec_bits;
3176 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3177 break;
3178 }
3179 for (i = 0; i < chip->max_codecs; i++)
3180 chip->codec_isr_bits |= chip->codec_bit[i];
3181
1da177e4
LT		 3182 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3183 snd_intel8x0_free(chip);
3184 return err;
3185 }
3186
2078f38c
TI		 3187 /* request irq after initializaing int_sta_mask, etc */
3188 if (request_irq(pci->irq, snd_intel8x0_interrupt,
934c2b6d 3189 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2078f38c
TI		 3190 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3191 snd_intel8x0_free(chip);
3192 return -EBUSY;
3193 }
3194 chip->irq = pci->irq;
3195
1da177e4
LT		 3196 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3197 snd_intel8x0_free(chip);
3198 return err;
3199 }
3200
3201 snd_card_set_dev(card, &pci->dev);
3202
3203 *r_intel8x0 = chip;
3204 return 0;
3205}
3206
3207static struct shortname_table {
3208 unsigned int id;
3209 const char *s;
3210} shortnames[] __devinitdata = {
8cdfd251
TI		 3211 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3212 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3213 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 3214 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 3215 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3216 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3217 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 3218 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3219 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3220 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 3221 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 3222 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 3223 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 3224 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3225 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3226 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3227 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3228 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3229 { 0x003a, "NVidia MCP04" },
3230 { 0x746d, "AMD AMD8111" },
3231 { 0x7445, "AMD AMD768" },
3232 { 0x5455, "ALi M5455" },
3233 { 0, NULL },
3234};
3235
a9e99660
TI		 3236static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3237 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3238 { } /* end */
3239};
3240
3241/* look up white/black list for SPDIF over ac-link */
3242static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3243{
3244 const struct snd_pci_quirk *w;
3245
3246 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3247 if (w) {
3248 if (w->value)
3249 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3250 "AC-Link for %s\n", w->name);
3251 else
3252 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3253 "SPDIF DMA for %s\n", w->name);
3254 return w->value;
3255 }
3256 return 0;
3257}
3258
1da177e4
LT		 3259static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3260 const struct pci_device_id *pci_id)
3261{
6b75a9d8
TI		 3262 struct snd_card *card;
3263 struct intel8x0 *chip;
1da177e4
LT		 3264 int err;
3265 struct shortname_table *name;
3266
e58de7ba
TI		 3267 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3268 if (err < 0)
3269 return err;
1da177e4 3270
a9e99660
TI		 3271 if (spdif_aclink < 0)
3272 spdif_aclink = check_default_spdif_aclink(pci);
3273
3274 strcpy(card->driver, "ICH");
3275 if (!spdif_aclink) {
3276 switch (pci_id->driver_data) {
3277 case DEVICE_NFORCE:
3278 strcpy(card->driver, "NFORCE");
3279 break;
3280 case DEVICE_INTEL_ICH4:
3281 strcpy(card->driver, "ICH4");
3282 }
1da177e4
LT		 3283 }
3284
3285 strcpy(card->shortname, "Intel ICH");
3286 for (name = shortnames; name->id; name++) {
3287 if (pci->device == name->id) {
3288 strcpy(card->shortname, name->s);
3289 break;
3290 }
3291 }
3292
beef08a5
TI		 3293 if (buggy_irq < 0) {
3294 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3295 * Needs to return IRQ_HANDLED for unknown irqs.
3296 */
3297 if (pci_id->driver_data == DEVICE_NFORCE)
3298 buggy_irq = 1;
3299 else
3300 buggy_irq = 0;
3301 }
3302
a06147d2 3303 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
c829b052 3304 &chip)) < 0) {
1da177e4
LT		 3305 snd_card_free(card);
3306 return err;
3307 }
5809c6c4 3308 card->private_data = chip;
1da177e4 3309
b7fe4622 3310 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
1da177e4
LT		 3311 snd_card_free(card);
3312 return err;
3313 }
3314 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3315 snd_card_free(card);
3316 return err;
3317 }
3318
3319 snd_intel8x0_proc_init(chip);
3320
3321 snprintf(card->longname, sizeof(card->longname),
3388c37e
TI		 3322 "%s with %s at irq %i", card->shortname,
3323 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
1da177e4 3324
2b3b5485
JK		 3325 if (ac97_clock == 0 || ac97_clock == 1) {
3326 if (ac97_clock == 0) {
3327 if (intel8x0_in_clock_list(chip) == 0)
3328 intel8x0_measure_ac97_clock(chip);
3329 } else {
3330 intel8x0_measure_ac97_clock(chip);
3331 }
3332 }
1da177e4
LT		 3333
3334 if ((err = snd_card_register(card)) < 0) {
3335 snd_card_free(card);
3336 return err;
3337 }
3338 pci_set_drvdata(pci, card);
1da177e4
LT		 3339 return 0;
3340}
3341
3342static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3343{
3344 snd_card_free(pci_get_drvdata(pci));
3345 pci_set_drvdata(pci, NULL);
3346}
3347
e9f66d9b 3348static struct pci_driver intel8x0_driver = {
3733e424 3349 .name = KBUILD_MODNAME,
1da177e4
LT		 3350 .id_table = snd_intel8x0_ids,
3351 .probe = snd_intel8x0_probe,
3352 .remove = __devexit_p(snd_intel8x0_remove),
68cb2b55
TI		 3353 .driver = {
3354 .pm = INTEL8X0_PM_OPS,
3355 },
1da177e4
LT		 3356};
3357
e9f66d9b 3358module_pci_driver(intel8x0_driver);
Linux kernel - Deliverables
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