Commit | Line | Data |
---|---|---|
d0ce9946 | 1 | /* |
873591db | 2 | * C-Media CMI8788 driver for C-Media's reference design and similar models |
d0ce9946 CL |
3 | * |
4 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
5 | * | |
6 | * | |
7 | * This driver is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License, version 2. | |
9 | * | |
10 | * This driver is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this driver; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | /* | |
dc0adf48 CL |
21 | * CMI8788: |
22 | * | |
de664936 CL |
23 | * SPI 0 -> 1st AK4396 (front) |
24 | * SPI 1 -> 2nd AK4396 (surround) | |
25 | * SPI 2 -> 3rd AK4396 (center/LFE) | |
26 | * SPI 3 -> WM8785 | |
27 | * SPI 4 -> 4th AK4396 (back) | |
d0ce9946 | 28 | * |
de664936 CL |
29 | * GPIO 0 -> DFS0 of AK5385 |
30 | * GPIO 1 -> DFS1 of AK5385 | |
64878dfb CL |
31 | * |
32 | * X-Meridian models: | |
33 | * GPIO 4 -> enable extension S/PDIF input | |
34 | * GPIO 6 -> enable on-board S/PDIF input | |
35 | * | |
36 | * Claro models: | |
d1d7093f | 37 | * GPIO 6 -> S/PDIF from optical (0) or coaxial (1) input |
64878dfb | 38 | * GPIO 8 -> enable headphone amplifier |
dc0adf48 CL |
39 | * |
40 | * CM9780: | |
41 | * | |
de664936 CL |
42 | * LINE_OUT -> input of ADC |
43 | * | |
44 | * AUX_IN <- aux | |
45 | * CD_IN <- CD | |
46 | * MIC_IN <- mic | |
47 | * | |
48 | * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input | |
d0ce9946 CL |
49 | */ |
50 | ||
df91bc23 | 51 | #include <linux/delay.h> |
902b05c1 | 52 | #include <linux/mutex.h> |
d0ce9946 | 53 | #include <linux/pci.h> |
da155d5b | 54 | #include <linux/module.h> |
902b05c1 | 55 | #include <sound/ac97_codec.h> |
ccc80fb4 | 56 | #include <sound/control.h> |
d0ce9946 | 57 | #include <sound/core.h> |
9719fcaa | 58 | #include <sound/info.h> |
d0ce9946 CL |
59 | #include <sound/initval.h> |
60 | #include <sound/pcm.h> | |
61 | #include <sound/pcm_params.h> | |
62 | #include <sound/tlv.h> | |
63 | #include "oxygen.h" | |
66410bfd | 64 | #include "xonar_dg.h" |
c626026d | 65 | #include "ak4396.h" |
f5b2368b | 66 | #include "wm8785.h" |
d0ce9946 CL |
67 | |
68 | MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); | |
69 | MODULE_DESCRIPTION("C-Media CMI8788 driver"); | |
d023dc0a | 70 | MODULE_LICENSE("GPL v2"); |
66410bfd CL |
71 | MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8786}" |
72 | ",{C-Media,CMI8787}" | |
73 | ",{C-Media,CMI8788}}"); | |
d0ce9946 CL |
74 | |
75 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; | |
76 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
a67ff6a5 | 77 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
d0ce9946 CL |
78 | |
79 | module_param_array(index, int, NULL, 0444); | |
80 | MODULE_PARM_DESC(index, "card index"); | |
81 | module_param_array(id, charp, NULL, 0444); | |
82 | MODULE_PARM_DESC(id, "ID string"); | |
83 | module_param_array(enable, bool, NULL, 0444); | |
84 | MODULE_PARM_DESC(enable, "enable card"); | |
85 | ||
2f1b0ec7 | 86 | enum { |
18f24839 CL |
87 | MODEL_CMEDIA_REF, |
88 | MODEL_MERIDIAN, | |
a4b16969 | 89 | MODEL_MERIDIAN_2G, |
18f24839 CL |
90 | MODEL_CLARO, |
91 | MODEL_CLARO_HALO, | |
2146dcfd | 92 | MODEL_FANTASIA, |
a4b16969 | 93 | MODEL_SERENADE, |
2146dcfd | 94 | MODEL_2CH_OUTPUT, |
a4b16969 | 95 | MODEL_HG2PCI, |
66410bfd | 96 | MODEL_XONAR_DG, |
2f1b0ec7 CL |
97 | }; |
98 | ||
cebe41d4 | 99 | static DEFINE_PCI_DEVICE_TABLE(oxygen_ids) = { |
18f24839 | 100 | /* C-Media's reference design */ |
2f1b0ec7 | 101 | { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF }, |
8c50b759 | 102 | { OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF }, |
2f1b0ec7 CL |
103 | { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF }, |
104 | { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF }, | |
105 | { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF }, | |
106 | { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF }, | |
107 | { OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF }, | |
108 | { OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF }, | |
18f24839 | 109 | { OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF }, |
66410bfd CL |
110 | /* Asus Xonar DG */ |
111 | { OXYGEN_PCI_SUBID(0x1043, 0x8467), .driver_data = MODEL_XONAR_DG }, | |
8c50b759 CL |
112 | /* PCI 2.0 HD Audio */ |
113 | { OXYGEN_PCI_SUBID(0x13f6, 0x8782), .driver_data = MODEL_2CH_OUTPUT }, | |
18f24839 | 114 | /* Kuroutoshikou CMI8787-HG2PCI */ |
a4b16969 | 115 | { OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_HG2PCI }, |
18f24839 | 116 | /* TempoTec HiFier Fantasia */ |
2146dcfd CL |
117 | { OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA }, |
118 | /* TempoTec HiFier Serenade */ | |
a4b16969 | 119 | { OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_SERENADE }, |
18f24839 | 120 | /* AuzenTech X-Meridian */ |
2f1b0ec7 | 121 | { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN }, |
8443d2eb | 122 | /* AuzenTech X-Meridian 2G */ |
a4b16969 | 123 | { OXYGEN_PCI_SUBID(0x5431, 0x017a), .driver_data = MODEL_MERIDIAN_2G }, |
18f24839 | 124 | /* HT-Omega Claro */ |
873591db | 125 | { OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO }, |
18f24839 | 126 | /* HT-Omega Claro halo */ |
873591db | 127 | { OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO }, |
d0ce9946 CL |
128 | { } |
129 | }; | |
130 | MODULE_DEVICE_TABLE(pci, oxygen_ids); | |
131 | ||
878ac3ee CL |
132 | |
133 | #define GPIO_AK5385_DFS_MASK 0x0003 | |
134 | #define GPIO_AK5385_DFS_NORMAL 0x0000 | |
135 | #define GPIO_AK5385_DFS_DOUBLE 0x0001 | |
136 | #define GPIO_AK5385_DFS_QUAD 0x0002 | |
137 | ||
64878dfb CL |
138 | #define GPIO_MERIDIAN_DIG_MASK 0x0050 |
139 | #define GPIO_MERIDIAN_DIG_EXT 0x0010 | |
140 | #define GPIO_MERIDIAN_DIG_BOARD 0x0040 | |
141 | ||
d1d7093f | 142 | #define GPIO_CLARO_DIG_COAX 0x0040 |
873591db CL |
143 | #define GPIO_CLARO_HP 0x0100 |
144 | ||
7ef37cd9 | 145 | struct generic_data { |
45c1de8e | 146 | unsigned int dacs; |
6f0de3ce | 147 | u8 ak4396_regs[4][5]; |
1ff04886 | 148 | u16 wm8785_regs[3]; |
7ef37cd9 CL |
149 | }; |
150 | ||
d0ce9946 CL |
151 | static void ak4396_write(struct oxygen *chip, unsigned int codec, |
152 | u8 reg, u8 value) | |
153 | { | |
154 | /* maps ALSA channel pair number to SPI output */ | |
155 | static const u8 codec_spi_map[4] = { | |
7113e958 | 156 | 0, 1, 2, 4 |
d0ce9946 | 157 | }; |
6f0de3ce CL |
158 | struct generic_data *data = chip->model_data; |
159 | ||
c2353a08 | 160 | oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | |
d0ce9946 | 161 | OXYGEN_SPI_DATA_LENGTH_2 | |
2ea85986 | 162 | OXYGEN_SPI_CLOCK_160 | |
d0ce9946 | 163 | (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | |
c2353a08 | 164 | OXYGEN_SPI_CEN_LATCH_CLOCK_HI, |
d0ce9946 | 165 | AK4396_WRITE | (reg << 8) | value); |
6f0de3ce CL |
166 | data->ak4396_regs[codec][reg] = value; |
167 | } | |
168 | ||
169 | static void ak4396_write_cached(struct oxygen *chip, unsigned int codec, | |
170 | u8 reg, u8 value) | |
171 | { | |
172 | struct generic_data *data = chip->model_data; | |
173 | ||
174 | if (value != data->ak4396_regs[codec][reg]) | |
175 | ak4396_write(chip, codec, reg, value); | |
d0ce9946 CL |
176 | } |
177 | ||
178 | static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value) | |
179 | { | |
e58aee95 CL |
180 | struct generic_data *data = chip->model_data; |
181 | ||
c2353a08 | 182 | oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | |
d0ce9946 | 183 | OXYGEN_SPI_DATA_LENGTH_2 | |
2ea85986 | 184 | OXYGEN_SPI_CLOCK_160 | |
c2353a08 CL |
185 | (3 << OXYGEN_SPI_CODEC_SHIFT) | |
186 | OXYGEN_SPI_CEN_LATCH_CLOCK_LO, | |
d0ce9946 | 187 | (reg << 9) | value); |
6f0de3ce CL |
188 | if (reg < ARRAY_SIZE(data->wm8785_regs)) |
189 | data->wm8785_regs[reg] = value; | |
bbbfb552 CL |
190 | } |
191 | ||
75146fc0 | 192 | static void ak4396_registers_init(struct oxygen *chip) |
d0ce9946 | 193 | { |
7ef37cd9 | 194 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
195 | unsigned int i; |
196 | ||
45c1de8e | 197 | for (i = 0; i < data->dacs; ++i) { |
6f0de3ce CL |
198 | ak4396_write(chip, i, AK4396_CONTROL_1, |
199 | AK4396_DIF_24_MSB | AK4396_RSTN); | |
200 | ak4396_write(chip, i, AK4396_CONTROL_2, | |
201 | data->ak4396_regs[0][AK4396_CONTROL_2]); | |
202 | ak4396_write(chip, i, AK4396_CONTROL_3, | |
203 | AK4396_PCM); | |
204 | ak4396_write(chip, i, AK4396_LCH_ATT, | |
205 | chip->dac_volume[i * 2]); | |
206 | ak4396_write(chip, i, AK4396_RCH_ATT, | |
207 | chip->dac_volume[i * 2 + 1]); | |
d0ce9946 | 208 | } |
75146fc0 CL |
209 | } |
210 | ||
211 | static void ak4396_init(struct oxygen *chip) | |
212 | { | |
213 | struct generic_data *data = chip->model_data; | |
214 | ||
1f4d7be7 | 215 | data->dacs = chip->model.dac_channels_pcm / 2; |
6f0de3ce CL |
216 | data->ak4396_regs[0][AK4396_CONTROL_2] = |
217 | AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL; | |
75146fc0 | 218 | ak4396_registers_init(chip); |
d0ce9946 CL |
219 | snd_component_add(chip->card, "AK4396"); |
220 | } | |
221 | ||
222 | static void ak5385_init(struct oxygen *chip) | |
223 | { | |
878ac3ee CL |
224 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK); |
225 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK); | |
d0ce9946 CL |
226 | snd_component_add(chip->card, "AK5385"); |
227 | } | |
228 | ||
75146fc0 | 229 | static void wm8785_registers_init(struct oxygen *chip) |
d0ce9946 | 230 | { |
e58aee95 CL |
231 | struct generic_data *data = chip->model_data; |
232 | ||
878ac3ee | 233 | wm8785_write(chip, WM8785_R7, 0); |
6f0de3ce | 234 | wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]); |
1ff04886 | 235 | wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]); |
75146fc0 | 236 | } |
e58aee95 | 237 | |
75146fc0 CL |
238 | static void wm8785_init(struct oxygen *chip) |
239 | { | |
240 | struct generic_data *data = chip->model_data; | |
241 | ||
6f0de3ce CL |
242 | data->wm8785_regs[0] = |
243 | WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST; | |
1ff04886 | 244 | data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL; |
75146fc0 | 245 | wm8785_registers_init(chip); |
d0ce9946 CL |
246 | snd_component_add(chip->card, "WM8785"); |
247 | } | |
248 | ||
249 | static void generic_init(struct oxygen *chip) | |
250 | { | |
251 | ak4396_init(chip); | |
252 | wm8785_init(chip); | |
253 | } | |
254 | ||
255 | static void meridian_init(struct oxygen *chip) | |
256 | { | |
64878dfb CL |
257 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, |
258 | GPIO_MERIDIAN_DIG_MASK); | |
259 | oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, | |
260 | GPIO_MERIDIAN_DIG_BOARD, GPIO_MERIDIAN_DIG_MASK); | |
d0ce9946 CL |
261 | ak4396_init(chip); |
262 | ak5385_init(chip); | |
263 | } | |
264 | ||
873591db CL |
265 | static void claro_enable_hp(struct oxygen *chip) |
266 | { | |
267 | msleep(300); | |
268 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP); | |
269 | oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP); | |
270 | } | |
271 | ||
272 | static void claro_init(struct oxygen *chip) | |
273 | { | |
d1d7093f CL |
274 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX); |
275 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX); | |
873591db CL |
276 | ak4396_init(chip); |
277 | wm8785_init(chip); | |
278 | claro_enable_hp(chip); | |
279 | } | |
280 | ||
281 | static void claro_halo_init(struct oxygen *chip) | |
d91b424d | 282 | { |
d1d7093f CL |
283 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX); |
284 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX); | |
d91b424d CL |
285 | ak4396_init(chip); |
286 | ak5385_init(chip); | |
873591db | 287 | claro_enable_hp(chip); |
d91b424d CL |
288 | } |
289 | ||
2146dcfd | 290 | static void fantasia_init(struct oxygen *chip) |
45c1de8e CL |
291 | { |
292 | ak4396_init(chip); | |
293 | snd_component_add(chip->card, "CS5340"); | |
294 | } | |
295 | ||
2146dcfd | 296 | static void stereo_output_init(struct oxygen *chip) |
31f86bac CL |
297 | { |
298 | ak4396_init(chip); | |
299 | } | |
300 | ||
d0ce9946 CL |
301 | static void generic_cleanup(struct oxygen *chip) |
302 | { | |
303 | } | |
304 | ||
873591db CL |
305 | static void claro_disable_hp(struct oxygen *chip) |
306 | { | |
307 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP); | |
308 | } | |
309 | ||
310 | static void claro_cleanup(struct oxygen *chip) | |
311 | { | |
312 | claro_disable_hp(chip); | |
313 | } | |
314 | ||
315 | static void claro_suspend(struct oxygen *chip) | |
316 | { | |
317 | claro_disable_hp(chip); | |
318 | } | |
319 | ||
4a4bc53b CL |
320 | static void generic_resume(struct oxygen *chip) |
321 | { | |
322 | ak4396_registers_init(chip); | |
323 | wm8785_registers_init(chip); | |
324 | } | |
325 | ||
c2bc4ff5 CL |
326 | static void meridian_resume(struct oxygen *chip) |
327 | { | |
328 | ak4396_registers_init(chip); | |
329 | } | |
330 | ||
873591db | 331 | static void claro_resume(struct oxygen *chip) |
d91b424d CL |
332 | { |
333 | ak4396_registers_init(chip); | |
873591db | 334 | claro_enable_hp(chip); |
d91b424d CL |
335 | } |
336 | ||
45c1de8e CL |
337 | static void stereo_resume(struct oxygen *chip) |
338 | { | |
339 | ak4396_registers_init(chip); | |
340 | } | |
341 | ||
d0ce9946 CL |
342 | static void set_ak4396_params(struct oxygen *chip, |
343 | struct snd_pcm_hw_params *params) | |
344 | { | |
7ef37cd9 | 345 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
346 | unsigned int i; |
347 | u8 value; | |
348 | ||
6f0de3ce | 349 | value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK; |
d0ce9946 CL |
350 | if (params_rate(params) <= 54000) |
351 | value |= AK4396_DFS_NORMAL; | |
236c4920 | 352 | else if (params_rate(params) <= 108000) |
d0ce9946 CL |
353 | value |= AK4396_DFS_DOUBLE; |
354 | else | |
355 | value |= AK4396_DFS_QUAD; | |
df91bc23 CL |
356 | |
357 | msleep(1); /* wait for the new MCLK to become stable */ | |
358 | ||
6f0de3ce | 359 | if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) { |
45c1de8e | 360 | for (i = 0; i < data->dacs; ++i) { |
6f0de3ce CL |
361 | ak4396_write(chip, i, AK4396_CONTROL_1, |
362 | AK4396_DIF_24_MSB); | |
363 | ak4396_write(chip, i, AK4396_CONTROL_2, value); | |
364 | ak4396_write(chip, i, AK4396_CONTROL_1, | |
365 | AK4396_DIF_24_MSB | AK4396_RSTN); | |
366 | } | |
367 | } | |
368 | } | |
369 | ||
370 | static void update_ak4396_volume(struct oxygen *chip) | |
371 | { | |
45c1de8e | 372 | struct generic_data *data = chip->model_data; |
6f0de3ce CL |
373 | unsigned int i; |
374 | ||
45c1de8e | 375 | for (i = 0; i < data->dacs; ++i) { |
6f0de3ce CL |
376 | ak4396_write_cached(chip, i, AK4396_LCH_ATT, |
377 | chip->dac_volume[i * 2]); | |
378 | ak4396_write_cached(chip, i, AK4396_RCH_ATT, | |
379 | chip->dac_volume[i * 2 + 1]); | |
d0ce9946 CL |
380 | } |
381 | } | |
382 | ||
d0ce9946 CL |
383 | static void update_ak4396_mute(struct oxygen *chip) |
384 | { | |
7ef37cd9 | 385 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
386 | unsigned int i; |
387 | u8 value; | |
388 | ||
6f0de3ce | 389 | value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE; |
d0ce9946 CL |
390 | if (chip->dac_mute) |
391 | value |= AK4396_SMUTE; | |
45c1de8e | 392 | for (i = 0; i < data->dacs; ++i) |
6f0de3ce | 393 | ak4396_write_cached(chip, i, AK4396_CONTROL_2, value); |
d0ce9946 CL |
394 | } |
395 | ||
396 | static void set_wm8785_params(struct oxygen *chip, | |
397 | struct snd_pcm_hw_params *params) | |
398 | { | |
6f0de3ce | 399 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
400 | unsigned int value; |
401 | ||
878ac3ee | 402 | value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST; |
71e22a4b CL |
403 | if (params_rate(params) <= 48000) |
404 | value |= WM8785_OSR_SINGLE; | |
405 | else if (params_rate(params) <= 96000) | |
d0ce9946 | 406 | value |= WM8785_OSR_DOUBLE; |
d0ce9946 | 407 | else |
71e22a4b | 408 | value |= WM8785_OSR_QUAD; |
6f0de3ce CL |
409 | if (value != data->wm8785_regs[0]) { |
410 | wm8785_write(chip, WM8785_R7, 0); | |
411 | wm8785_write(chip, WM8785_R0, value); | |
1ff04886 | 412 | wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]); |
6f0de3ce | 413 | } |
d0ce9946 CL |
414 | } |
415 | ||
416 | static void set_ak5385_params(struct oxygen *chip, | |
417 | struct snd_pcm_hw_params *params) | |
418 | { | |
419 | unsigned int value; | |
420 | ||
421 | if (params_rate(params) <= 54000) | |
878ac3ee | 422 | value = GPIO_AK5385_DFS_NORMAL; |
d0ce9946 | 423 | else if (params_rate(params) <= 108000) |
878ac3ee | 424 | value = GPIO_AK5385_DFS_DOUBLE; |
d0ce9946 | 425 | else |
878ac3ee CL |
426 | value = GPIO_AK5385_DFS_QUAD; |
427 | oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, | |
428 | value, GPIO_AK5385_DFS_MASK); | |
d0ce9946 CL |
429 | } |
430 | ||
45c1de8e CL |
431 | static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params) |
432 | { | |
433 | } | |
434 | ||
4852ad02 CL |
435 | static int rolloff_info(struct snd_kcontrol *ctl, |
436 | struct snd_ctl_elem_info *info) | |
437 | { | |
438 | static const char *const names[2] = { | |
439 | "Sharp Roll-off", "Slow Roll-off" | |
440 | }; | |
441 | ||
9600732b | 442 | return snd_ctl_enum_info(info, 1, 2, names); |
4852ad02 CL |
443 | } |
444 | ||
445 | static int rolloff_get(struct snd_kcontrol *ctl, | |
446 | struct snd_ctl_elem_value *value) | |
447 | { | |
448 | struct oxygen *chip = ctl->private_data; | |
449 | struct generic_data *data = chip->model_data; | |
450 | ||
451 | value->value.enumerated.item[0] = | |
452 | (data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0; | |
453 | return 0; | |
454 | } | |
455 | ||
456 | static int rolloff_put(struct snd_kcontrol *ctl, | |
457 | struct snd_ctl_elem_value *value) | |
458 | { | |
459 | struct oxygen *chip = ctl->private_data; | |
460 | struct generic_data *data = chip->model_data; | |
461 | unsigned int i; | |
462 | int changed; | |
463 | u8 reg; | |
464 | ||
465 | mutex_lock(&chip->mutex); | |
466 | reg = data->ak4396_regs[0][AK4396_CONTROL_2]; | |
467 | if (value->value.enumerated.item[0]) | |
468 | reg |= AK4396_SLOW; | |
469 | else | |
470 | reg &= ~AK4396_SLOW; | |
471 | changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2]; | |
472 | if (changed) { | |
45c1de8e | 473 | for (i = 0; i < data->dacs; ++i) |
4852ad02 CL |
474 | ak4396_write(chip, i, AK4396_CONTROL_2, reg); |
475 | } | |
476 | mutex_unlock(&chip->mutex); | |
477 | return changed; | |
478 | } | |
479 | ||
480 | static const struct snd_kcontrol_new rolloff_control = { | |
481 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
482 | .name = "DAC Filter Playback Enum", | |
483 | .info = rolloff_info, | |
484 | .get = rolloff_get, | |
485 | .put = rolloff_put, | |
486 | }; | |
487 | ||
1ff04886 CL |
488 | static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) |
489 | { | |
490 | static const char *const names[2] = { | |
491 | "None", "High-pass Filter" | |
492 | }; | |
493 | ||
9600732b | 494 | return snd_ctl_enum_info(info, 1, 2, names); |
1ff04886 CL |
495 | } |
496 | ||
497 | static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) | |
498 | { | |
499 | struct oxygen *chip = ctl->private_data; | |
500 | struct generic_data *data = chip->model_data; | |
501 | ||
502 | value->value.enumerated.item[0] = | |
503 | (data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0; | |
504 | return 0; | |
505 | } | |
506 | ||
507 | static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) | |
508 | { | |
509 | struct oxygen *chip = ctl->private_data; | |
510 | struct generic_data *data = chip->model_data; | |
511 | unsigned int reg; | |
512 | int changed; | |
513 | ||
514 | mutex_lock(&chip->mutex); | |
515 | reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL); | |
516 | if (value->value.enumerated.item[0]) | |
517 | reg |= WM8785_HPFR | WM8785_HPFL; | |
518 | changed = reg != data->wm8785_regs[WM8785_R2]; | |
519 | if (changed) | |
520 | wm8785_write(chip, WM8785_R2, reg); | |
521 | mutex_unlock(&chip->mutex); | |
522 | return changed; | |
523 | } | |
524 | ||
525 | static const struct snd_kcontrol_new hpf_control = { | |
526 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
527 | .name = "ADC Filter Capture Enum", | |
528 | .info = hpf_info, | |
529 | .get = hpf_get, | |
530 | .put = hpf_put, | |
531 | }; | |
532 | ||
d1d7093f CL |
533 | static int meridian_dig_source_info(struct snd_kcontrol *ctl, |
534 | struct snd_ctl_elem_info *info) | |
64878dfb CL |
535 | { |
536 | static const char *const names[2] = { "On-board", "Extension" }; | |
537 | ||
538 | return snd_ctl_enum_info(info, 1, 2, names); | |
539 | } | |
540 | ||
d1d7093f CL |
541 | static int claro_dig_source_info(struct snd_kcontrol *ctl, |
542 | struct snd_ctl_elem_info *info) | |
543 | { | |
544 | static const char *const names[2] = { "Optical", "Coaxial" }; | |
545 | ||
546 | return snd_ctl_enum_info(info, 1, 2, names); | |
547 | } | |
548 | ||
549 | static int meridian_dig_source_get(struct snd_kcontrol *ctl, | |
550 | struct snd_ctl_elem_value *value) | |
64878dfb CL |
551 | { |
552 | struct oxygen *chip = ctl->private_data; | |
553 | ||
554 | value->value.enumerated.item[0] = | |
555 | !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) & | |
556 | GPIO_MERIDIAN_DIG_EXT); | |
557 | return 0; | |
558 | } | |
559 | ||
d1d7093f CL |
560 | static int claro_dig_source_get(struct snd_kcontrol *ctl, |
561 | struct snd_ctl_elem_value *value) | |
562 | { | |
563 | struct oxygen *chip = ctl->private_data; | |
564 | ||
565 | value->value.enumerated.item[0] = | |
566 | !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) & | |
567 | GPIO_CLARO_DIG_COAX); | |
568 | return 0; | |
569 | } | |
570 | ||
571 | static int meridian_dig_source_put(struct snd_kcontrol *ctl, | |
572 | struct snd_ctl_elem_value *value) | |
64878dfb CL |
573 | { |
574 | struct oxygen *chip = ctl->private_data; | |
575 | u16 old_reg, new_reg; | |
576 | int changed; | |
577 | ||
578 | mutex_lock(&chip->mutex); | |
579 | old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA); | |
580 | new_reg = old_reg & ~GPIO_MERIDIAN_DIG_MASK; | |
581 | if (value->value.enumerated.item[0] == 0) | |
582 | new_reg |= GPIO_MERIDIAN_DIG_BOARD; | |
583 | else | |
584 | new_reg |= GPIO_MERIDIAN_DIG_EXT; | |
585 | changed = new_reg != old_reg; | |
586 | if (changed) | |
587 | oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg); | |
588 | mutex_unlock(&chip->mutex); | |
589 | return changed; | |
590 | } | |
591 | ||
d1d7093f CL |
592 | static int claro_dig_source_put(struct snd_kcontrol *ctl, |
593 | struct snd_ctl_elem_value *value) | |
594 | { | |
595 | struct oxygen *chip = ctl->private_data; | |
596 | u16 old_reg, new_reg; | |
597 | int changed; | |
598 | ||
599 | mutex_lock(&chip->mutex); | |
600 | old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA); | |
601 | new_reg = old_reg & ~GPIO_CLARO_DIG_COAX; | |
602 | if (value->value.enumerated.item[0]) | |
603 | new_reg |= GPIO_CLARO_DIG_COAX; | |
604 | changed = new_reg != old_reg; | |
605 | if (changed) | |
606 | oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg); | |
607 | mutex_unlock(&chip->mutex); | |
608 | return changed; | |
609 | } | |
610 | ||
64878dfb CL |
611 | static const struct snd_kcontrol_new meridian_dig_source_control = { |
612 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
613 | .name = "IEC958 Source Capture Enum", | |
614 | .info = meridian_dig_source_info, | |
615 | .get = meridian_dig_source_get, | |
616 | .put = meridian_dig_source_put, | |
617 | }; | |
618 | ||
d1d7093f CL |
619 | static const struct snd_kcontrol_new claro_dig_source_control = { |
620 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
621 | .name = "IEC958 Source Capture Enum", | |
622 | .info = claro_dig_source_info, | |
623 | .get = claro_dig_source_get, | |
624 | .put = claro_dig_source_put, | |
625 | }; | |
626 | ||
4852ad02 CL |
627 | static int generic_mixer_init(struct oxygen *chip) |
628 | { | |
629 | return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip)); | |
630 | } | |
631 | ||
1ff04886 CL |
632 | static int generic_wm8785_mixer_init(struct oxygen *chip) |
633 | { | |
634 | int err; | |
635 | ||
636 | err = generic_mixer_init(chip); | |
637 | if (err < 0) | |
638 | return err; | |
639 | err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip)); | |
640 | if (err < 0) | |
641 | return err; | |
642 | return 0; | |
643 | } | |
644 | ||
64878dfb CL |
645 | static int meridian_mixer_init(struct oxygen *chip) |
646 | { | |
647 | int err; | |
648 | ||
649 | err = generic_mixer_init(chip); | |
650 | if (err < 0) | |
651 | return err; | |
652 | err = snd_ctl_add(chip->card, | |
653 | snd_ctl_new1(&meridian_dig_source_control, chip)); | |
654 | if (err < 0) | |
655 | return err; | |
656 | return 0; | |
657 | } | |
658 | ||
d1d7093f CL |
659 | static int claro_mixer_init(struct oxygen *chip) |
660 | { | |
661 | int err; | |
662 | ||
663 | err = generic_wm8785_mixer_init(chip); | |
664 | if (err < 0) | |
665 | return err; | |
666 | err = snd_ctl_add(chip->card, | |
667 | snd_ctl_new1(&claro_dig_source_control, chip)); | |
668 | if (err < 0) | |
669 | return err; | |
670 | return 0; | |
671 | } | |
672 | ||
673 | static int claro_halo_mixer_init(struct oxygen *chip) | |
674 | { | |
675 | int err; | |
676 | ||
677 | err = generic_mixer_init(chip); | |
678 | if (err < 0) | |
679 | return err; | |
680 | err = snd_ctl_add(chip->card, | |
681 | snd_ctl_new1(&claro_dig_source_control, chip)); | |
682 | if (err < 0) | |
683 | return err; | |
684 | return 0; | |
685 | } | |
686 | ||
9719fcaa CL |
687 | static void dump_ak4396_registers(struct oxygen *chip, |
688 | struct snd_info_buffer *buffer) | |
689 | { | |
690 | struct generic_data *data = chip->model_data; | |
691 | unsigned int dac, i; | |
692 | ||
693 | for (dac = 0; dac < data->dacs; ++dac) { | |
694 | snd_iprintf(buffer, "\nAK4396 %u:", dac + 1); | |
695 | for (i = 0; i < 5; ++i) | |
696 | snd_iprintf(buffer, " %02x", data->ak4396_regs[dac][i]); | |
697 | } | |
698 | snd_iprintf(buffer, "\n"); | |
699 | } | |
700 | ||
701 | static void dump_wm8785_registers(struct oxygen *chip, | |
702 | struct snd_info_buffer *buffer) | |
703 | { | |
704 | struct generic_data *data = chip->model_data; | |
705 | unsigned int i; | |
706 | ||
707 | snd_iprintf(buffer, "\nWM8785:"); | |
708 | for (i = 0; i < 3; ++i) | |
709 | snd_iprintf(buffer, " %03x", data->wm8785_regs[i]); | |
710 | snd_iprintf(buffer, "\n"); | |
711 | } | |
712 | ||
713 | static void dump_oxygen_registers(struct oxygen *chip, | |
714 | struct snd_info_buffer *buffer) | |
715 | { | |
716 | dump_ak4396_registers(chip, buffer); | |
717 | dump_wm8785_registers(chip, buffer); | |
718 | } | |
719 | ||
d0ce9946 CL |
720 | static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0); |
721 | ||
722 | static const struct oxygen_model model_generic = { | |
723 | .shortname = "C-Media CMI8788", | |
724 | .longname = "C-Media Oxygen HD Audio", | |
725 | .chip = "CMI8788", | |
d0ce9946 | 726 | .init = generic_init, |
1ff04886 | 727 | .mixer_init = generic_wm8785_mixer_init, |
d0ce9946 | 728 | .cleanup = generic_cleanup, |
4a4bc53b | 729 | .resume = generic_resume, |
d0ce9946 CL |
730 | .set_dac_params = set_ak4396_params, |
731 | .set_adc_params = set_wm8785_params, | |
732 | .update_dac_volume = update_ak4396_volume, | |
733 | .update_dac_mute = update_ak4396_mute, | |
9719fcaa | 734 | .dump_registers = dump_oxygen_registers, |
4972a177 | 735 | .dac_tlv = ak4396_db_scale, |
7ef37cd9 | 736 | .model_data_size = sizeof(struct generic_data), |
d76596b1 CL |
737 | .device_config = PLAYBACK_0_TO_I2S | |
738 | PLAYBACK_1_TO_SPDIF | | |
739 | PLAYBACK_2_TO_AC97_1 | | |
740 | CAPTURE_0_FROM_I2S_1 | | |
741 | CAPTURE_1_FROM_SPDIF | | |
b6ca8ab3 CL |
742 | CAPTURE_2_FROM_AC97_1 | |
743 | AC97_CD_INPUT, | |
1f4d7be7 CL |
744 | .dac_channels_pcm = 8, |
745 | .dac_channels_mixer = 8, | |
193e8138 CL |
746 | .dac_volume_min = 0, |
747 | .dac_volume_max = 255, | |
87eedd2f CL |
748 | .function_flags = OXYGEN_FUNCTION_SPI | |
749 | OXYGEN_FUNCTION_ENABLE_SPI_4_5, | |
ce2c4920 | 750 | .dac_mclks = OXYGEN_MCLKS(256, 128, 128), |
5b8bf2a5 | 751 | .adc_mclks = OXYGEN_MCLKS(256, 256, 128), |
05855ba3 CL |
752 | .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, |
753 | .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, | |
d0ce9946 | 754 | }; |
d0ce9946 | 755 | |
30459d7b CL |
756 | static int __devinit get_oxygen_model(struct oxygen *chip, |
757 | const struct pci_device_id *id) | |
758 | { | |
a4b16969 CL |
759 | static const char *const names[] = { |
760 | [MODEL_MERIDIAN] = "AuzenTech X-Meridian", | |
761 | [MODEL_MERIDIAN_2G] = "AuzenTech X-Meridian 2G", | |
762 | [MODEL_CLARO] = "HT-Omega Claro", | |
763 | [MODEL_CLARO_HALO] = "HT-Omega Claro halo", | |
764 | [MODEL_FANTASIA] = "TempoTec HiFier Fantasia", | |
765 | [MODEL_SERENADE] = "TempoTec HiFier Serenade", | |
766 | [MODEL_HG2PCI] = "CMI8787-HG2PCI", | |
767 | }; | |
768 | ||
30459d7b CL |
769 | chip->model = model_generic; |
770 | switch (id->driver_data) { | |
771 | case MODEL_MERIDIAN: | |
a4b16969 | 772 | case MODEL_MERIDIAN_2G: |
30459d7b | 773 | chip->model.init = meridian_init; |
64878dfb | 774 | chip->model.mixer_init = meridian_mixer_init; |
30459d7b CL |
775 | chip->model.resume = meridian_resume; |
776 | chip->model.set_adc_params = set_ak5385_params; | |
9719fcaa | 777 | chip->model.dump_registers = dump_ak4396_registers; |
30459d7b CL |
778 | chip->model.device_config = PLAYBACK_0_TO_I2S | |
779 | PLAYBACK_1_TO_SPDIF | | |
780 | CAPTURE_0_FROM_I2S_2 | | |
781 | CAPTURE_1_FROM_SPDIF; | |
5fc51524 CL |
782 | if (id->driver_data == MODEL_MERIDIAN) |
783 | chip->model.device_config |= AC97_CD_INPUT; | |
30459d7b | 784 | break; |
873591db CL |
785 | case MODEL_CLARO: |
786 | chip->model.init = claro_init; | |
d1d7093f | 787 | chip->model.mixer_init = claro_mixer_init; |
873591db CL |
788 | chip->model.cleanup = claro_cleanup; |
789 | chip->model.suspend = claro_suspend; | |
790 | chip->model.resume = claro_resume; | |
791 | break; | |
792 | case MODEL_CLARO_HALO: | |
793 | chip->model.init = claro_halo_init; | |
d1d7093f | 794 | chip->model.mixer_init = claro_halo_mixer_init; |
873591db CL |
795 | chip->model.cleanup = claro_cleanup; |
796 | chip->model.suspend = claro_suspend; | |
797 | chip->model.resume = claro_resume; | |
d91b424d | 798 | chip->model.set_adc_params = set_ak5385_params; |
9719fcaa | 799 | chip->model.dump_registers = dump_ak4396_registers; |
0873a5ae ES |
800 | chip->model.device_config = PLAYBACK_0_TO_I2S | |
801 | PLAYBACK_1_TO_SPDIF | | |
802 | CAPTURE_0_FROM_I2S_2 | | |
803 | CAPTURE_1_FROM_SPDIF; | |
d91b424d | 804 | break; |
2146dcfd | 805 | case MODEL_FANTASIA: |
a4b16969 | 806 | case MODEL_SERENADE: |
2146dcfd | 807 | case MODEL_2CH_OUTPUT: |
a4b16969 | 808 | case MODEL_HG2PCI: |
45c1de8e CL |
809 | chip->model.shortname = "C-Media CMI8787"; |
810 | chip->model.chip = "CMI8787"; | |
2146dcfd CL |
811 | if (id->driver_data == MODEL_FANTASIA) |
812 | chip->model.init = fantasia_init; | |
31f86bac | 813 | else |
2146dcfd | 814 | chip->model.init = stereo_output_init; |
45c1de8e CL |
815 | chip->model.resume = stereo_resume; |
816 | chip->model.mixer_init = generic_mixer_init; | |
817 | chip->model.set_adc_params = set_no_params; | |
9719fcaa | 818 | chip->model.dump_registers = dump_ak4396_registers; |
45c1de8e | 819 | chip->model.device_config = PLAYBACK_0_TO_I2S | |
31f86bac | 820 | PLAYBACK_1_TO_SPDIF; |
ce2c4920 | 821 | if (id->driver_data == MODEL_FANTASIA) { |
31f86bac | 822 | chip->model.device_config |= CAPTURE_0_FROM_I2S_1; |
ce2c4920 CL |
823 | chip->model.adc_mclks = OXYGEN_MCLKS(256, 128, 128); |
824 | } | |
1f4d7be7 CL |
825 | chip->model.dac_channels_pcm = 2; |
826 | chip->model.dac_channels_mixer = 2; | |
45c1de8e | 827 | break; |
66410bfd CL |
828 | case MODEL_XONAR_DG: |
829 | chip->model = model_xonar_dg; | |
830 | break; | |
30459d7b CL |
831 | } |
832 | if (id->driver_data == MODEL_MERIDIAN || | |
5fc51524 | 833 | id->driver_data == MODEL_MERIDIAN_2G || |
873591db | 834 | id->driver_data == MODEL_CLARO_HALO) { |
30459d7b CL |
835 | chip->model.misc_flags = OXYGEN_MISC_MIDI; |
836 | chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT; | |
837 | } | |
a4b16969 CL |
838 | if (id->driver_data < ARRAY_SIZE(names) && names[id->driver_data]) |
839 | chip->model.shortname = names[id->driver_data]; | |
30459d7b CL |
840 | return 0; |
841 | } | |
842 | ||
d0ce9946 CL |
843 | static int __devinit generic_oxygen_probe(struct pci_dev *pci, |
844 | const struct pci_device_id *pci_id) | |
845 | { | |
846 | static int dev; | |
d0ce9946 CL |
847 | int err; |
848 | ||
849 | if (dev >= SNDRV_CARDS) | |
850 | return -ENODEV; | |
851 | if (!enable[dev]) { | |
852 | ++dev; | |
853 | return -ENOENT; | |
854 | } | |
bb718588 | 855 | err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE, |
30459d7b | 856 | oxygen_ids, get_oxygen_model); |
d0ce9946 CL |
857 | if (err >= 0) |
858 | ++dev; | |
859 | return err; | |
860 | } | |
861 | ||
862 | static struct pci_driver oxygen_driver = { | |
3733e424 | 863 | .name = KBUILD_MODNAME, |
d0ce9946 CL |
864 | .id_table = oxygen_ids, |
865 | .probe = generic_oxygen_probe, | |
866 | .remove = __devexit_p(oxygen_pci_remove), | |
4a4bc53b CL |
867 | #ifdef CONFIG_PM |
868 | .suspend = oxygen_pci_suspend, | |
869 | .resume = oxygen_pci_resume, | |
870 | #endif | |
d0ce9946 CL |
871 | }; |
872 | ||
873 | static int __init alsa_card_oxygen_init(void) | |
874 | { | |
875 | return pci_register_driver(&oxygen_driver); | |
876 | } | |
877 | ||
878 | static void __exit alsa_card_oxygen_exit(void) | |
879 | { | |
880 | pci_unregister_driver(&oxygen_driver); | |
881 | } | |
882 | ||
883 | module_init(alsa_card_oxygen_init) | |
884 | module_exit(alsa_card_oxygen_exit) |