ALSA: oxygen: do not show chip revision in card longname
[deliverable/linux.git] / sound / pci / oxygen / oxygen.c
CommitLineData
d0ce9946 1/*
873591db 2 * C-Media CMI8788 driver for C-Media's reference design and similar models
d0ce9946
CL
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/*
dc0adf48
CL
21 * CMI8788:
22 *
de664936
CL
23 * SPI 0 -> 1st AK4396 (front)
24 * SPI 1 -> 2nd AK4396 (surround)
25 * SPI 2 -> 3rd AK4396 (center/LFE)
26 * SPI 3 -> WM8785
27 * SPI 4 -> 4th AK4396 (back)
d0ce9946 28 *
de664936
CL
29 * GPIO 0 -> DFS0 of AK5385
30 * GPIO 1 -> DFS1 of AK5385
64878dfb
CL
31 *
32 * X-Meridian models:
33 * GPIO 4 -> enable extension S/PDIF input
34 * GPIO 6 -> enable on-board S/PDIF input
35 *
36 * Claro models:
37 * GPIO 8 -> enable headphone amplifier
dc0adf48
CL
38 *
39 * CM9780:
40 *
de664936
CL
41 * LINE_OUT -> input of ADC
42 *
43 * AUX_IN <- aux
44 * CD_IN <- CD
45 * MIC_IN <- mic
46 *
47 * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
d0ce9946
CL
48 */
49
df91bc23 50#include <linux/delay.h>
902b05c1 51#include <linux/mutex.h>
d0ce9946 52#include <linux/pci.h>
902b05c1 53#include <sound/ac97_codec.h>
ccc80fb4 54#include <sound/control.h>
d0ce9946 55#include <sound/core.h>
9719fcaa 56#include <sound/info.h>
d0ce9946
CL
57#include <sound/initval.h>
58#include <sound/pcm.h>
59#include <sound/pcm_params.h>
60#include <sound/tlv.h>
61#include "oxygen.h"
66410bfd 62#include "xonar_dg.h"
c626026d 63#include "ak4396.h"
f5b2368b 64#include "wm8785.h"
d0ce9946
CL
65
66MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
67MODULE_DESCRIPTION("C-Media CMI8788 driver");
d023dc0a 68MODULE_LICENSE("GPL v2");
66410bfd
CL
69MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8786}"
70 ",{C-Media,CMI8787}"
71 ",{C-Media,CMI8788}}");
d0ce9946
CL
72
73static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
74static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
75static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
76
77module_param_array(index, int, NULL, 0444);
78MODULE_PARM_DESC(index, "card index");
79module_param_array(id, charp, NULL, 0444);
80MODULE_PARM_DESC(id, "ID string");
81module_param_array(enable, bool, NULL, 0444);
82MODULE_PARM_DESC(enable, "enable card");
83
2f1b0ec7 84enum {
18f24839
CL
85 MODEL_CMEDIA_REF,
86 MODEL_MERIDIAN,
87 MODEL_CLARO,
88 MODEL_CLARO_HALO,
2146dcfd
CL
89 MODEL_FANTASIA,
90 MODEL_2CH_OUTPUT,
66410bfd 91 MODEL_XONAR_DG,
2f1b0ec7
CL
92};
93
cebe41d4 94static DEFINE_PCI_DEVICE_TABLE(oxygen_ids) = {
18f24839 95 /* C-Media's reference design */
2f1b0ec7 96 { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
8c50b759 97 { OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF },
2f1b0ec7
CL
98 { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
99 { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
100 { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
101 { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
102 { OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF },
103 { OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF },
18f24839 104 { OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF },
66410bfd
CL
105 /* Asus Xonar DG */
106 { OXYGEN_PCI_SUBID(0x1043, 0x8467), .driver_data = MODEL_XONAR_DG },
8c50b759
CL
107 /* PCI 2.0 HD Audio */
108 { OXYGEN_PCI_SUBID(0x13f6, 0x8782), .driver_data = MODEL_2CH_OUTPUT },
18f24839 109 /* Kuroutoshikou CMI8787-HG2PCI */
2146dcfd 110 { OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_2CH_OUTPUT },
18f24839 111 /* TempoTec HiFier Fantasia */
2146dcfd
CL
112 { OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA },
113 /* TempoTec HiFier Serenade */
114 { OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_2CH_OUTPUT },
18f24839 115 /* AuzenTech X-Meridian */
2f1b0ec7 116 { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN },
8443d2eb
CL
117 /* AuzenTech X-Meridian 2G */
118 { OXYGEN_PCI_SUBID(0x5431, 0x017a), .driver_data = MODEL_MERIDIAN },
18f24839 119 /* HT-Omega Claro */
873591db 120 { OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
18f24839 121 /* HT-Omega Claro halo */
873591db 122 { OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
d0ce9946
CL
123 { }
124};
125MODULE_DEVICE_TABLE(pci, oxygen_ids);
126
878ac3ee
CL
127
128#define GPIO_AK5385_DFS_MASK 0x0003
129#define GPIO_AK5385_DFS_NORMAL 0x0000
130#define GPIO_AK5385_DFS_DOUBLE 0x0001
131#define GPIO_AK5385_DFS_QUAD 0x0002
132
64878dfb
CL
133#define GPIO_MERIDIAN_DIG_MASK 0x0050
134#define GPIO_MERIDIAN_DIG_EXT 0x0010
135#define GPIO_MERIDIAN_DIG_BOARD 0x0040
136
873591db
CL
137#define GPIO_CLARO_HP 0x0100
138
7ef37cd9 139struct generic_data {
45c1de8e 140 unsigned int dacs;
6f0de3ce 141 u8 ak4396_regs[4][5];
1ff04886 142 u16 wm8785_regs[3];
7ef37cd9
CL
143};
144
d0ce9946
CL
145static void ak4396_write(struct oxygen *chip, unsigned int codec,
146 u8 reg, u8 value)
147{
148 /* maps ALSA channel pair number to SPI output */
149 static const u8 codec_spi_map[4] = {
7113e958 150 0, 1, 2, 4
d0ce9946 151 };
6f0de3ce
CL
152 struct generic_data *data = chip->model_data;
153
c2353a08 154 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
d0ce9946 155 OXYGEN_SPI_DATA_LENGTH_2 |
2ea85986 156 OXYGEN_SPI_CLOCK_160 |
d0ce9946 157 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
c2353a08 158 OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
d0ce9946 159 AK4396_WRITE | (reg << 8) | value);
6f0de3ce
CL
160 data->ak4396_regs[codec][reg] = value;
161}
162
163static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
164 u8 reg, u8 value)
165{
166 struct generic_data *data = chip->model_data;
167
168 if (value != data->ak4396_regs[codec][reg])
169 ak4396_write(chip, codec, reg, value);
d0ce9946
CL
170}
171
172static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
173{
e58aee95
CL
174 struct generic_data *data = chip->model_data;
175
c2353a08 176 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
d0ce9946 177 OXYGEN_SPI_DATA_LENGTH_2 |
2ea85986 178 OXYGEN_SPI_CLOCK_160 |
c2353a08
CL
179 (3 << OXYGEN_SPI_CODEC_SHIFT) |
180 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
d0ce9946 181 (reg << 9) | value);
6f0de3ce
CL
182 if (reg < ARRAY_SIZE(data->wm8785_regs))
183 data->wm8785_regs[reg] = value;
bbbfb552
CL
184}
185
75146fc0 186static void ak4396_registers_init(struct oxygen *chip)
d0ce9946 187{
7ef37cd9 188 struct generic_data *data = chip->model_data;
d0ce9946
CL
189 unsigned int i;
190
45c1de8e 191 for (i = 0; i < data->dacs; ++i) {
6f0de3ce
CL
192 ak4396_write(chip, i, AK4396_CONTROL_1,
193 AK4396_DIF_24_MSB | AK4396_RSTN);
194 ak4396_write(chip, i, AK4396_CONTROL_2,
195 data->ak4396_regs[0][AK4396_CONTROL_2]);
196 ak4396_write(chip, i, AK4396_CONTROL_3,
197 AK4396_PCM);
198 ak4396_write(chip, i, AK4396_LCH_ATT,
199 chip->dac_volume[i * 2]);
200 ak4396_write(chip, i, AK4396_RCH_ATT,
201 chip->dac_volume[i * 2 + 1]);
d0ce9946 202 }
75146fc0
CL
203}
204
205static void ak4396_init(struct oxygen *chip)
206{
207 struct generic_data *data = chip->model_data;
208
1f4d7be7 209 data->dacs = chip->model.dac_channels_pcm / 2;
6f0de3ce
CL
210 data->ak4396_regs[0][AK4396_CONTROL_2] =
211 AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
75146fc0 212 ak4396_registers_init(chip);
d0ce9946
CL
213 snd_component_add(chip->card, "AK4396");
214}
215
216static void ak5385_init(struct oxygen *chip)
217{
878ac3ee
CL
218 oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK);
219 oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK);
d0ce9946
CL
220 snd_component_add(chip->card, "AK5385");
221}
222
75146fc0 223static void wm8785_registers_init(struct oxygen *chip)
d0ce9946 224{
e58aee95
CL
225 struct generic_data *data = chip->model_data;
226
878ac3ee 227 wm8785_write(chip, WM8785_R7, 0);
6f0de3ce 228 wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]);
1ff04886 229 wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
75146fc0 230}
e58aee95 231
75146fc0
CL
232static void wm8785_init(struct oxygen *chip)
233{
234 struct generic_data *data = chip->model_data;
235
6f0de3ce
CL
236 data->wm8785_regs[0] =
237 WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST;
1ff04886 238 data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL;
75146fc0 239 wm8785_registers_init(chip);
d0ce9946
CL
240 snd_component_add(chip->card, "WM8785");
241}
242
243static void generic_init(struct oxygen *chip)
244{
245 ak4396_init(chip);
246 wm8785_init(chip);
247}
248
249static void meridian_init(struct oxygen *chip)
250{
64878dfb
CL
251 oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
252 GPIO_MERIDIAN_DIG_MASK);
253 oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
254 GPIO_MERIDIAN_DIG_BOARD, GPIO_MERIDIAN_DIG_MASK);
d0ce9946
CL
255 ak4396_init(chip);
256 ak5385_init(chip);
257}
258
873591db
CL
259static void claro_enable_hp(struct oxygen *chip)
260{
261 msleep(300);
262 oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP);
263 oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
264}
265
266static void claro_init(struct oxygen *chip)
267{
268 ak4396_init(chip);
269 wm8785_init(chip);
270 claro_enable_hp(chip);
271}
272
273static void claro_halo_init(struct oxygen *chip)
d91b424d
CL
274{
275 ak4396_init(chip);
276 ak5385_init(chip);
873591db 277 claro_enable_hp(chip);
d91b424d
CL
278}
279
2146dcfd 280static void fantasia_init(struct oxygen *chip)
45c1de8e
CL
281{
282 ak4396_init(chip);
283 snd_component_add(chip->card, "CS5340");
284}
285
2146dcfd 286static void stereo_output_init(struct oxygen *chip)
31f86bac
CL
287{
288 ak4396_init(chip);
289}
290
d0ce9946
CL
291static void generic_cleanup(struct oxygen *chip)
292{
293}
294
873591db
CL
295static void claro_disable_hp(struct oxygen *chip)
296{
297 oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
298}
299
300static void claro_cleanup(struct oxygen *chip)
301{
302 claro_disable_hp(chip);
303}
304
305static void claro_suspend(struct oxygen *chip)
306{
307 claro_disable_hp(chip);
308}
309
4a4bc53b
CL
310static void generic_resume(struct oxygen *chip)
311{
312 ak4396_registers_init(chip);
313 wm8785_registers_init(chip);
314}
315
c2bc4ff5
CL
316static void meridian_resume(struct oxygen *chip)
317{
318 ak4396_registers_init(chip);
319}
320
873591db 321static void claro_resume(struct oxygen *chip)
d91b424d
CL
322{
323 ak4396_registers_init(chip);
873591db 324 claro_enable_hp(chip);
d91b424d
CL
325}
326
45c1de8e
CL
327static void stereo_resume(struct oxygen *chip)
328{
329 ak4396_registers_init(chip);
330}
331
d0ce9946
CL
332static void set_ak4396_params(struct oxygen *chip,
333 struct snd_pcm_hw_params *params)
334{
7ef37cd9 335 struct generic_data *data = chip->model_data;
d0ce9946
CL
336 unsigned int i;
337 u8 value;
338
6f0de3ce 339 value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
d0ce9946
CL
340 if (params_rate(params) <= 54000)
341 value |= AK4396_DFS_NORMAL;
236c4920 342 else if (params_rate(params) <= 108000)
d0ce9946
CL
343 value |= AK4396_DFS_DOUBLE;
344 else
345 value |= AK4396_DFS_QUAD;
df91bc23
CL
346
347 msleep(1); /* wait for the new MCLK to become stable */
348
6f0de3ce 349 if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
45c1de8e 350 for (i = 0; i < data->dacs; ++i) {
6f0de3ce
CL
351 ak4396_write(chip, i, AK4396_CONTROL_1,
352 AK4396_DIF_24_MSB);
353 ak4396_write(chip, i, AK4396_CONTROL_2, value);
354 ak4396_write(chip, i, AK4396_CONTROL_1,
355 AK4396_DIF_24_MSB | AK4396_RSTN);
356 }
357 }
358}
359
360static void update_ak4396_volume(struct oxygen *chip)
361{
45c1de8e 362 struct generic_data *data = chip->model_data;
6f0de3ce
CL
363 unsigned int i;
364
45c1de8e 365 for (i = 0; i < data->dacs; ++i) {
6f0de3ce
CL
366 ak4396_write_cached(chip, i, AK4396_LCH_ATT,
367 chip->dac_volume[i * 2]);
368 ak4396_write_cached(chip, i, AK4396_RCH_ATT,
369 chip->dac_volume[i * 2 + 1]);
d0ce9946
CL
370 }
371}
372
d0ce9946
CL
373static void update_ak4396_mute(struct oxygen *chip)
374{
7ef37cd9 375 struct generic_data *data = chip->model_data;
d0ce9946
CL
376 unsigned int i;
377 u8 value;
378
6f0de3ce 379 value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
d0ce9946
CL
380 if (chip->dac_mute)
381 value |= AK4396_SMUTE;
45c1de8e 382 for (i = 0; i < data->dacs; ++i)
6f0de3ce 383 ak4396_write_cached(chip, i, AK4396_CONTROL_2, value);
d0ce9946
CL
384}
385
386static void set_wm8785_params(struct oxygen *chip,
387 struct snd_pcm_hw_params *params)
388{
6f0de3ce 389 struct generic_data *data = chip->model_data;
d0ce9946
CL
390 unsigned int value;
391
878ac3ee 392 value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST;
71e22a4b
CL
393 if (params_rate(params) <= 48000)
394 value |= WM8785_OSR_SINGLE;
395 else if (params_rate(params) <= 96000)
d0ce9946 396 value |= WM8785_OSR_DOUBLE;
d0ce9946 397 else
71e22a4b 398 value |= WM8785_OSR_QUAD;
6f0de3ce
CL
399 if (value != data->wm8785_regs[0]) {
400 wm8785_write(chip, WM8785_R7, 0);
401 wm8785_write(chip, WM8785_R0, value);
1ff04886 402 wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
6f0de3ce 403 }
d0ce9946
CL
404}
405
406static void set_ak5385_params(struct oxygen *chip,
407 struct snd_pcm_hw_params *params)
408{
409 unsigned int value;
410
411 if (params_rate(params) <= 54000)
878ac3ee 412 value = GPIO_AK5385_DFS_NORMAL;
d0ce9946 413 else if (params_rate(params) <= 108000)
878ac3ee 414 value = GPIO_AK5385_DFS_DOUBLE;
d0ce9946 415 else
878ac3ee
CL
416 value = GPIO_AK5385_DFS_QUAD;
417 oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
418 value, GPIO_AK5385_DFS_MASK);
d0ce9946
CL
419}
420
45c1de8e
CL
421static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params)
422{
423}
424
4852ad02
CL
425static int rolloff_info(struct snd_kcontrol *ctl,
426 struct snd_ctl_elem_info *info)
427{
428 static const char *const names[2] = {
429 "Sharp Roll-off", "Slow Roll-off"
430 };
431
9600732b 432 return snd_ctl_enum_info(info, 1, 2, names);
4852ad02
CL
433}
434
435static int rolloff_get(struct snd_kcontrol *ctl,
436 struct snd_ctl_elem_value *value)
437{
438 struct oxygen *chip = ctl->private_data;
439 struct generic_data *data = chip->model_data;
440
441 value->value.enumerated.item[0] =
442 (data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0;
443 return 0;
444}
445
446static int rolloff_put(struct snd_kcontrol *ctl,
447 struct snd_ctl_elem_value *value)
448{
449 struct oxygen *chip = ctl->private_data;
450 struct generic_data *data = chip->model_data;
451 unsigned int i;
452 int changed;
453 u8 reg;
454
455 mutex_lock(&chip->mutex);
456 reg = data->ak4396_regs[0][AK4396_CONTROL_2];
457 if (value->value.enumerated.item[0])
458 reg |= AK4396_SLOW;
459 else
460 reg &= ~AK4396_SLOW;
461 changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2];
462 if (changed) {
45c1de8e 463 for (i = 0; i < data->dacs; ++i)
4852ad02
CL
464 ak4396_write(chip, i, AK4396_CONTROL_2, reg);
465 }
466 mutex_unlock(&chip->mutex);
467 return changed;
468}
469
470static const struct snd_kcontrol_new rolloff_control = {
471 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
472 .name = "DAC Filter Playback Enum",
473 .info = rolloff_info,
474 .get = rolloff_get,
475 .put = rolloff_put,
476};
477
1ff04886
CL
478static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
479{
480 static const char *const names[2] = {
481 "None", "High-pass Filter"
482 };
483
9600732b 484 return snd_ctl_enum_info(info, 1, 2, names);
1ff04886
CL
485}
486
487static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
488{
489 struct oxygen *chip = ctl->private_data;
490 struct generic_data *data = chip->model_data;
491
492 value->value.enumerated.item[0] =
493 (data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0;
494 return 0;
495}
496
497static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
498{
499 struct oxygen *chip = ctl->private_data;
500 struct generic_data *data = chip->model_data;
501 unsigned int reg;
502 int changed;
503
504 mutex_lock(&chip->mutex);
505 reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL);
506 if (value->value.enumerated.item[0])
507 reg |= WM8785_HPFR | WM8785_HPFL;
508 changed = reg != data->wm8785_regs[WM8785_R2];
509 if (changed)
510 wm8785_write(chip, WM8785_R2, reg);
511 mutex_unlock(&chip->mutex);
512 return changed;
513}
514
515static const struct snd_kcontrol_new hpf_control = {
516 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
517 .name = "ADC Filter Capture Enum",
518 .info = hpf_info,
519 .get = hpf_get,
520 .put = hpf_put,
521};
522
64878dfb
CL
523static int meridian_dig_source_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
524{
525 static const char *const names[2] = { "On-board", "Extension" };
526
527 return snd_ctl_enum_info(info, 1, 2, names);
528}
529
530static int meridian_dig_source_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
531{
532 struct oxygen *chip = ctl->private_data;
533
534 value->value.enumerated.item[0] =
535 !!(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
536 GPIO_MERIDIAN_DIG_EXT);
537 return 0;
538}
539
540static int meridian_dig_source_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
541{
542 struct oxygen *chip = ctl->private_data;
543 u16 old_reg, new_reg;
544 int changed;
545
546 mutex_lock(&chip->mutex);
547 old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA);
548 new_reg = old_reg & ~GPIO_MERIDIAN_DIG_MASK;
549 if (value->value.enumerated.item[0] == 0)
550 new_reg |= GPIO_MERIDIAN_DIG_BOARD;
551 else
552 new_reg |= GPIO_MERIDIAN_DIG_EXT;
553 changed = new_reg != old_reg;
554 if (changed)
555 oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg);
556 mutex_unlock(&chip->mutex);
557 return changed;
558}
559
560static const struct snd_kcontrol_new meridian_dig_source_control = {
561 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
562 .name = "IEC958 Source Capture Enum",
563 .info = meridian_dig_source_info,
564 .get = meridian_dig_source_get,
565 .put = meridian_dig_source_put,
566};
567
4852ad02
CL
568static int generic_mixer_init(struct oxygen *chip)
569{
570 return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
571}
572
1ff04886
CL
573static int generic_wm8785_mixer_init(struct oxygen *chip)
574{
575 int err;
576
577 err = generic_mixer_init(chip);
578 if (err < 0)
579 return err;
580 err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip));
581 if (err < 0)
582 return err;
583 return 0;
584}
585
64878dfb
CL
586static int meridian_mixer_init(struct oxygen *chip)
587{
588 int err;
589
590 err = generic_mixer_init(chip);
591 if (err < 0)
592 return err;
593 err = snd_ctl_add(chip->card,
594 snd_ctl_new1(&meridian_dig_source_control, chip));
595 if (err < 0)
596 return err;
597 return 0;
598}
599
9719fcaa
CL
600static void dump_ak4396_registers(struct oxygen *chip,
601 struct snd_info_buffer *buffer)
602{
603 struct generic_data *data = chip->model_data;
604 unsigned int dac, i;
605
606 for (dac = 0; dac < data->dacs; ++dac) {
607 snd_iprintf(buffer, "\nAK4396 %u:", dac + 1);
608 for (i = 0; i < 5; ++i)
609 snd_iprintf(buffer, " %02x", data->ak4396_regs[dac][i]);
610 }
611 snd_iprintf(buffer, "\n");
612}
613
614static void dump_wm8785_registers(struct oxygen *chip,
615 struct snd_info_buffer *buffer)
616{
617 struct generic_data *data = chip->model_data;
618 unsigned int i;
619
620 snd_iprintf(buffer, "\nWM8785:");
621 for (i = 0; i < 3; ++i)
622 snd_iprintf(buffer, " %03x", data->wm8785_regs[i]);
623 snd_iprintf(buffer, "\n");
624}
625
626static void dump_oxygen_registers(struct oxygen *chip,
627 struct snd_info_buffer *buffer)
628{
629 dump_ak4396_registers(chip, buffer);
630 dump_wm8785_registers(chip, buffer);
631}
632
d0ce9946
CL
633static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
634
635static const struct oxygen_model model_generic = {
636 .shortname = "C-Media CMI8788",
637 .longname = "C-Media Oxygen HD Audio",
638 .chip = "CMI8788",
d0ce9946 639 .init = generic_init,
1ff04886 640 .mixer_init = generic_wm8785_mixer_init,
d0ce9946 641 .cleanup = generic_cleanup,
4a4bc53b 642 .resume = generic_resume,
d0ce9946
CL
643 .set_dac_params = set_ak4396_params,
644 .set_adc_params = set_wm8785_params,
645 .update_dac_volume = update_ak4396_volume,
646 .update_dac_mute = update_ak4396_mute,
9719fcaa 647 .dump_registers = dump_oxygen_registers,
4972a177 648 .dac_tlv = ak4396_db_scale,
7ef37cd9 649 .model_data_size = sizeof(struct generic_data),
d76596b1
CL
650 .device_config = PLAYBACK_0_TO_I2S |
651 PLAYBACK_1_TO_SPDIF |
652 PLAYBACK_2_TO_AC97_1 |
653 CAPTURE_0_FROM_I2S_1 |
654 CAPTURE_1_FROM_SPDIF |
b6ca8ab3
CL
655 CAPTURE_2_FROM_AC97_1 |
656 AC97_CD_INPUT,
1f4d7be7
CL
657 .dac_channels_pcm = 8,
658 .dac_channels_mixer = 8,
193e8138
CL
659 .dac_volume_min = 0,
660 .dac_volume_max = 255,
87eedd2f
CL
661 .function_flags = OXYGEN_FUNCTION_SPI |
662 OXYGEN_FUNCTION_ENABLE_SPI_4_5,
ce2c4920 663 .dac_mclks = OXYGEN_MCLKS(256, 128, 128),
5b8bf2a5 664 .adc_mclks = OXYGEN_MCLKS(256, 256, 128),
05855ba3
CL
665 .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
666 .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
d0ce9946 667};
d0ce9946 668
30459d7b
CL
669static int __devinit get_oxygen_model(struct oxygen *chip,
670 const struct pci_device_id *id)
671{
672 chip->model = model_generic;
673 switch (id->driver_data) {
674 case MODEL_MERIDIAN:
675 chip->model.init = meridian_init;
64878dfb 676 chip->model.mixer_init = meridian_mixer_init;
30459d7b
CL
677 chip->model.resume = meridian_resume;
678 chip->model.set_adc_params = set_ak5385_params;
9719fcaa 679 chip->model.dump_registers = dump_ak4396_registers;
30459d7b
CL
680 chip->model.device_config = PLAYBACK_0_TO_I2S |
681 PLAYBACK_1_TO_SPDIF |
682 CAPTURE_0_FROM_I2S_2 |
683 CAPTURE_1_FROM_SPDIF;
684 break;
873591db
CL
685 case MODEL_CLARO:
686 chip->model.init = claro_init;
687 chip->model.cleanup = claro_cleanup;
688 chip->model.suspend = claro_suspend;
689 chip->model.resume = claro_resume;
690 break;
691 case MODEL_CLARO_HALO:
692 chip->model.init = claro_halo_init;
1ff04886 693 chip->model.mixer_init = generic_mixer_init;
873591db
CL
694 chip->model.cleanup = claro_cleanup;
695 chip->model.suspend = claro_suspend;
696 chip->model.resume = claro_resume;
d91b424d 697 chip->model.set_adc_params = set_ak5385_params;
9719fcaa 698 chip->model.dump_registers = dump_ak4396_registers;
0873a5ae
ES
699 chip->model.device_config = PLAYBACK_0_TO_I2S |
700 PLAYBACK_1_TO_SPDIF |
701 CAPTURE_0_FROM_I2S_2 |
702 CAPTURE_1_FROM_SPDIF;
d91b424d 703 break;
2146dcfd
CL
704 case MODEL_FANTASIA:
705 case MODEL_2CH_OUTPUT:
45c1de8e
CL
706 chip->model.shortname = "C-Media CMI8787";
707 chip->model.chip = "CMI8787";
2146dcfd
CL
708 if (id->driver_data == MODEL_FANTASIA)
709 chip->model.init = fantasia_init;
31f86bac 710 else
2146dcfd 711 chip->model.init = stereo_output_init;
45c1de8e
CL
712 chip->model.resume = stereo_resume;
713 chip->model.mixer_init = generic_mixer_init;
714 chip->model.set_adc_params = set_no_params;
9719fcaa 715 chip->model.dump_registers = dump_ak4396_registers;
45c1de8e 716 chip->model.device_config = PLAYBACK_0_TO_I2S |
31f86bac 717 PLAYBACK_1_TO_SPDIF;
ce2c4920 718 if (id->driver_data == MODEL_FANTASIA) {
31f86bac 719 chip->model.device_config |= CAPTURE_0_FROM_I2S_1;
ce2c4920
CL
720 chip->model.adc_mclks = OXYGEN_MCLKS(256, 128, 128);
721 }
1f4d7be7
CL
722 chip->model.dac_channels_pcm = 2;
723 chip->model.dac_channels_mixer = 2;
45c1de8e 724 break;
66410bfd
CL
725 case MODEL_XONAR_DG:
726 chip->model = model_xonar_dg;
727 break;
30459d7b
CL
728 }
729 if (id->driver_data == MODEL_MERIDIAN ||
873591db 730 id->driver_data == MODEL_CLARO_HALO) {
30459d7b
CL
731 chip->model.misc_flags = OXYGEN_MISC_MIDI;
732 chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT;
733 }
734 return 0;
735}
736
d0ce9946
CL
737static int __devinit generic_oxygen_probe(struct pci_dev *pci,
738 const struct pci_device_id *pci_id)
739{
740 static int dev;
d0ce9946
CL
741 int err;
742
743 if (dev >= SNDRV_CARDS)
744 return -ENODEV;
745 if (!enable[dev]) {
746 ++dev;
747 return -ENOENT;
748 }
bb718588 749 err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE,
30459d7b 750 oxygen_ids, get_oxygen_model);
d0ce9946
CL
751 if (err >= 0)
752 ++dev;
753 return err;
754}
755
756static struct pci_driver oxygen_driver = {
757 .name = "CMI8788",
758 .id_table = oxygen_ids,
759 .probe = generic_oxygen_probe,
760 .remove = __devexit_p(oxygen_pci_remove),
4a4bc53b
CL
761#ifdef CONFIG_PM
762 .suspend = oxygen_pci_suspend,
763 .resume = oxygen_pci_resume,
764#endif
d0ce9946
CL
765};
766
767static int __init alsa_card_oxygen_init(void)
768{
769 return pci_register_driver(&oxygen_driver);
770}
771
772static void __exit alsa_card_oxygen_exit(void)
773{
774 pci_unregister_driver(&oxygen_driver);
775}
776
777module_init(alsa_card_oxygen_init)
778module_exit(alsa_card_oxygen_exit)
This page took 0.419263 seconds and 5 git commands to generate.