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d0ce9946 CL |
1 | /* |
2 | * C-Media CMI8788 driver for C-Media's reference design and for the X-Meridian | |
3 | * | |
4 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
5 | * | |
6 | * | |
7 | * This driver is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License, version 2. | |
9 | * | |
10 | * This driver is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this driver; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | /* | |
21 | * SPI 0 -> 1st AK4396 (front) | |
7113e958 | 22 | * SPI 1 -> 2nd AK4396 (surround) |
d0ce9946 CL |
23 | * SPI 2 -> 3rd AK4396 (center/LFE) |
24 | * SPI 3 -> WM8785 | |
7113e958 | 25 | * SPI 4 -> 4th AK4396 (back) |
d0ce9946 CL |
26 | * |
27 | * GPIO 0 -> DFS0 of AK5385 | |
28 | * GPIO 1 -> DFS1 of AK5385 | |
29 | */ | |
30 | ||
902b05c1 | 31 | #include <linux/mutex.h> |
d0ce9946 | 32 | #include <linux/pci.h> |
902b05c1 | 33 | #include <sound/ac97_codec.h> |
ccc80fb4 | 34 | #include <sound/control.h> |
d0ce9946 CL |
35 | #include <sound/core.h> |
36 | #include <sound/initval.h> | |
37 | #include <sound/pcm.h> | |
38 | #include <sound/pcm_params.h> | |
39 | #include <sound/tlv.h> | |
40 | #include "oxygen.h" | |
c626026d | 41 | #include "ak4396.h" |
902b05c1 | 42 | #include "cm9780.h" |
d0ce9946 CL |
43 | |
44 | MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); | |
45 | MODULE_DESCRIPTION("C-Media CMI8788 driver"); | |
46 | MODULE_LICENSE("GPL"); | |
47 | MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8788}}"); | |
48 | ||
49 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; | |
50 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
51 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | |
52 | ||
53 | module_param_array(index, int, NULL, 0444); | |
54 | MODULE_PARM_DESC(index, "card index"); | |
55 | module_param_array(id, charp, NULL, 0444); | |
56 | MODULE_PARM_DESC(id, "ID string"); | |
57 | module_param_array(enable, bool, NULL, 0444); | |
58 | MODULE_PARM_DESC(enable, "enable card"); | |
59 | ||
60 | static struct pci_device_id oxygen_ids[] __devinitdata = { | |
61 | { OXYGEN_PCI_SUBID(0x10b0, 0x0216) }, | |
62 | { OXYGEN_PCI_SUBID(0x10b0, 0x0218) }, | |
63 | { OXYGEN_PCI_SUBID(0x10b0, 0x0219) }, | |
64 | { OXYGEN_PCI_SUBID(0x13f6, 0x0001) }, | |
65 | { OXYGEN_PCI_SUBID(0x13f6, 0x0010) }, | |
66 | { OXYGEN_PCI_SUBID(0x13f6, 0x8788) }, | |
67 | { OXYGEN_PCI_SUBID(0x147a, 0xa017) }, | |
d0ce9946 CL |
68 | { OXYGEN_PCI_SUBID(0x1a58, 0x0910) }, |
69 | { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = 1 }, | |
70 | { OXYGEN_PCI_SUBID(0x7284, 0x9761) }, | |
71 | { } | |
72 | }; | |
73 | MODULE_DEVICE_TABLE(pci, oxygen_ids); | |
74 | ||
878ac3ee CL |
75 | |
76 | #define GPIO_AK5385_DFS_MASK 0x0003 | |
77 | #define GPIO_AK5385_DFS_NORMAL 0x0000 | |
78 | #define GPIO_AK5385_DFS_DOUBLE 0x0001 | |
79 | #define GPIO_AK5385_DFS_QUAD 0x0002 | |
80 | ||
902b05c1 CL |
81 | #define GPIO_LINE_MUTE CM9780_GPO0 |
82 | ||
878ac3ee CL |
83 | #define WM8785_R0 0 |
84 | #define WM8785_R1 1 | |
85 | #define WM8785_R2 2 | |
86 | #define WM8785_R7 7 | |
87 | ||
88 | /* R0 */ | |
89 | #define WM8785_MCR_MASK 0x007 | |
90 | #define WM8785_MCR_SLAVE 0x000 | |
91 | #define WM8785_MCR_MASTER_128 0x001 | |
92 | #define WM8785_MCR_MASTER_192 0x002 | |
93 | #define WM8785_MCR_MASTER_256 0x003 | |
94 | #define WM8785_MCR_MASTER_384 0x004 | |
95 | #define WM8785_MCR_MASTER_512 0x005 | |
96 | #define WM8785_MCR_MASTER_768 0x006 | |
97 | #define WM8785_OSR_MASK 0x018 | |
d0ce9946 CL |
98 | #define WM8785_OSR_SINGLE 0x000 |
99 | #define WM8785_OSR_DOUBLE 0x008 | |
100 | #define WM8785_OSR_QUAD 0x010 | |
878ac3ee CL |
101 | #define WM8785_FORMAT_MASK 0x060 |
102 | #define WM8785_FORMAT_RJUST 0x000 | |
d0ce9946 CL |
103 | #define WM8785_FORMAT_LJUST 0x020 |
104 | #define WM8785_FORMAT_I2S 0x040 | |
878ac3ee CL |
105 | #define WM8785_FORMAT_DSP 0x060 |
106 | /* R1 */ | |
107 | #define WM8785_WL_MASK 0x003 | |
d0ce9946 CL |
108 | #define WM8785_WL_16 0x000 |
109 | #define WM8785_WL_20 0x001 | |
110 | #define WM8785_WL_24 0x002 | |
111 | #define WM8785_WL_32 0x003 | |
878ac3ee CL |
112 | #define WM8785_LRP 0x004 |
113 | #define WM8785_BCLKINV 0x008 | |
114 | #define WM8785_LRSWAP 0x010 | |
115 | #define WM8785_DEVNO_MASK 0x0e0 | |
116 | /* R2 */ | |
117 | #define WM8785_HPFR 0x001 | |
118 | #define WM8785_HPFL 0x002 | |
119 | #define WM8785_SDODIS 0x004 | |
120 | #define WM8785_PWRDNR 0x008 | |
121 | #define WM8785_PWRDNL 0x010 | |
122 | #define WM8785_TDM_MASK 0x1c0 | |
d0ce9946 | 123 | |
7ef37cd9 CL |
124 | struct generic_data { |
125 | u8 ak4396_ctl2; | |
126 | }; | |
127 | ||
d0ce9946 CL |
128 | static void ak4396_write(struct oxygen *chip, unsigned int codec, |
129 | u8 reg, u8 value) | |
130 | { | |
131 | /* maps ALSA channel pair number to SPI output */ | |
132 | static const u8 codec_spi_map[4] = { | |
7113e958 | 133 | 0, 1, 2, 4 |
d0ce9946 | 134 | }; |
c2353a08 | 135 | oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | |
d0ce9946 | 136 | OXYGEN_SPI_DATA_LENGTH_2 | |
2ea85986 | 137 | OXYGEN_SPI_CLOCK_160 | |
d0ce9946 | 138 | (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | |
c2353a08 | 139 | OXYGEN_SPI_CEN_LATCH_CLOCK_HI, |
d0ce9946 CL |
140 | AK4396_WRITE | (reg << 8) | value); |
141 | } | |
142 | ||
143 | static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value) | |
144 | { | |
c2353a08 | 145 | oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | |
d0ce9946 | 146 | OXYGEN_SPI_DATA_LENGTH_2 | |
2ea85986 | 147 | OXYGEN_SPI_CLOCK_160 | |
c2353a08 CL |
148 | (3 << OXYGEN_SPI_CODEC_SHIFT) | |
149 | OXYGEN_SPI_CEN_LATCH_CLOCK_LO, | |
d0ce9946 CL |
150 | (reg << 9) | value); |
151 | } | |
152 | ||
153 | static void ak4396_init(struct oxygen *chip) | |
154 | { | |
7ef37cd9 | 155 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
156 | unsigned int i; |
157 | ||
7ef37cd9 | 158 | data->ak4396_ctl2 = AK4396_DEM_OFF | AK4396_DFS_NORMAL; |
d0ce9946 | 159 | for (i = 0; i < 4; ++i) { |
878ac3ee CL |
160 | ak4396_write(chip, i, |
161 | AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_RSTN); | |
162 | ak4396_write(chip, i, | |
7ef37cd9 | 163 | AK4396_CONTROL_2, data->ak4396_ctl2); |
878ac3ee CL |
164 | ak4396_write(chip, i, |
165 | AK4396_CONTROL_3, AK4396_PCM); | |
166 | ak4396_write(chip, i, AK4396_LCH_ATT, 0xff); | |
167 | ak4396_write(chip, i, AK4396_RCH_ATT, 0xff); | |
d0ce9946 CL |
168 | } |
169 | snd_component_add(chip->card, "AK4396"); | |
170 | } | |
171 | ||
172 | static void ak5385_init(struct oxygen *chip) | |
173 | { | |
878ac3ee CL |
174 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK); |
175 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK); | |
d0ce9946 CL |
176 | snd_component_add(chip->card, "AK5385"); |
177 | } | |
178 | ||
179 | static void wm8785_init(struct oxygen *chip) | |
180 | { | |
878ac3ee CL |
181 | wm8785_write(chip, WM8785_R7, 0); |
182 | wm8785_write(chip, WM8785_R0, WM8785_MCR_SLAVE | | |
183 | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST); | |
184 | wm8785_write(chip, WM8785_R1, WM8785_WL_24); | |
d0ce9946 CL |
185 | snd_component_add(chip->card, "WM8785"); |
186 | } | |
187 | ||
902b05c1 CL |
188 | static void cmi9780_init(struct oxygen *chip) |
189 | { | |
190 | oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, GPIO_LINE_MUTE); | |
191 | } | |
192 | ||
d0ce9946 CL |
193 | static void generic_init(struct oxygen *chip) |
194 | { | |
195 | ak4396_init(chip); | |
196 | wm8785_init(chip); | |
902b05c1 | 197 | cmi9780_init(chip); |
d0ce9946 CL |
198 | } |
199 | ||
200 | static void meridian_init(struct oxygen *chip) | |
201 | { | |
202 | ak4396_init(chip); | |
203 | ak5385_init(chip); | |
902b05c1 | 204 | cmi9780_init(chip); |
d0ce9946 CL |
205 | } |
206 | ||
207 | static void generic_cleanup(struct oxygen *chip) | |
208 | { | |
209 | } | |
210 | ||
211 | static void set_ak4396_params(struct oxygen *chip, | |
212 | struct snd_pcm_hw_params *params) | |
213 | { | |
7ef37cd9 | 214 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
215 | unsigned int i; |
216 | u8 value; | |
217 | ||
7ef37cd9 | 218 | value = data->ak4396_ctl2 & ~AK4396_DFS_MASK; |
d0ce9946 CL |
219 | if (params_rate(params) <= 54000) |
220 | value |= AK4396_DFS_NORMAL; | |
236c4920 | 221 | else if (params_rate(params) <= 108000) |
d0ce9946 CL |
222 | value |= AK4396_DFS_DOUBLE; |
223 | else | |
224 | value |= AK4396_DFS_QUAD; | |
7ef37cd9 | 225 | data->ak4396_ctl2 = value; |
d0ce9946 | 226 | for (i = 0; i < 4; ++i) { |
878ac3ee CL |
227 | ak4396_write(chip, i, |
228 | AK4396_CONTROL_1, AK4396_DIF_24_MSB); | |
229 | ak4396_write(chip, i, | |
230 | AK4396_CONTROL_2, value); | |
231 | ak4396_write(chip, i, | |
232 | AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_RSTN); | |
d0ce9946 CL |
233 | } |
234 | } | |
235 | ||
236 | static void update_ak4396_volume(struct oxygen *chip) | |
237 | { | |
238 | unsigned int i; | |
239 | ||
240 | for (i = 0; i < 4; ++i) { | |
878ac3ee CL |
241 | ak4396_write(chip, i, |
242 | AK4396_LCH_ATT, chip->dac_volume[i * 2]); | |
243 | ak4396_write(chip, i, | |
244 | AK4396_RCH_ATT, chip->dac_volume[i * 2 + 1]); | |
d0ce9946 CL |
245 | } |
246 | } | |
247 | ||
248 | static void update_ak4396_mute(struct oxygen *chip) | |
249 | { | |
7ef37cd9 | 250 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
251 | unsigned int i; |
252 | u8 value; | |
253 | ||
7ef37cd9 | 254 | value = data->ak4396_ctl2 & ~AK4396_SMUTE; |
d0ce9946 CL |
255 | if (chip->dac_mute) |
256 | value |= AK4396_SMUTE; | |
7ef37cd9 | 257 | data->ak4396_ctl2 = value; |
d0ce9946 | 258 | for (i = 0; i < 4; ++i) |
878ac3ee | 259 | ak4396_write(chip, i, AK4396_CONTROL_2, value); |
d0ce9946 CL |
260 | } |
261 | ||
262 | static void set_wm8785_params(struct oxygen *chip, | |
263 | struct snd_pcm_hw_params *params) | |
264 | { | |
265 | unsigned int value; | |
266 | ||
878ac3ee | 267 | wm8785_write(chip, WM8785_R7, 0); |
d0ce9946 | 268 | |
878ac3ee | 269 | value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST; |
71e22a4b CL |
270 | if (params_rate(params) <= 48000) |
271 | value |= WM8785_OSR_SINGLE; | |
272 | else if (params_rate(params) <= 96000) | |
d0ce9946 | 273 | value |= WM8785_OSR_DOUBLE; |
d0ce9946 | 274 | else |
71e22a4b | 275 | value |= WM8785_OSR_QUAD; |
878ac3ee | 276 | wm8785_write(chip, WM8785_R0, value); |
d0ce9946 CL |
277 | |
278 | if (snd_pcm_format_width(params_format(params)) <= 16) | |
279 | value = WM8785_WL_16; | |
280 | else | |
281 | value = WM8785_WL_24; | |
878ac3ee | 282 | wm8785_write(chip, WM8785_R1, value); |
d0ce9946 CL |
283 | } |
284 | ||
285 | static void set_ak5385_params(struct oxygen *chip, | |
286 | struct snd_pcm_hw_params *params) | |
287 | { | |
288 | unsigned int value; | |
289 | ||
290 | if (params_rate(params) <= 54000) | |
878ac3ee | 291 | value = GPIO_AK5385_DFS_NORMAL; |
d0ce9946 | 292 | else if (params_rate(params) <= 108000) |
878ac3ee | 293 | value = GPIO_AK5385_DFS_DOUBLE; |
d0ce9946 | 294 | else |
878ac3ee CL |
295 | value = GPIO_AK5385_DFS_QUAD; |
296 | oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, | |
297 | value, GPIO_AK5385_DFS_MASK); | |
d0ce9946 CL |
298 | } |
299 | ||
902b05c1 CL |
300 | static void cmi9780_switch_hook(struct oxygen *chip, unsigned int codec, |
301 | unsigned int reg, int mute) | |
302 | { | |
303 | if (codec != 0) | |
304 | return; | |
305 | switch (reg) { | |
306 | case AC97_LINE: | |
307 | oxygen_write_ac97_masked(chip, 0, CM9780_GPIO_STATUS, | |
308 | mute ? GPIO_LINE_MUTE : 0, | |
309 | GPIO_LINE_MUTE); | |
310 | break; | |
311 | case AC97_MIC: | |
312 | case AC97_CD: | |
313 | case AC97_AUX: | |
314 | if (!mute) | |
315 | oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_STATUS, | |
316 | GPIO_LINE_MUTE); | |
317 | break; | |
318 | } | |
319 | } | |
320 | ||
d0ce9946 CL |
321 | static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0); |
322 | ||
ccc80fb4 CL |
323 | static int ak4396_control_filter(struct snd_kcontrol_new *template) |
324 | { | |
325 | if (!strcmp(template->name, "Master Playback Volume")) { | |
326 | template->access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ; | |
327 | template->tlv.p = ak4396_db_scale; | |
328 | } | |
329 | return 0; | |
330 | } | |
331 | ||
d0ce9946 CL |
332 | static const struct oxygen_model model_generic = { |
333 | .shortname = "C-Media CMI8788", | |
334 | .longname = "C-Media Oxygen HD Audio", | |
335 | .chip = "CMI8788", | |
336 | .owner = THIS_MODULE, | |
337 | .init = generic_init, | |
ccc80fb4 | 338 | .control_filter = ak4396_control_filter, |
d0ce9946 CL |
339 | .cleanup = generic_cleanup, |
340 | .set_dac_params = set_ak4396_params, | |
341 | .set_adc_params = set_wm8785_params, | |
342 | .update_dac_volume = update_ak4396_volume, | |
343 | .update_dac_mute = update_ak4396_mute, | |
902b05c1 | 344 | .ac97_switch_hook = cmi9780_switch_hook, |
7ef37cd9 | 345 | .model_data_size = sizeof(struct generic_data), |
976cd627 | 346 | .dac_channels = 8, |
e85e0925 CL |
347 | .used_channels = OXYGEN_CHANNEL_A | |
348 | OXYGEN_CHANNEL_C | | |
349 | OXYGEN_CHANNEL_SPDIF | | |
350 | OXYGEN_CHANNEL_MULTICH | | |
351 | OXYGEN_CHANNEL_AC97, | |
84aa6b7b | 352 | .function_flags = OXYGEN_FUNCTION_ENABLE_SPI_4_5, |
05855ba3 CL |
353 | .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, |
354 | .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, | |
d0ce9946 CL |
355 | }; |
356 | static const struct oxygen_model model_meridian = { | |
357 | .shortname = "C-Media CMI8788", | |
358 | .longname = "C-Media Oxygen HD Audio", | |
359 | .chip = "CMI8788", | |
360 | .owner = THIS_MODULE, | |
361 | .init = meridian_init, | |
ccc80fb4 | 362 | .control_filter = ak4396_control_filter, |
d0ce9946 CL |
363 | .cleanup = generic_cleanup, |
364 | .set_dac_params = set_ak4396_params, | |
365 | .set_adc_params = set_ak5385_params, | |
366 | .update_dac_volume = update_ak4396_volume, | |
367 | .update_dac_mute = update_ak4396_mute, | |
902b05c1 | 368 | .ac97_switch_hook = cmi9780_switch_hook, |
7ef37cd9 | 369 | .model_data_size = sizeof(struct generic_data), |
976cd627 | 370 | .dac_channels = 8, |
e85e0925 CL |
371 | .used_channels = OXYGEN_CHANNEL_B | |
372 | OXYGEN_CHANNEL_C | | |
373 | OXYGEN_CHANNEL_SPDIF | | |
374 | OXYGEN_CHANNEL_MULTICH | | |
375 | OXYGEN_CHANNEL_AC97, | |
84aa6b7b | 376 | .function_flags = OXYGEN_FUNCTION_ENABLE_SPI_4_5, |
05855ba3 CL |
377 | .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, |
378 | .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, | |
d0ce9946 CL |
379 | }; |
380 | ||
381 | static int __devinit generic_oxygen_probe(struct pci_dev *pci, | |
382 | const struct pci_device_id *pci_id) | |
383 | { | |
384 | static int dev; | |
cd93dc8c | 385 | int is_meridian; |
d0ce9946 CL |
386 | int err; |
387 | ||
388 | if (dev >= SNDRV_CARDS) | |
389 | return -ENODEV; | |
390 | if (!enable[dev]) { | |
391 | ++dev; | |
392 | return -ENOENT; | |
393 | } | |
cd93dc8c CL |
394 | is_meridian = pci_id->driver_data; |
395 | err = oxygen_pci_probe(pci, index[dev], id[dev], is_meridian, | |
396 | is_meridian ? &model_meridian : &model_generic); | |
d0ce9946 CL |
397 | if (err >= 0) |
398 | ++dev; | |
399 | return err; | |
400 | } | |
401 | ||
402 | static struct pci_driver oxygen_driver = { | |
403 | .name = "CMI8788", | |
404 | .id_table = oxygen_ids, | |
405 | .probe = generic_oxygen_probe, | |
406 | .remove = __devexit_p(oxygen_pci_remove), | |
407 | }; | |
408 | ||
409 | static int __init alsa_card_oxygen_init(void) | |
410 | { | |
411 | return pci_register_driver(&oxygen_driver); | |
412 | } | |
413 | ||
414 | static void __exit alsa_card_oxygen_exit(void) | |
415 | { | |
416 | pci_unregister_driver(&oxygen_driver); | |
417 | } | |
418 | ||
419 | module_init(alsa_card_oxygen_init) | |
420 | module_exit(alsa_card_oxygen_exit) |