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serial: 8250_dw: get index of serial line from DT aliases
[deliverable/linux.git] / sound / pci / rme96.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1da177e4
LT		 26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/pci.h>
65a77217 30#include <linux/module.h>
a8cc2099 31#include <linux/vmalloc.h>
1da177e4
LT		 32
33#include <sound/core.h>
34#include <sound/info.h>
35#include <sound/control.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/asoundef.h>
39#include <sound/initval.h>
40
41#include <asm/io.h>
42
43/* note, two last pcis should be equal, it is not a bug */
44
45MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
46MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
47 "Digi96/8 PAD");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
50 "{RME,Digi96/8},"
51 "{RME,Digi96/8 PRO},"
52 "{RME,Digi96/8 PST},"
53 "{RME,Digi96/8 PAD}}");
54
55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 57static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 58
59module_param_array(index, int, NULL, 0444);
60MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
61module_param_array(id, charp, NULL, 0444);
62MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
63module_param_array(enable, bool, NULL, 0444);
64MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
65
66/*
67 * Defines for RME Digi96 series, from internal RME reference documents
68 * dated 12.01.00
69 */
70
71#define RME96_SPDIF_NCHANNELS 2
72
73/* Playback and capture buffer size */
74#define RME96_BUFFER_SIZE 0x10000
75
76/* IO area size */
77#define RME96_IO_SIZE 0x60000
78
79/* IO area offsets */
80#define RME96_IO_PLAY_BUFFER 0x0
81#define RME96_IO_REC_BUFFER 0x10000
82#define RME96_IO_CONTROL_REGISTER 0x20000
83#define RME96_IO_ADDITIONAL_REG 0x20004
84#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
85#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
86#define RME96_IO_SET_PLAY_POS 0x40000
87#define RME96_IO_RESET_PLAY_POS 0x4FFFC
88#define RME96_IO_SET_REC_POS 0x50000
89#define RME96_IO_RESET_REC_POS 0x5FFFC
90#define RME96_IO_GET_PLAY_POS 0x20000
91#define RME96_IO_GET_REC_POS 0x30000
92
93/* Write control register bits */
94#define RME96_WCR_START (1 << 0)
95#define RME96_WCR_START_2 (1 << 1)
96#define RME96_WCR_GAIN_0 (1 << 2)
97#define RME96_WCR_GAIN_1 (1 << 3)
98#define RME96_WCR_MODE24 (1 << 4)
99#define RME96_WCR_MODE24_2 (1 << 5)
100#define RME96_WCR_BM (1 << 6)
101#define RME96_WCR_BM_2 (1 << 7)
102#define RME96_WCR_ADAT (1 << 8)
103#define RME96_WCR_FREQ_0 (1 << 9)
104#define RME96_WCR_FREQ_1 (1 << 10)
105#define RME96_WCR_DS (1 << 11)
106#define RME96_WCR_PRO (1 << 12)
107#define RME96_WCR_EMP (1 << 13)
108#define RME96_WCR_SEL (1 << 14)
109#define RME96_WCR_MASTER (1 << 15)
110#define RME96_WCR_PD (1 << 16)
111#define RME96_WCR_INP_0 (1 << 17)
112#define RME96_WCR_INP_1 (1 << 18)
113#define RME96_WCR_THRU_0 (1 << 19)
114#define RME96_WCR_THRU_1 (1 << 20)
115#define RME96_WCR_THRU_2 (1 << 21)
116#define RME96_WCR_THRU_3 (1 << 22)
117#define RME96_WCR_THRU_4 (1 << 23)
118#define RME96_WCR_THRU_5 (1 << 24)
119#define RME96_WCR_THRU_6 (1 << 25)
120#define RME96_WCR_THRU_7 (1 << 26)
121#define RME96_WCR_DOLBY (1 << 27)
122#define RME96_WCR_MONITOR_0 (1 << 28)
123#define RME96_WCR_MONITOR_1 (1 << 29)
124#define RME96_WCR_ISEL (1 << 30)
125#define RME96_WCR_IDIS (1 << 31)
126
127#define RME96_WCR_BITPOS_GAIN_0 2
128#define RME96_WCR_BITPOS_GAIN_1 3
129#define RME96_WCR_BITPOS_FREQ_0 9
130#define RME96_WCR_BITPOS_FREQ_1 10
131#define RME96_WCR_BITPOS_INP_0 17
132#define RME96_WCR_BITPOS_INP_1 18
133#define RME96_WCR_BITPOS_MONITOR_0 28
134#define RME96_WCR_BITPOS_MONITOR_1 29
135
136/* Read control register bits */
137#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
138#define RME96_RCR_IRQ_2 (1 << 16)
139#define RME96_RCR_T_OUT (1 << 17)
140#define RME96_RCR_DEV_ID_0 (1 << 21)
141#define RME96_RCR_DEV_ID_1 (1 << 22)
142#define RME96_RCR_LOCK (1 << 23)
143#define RME96_RCR_VERF (1 << 26)
144#define RME96_RCR_F0 (1 << 27)
145#define RME96_RCR_F1 (1 << 28)
146#define RME96_RCR_F2 (1 << 29)
147#define RME96_RCR_AUTOSYNC (1 << 30)
148#define RME96_RCR_IRQ (1 << 31)
149
150#define RME96_RCR_BITPOS_F0 27
151#define RME96_RCR_BITPOS_F1 28
152#define RME96_RCR_BITPOS_F2 29
153
25985edc 154/* Additional register bits */
1da177e4
LT		 155#define RME96_AR_WSEL (1 << 0)
156#define RME96_AR_ANALOG (1 << 1)
157#define RME96_AR_FREQPAD_0 (1 << 2)
158#define RME96_AR_FREQPAD_1 (1 << 3)
159#define RME96_AR_FREQPAD_2 (1 << 4)
160#define RME96_AR_PD2 (1 << 5)
161#define RME96_AR_DAC_EN (1 << 6)
162#define RME96_AR_CLATCH (1 << 7)
163#define RME96_AR_CCLK (1 << 8)
164#define RME96_AR_CDATA (1 << 9)
165
166#define RME96_AR_BITPOS_F0 2
167#define RME96_AR_BITPOS_F1 3
168#define RME96_AR_BITPOS_F2 4
169
170/* Monitor tracks */
171#define RME96_MONITOR_TRACKS_1_2 0
172#define RME96_MONITOR_TRACKS_3_4 1
173#define RME96_MONITOR_TRACKS_5_6 2
174#define RME96_MONITOR_TRACKS_7_8 3
175
176/* Attenuation */
177#define RME96_ATTENUATION_0 0
178#define RME96_ATTENUATION_6 1
179#define RME96_ATTENUATION_12 2
180#define RME96_ATTENUATION_18 3
181
182/* Input types */
183#define RME96_INPUT_OPTICAL 0
184#define RME96_INPUT_COAXIAL 1
185#define RME96_INPUT_INTERNAL 2
186#define RME96_INPUT_XLR 3
187#define RME96_INPUT_ANALOG 4
188
189/* Clock modes */
190#define RME96_CLOCKMODE_SLAVE 0
191#define RME96_CLOCKMODE_MASTER 1
192#define RME96_CLOCKMODE_WORDCLOCK 2
193
194/* Block sizes in bytes */
195#define RME96_SMALL_BLOCK_SIZE 2048
196#define RME96_LARGE_BLOCK_SIZE 8192
197
198/* Volume control */
199#define RME96_AD1852_VOL_BITS 14
200#define RME96_AD1855_VOL_BITS 10
201
b892ca1c
KP		 202/* Defines for snd_rme96_trigger */
203#define RME96_TB_START_PLAYBACK 1
204#define RME96_TB_START_CAPTURE 2
205#define RME96_TB_STOP_PLAYBACK 4
206#define RME96_TB_STOP_CAPTURE 8
207#define RME96_TB_RESET_PLAYPOS 16
208#define RME96_TB_RESET_CAPTUREPOS 32
209#define RME96_TB_CLEAR_PLAYBACK_IRQ 64
210#define RME96_TB_CLEAR_CAPTURE_IRQ 128
211#define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
212#define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
213#define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
214 | RME96_RESUME_CAPTURE)
215#define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
216 | RME96_TB_RESET_PLAYPOS)
217#define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
218 | RME96_TB_RESET_CAPTUREPOS)
219#define RME96_START_BOTH (RME96_START_PLAYBACK \
220 | RME96_START_CAPTURE)
221#define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
222 | RME96_TB_CLEAR_PLAYBACK_IRQ)
223#define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
224 | RME96_TB_CLEAR_CAPTURE_IRQ)
225#define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
226 | RME96_STOP_CAPTURE)
1da177e4 227
a3aefd88 228struct rme96 {
1da177e4
LT		 229 spinlock_t lock;
230 int irq;
231 unsigned long port;
232 void __iomem *iobase;
233
234 u32 wcreg; /* cached write control register value */
235 u32 wcreg_spdif; /* S/PDIF setup */
236 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
237 u32 rcreg; /* cached read control register value */
238 u32 areg; /* cached additional register value */
239 u16 vol[2]; /* cached volume of analog output */
240
241 u8 rev; /* card revision number */
242
a932be91 243#ifdef CONFIG_PM_SLEEP
528ba522
KP		 244 u32 playback_pointer;
245 u32 capture_pointer;
246 void *playback_suspend_buffer;
247 void *capture_suspend_buffer;
248#endif
249
a3aefd88
TI		 250 struct snd_pcm_substream *playback_substream;
251 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 252
253 int playback_frlog; /* log2 of framesize */
254 int capture_frlog;
255
256 size_t playback_periodsize; /* in bytes, zero if not used */
257 size_t capture_periodsize; /* in bytes, zero if not used */
258
a3aefd88
TI		 259 struct snd_card *card;
260 struct snd_pcm *spdif_pcm;
261 struct snd_pcm *adat_pcm;
1da177e4 262 struct pci_dev *pci;
a3aefd88
TI		 263 struct snd_kcontrol *spdif_ctl;
264};
1da177e4 265
9baa3c34 266static const struct pci_device_id snd_rme96_ids[] = {
28d27aae
JP		 267 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
268 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
269 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
270 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
1da177e4
LT		 271 { 0, }
272};
273
274MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
275
276#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
277#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
8b7fc421
RD		 278#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
279#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
280 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
1da177e4 281#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
8b7fc421
RD		 282#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
283 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
1da177e4
LT		 284#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
285
286static int
a3aefd88 287snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 288
289static int
a3aefd88 290snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 291
292static int
a3aefd88 293snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 294 int cmd);
295
296static int
a3aefd88 297snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 298 int cmd);
299
300static snd_pcm_uframes_t
a3aefd88 301snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
1da177e4
LT		 302
303static snd_pcm_uframes_t
a3aefd88 304snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
1da177e4 305
e23e7a14 306static void snd_rme96_proc_init(struct rme96 *rme96);
1da177e4
LT		 307
308static int
a3aefd88
TI		 309snd_rme96_create_switches(struct snd_card *card,
310 struct rme96 *rme96);
1da177e4
LT		 311
312static int
a3aefd88 313snd_rme96_getinputtype(struct rme96 *rme96);
1da177e4
LT		 314
315static inline unsigned int
a3aefd88 316snd_rme96_playback_ptr(struct rme96 *rme96)
1da177e4
LT		 317{
318 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
319 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
320}
321
322static inline unsigned int
a3aefd88 323snd_rme96_capture_ptr(struct rme96 *rme96)
1da177e4
LT		 324{
325 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
326 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
327}
328
1da177e4 329static int
a3aefd88 330snd_rme96_playback_silence(struct snd_pcm_substream *substream,
1da177e4
LT		 331 int channel, /* not used (interleaved data) */
332 snd_pcm_uframes_t pos,
333 snd_pcm_uframes_t count)
334{
a3aefd88 335 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 336 count <<= rme96->playback_frlog;
337 pos <<= rme96->playback_frlog;
338 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
339 0, count);
340 return 0;
341}
342
343static int
a3aefd88 344snd_rme96_playback_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 345 int channel, /* not used (interleaved data) */
346 snd_pcm_uframes_t pos,
347 void __user *src,
348 snd_pcm_uframes_t count)
349{
a3aefd88 350 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 351 count <<= rme96->playback_frlog;
352 pos <<= rme96->playback_frlog;
2026d24e
TI		 353 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
354 count);
1da177e4
LT		 355}
356
357static int
a3aefd88 358snd_rme96_capture_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 359 int channel, /* not used (interleaved data) */
360 snd_pcm_uframes_t pos,
361 void __user *dst,
362 snd_pcm_uframes_t count)
363{
a3aefd88 364 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 365 count <<= rme96->capture_frlog;
366 pos <<= rme96->capture_frlog;
2026d24e
TI		 367 return copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
368 count);
1da177e4
LT		 369}
370
371/*
7f927fcc 372 * Digital output capabilities (S/PDIF)
1da177e4 373 */
a3aefd88 374static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
1da177e4
LT		 375{
376 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
377 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 378 SNDRV_PCM_INFO_SYNC_START |
528ba522 379 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 380 SNDRV_PCM_INFO_INTERLEAVED |
381 SNDRV_PCM_INFO_PAUSE),
382 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
383 SNDRV_PCM_FMTBIT_S32_LE),
384 .rates = (SNDRV_PCM_RATE_32000 |
385 SNDRV_PCM_RATE_44100 |
386 SNDRV_PCM_RATE_48000 |
387 SNDRV_PCM_RATE_64000 |
388 SNDRV_PCM_RATE_88200 |
389 SNDRV_PCM_RATE_96000),
390 .rate_min = 32000,
391 .rate_max = 96000,
392 .channels_min = 2,
393 .channels_max = 2,
394 .buffer_bytes_max = RME96_BUFFER_SIZE,
395 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
396 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
397 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
398 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
399 .fifo_size = 0,
400};
401
402/*
7f927fcc 403 * Digital input capabilities (S/PDIF)
1da177e4 404 */
a3aefd88 405static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
1da177e4
LT		 406{
407 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
408 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 409 SNDRV_PCM_INFO_SYNC_START |
528ba522 410 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 411 SNDRV_PCM_INFO_INTERLEAVED |
412 SNDRV_PCM_INFO_PAUSE),
413 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
414 SNDRV_PCM_FMTBIT_S32_LE),
415 .rates = (SNDRV_PCM_RATE_32000 |
416 SNDRV_PCM_RATE_44100 |
417 SNDRV_PCM_RATE_48000 |
418 SNDRV_PCM_RATE_64000 |
419 SNDRV_PCM_RATE_88200 |
420 SNDRV_PCM_RATE_96000),
421 .rate_min = 32000,
422 .rate_max = 96000,
423 .channels_min = 2,
424 .channels_max = 2,
425 .buffer_bytes_max = RME96_BUFFER_SIZE,
426 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
427 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
428 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
429 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
430 .fifo_size = 0,
431};
432
433/*
7f927fcc 434 * Digital output capabilities (ADAT)
1da177e4 435 */
a3aefd88 436static struct snd_pcm_hardware snd_rme96_playback_adat_info =
1da177e4
LT		 437{
438 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
439 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 440 SNDRV_PCM_INFO_SYNC_START |
528ba522 441 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 442 SNDRV_PCM_INFO_INTERLEAVED |
443 SNDRV_PCM_INFO_PAUSE),
444 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
445 SNDRV_PCM_FMTBIT_S32_LE),
446 .rates = (SNDRV_PCM_RATE_44100 |
447 SNDRV_PCM_RATE_48000),
448 .rate_min = 44100,
449 .rate_max = 48000,
450 .channels_min = 8,
451 .channels_max = 8,
452 .buffer_bytes_max = RME96_BUFFER_SIZE,
453 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
454 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
455 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
456 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
457 .fifo_size = 0,
458};
459
460/*
7f927fcc 461 * Digital input capabilities (ADAT)
1da177e4 462 */
a3aefd88 463static struct snd_pcm_hardware snd_rme96_capture_adat_info =
1da177e4
LT		 464{
465 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
466 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 467 SNDRV_PCM_INFO_SYNC_START |
528ba522 468 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 469 SNDRV_PCM_INFO_INTERLEAVED |
470 SNDRV_PCM_INFO_PAUSE),
471 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
472 SNDRV_PCM_FMTBIT_S32_LE),
473 .rates = (SNDRV_PCM_RATE_44100 |
474 SNDRV_PCM_RATE_48000),
475 .rate_min = 44100,
476 .rate_max = 48000,
477 .channels_min = 8,
478 .channels_max = 8,
479 .buffer_bytes_max = RME96_BUFFER_SIZE,
480 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
481 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
482 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
483 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
484 .fifo_size = 0,
485};
486
487/*
488 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
489 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
490 * on the falling edge of CCLK and be stable on the rising edge. The rising
491 * edge of CLATCH after the last data bit clocks in the whole data word.
492 * A fast processor could probably drive the SPI interface faster than the
493 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
494 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
495 *
496 * NOTE: increased delay from 1 to 10, since there where problems setting
497 * the volume.
498 */
499static void
a3aefd88 500snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
1da177e4
LT		 501{
502 int i;
503
504 for (i = 0; i < 16; i++) {
505 if (val & 0x8000) {
506 rme96->areg |= RME96_AR_CDATA;
507 } else {
508 rme96->areg &= ~RME96_AR_CDATA;
509 }
510 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
511 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
512 udelay(10);
513 rme96->areg |= RME96_AR_CCLK;
514 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
515 udelay(10);
516 val <<= 1;
517 }
518 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
519 rme96->areg |= RME96_AR_CLATCH;
520 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
521 udelay(10);
522 rme96->areg &= ~RME96_AR_CLATCH;
523 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
524}
525
526static void
a3aefd88 527snd_rme96_apply_dac_volume(struct rme96 *rme96)
1da177e4
LT		 528{
529 if (RME96_DAC_IS_1852(rme96)) {
530 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
531 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
532 } else if (RME96_DAC_IS_1855(rme96)) {
533 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
534 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
535 }
536}
537
538static void
a3aefd88 539snd_rme96_reset_dac(struct rme96 *rme96)
1da177e4
LT		 540{
541 writel(rme96->wcreg | RME96_WCR_PD,
542 rme96->iobase + RME96_IO_CONTROL_REGISTER);
543 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
544}
545
546static int
a3aefd88 547snd_rme96_getmontracks(struct rme96 *rme96)
1da177e4
LT		 548{
549 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
550 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
551}
552
553static int
a3aefd88 554snd_rme96_setmontracks(struct rme96 *rme96,
1da177e4
LT		 555 int montracks)
556{
557 if (montracks & 1) {
558 rme96->wcreg |= RME96_WCR_MONITOR_0;
559 } else {
560 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
561 }
562 if (montracks & 2) {
563 rme96->wcreg |= RME96_WCR_MONITOR_1;
564 } else {
565 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
566 }
567 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
568 return 0;
569}
570
571static int
a3aefd88 572snd_rme96_getattenuation(struct rme96 *rme96)
1da177e4
LT		 573{
574 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
575 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
576}
577
578static int
a3aefd88 579snd_rme96_setattenuation(struct rme96 *rme96,
1da177e4
LT		 580 int attenuation)
581{
582 switch (attenuation) {
583 case 0:
584 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
585 ~RME96_WCR_GAIN_1;
586 break;
587 case 1:
588 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
589 ~RME96_WCR_GAIN_1;
590 break;
591 case 2:
592 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
593 RME96_WCR_GAIN_1;
594 break;
595 case 3:
596 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
597 RME96_WCR_GAIN_1;
598 break;
599 default:
600 return -EINVAL;
601 }
602 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
603 return 0;
604}
605
606static int
a3aefd88 607snd_rme96_capture_getrate(struct rme96 *rme96,
1da177e4
LT		 608 int *is_adat)
609{
610 int n, rate;
611
612 *is_adat = 0;
613 if (rme96->areg & RME96_AR_ANALOG) {
614 /* Analog input, overrides S/PDIF setting */
615 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
616 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
617 switch (n) {
618 case 1:
619 rate = 32000;
620 break;
621 case 2:
622 rate = 44100;
623 break;
624 case 3:
625 rate = 48000;
626 break;
627 default:
628 return -1;
629 }
630 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
631 }
632
633 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
634 if (rme96->rcreg & RME96_RCR_LOCK) {
635 /* ADAT rate */
636 *is_adat = 1;
637 if (rme96->rcreg & RME96_RCR_T_OUT) {
638 return 48000;
639 }
640 return 44100;
641 }
642
643 if (rme96->rcreg & RME96_RCR_VERF) {
644 return -1;
645 }
646
647 /* S/PDIF rate */
648 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
649 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
650 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
651
652 switch (n) {
653 case 0:
654 if (rme96->rcreg & RME96_RCR_T_OUT) {
655 return 64000;
656 }
657 return -1;
658 case 3: return 96000;
659 case 4: return 88200;
660 case 5: return 48000;
661 case 6: return 44100;
662 case 7: return 32000;
663 default:
664 break;
665 }
666 return -1;
667}
668
669static int
a3aefd88 670snd_rme96_playback_getrate(struct rme96 *rme96)
1da177e4
LT		 671{
672 int rate, dummy;
673
674 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
675 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
676 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
677 {
678 /* slave clock */
679 return rate;
680 }
681 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
682 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
683 switch (rate) {
684 case 1:
685 rate = 32000;
686 break;
687 case 2:
688 rate = 44100;
689 break;
690 case 3:
691 rate = 48000;
692 break;
693 default:
694 return -1;
695 }
696 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
697}
698
699static int
a3aefd88 700snd_rme96_playback_setrate(struct rme96 *rme96,
1da177e4
LT		 701 int rate)
702{
703 int ds;
704
705 ds = rme96->wcreg & RME96_WCR_DS;
706 switch (rate) {
707 case 32000:
708 rme96->wcreg &= ~RME96_WCR_DS;
709 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
710 ~RME96_WCR_FREQ_1;
711 break;
712 case 44100:
713 rme96->wcreg &= ~RME96_WCR_DS;
714 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
715 ~RME96_WCR_FREQ_0;
716 break;
717 case 48000:
718 rme96->wcreg &= ~RME96_WCR_DS;
719 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
720 RME96_WCR_FREQ_1;
721 break;
722 case 64000:
723 rme96->wcreg |= RME96_WCR_DS;
724 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
725 ~RME96_WCR_FREQ_1;
726 break;
727 case 88200:
728 rme96->wcreg |= RME96_WCR_DS;
729 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
730 ~RME96_WCR_FREQ_0;
731 break;
732 case 96000:
733 rme96->wcreg |= RME96_WCR_DS;
734 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
735 RME96_WCR_FREQ_1;
736 break;
737 default:
738 return -EINVAL;
739 }
740 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
741 (ds && !(rme96->wcreg & RME96_WCR_DS)))
742 {
743 /* change to/from double-speed: reset the DAC (if available) */
744 snd_rme96_reset_dac(rme96);
745 } else {
746 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
747 }
748 return 0;
749}
750
751static int
a3aefd88 752snd_rme96_capture_analog_setrate(struct rme96 *rme96,
1da177e4
LT		 753 int rate)
754{
755 switch (rate) {
756 case 32000:
757 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
758 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
759 break;
760 case 44100:
761 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
762 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
763 break;
764 case 48000:
765 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
766 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
767 break;
768 case 64000:
769 if (rme96->rev < 4) {
770 return -EINVAL;
771 }
772 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
773 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
774 break;
775 case 88200:
776 if (rme96->rev < 4) {
777 return -EINVAL;
778 }
779 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
780 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
781 break;
782 case 96000:
783 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
784 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
785 break;
786 default:
787 return -EINVAL;
788 }
789 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
790 return 0;
791}
792
793static int
a3aefd88 794snd_rme96_setclockmode(struct rme96 *rme96,
1da177e4
LT		 795 int mode)
796{
797 switch (mode) {
798 case RME96_CLOCKMODE_SLAVE:
799 /* AutoSync */
800 rme96->wcreg &= ~RME96_WCR_MASTER;
801 rme96->areg &= ~RME96_AR_WSEL;
802 break;
803 case RME96_CLOCKMODE_MASTER:
804 /* Internal */
805 rme96->wcreg |= RME96_WCR_MASTER;
806 rme96->areg &= ~RME96_AR_WSEL;
807 break;
808 case RME96_CLOCKMODE_WORDCLOCK:
809 /* Word clock is a master mode */
810 rme96->wcreg |= RME96_WCR_MASTER;
811 rme96->areg |= RME96_AR_WSEL;
812 break;
813 default:
814 return -EINVAL;
815 }
816 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
817 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
818 return 0;
819}
820
821static int
a3aefd88 822snd_rme96_getclockmode(struct rme96 *rme96)
1da177e4
LT		 823{
824 if (rme96->areg & RME96_AR_WSEL) {
825 return RME96_CLOCKMODE_WORDCLOCK;
826 }
827 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
828 RME96_CLOCKMODE_SLAVE;
829}
830
831static int
a3aefd88 832snd_rme96_setinputtype(struct rme96 *rme96,
1da177e4
LT		 833 int type)
834{
835 int n;
836
837 switch (type) {
838 case RME96_INPUT_OPTICAL:
839 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
840 ~RME96_WCR_INP_1;
841 break;
842 case RME96_INPUT_COAXIAL:
843 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
844 ~RME96_WCR_INP_1;
845 break;
846 case RME96_INPUT_INTERNAL:
847 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
848 RME96_WCR_INP_1;
849 break;
850 case RME96_INPUT_XLR:
8b7fc421
RD		 851 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
852 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
853 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
1da177e4
LT		 854 rme96->rev > 4))
855 {
856 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
857 return -EINVAL;
858 }
859 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
860 RME96_WCR_INP_1;
861 break;
862 case RME96_INPUT_ANALOG:
863 if (!RME96_HAS_ANALOG_IN(rme96)) {
864 return -EINVAL;
865 }
866 rme96->areg |= RME96_AR_ANALOG;
867 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
868 if (rme96->rev < 4) {
869 /*
870 * Revision less than 004 does not support 64 and
871 * 88.2 kHz
872 */
873 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
874 snd_rme96_capture_analog_setrate(rme96, 44100);
875 }
876 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
877 snd_rme96_capture_analog_setrate(rme96, 32000);
878 }
879 }
880 return 0;
881 default:
882 return -EINVAL;
883 }
884 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
885 rme96->areg &= ~RME96_AR_ANALOG;
886 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
887 }
888 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
889 return 0;
890}
891
892static int
a3aefd88 893snd_rme96_getinputtype(struct rme96 *rme96)
1da177e4
LT		 894{
895 if (rme96->areg & RME96_AR_ANALOG) {
896 return RME96_INPUT_ANALOG;
897 }
898 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
899 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
900}
901
902static void
a3aefd88 903snd_rme96_setframelog(struct rme96 *rme96,
1da177e4
LT		 904 int n_channels,
905 int is_playback)
906{
907 int frlog;
908
909 if (n_channels == 2) {
910 frlog = 1;
911 } else {
912 /* assume 8 channels */
913 frlog = 3;
914 }
915 if (is_playback) {
916 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
917 rme96->playback_frlog = frlog;
918 } else {
919 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
920 rme96->capture_frlog = frlog;
921 }
922}
923
924static int
a3aefd88 925snd_rme96_playback_setformat(struct rme96 *rme96,
1da177e4
LT		 926 int format)
927{
928 switch (format) {
929 case SNDRV_PCM_FORMAT_S16_LE:
930 rme96->wcreg &= ~RME96_WCR_MODE24;
931 break;
932 case SNDRV_PCM_FORMAT_S32_LE:
933 rme96->wcreg |= RME96_WCR_MODE24;
934 break;
935 default:
936 return -EINVAL;
937 }
938 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
939 return 0;
940}
941
942static int
a3aefd88 943snd_rme96_capture_setformat(struct rme96 *rme96,
1da177e4
LT		 944 int format)
945{
946 switch (format) {
947 case SNDRV_PCM_FORMAT_S16_LE:
948 rme96->wcreg &= ~RME96_WCR_MODE24_2;
949 break;
950 case SNDRV_PCM_FORMAT_S32_LE:
951 rme96->wcreg |= RME96_WCR_MODE24_2;
952 break;
953 default:
954 return -EINVAL;
955 }
956 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
957 return 0;
958}
959
960static void
a3aefd88 961snd_rme96_set_period_properties(struct rme96 *rme96,
1da177e4
LT		 962 size_t period_bytes)
963{
964 switch (period_bytes) {
965 case RME96_LARGE_BLOCK_SIZE:
966 rme96->wcreg &= ~RME96_WCR_ISEL;
967 break;
968 case RME96_SMALL_BLOCK_SIZE:
969 rme96->wcreg |= RME96_WCR_ISEL;
970 break;
971 default:
972 snd_BUG();
973 break;
974 }
975 rme96->wcreg &= ~RME96_WCR_IDIS;
976 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
977}
978
979static int
a3aefd88
TI		 980snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
981 struct snd_pcm_hw_params *params)
1da177e4 982{
a3aefd88
TI		 983 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
984 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 985 int err, rate, dummy;
986
4d23359b
CL		 987 runtime->dma_area = (void __force *)(rme96->iobase +
988 RME96_IO_PLAY_BUFFER);
1da177e4
LT		 989 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
990 runtime->dma_bytes = RME96_BUFFER_SIZE;
991
992 spin_lock_irq(&rme96->lock);
993 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
994 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
995 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
996 {
997 /* slave clock */
998 if ((int)params_rate(params) != rate) {
999 spin_unlock_irq(&rme96->lock);
1000 return -EIO;
1001 }
1002 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1003 spin_unlock_irq(&rme96->lock);
1004 return err;
1005 }
1006 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1007 spin_unlock_irq(&rme96->lock);
1008 return err;
1009 }
1010 snd_rme96_setframelog(rme96, params_channels(params), 1);
1011 if (rme96->capture_periodsize != 0) {
1012 if (params_period_size(params) << rme96->playback_frlog !=
1013 rme96->capture_periodsize)
1014 {
1015 spin_unlock_irq(&rme96->lock);
1016 return -EBUSY;
1017 }
1018 }
1019 rme96->playback_periodsize =
1020 params_period_size(params) << rme96->playback_frlog;
1021 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1022 /* S/PDIF setup */
1023 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1024 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1025 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1026 }
1027 spin_unlock_irq(&rme96->lock);
1028
1029 return 0;
1030}
1031
1032static int
a3aefd88
TI		 1033snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1034 struct snd_pcm_hw_params *params)
1da177e4 1035{
a3aefd88
TI		 1036 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1037 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1038 int err, isadat, rate;
1039
4d23359b
CL		 1040 runtime->dma_area = (void __force *)(rme96->iobase +
1041 RME96_IO_REC_BUFFER);
1da177e4
LT		 1042 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1043 runtime->dma_bytes = RME96_BUFFER_SIZE;
1044
1045 spin_lock_irq(&rme96->lock);
1046 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1047 spin_unlock_irq(&rme96->lock);
1048 return err;
1049 }
1050 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1051 if ((err = snd_rme96_capture_analog_setrate(rme96,
1052 params_rate(params))) < 0)
1053 {
1054 spin_unlock_irq(&rme96->lock);
1055 return err;
1056 }
1057 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1058 if ((int)params_rate(params) != rate) {
1059 spin_unlock_irq(&rme96->lock);
1060 return -EIO;
1061 }
1062 if ((isadat && runtime->hw.channels_min == 2) ||
1063 (!isadat && runtime->hw.channels_min == 8))
1064 {
1065 spin_unlock_irq(&rme96->lock);
1066 return -EIO;
1067 }
1068 }
1069 snd_rme96_setframelog(rme96, params_channels(params), 0);
1070 if (rme96->playback_periodsize != 0) {
1071 if (params_period_size(params) << rme96->capture_frlog !=
1072 rme96->playback_periodsize)
1073 {
1074 spin_unlock_irq(&rme96->lock);
1075 return -EBUSY;
1076 }
1077 }
1078 rme96->capture_periodsize =
1079 params_period_size(params) << rme96->capture_frlog;
1080 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1081 spin_unlock_irq(&rme96->lock);
1082
1083 return 0;
1084}
1085
1086static void
b892ca1c
KP		 1087snd_rme96_trigger(struct rme96 *rme96,
1088 int op)
1da177e4 1089{
b892ca1c 1090 if (op & RME96_TB_RESET_PLAYPOS)
1da177e4 1091 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
b892ca1c 1092 if (op & RME96_TB_RESET_CAPTUREPOS)
1da177e4 1093 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
b892ca1c
KP		 1094 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1095 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1096 if (rme96->rcreg & RME96_RCR_IRQ)
1097 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1da177e4 1098 }
b892ca1c
KP		 1099 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1100 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1101 if (rme96->rcreg & RME96_RCR_IRQ_2)
1102 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1103 }
1104 if (op & RME96_TB_START_PLAYBACK)
1105 rme96->wcreg |= RME96_WCR_START;
1106 if (op & RME96_TB_STOP_PLAYBACK)
1107 rme96->wcreg &= ~RME96_WCR_START;
1108 if (op & RME96_TB_START_CAPTURE)
1109 rme96->wcreg |= RME96_WCR_START_2;
1110 if (op & RME96_TB_STOP_CAPTURE)
1111 rme96->wcreg &= ~RME96_WCR_START_2;
1da177e4
LT		 1112 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1113}
1114
1da177e4 1115
1da177e4
LT		 1116
1117static irqreturn_t
1118snd_rme96_interrupt(int irq,
7d12e780 1119 void *dev_id)
1da177e4 1120{
a3aefd88 1121 struct rme96 *rme96 = (struct rme96 *)dev_id;
1da177e4
LT		 1122
1123 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1124 /* fastpath out, to ease interrupt sharing */
1125 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1126 (rme96->rcreg & RME96_RCR_IRQ_2)))
1127 {
1128 return IRQ_NONE;
1129 }
1130
1131 if (rme96->rcreg & RME96_RCR_IRQ) {
1132 /* playback */
1133 snd_pcm_period_elapsed(rme96->playback_substream);
1134 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1135 }
1136 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1137 /* capture */
1138 snd_pcm_period_elapsed(rme96->capture_substream);
1139 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1140 }
1141 return IRQ_HANDLED;
1142}
1143
1144static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1145
a3aefd88 1146static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 1147 .count = ARRAY_SIZE(period_bytes),
1148 .list = period_bytes,
1149 .mask = 0
1150};
1151
2ce7fb57
TI		 1152static void
1153rme96_set_buffer_size_constraint(struct rme96 *rme96,
1154 struct snd_pcm_runtime *runtime)
1155{
1156 unsigned int size;
1157
1158 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1159 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1160 if ((size = rme96->playback_periodsize) != 0 ||
1161 (size = rme96->capture_periodsize) != 0)
1162 snd_pcm_hw_constraint_minmax(runtime,
1163 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1164 size, size);
1165 else
1166 snd_pcm_hw_constraint_list(runtime, 0,
1167 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1168 &hw_constraints_period_bytes);
1169}
1170
1da177e4 1171static int
a3aefd88 1172snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1173{
1174 int rate, dummy;
a3aefd88
TI		 1175 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1176 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1177
b892ca1c 1178 snd_pcm_set_sync(substream);
1da177e4
LT		 1179 spin_lock_irq(&rme96->lock);
1180 if (rme96->playback_substream != NULL) {
1181 spin_unlock_irq(&rme96->lock);
1182 return -EBUSY;
1183 }
1184 rme96->wcreg &= ~RME96_WCR_ADAT;
1185 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1186 rme96->playback_substream = substream;
1187 spin_unlock_irq(&rme96->lock);
1188
1189 runtime->hw = snd_rme96_playback_spdif_info;
1190 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1191 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1192 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1193 {
1194 /* slave clock */
918f3a0e 1195 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1196 runtime->hw.rate_min = rate;
1197 runtime->hw.rate_max = rate;
1198 }
2ce7fb57 1199 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1200
1201 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1202 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1203 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1204 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1205 return 0;
1206}
1207
1208static int
a3aefd88 1209snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1210{
1211 int isadat, rate;
a3aefd88
TI		 1212 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1213 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1214
b892ca1c 1215 snd_pcm_set_sync(substream);
1da177e4
LT		 1216 runtime->hw = snd_rme96_capture_spdif_info;
1217 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1218 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1219 {
1220 if (isadat) {
1221 return -EIO;
1222 }
918f3a0e 1223 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1224 runtime->hw.rate_min = rate;
1225 runtime->hw.rate_max = rate;
1226 }
1227
1228 spin_lock_irq(&rme96->lock);
1229 if (rme96->capture_substream != NULL) {
1230 spin_unlock_irq(&rme96->lock);
1231 return -EBUSY;
1232 }
1233 rme96->capture_substream = substream;
1234 spin_unlock_irq(&rme96->lock);
1235
2ce7fb57 1236 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1237 return 0;
1238}
1239
1240static int
a3aefd88 1241snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1242{
1243 int rate, dummy;
a3aefd88
TI		 1244 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1245 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1246
b892ca1c 1247 snd_pcm_set_sync(substream);
1da177e4
LT		 1248 spin_lock_irq(&rme96->lock);
1249 if (rme96->playback_substream != NULL) {
1250 spin_unlock_irq(&rme96->lock);
1251 return -EBUSY;
1252 }
1253 rme96->wcreg |= RME96_WCR_ADAT;
1254 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1255 rme96->playback_substream = substream;
1256 spin_unlock_irq(&rme96->lock);
1257
1258 runtime->hw = snd_rme96_playback_adat_info;
1259 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1260 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1261 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1262 {
1263 /* slave clock */
918f3a0e 1264 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1265 runtime->hw.rate_min = rate;
1266 runtime->hw.rate_max = rate;
1267 }
2ce7fb57 1268 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1269 return 0;
1270}
1271
1272static int
a3aefd88 1273snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1274{
1275 int isadat, rate;
a3aefd88
TI		 1276 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1277 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1278
b892ca1c 1279 snd_pcm_set_sync(substream);
1da177e4
LT		 1280 runtime->hw = snd_rme96_capture_adat_info;
1281 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1282 /* makes no sense to use analog input. Note that analog
1283 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1284 return -EIO;
1285 }
1286 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1287 if (!isadat) {
1288 return -EIO;
1289 }
918f3a0e 1290 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1291 runtime->hw.rate_min = rate;
1292 runtime->hw.rate_max = rate;
1293 }
1294
1295 spin_lock_irq(&rme96->lock);
1296 if (rme96->capture_substream != NULL) {
1297 spin_unlock_irq(&rme96->lock);
1298 return -EBUSY;
1299 }
1300 rme96->capture_substream = substream;
1301 spin_unlock_irq(&rme96->lock);
1302
2ce7fb57 1303 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1304 return 0;
1305}
1306
1307static int
a3aefd88 1308snd_rme96_playback_close(struct snd_pcm_substream *substream)
1da177e4 1309{
a3aefd88 1310 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1311 int spdif = 0;
1312
1313 spin_lock_irq(&rme96->lock);
1314 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1315 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1316 }
1317 rme96->playback_substream = NULL;
1318 rme96->playback_periodsize = 0;
1319 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1320 spin_unlock_irq(&rme96->lock);
1321 if (spdif) {
1322 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1323 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1324 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1325 }
1326 return 0;
1327}
1328
1329static int
a3aefd88 1330snd_rme96_capture_close(struct snd_pcm_substream *substream)
1da177e4 1331{
a3aefd88 1332 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1333
1334 spin_lock_irq(&rme96->lock);
1335 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1336 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1337 }
1338 rme96->capture_substream = NULL;
1339 rme96->capture_periodsize = 0;
1340 spin_unlock_irq(&rme96->lock);
1341 return 0;
1342}
1343
1344static int
a3aefd88 1345snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1346{
a3aefd88 1347 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1348
1349 spin_lock_irq(&rme96->lock);
1350 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1351 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1352 }
1353 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1354 spin_unlock_irq(&rme96->lock);
1355 return 0;
1356}
1357
1358static int
a3aefd88 1359snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1360{
a3aefd88 1361 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1362
1363 spin_lock_irq(&rme96->lock);
1364 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1365 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1366 }
1367 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1368 spin_unlock_irq(&rme96->lock);
1369 return 0;
1370}
1371
1372static int
a3aefd88 1373snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1374 int cmd)
1375{
a3aefd88 1376 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1377 struct snd_pcm_substream *s;
1378 bool sync;
1379
1380 snd_pcm_group_for_each_entry(s, substream) {
1381 if (snd_pcm_substream_chip(s) == rme96)
1382 snd_pcm_trigger_done(s, substream);
1383 }
1384
1385 sync = (rme96->playback_substream && rme96->capture_substream) &&
1386 (rme96->playback_substream->group ==
1387 rme96->capture_substream->group);
1da177e4
LT		 1388
1389 switch (cmd) {
1390 case SNDRV_PCM_TRIGGER_START:
1391 if (!RME96_ISPLAYING(rme96)) {
b892ca1c 1392 if (substream != rme96->playback_substream)
1da177e4 1393 return -EBUSY;
b892ca1c
KP		 1394 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1395 : RME96_START_PLAYBACK);
1da177e4
LT		 1396 }
1397 break;
1398
528ba522 1399 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1400 case SNDRV_PCM_TRIGGER_STOP:
1401 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1402 if (substream != rme96->playback_substream)
1da177e4 1403 return -EBUSY;
b892ca1c
KP		 1404 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1405 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1406 }
1407 break;
1408
1409 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1410 if (RME96_ISPLAYING(rme96))
1411 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1412 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1413 break;
1414
528ba522 1415 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1416 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1417 if (!RME96_ISPLAYING(rme96))
1418 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1419 : RME96_RESUME_PLAYBACK);
1da177e4 1420 break;
b892ca1c 1421
1da177e4
LT		 1422 default:
1423 return -EINVAL;
1424 }
b892ca1c 1425
1da177e4
LT		 1426 return 0;
1427}
1428
1429static int
a3aefd88 1430snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1431 int cmd)
1432{
a3aefd88 1433 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1434 struct snd_pcm_substream *s;
1435 bool sync;
1436
1437 snd_pcm_group_for_each_entry(s, substream) {
1438 if (snd_pcm_substream_chip(s) == rme96)
1439 snd_pcm_trigger_done(s, substream);
1440 }
1441
1442 sync = (rme96->playback_substream && rme96->capture_substream) &&
1443 (rme96->playback_substream->group ==
1444 rme96->capture_substream->group);
1da177e4
LT		 1445
1446 switch (cmd) {
1447 case SNDRV_PCM_TRIGGER_START:
1448 if (!RME96_ISRECORDING(rme96)) {
b892ca1c 1449 if (substream != rme96->capture_substream)
1da177e4 1450 return -EBUSY;
b892ca1c
KP		 1451 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1452 : RME96_START_CAPTURE);
1da177e4
LT		 1453 }
1454 break;
1455
528ba522 1456 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1457 case SNDRV_PCM_TRIGGER_STOP:
1458 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1459 if (substream != rme96->capture_substream)
1da177e4 1460 return -EBUSY;
b892ca1c
KP		 1461 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1462 : RME96_STOP_CAPTURE);
1da177e4
LT		 1463 }
1464 break;
1465
1466 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1467 if (RME96_ISRECORDING(rme96))
1468 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1469 : RME96_STOP_CAPTURE);
1da177e4
LT		 1470 break;
1471
528ba522 1472 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1473 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1474 if (!RME96_ISRECORDING(rme96))
1475 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1476 : RME96_RESUME_CAPTURE);
1da177e4 1477 break;
b892ca1c 1478
1da177e4
LT		 1479 default:
1480 return -EINVAL;
1481 }
1482
1483 return 0;
1484}
1485
1486static snd_pcm_uframes_t
a3aefd88 1487snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1488{
a3aefd88 1489 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1490 return snd_rme96_playback_ptr(rme96);
1491}
1492
1493static snd_pcm_uframes_t
a3aefd88 1494snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1495{
a3aefd88 1496 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1497 return snd_rme96_capture_ptr(rme96);
1498}
1499
a3aefd88 1500static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1da177e4
LT		 1501 .open = snd_rme96_playback_spdif_open,
1502 .close = snd_rme96_playback_close,
1503 .ioctl = snd_pcm_lib_ioctl,
1504 .hw_params = snd_rme96_playback_hw_params,
1505 .prepare = snd_rme96_playback_prepare,
1506 .trigger = snd_rme96_playback_trigger,
1507 .pointer = snd_rme96_playback_pointer,
1508 .copy = snd_rme96_playback_copy,
1509 .silence = snd_rme96_playback_silence,
1510 .mmap = snd_pcm_lib_mmap_iomem,
1511};
1512
a3aefd88 1513static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1da177e4
LT		 1514 .open = snd_rme96_capture_spdif_open,
1515 .close = snd_rme96_capture_close,
1516 .ioctl = snd_pcm_lib_ioctl,
1517 .hw_params = snd_rme96_capture_hw_params,
1518 .prepare = snd_rme96_capture_prepare,
1519 .trigger = snd_rme96_capture_trigger,
1520 .pointer = snd_rme96_capture_pointer,
1521 .copy = snd_rme96_capture_copy,
1522 .mmap = snd_pcm_lib_mmap_iomem,
1523};
1524
a3aefd88 1525static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1da177e4
LT		 1526 .open = snd_rme96_playback_adat_open,
1527 .close = snd_rme96_playback_close,
1528 .ioctl = snd_pcm_lib_ioctl,
1529 .hw_params = snd_rme96_playback_hw_params,
1530 .prepare = snd_rme96_playback_prepare,
1531 .trigger = snd_rme96_playback_trigger,
1532 .pointer = snd_rme96_playback_pointer,
1533 .copy = snd_rme96_playback_copy,
1534 .silence = snd_rme96_playback_silence,
1535 .mmap = snd_pcm_lib_mmap_iomem,
1536};
1537
a3aefd88 1538static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1da177e4
LT		 1539 .open = snd_rme96_capture_adat_open,
1540 .close = snd_rme96_capture_close,
1541 .ioctl = snd_pcm_lib_ioctl,
1542 .hw_params = snd_rme96_capture_hw_params,
1543 .prepare = snd_rme96_capture_prepare,
1544 .trigger = snd_rme96_capture_trigger,
1545 .pointer = snd_rme96_capture_pointer,
1546 .copy = snd_rme96_capture_copy,
1547 .mmap = snd_pcm_lib_mmap_iomem,
1548};
1549
1550static void
1551snd_rme96_free(void *private_data)
1552{
a3aefd88 1553 struct rme96 *rme96 = (struct rme96 *)private_data;
1da177e4
LT		 1554
1555 if (rme96 == NULL) {
1556 return;
1557 }
1558 if (rme96->irq >= 0) {
b892ca1c 1559 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1560 rme96->areg &= ~RME96_AR_DAC_EN;
1561 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1562 free_irq(rme96->irq, (void *)rme96);
1563 rme96->irq = -1;
1564 }
1565 if (rme96->iobase) {
1566 iounmap(rme96->iobase);
1567 rme96->iobase = NULL;
1568 }
1569 if (rme96->port) {
1570 pci_release_regions(rme96->pci);
1571 rme96->port = 0;
1572 }
a932be91 1573#ifdef CONFIG_PM_SLEEP
528ba522
KP		 1574 vfree(rme96->playback_suspend_buffer);
1575 vfree(rme96->capture_suspend_buffer);
1576#endif
1da177e4
LT		 1577 pci_disable_device(rme96->pci);
1578}
1579
1580static void
a3aefd88 1581snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1582{
9fe856e4 1583 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1584 rme96->spdif_pcm = NULL;
1585}
1586
1587static void
a3aefd88 1588snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1589{
9fe856e4 1590 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1591 rme96->adat_pcm = NULL;
1592}
1593
e23e7a14 1594static int
a3aefd88 1595snd_rme96_create(struct rme96 *rme96)
1da177e4
LT		 1596{
1597 struct pci_dev *pci = rme96->pci;
1598 int err;
1599
1600 rme96->irq = -1;
1601 spin_lock_init(&rme96->lock);
1602
1603 if ((err = pci_enable_device(pci)) < 0)
1604 return err;
1605
1606 if ((err = pci_request_regions(pci, "RME96")) < 0)
1607 return err;
1608 rme96->port = pci_resource_start(rme96->pci, 0);
1609
44977b71
HH		 1610 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1611 if (!rme96->iobase) {
342cd934
TI		 1612 dev_err(rme96->card->dev,
1613 "unable to remap memory region 0x%lx-0x%lx\n",
1614 rme96->port, rme96->port + RME96_IO_SIZE - 1);
688956f2
TI		 1615 return -ENOMEM;
1616 }
1617
437a5a46 1618 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
934c2b6d 1619 KBUILD_MODNAME, rme96)) {
342cd934 1620 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1621 return -EBUSY;
1622 }
1623 rme96->irq = pci->irq;
1624
1da177e4
LT		 1625 /* read the card's revision number */
1626 pci_read_config_byte(pci, 8, &rme96->rev);
1627
1628 /* set up ALSA pcm device for S/PDIF */
1629 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1630 1, 1, &rme96->spdif_pcm)) < 0)
1631 {
1632 return err;
1633 }
1634 rme96->spdif_pcm->private_data = rme96;
1635 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1636 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1637 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1638 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1639
1640 rme96->spdif_pcm->info_flags = 0;
1641
1642 /* set up ALSA pcm device for ADAT */
8b7fc421 1643 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1da177e4
LT		 1644 /* ADAT is not available on the base model */
1645 rme96->adat_pcm = NULL;
1646 } else {
1647 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1648 1, 1, &rme96->adat_pcm)) < 0)
1649 {
1650 return err;
1651 }
1652 rme96->adat_pcm->private_data = rme96;
1653 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1654 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1655 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1656 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1657
1658 rme96->adat_pcm->info_flags = 0;
1659 }
1660
1661 rme96->playback_periodsize = 0;
1662 rme96->capture_periodsize = 0;
1663
1664 /* make sure playback/capture is stopped, if by some reason active */
b892ca1c 1665 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1666
1667 /* set default values in registers */
1668 rme96->wcreg =
1669 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1670 RME96_WCR_SEL | /* normal playback */
1671 RME96_WCR_MASTER | /* set to master clock mode */
1672 RME96_WCR_INP_0; /* set coaxial input */
1673
1674 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1675
1676 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1677 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1678
1679 /* reset the ADC */
1680 writel(rme96->areg | RME96_AR_PD2,
1681 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1682 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1683
1684 /* reset and enable the DAC (order is important). */
1685 snd_rme96_reset_dac(rme96);
1686 rme96->areg |= RME96_AR_DAC_EN;
1687 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1688
1689 /* reset playback and record buffer pointers */
1690 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1691 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1692
1693 /* reset volume */
1694 rme96->vol[0] = rme96->vol[1] = 0;
1695 if (RME96_HAS_ANALOG_OUT(rme96)) {
1696 snd_rme96_apply_dac_volume(rme96);
1697 }
1698
1699 /* init switch interface */
1700 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1701 return err;
1702 }
1703
1704 /* init proc interface */
1705 snd_rme96_proc_init(rme96);
1706
1707 return 0;
1708}
1709
1710/*
1711 * proc interface
1712 */
1713
1714static void
a3aefd88 1715snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1716{
1717 int n;
9fe856e4 1718 struct rme96 *rme96 = entry->private_data;
1da177e4
LT		 1719
1720 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1721
1722 snd_iprintf(buffer, rme96->card->longname);
1723 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1724
1725 snd_iprintf(buffer, "\nGeneral settings\n");
1726 if (rme96->wcreg & RME96_WCR_IDIS) {
1727 snd_iprintf(buffer, " period size: N/A (interrupts "
1728 "disabled)\n");
1729 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1730 snd_iprintf(buffer, " period size: 2048 bytes\n");
1731 } else {
1732 snd_iprintf(buffer, " period size: 8192 bytes\n");
1733 }
1734 snd_iprintf(buffer, "\nInput settings\n");
1735 switch (snd_rme96_getinputtype(rme96)) {
1736 case RME96_INPUT_OPTICAL:
1737 snd_iprintf(buffer, " input: optical");
1738 break;
1739 case RME96_INPUT_COAXIAL:
1740 snd_iprintf(buffer, " input: coaxial");
1741 break;
1742 case RME96_INPUT_INTERNAL:
1743 snd_iprintf(buffer, " input: internal");
1744 break;
1745 case RME96_INPUT_XLR:
1746 snd_iprintf(buffer, " input: XLR");
1747 break;
1748 case RME96_INPUT_ANALOG:
1749 snd_iprintf(buffer, " input: analog");
1750 break;
1751 }
1752 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1753 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1754 } else {
1755 if (n) {
1756 snd_iprintf(buffer, " (8 channels)\n");
1757 } else {
1758 snd_iprintf(buffer, " (2 channels)\n");
1759 }
1760 snd_iprintf(buffer, " sample rate: %d Hz\n",
1761 snd_rme96_capture_getrate(rme96, &n));
1762 }
1763 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1764 snd_iprintf(buffer, " sample format: 24 bit\n");
1765 } else {
1766 snd_iprintf(buffer, " sample format: 16 bit\n");
1767 }
1768
1769 snd_iprintf(buffer, "\nOutput settings\n");
1770 if (rme96->wcreg & RME96_WCR_SEL) {
1771 snd_iprintf(buffer, " output signal: normal playback\n");
1772 } else {
1773 snd_iprintf(buffer, " output signal: same as input\n");
1774 }
1775 snd_iprintf(buffer, " sample rate: %d Hz\n",
1776 snd_rme96_playback_getrate(rme96));
1777 if (rme96->wcreg & RME96_WCR_MODE24) {
1778 snd_iprintf(buffer, " sample format: 24 bit\n");
1779 } else {
1780 snd_iprintf(buffer, " sample format: 16 bit\n");
1781 }
1782 if (rme96->areg & RME96_AR_WSEL) {
1783 snd_iprintf(buffer, " sample clock source: word clock\n");
1784 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1785 snd_iprintf(buffer, " sample clock source: internal\n");
1786 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1787 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1788 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1789 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1790 } else {
1791 snd_iprintf(buffer, " sample clock source: autosync\n");
1792 }
1793 if (rme96->wcreg & RME96_WCR_PRO) {
1794 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1795 } else {
1796 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1797 }
1798 if (rme96->wcreg & RME96_WCR_EMP) {
1799 snd_iprintf(buffer, " emphasis: on\n");
1800 } else {
1801 snd_iprintf(buffer, " emphasis: off\n");
1802 }
1803 if (rme96->wcreg & RME96_WCR_DOLBY) {
1804 snd_iprintf(buffer, " non-audio (dolby): on\n");
1805 } else {
1806 snd_iprintf(buffer, " non-audio (dolby): off\n");
1807 }
1808 if (RME96_HAS_ANALOG_IN(rme96)) {
1809 snd_iprintf(buffer, "\nAnalog output settings\n");
1810 switch (snd_rme96_getmontracks(rme96)) {
1811 case RME96_MONITOR_TRACKS_1_2:
1812 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1813 break;
1814 case RME96_MONITOR_TRACKS_3_4:
1815 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1816 break;
1817 case RME96_MONITOR_TRACKS_5_6:
1818 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1819 break;
1820 case RME96_MONITOR_TRACKS_7_8:
1821 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1822 break;
1823 }
1824 switch (snd_rme96_getattenuation(rme96)) {
1825 case RME96_ATTENUATION_0:
1826 snd_iprintf(buffer, " attenuation: 0 dB\n");
1827 break;
1828 case RME96_ATTENUATION_6:
1829 snd_iprintf(buffer, " attenuation: -6 dB\n");
1830 break;
1831 case RME96_ATTENUATION_12:
1832 snd_iprintf(buffer, " attenuation: -12 dB\n");
1833 break;
1834 case RME96_ATTENUATION_18:
1835 snd_iprintf(buffer, " attenuation: -18 dB\n");
1836 break;
1837 }
1838 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1839 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1840 }
1841}
1842
e23e7a14 1843static void snd_rme96_proc_init(struct rme96 *rme96)
1da177e4 1844{
a3aefd88 1845 struct snd_info_entry *entry;
1da177e4
LT		 1846
1847 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
bf850204 1848 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1da177e4
LT		 1849}
1850
1851/*
1852 * control interface
1853 */
1854
a5ce8890
TI		 1855#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1856
1da177e4 1857static int
a3aefd88 1858snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1859{
a3aefd88 1860 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1861
1862 spin_lock_irq(&rme96->lock);
1863 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1864 spin_unlock_irq(&rme96->lock);
1865 return 0;
1866}
1867static int
a3aefd88 1868snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1869{
a3aefd88 1870 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1871 unsigned int val;
1872 int change;
1873
1874 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1875 spin_lock_irq(&rme96->lock);
1876 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1877 change = val != rme96->wcreg;
1878 rme96->wcreg = val;
1879 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1880 spin_unlock_irq(&rme96->lock);
1881 return change;
1882}
1883
1884static int
a3aefd88 1885snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1886{
1887 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
a3aefd88 1888 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1889 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1890
1891 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1892 uinfo->count = 1;
1893 switch (rme96->pci->device) {
8b7fc421
RD		 1894 case PCI_DEVICE_ID_RME_DIGI96:
1895 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1896 uinfo->value.enumerated.items = 3;
1897 break;
8b7fc421 1898 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1899 uinfo->value.enumerated.items = 4;
1900 break;
8b7fc421 1901 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1902 if (rme96->rev > 4) {
1903 /* PST */
1904 uinfo->value.enumerated.items = 4;
1905 texts[3] = _texts[4]; /* Analog instead of XLR */
1906 } else {
1907 /* PAD */
1908 uinfo->value.enumerated.items = 5;
1909 }
1910 break;
1911 default:
1912 snd_BUG();
1913 break;
1914 }
1915 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1916 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1917 }
1918 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1919 return 0;
1920}
1921static int
a3aefd88 1922snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1923{
a3aefd88 1924 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1925 unsigned int items = 3;
1926
1927 spin_lock_irq(&rme96->lock);
1928 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1929
1930 switch (rme96->pci->device) {
8b7fc421
RD		 1931 case PCI_DEVICE_ID_RME_DIGI96:
1932 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1933 items = 3;
1934 break;
8b7fc421 1935 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1936 items = 4;
1937 break;
8b7fc421 1938 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1939 if (rme96->rev > 4) {
1940 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1941 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1942 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1943 }
1944 items = 4;
1945 } else {
1946 items = 5;
1947 }
1948 break;
1949 default:
1950 snd_BUG();
1951 break;
1952 }
1953 if (ucontrol->value.enumerated.item[0] >= items) {
1954 ucontrol->value.enumerated.item[0] = items - 1;
1955 }
1956
1957 spin_unlock_irq(&rme96->lock);
1958 return 0;
1959}
1960static int
a3aefd88 1961snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1962{
a3aefd88 1963 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1964 unsigned int val;
1965 int change, items = 3;
1966
1967 switch (rme96->pci->device) {
8b7fc421
RD		 1968 case PCI_DEVICE_ID_RME_DIGI96:
1969 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1970 items = 3;
1971 break;
8b7fc421 1972 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1973 items = 4;
1974 break;
8b7fc421 1975 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1976 if (rme96->rev > 4) {
1977 items = 4;
1978 } else {
1979 items = 5;
1980 }
1981 break;
1982 default:
1983 snd_BUG();
1984 break;
1985 }
1986 val = ucontrol->value.enumerated.item[0] % items;
1987
1988 /* special case for PST */
8b7fc421 1989 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1da177e4
LT		 1990 if (val == RME96_INPUT_XLR) {
1991 val = RME96_INPUT_ANALOG;
1992 }
1993 }
1994
1995 spin_lock_irq(&rme96->lock);
1996 change = (int)val != snd_rme96_getinputtype(rme96);
1997 snd_rme96_setinputtype(rme96, val);
1998 spin_unlock_irq(&rme96->lock);
1999 return change;
2000}
2001
2002static int
a3aefd88 2003snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2004{
2005 static char *texts[3] = { "AutoSync", "Internal", "Word" };
2006
2007 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2008 uinfo->count = 1;
2009 uinfo->value.enumerated.items = 3;
2010 if (uinfo->value.enumerated.item > 2) {
2011 uinfo->value.enumerated.item = 2;
2012 }
2013 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2014 return 0;
2015}
2016static int
a3aefd88 2017snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2018{
a3aefd88 2019 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2020
2021 spin_lock_irq(&rme96->lock);
2022 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2023 spin_unlock_irq(&rme96->lock);
2024 return 0;
2025}
2026static int
a3aefd88 2027snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2028{
a3aefd88 2029 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2030 unsigned int val;
2031 int change;
2032
2033 val = ucontrol->value.enumerated.item[0] % 3;
2034 spin_lock_irq(&rme96->lock);
2035 change = (int)val != snd_rme96_getclockmode(rme96);
2036 snd_rme96_setclockmode(rme96, val);
2037 spin_unlock_irq(&rme96->lock);
2038 return change;
2039}
2040
2041static int
a3aefd88 2042snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2043{
2044 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2045
2046 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2047 uinfo->count = 1;
2048 uinfo->value.enumerated.items = 4;
2049 if (uinfo->value.enumerated.item > 3) {
2050 uinfo->value.enumerated.item = 3;
2051 }
2052 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2053 return 0;
2054}
2055static int
a3aefd88 2056snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2057{
a3aefd88 2058 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2059
2060 spin_lock_irq(&rme96->lock);
2061 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2062 spin_unlock_irq(&rme96->lock);
2063 return 0;
2064}
2065static int
a3aefd88 2066snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2067{
a3aefd88 2068 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2069 unsigned int val;
2070 int change;
2071
2072 val = ucontrol->value.enumerated.item[0] % 4;
2073 spin_lock_irq(&rme96->lock);
2074
2075 change = (int)val != snd_rme96_getattenuation(rme96);
2076 snd_rme96_setattenuation(rme96, val);
2077 spin_unlock_irq(&rme96->lock);
2078 return change;
2079}
2080
2081static int
a3aefd88 2082snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2083{
2084 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2085
2086 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2087 uinfo->count = 1;
2088 uinfo->value.enumerated.items = 4;
2089 if (uinfo->value.enumerated.item > 3) {
2090 uinfo->value.enumerated.item = 3;
2091 }
2092 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2093 return 0;
2094}
2095static int
a3aefd88 2096snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2097{
a3aefd88 2098 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2099
2100 spin_lock_irq(&rme96->lock);
2101 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2102 spin_unlock_irq(&rme96->lock);
2103 return 0;
2104}
2105static int
a3aefd88 2106snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2107{
a3aefd88 2108 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2109 unsigned int val;
2110 int change;
2111
2112 val = ucontrol->value.enumerated.item[0] % 4;
2113 spin_lock_irq(&rme96->lock);
2114 change = (int)val != snd_rme96_getmontracks(rme96);
2115 snd_rme96_setmontracks(rme96, val);
2116 spin_unlock_irq(&rme96->lock);
2117 return change;
2118}
2119
a3aefd88 2120static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT		 2121{
2122 u32 val = 0;
2123 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2124 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2125 if (val & RME96_WCR_PRO)
2126 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2127 else
2128 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2129 return val;
2130}
2131
a3aefd88 2132static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT		 2133{
2134 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2135 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2136 if (val & RME96_WCR_PRO)
2137 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2138 else
2139 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2140}
2141
a3aefd88 2142static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2143{
2144 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2145 uinfo->count = 1;
2146 return 0;
2147}
2148
a3aefd88 2149static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2150{
a3aefd88 2151 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2152
2153 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2154 return 0;
2155}
2156
a3aefd88 2157static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2158{
a3aefd88 2159 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2160 int change;
2161 u32 val;
2162
2163 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2164 spin_lock_irq(&rme96->lock);
2165 change = val != rme96->wcreg_spdif;
2166 rme96->wcreg_spdif = val;
2167 spin_unlock_irq(&rme96->lock);
2168 return change;
2169}
2170
a3aefd88 2171static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2172{
2173 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2174 uinfo->count = 1;
2175 return 0;
2176}
2177
a3aefd88 2178static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2179{
a3aefd88 2180 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2181
2182 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2183 return 0;
2184}
2185
a3aefd88 2186static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2187{
a3aefd88 2188 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2189 int change;
2190 u32 val;
2191
2192 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2193 spin_lock_irq(&rme96->lock);
2194 change = val != rme96->wcreg_spdif_stream;
2195 rme96->wcreg_spdif_stream = val;
2196 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2197 rme96->wcreg |= val;
2198 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2199 spin_unlock_irq(&rme96->lock);
2200 return change;
2201}
2202
a3aefd88 2203static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2204{
2205 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2206 uinfo->count = 1;
2207 return 0;
2208}
2209
a3aefd88 2210static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2211{
2212 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2213 return 0;
2214}
2215
2216static int
a3aefd88 2217snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2218{
a3aefd88 2219 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2220
2221 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2222 uinfo->count = 2;
2223 uinfo->value.integer.min = 0;
2224 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2225 return 0;
2226}
2227
2228static int
a3aefd88 2229snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2230{
a3aefd88 2231 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2232
2233 spin_lock_irq(&rme96->lock);
2234 u->value.integer.value[0] = rme96->vol[0];
2235 u->value.integer.value[1] = rme96->vol[1];
2236 spin_unlock_irq(&rme96->lock);
2237
2238 return 0;
2239}
2240
2241static int
a3aefd88 2242snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2243{
a3aefd88 2244 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4 2245 int change = 0;
4e98d6a7 2246 unsigned int vol, maxvol;
1da177e4 2247
4e98d6a7
TI		 2248
2249 if (!RME96_HAS_ANALOG_OUT(rme96))
1da177e4 2250 return -EINVAL;
4e98d6a7 2251 maxvol = RME96_185X_MAX_OUT(rme96);
1da177e4 2252 spin_lock_irq(&rme96->lock);
4e98d6a7
TI		 2253 vol = u->value.integer.value[0];
2254 if (vol != rme96->vol[0] && vol <= maxvol) {
2255 rme96->vol[0] = vol;
2256 change = 1;
2257 }
2258 vol = u->value.integer.value[1];
2259 if (vol != rme96->vol[1] && vol <= maxvol) {
2260 rme96->vol[1] = vol;
2261 change = 1;
1da177e4 2262 }
4e98d6a7
TI		 2263 if (change)
2264 snd_rme96_apply_dac_volume(rme96);
1da177e4
LT		 2265 spin_unlock_irq(&rme96->lock);
2266
2267 return change;
2268}
2269
a3aefd88 2270static struct snd_kcontrol_new snd_rme96_controls[] = {
1da177e4
LT		 2271{
2272 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2273 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2274 .info = snd_rme96_control_spdif_info,
2275 .get = snd_rme96_control_spdif_get,
2276 .put = snd_rme96_control_spdif_put
2277},
2278{
2279 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2280 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2281 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2282 .info = snd_rme96_control_spdif_stream_info,
2283 .get = snd_rme96_control_spdif_stream_get,
2284 .put = snd_rme96_control_spdif_stream_put
2285},
2286{
2287 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2288 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2289 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2290 .info = snd_rme96_control_spdif_mask_info,
2291 .get = snd_rme96_control_spdif_mask_get,
2292 .private_value = IEC958_AES0_NONAUDIO |
2293 IEC958_AES0_PROFESSIONAL |
2294 IEC958_AES0_CON_EMPHASIS
2295},
2296{
2297 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2298 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2299 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2300 .info = snd_rme96_control_spdif_mask_info,
2301 .get = snd_rme96_control_spdif_mask_get,
2302 .private_value = IEC958_AES0_NONAUDIO |
2303 IEC958_AES0_PROFESSIONAL |
2304 IEC958_AES0_PRO_EMPHASIS
2305},
2306{
2307 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2308 .name = "Input Connector",
2309 .info = snd_rme96_info_inputtype_control,
2310 .get = snd_rme96_get_inputtype_control,
2311 .put = snd_rme96_put_inputtype_control
2312},
2313{
2314 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2315 .name = "Loopback Input",
2316 .info = snd_rme96_info_loopback_control,
2317 .get = snd_rme96_get_loopback_control,
2318 .put = snd_rme96_put_loopback_control
2319},
2320{
2321 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2322 .name = "Sample Clock Source",
2323 .info = snd_rme96_info_clockmode_control,
2324 .get = snd_rme96_get_clockmode_control,
2325 .put = snd_rme96_put_clockmode_control
2326},
2327{
2328 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2329 .name = "Monitor Tracks",
2330 .info = snd_rme96_info_montracks_control,
2331 .get = snd_rme96_get_montracks_control,
2332 .put = snd_rme96_put_montracks_control
2333},
2334{
2335 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2336 .name = "Attenuation",
2337 .info = snd_rme96_info_attenuation_control,
2338 .get = snd_rme96_get_attenuation_control,
2339 .put = snd_rme96_put_attenuation_control
2340},
2341{
2342 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2343 .name = "DAC Playback Volume",
2344 .info = snd_rme96_dac_volume_info,
2345 .get = snd_rme96_dac_volume_get,
2346 .put = snd_rme96_dac_volume_put
2347}
2348};
2349
2350static int
a3aefd88
TI		 2351snd_rme96_create_switches(struct snd_card *card,
2352 struct rme96 *rme96)
1da177e4
LT		 2353{
2354 int idx, err;
a3aefd88 2355 struct snd_kcontrol *kctl;
1da177e4
LT		 2356
2357 for (idx = 0; idx < 7; idx++) {
2358 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2359 return err;
2360 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2361 rme96->spdif_ctl = kctl;
2362 }
2363
2364 if (RME96_HAS_ANALOG_OUT(rme96)) {
2365 for (idx = 7; idx < 10; idx++)
2366 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2367 return err;
2368 }
2369
2370 return 0;
2371}
2372
2373/*
2374 * Card initialisation
2375 */
2376
a932be91 2377#ifdef CONFIG_PM_SLEEP
528ba522 2378
a932be91 2379static int rme96_suspend(struct device *dev)
528ba522 2380{
a932be91
TI		 2381 struct pci_dev *pci = to_pci_dev(dev);
2382 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2383 struct rme96 *rme96 = card->private_data;
2384
2385 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2386 snd_pcm_suspend(rme96->playback_substream);
2387 snd_pcm_suspend(rme96->capture_substream);
2388
2389 /* save capture & playback pointers */
2390 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2391 & RME96_RCR_AUDIO_ADDR_MASK;
2392 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2393 & RME96_RCR_AUDIO_ADDR_MASK;
2394
2395 /* save playback and capture buffers */
2396 memcpy_fromio(rme96->playback_suspend_buffer,
2397 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2398 memcpy_fromio(rme96->capture_suspend_buffer,
2399 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2400
2401 /* disable the DAC */
2402 rme96->areg &= ~RME96_AR_DAC_EN;
2403 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2404
2405 pci_disable_device(pci);
2406 pci_save_state(pci);
2407
2408 return 0;
2409}
2410
a932be91 2411static int rme96_resume(struct device *dev)
528ba522 2412{
a932be91
TI		 2413 struct pci_dev *pci = to_pci_dev(dev);
2414 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2415 struct rme96 *rme96 = card->private_data;
2416
2417 pci_restore_state(pci);
e58a244f 2418 if (pci_enable_device(pci) < 0) {
342cd934 2419 dev_err(dev, "pci_enable_device failed, disabling device\n");
e58a244f
TI		 2420 snd_card_disconnect(card);
2421 return -EIO;
2422 }
528ba522
KP		 2423
2424 /* reset playback and record buffer pointers */
2425 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2426 + rme96->playback_pointer);
2427 writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2428 + rme96->capture_pointer);
2429
2430 /* restore playback and capture buffers */
2431 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2432 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2433 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2434 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2435
2436 /* reset the ADC */
2437 writel(rme96->areg | RME96_AR_PD2,
2438 rme96->iobase + RME96_IO_ADDITIONAL_REG);
2439 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2440
2441 /* reset and enable DAC, restore analog volume */
2442 snd_rme96_reset_dac(rme96);
2443 rme96->areg |= RME96_AR_DAC_EN;
2444 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2445 if (RME96_HAS_ANALOG_OUT(rme96)) {
2446 usleep_range(3000, 10000);
2447 snd_rme96_apply_dac_volume(rme96);
2448 }
2449
2450 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2451
2452 return 0;
2453}
2454
a932be91
TI		 2455static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
2456#define RME96_PM_OPS &rme96_pm
2457#else
2458#define RME96_PM_OPS NULL
2459#endif /* CONFIG_PM_SLEEP */
528ba522 2460
a3aefd88 2461static void snd_rme96_card_free(struct snd_card *card)
1da177e4
LT		 2462{
2463 snd_rme96_free(card->private_data);
2464}
2465
e23e7a14 2466static int
1da177e4
LT		 2467snd_rme96_probe(struct pci_dev *pci,
2468 const struct pci_device_id *pci_id)
2469{
2470 static int dev;
a3aefd88
TI		 2471 struct rme96 *rme96;
2472 struct snd_card *card;
1da177e4
LT		 2473 int err;
2474 u8 val;
2475
2476 if (dev >= SNDRV_CARDS) {
2477 return -ENODEV;
2478 }
2479 if (!enable[dev]) {
2480 dev++;
2481 return -ENOENT;
2482 }
60c5772b
TI		 2483 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2484 sizeof(struct rme96), &card);
e58de7ba
TI		 2485 if (err < 0)
2486 return err;
1da177e4 2487 card->private_free = snd_rme96_card_free;
9fe856e4 2488 rme96 = card->private_data;
1da177e4
LT		 2489 rme96->card = card;
2490 rme96->pci = pci;
1da177e4
LT		 2491 if ((err = snd_rme96_create(rme96)) < 0) {
2492 snd_card_free(card);
2493 return err;
2494 }
2495
a932be91 2496#ifdef CONFIG_PM_SLEEP
528ba522
KP		 2497 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2498 if (!rme96->playback_suspend_buffer) {
342cd934 2499 dev_err(card->dev,
528ba522
KP		 2500 "Failed to allocate playback suspend buffer!\n");
2501 snd_card_free(card);
2502 return -ENOMEM;
2503 }
2504 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2505 if (!rme96->capture_suspend_buffer) {
342cd934 2506 dev_err(card->dev,
528ba522
KP		 2507 "Failed to allocate capture suspend buffer!\n");
2508 snd_card_free(card);
2509 return -ENOMEM;
2510 }
2511#endif
2512
1da177e4
LT		 2513 strcpy(card->driver, "Digi96");
2514 switch (rme96->pci->device) {
8b7fc421 2515 case PCI_DEVICE_ID_RME_DIGI96:
1da177e4
LT		 2516 strcpy(card->shortname, "RME Digi96");
2517 break;
8b7fc421 2518 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 2519 strcpy(card->shortname, "RME Digi96/8");
2520 break;
8b7fc421 2521 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 2522 strcpy(card->shortname, "RME Digi96/8 PRO");
2523 break;
8b7fc421 2524 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2525 pci_read_config_byte(rme96->pci, 8, &val);
2526 if (val < 5) {
2527 strcpy(card->shortname, "RME Digi96/8 PAD");
2528 } else {
2529 strcpy(card->shortname, "RME Digi96/8 PST");
2530 }
2531 break;
2532 }
2533 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2534 rme96->port, rme96->irq);
2535
2536 if ((err = snd_card_register(card)) < 0) {
2537 snd_card_free(card);
2538 return err;
2539 }
2540 pci_set_drvdata(pci, card);
2541 dev++;
2542 return 0;
2543}
2544
e23e7a14 2545static void snd_rme96_remove(struct pci_dev *pci)
1da177e4
LT		 2546{
2547 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 2548}
2549
e9f66d9b 2550static struct pci_driver rme96_driver = {
3733e424 2551 .name = KBUILD_MODNAME,
1da177e4
LT		 2552 .id_table = snd_rme96_ids,
2553 .probe = snd_rme96_probe,
e23e7a14 2554 .remove = snd_rme96_remove,
a932be91
TI		 2555 .driver = {
2556 .pm = RME96_PM_OPS,
2557 },
1da177e4
LT		 2558};
2559
e9f66d9b 2560module_pci_driver(rme96_driver);
Linux kernel - Deliverables
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