[ALSA] hdspm - Fix autosync bug
[deliverable/linux.git] / sound / pci / rme9652 / hdsp.c
CommitLineData
1da177e4
LT
1/*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <sound/driver.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/interrupt.h>
28#include <linux/slab.h>
29#include <linux/pci.h>
30#include <linux/firmware.h>
31#include <linux/moduleparam.h>
32
33#include <sound/core.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/info.h>
37#include <sound/asoundef.h>
38#include <sound/rawmidi.h>
39#include <sound/hwdep.h>
40#include <sound/initval.h>
41#include <sound/hdsp.h>
42
43#include <asm/byteorder.h>
44#include <asm/current.h>
45#include <asm/io.h>
46
47static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50
51module_param_array(index, int, NULL, 0444);
52MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53module_param_array(id, charp, NULL, 0444);
54MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55module_param_array(enable, bool, NULL, 0444);
56MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58MODULE_DESCRIPTION("RME Hammerfall DSP");
59MODULE_LICENSE("GPL");
60MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 "{RME HDSP-9652},"
62 "{RME HDSP-9632}}");
7e0af29d
CL
63#ifdef HDSP_FW_LOADER
64MODULE_FIRMWARE("multiface_firmware.bin");
65MODULE_FIRMWARE("multiface_firmware_rev11.bin");
66MODULE_FIRMWARE("digiface_firmware.bin");
67MODULE_FIRMWARE("digiface_firmware_rev11.bin");
68#endif
1da177e4
LT
69
70#define HDSP_MAX_CHANNELS 26
71#define HDSP_MAX_DS_CHANNELS 14
72#define HDSP_MAX_QS_CHANNELS 8
73#define DIGIFACE_SS_CHANNELS 26
74#define DIGIFACE_DS_CHANNELS 14
75#define MULTIFACE_SS_CHANNELS 18
76#define MULTIFACE_DS_CHANNELS 14
77#define H9652_SS_CHANNELS 26
78#define H9652_DS_CHANNELS 14
79/* This does not include possible Analog Extension Boards
80 AEBs are detected at card initialization
81*/
82#define H9632_SS_CHANNELS 12
83#define H9632_DS_CHANNELS 8
84#define H9632_QS_CHANNELS 4
85
86/* Write registers. These are defined as byte-offsets from the iobase value.
87 */
88#define HDSP_resetPointer 0
d7923b2a 89#define HDSP_freqReg 0
1da177e4
LT
90#define HDSP_outputBufferAddress 32
91#define HDSP_inputBufferAddress 36
92#define HDSP_controlRegister 64
93#define HDSP_interruptConfirmation 96
94#define HDSP_outputEnable 128
95#define HDSP_control2Reg 256
96#define HDSP_midiDataOut0 352
97#define HDSP_midiDataOut1 356
98#define HDSP_fifoData 368
99#define HDSP_inputEnable 384
100
101/* Read registers. These are defined as byte-offsets from the iobase value
102 */
103
104#define HDSP_statusRegister 0
105#define HDSP_timecode 128
106#define HDSP_status2Register 192
107#define HDSP_midiDataOut0 352
108#define HDSP_midiDataOut1 356
109#define HDSP_midiDataIn0 360
110#define HDSP_midiDataIn1 364
111#define HDSP_midiStatusOut0 384
112#define HDSP_midiStatusOut1 388
113#define HDSP_midiStatusIn0 392
114#define HDSP_midiStatusIn1 396
115#define HDSP_fifoStatus 400
116
117/* the meters are regular i/o-mapped registers, but offset
118 considerably from the rest. the peak registers are reset
119 when read; the least-significant 4 bits are full-scale counters;
120 the actual peak value is in the most-significant 24 bits.
121*/
122
123#define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
124#define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
125#define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
126#define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
127#define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
128
129
130/* This is for H9652 cards
131 Peak values are read downward from the base
132 Rms values are read upward
133 There are rms values for the outputs too
134 26*3 values are read in ss mode
135 14*3 in ds mode, with no gap between values
136*/
137#define HDSP_9652_peakBase 7164
138#define HDSP_9652_rmsBase 4096
139
140/* c.f. the hdsp_9632_meters_t struct */
141#define HDSP_9632_metersBase 4096
142
143#define HDSP_IO_EXTENT 7168
144
145/* control2 register bits */
146
147#define HDSP_TMS 0x01
148#define HDSP_TCK 0x02
149#define HDSP_TDI 0x04
150#define HDSP_JTAG 0x08
151#define HDSP_PWDN 0x10
152#define HDSP_PROGRAM 0x020
153#define HDSP_CONFIG_MODE_0 0x040
154#define HDSP_CONFIG_MODE_1 0x080
155#define HDSP_VERSION_BIT 0x100
156#define HDSP_BIGENDIAN_MODE 0x200
157#define HDSP_RD_MULTIPLE 0x400
158#define HDSP_9652_ENABLE_MIXER 0x800
159#define HDSP_TDO 0x10000000
160
161#define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
162#define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
163
164/* Control Register bits */
165
166#define HDSP_Start (1<<0) /* start engine */
167#define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
168#define HDSP_Latency1 (1<<2) /* [ see above ] */
169#define HDSP_Latency2 (1<<3) /* [ see above ] */
170#define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
171#define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
172#define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
173#define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
174#define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
175#define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
176#define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
177#define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
178#define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
179#define HDSP_SyncRef2 (1<<13)
180#define HDSP_SPDIFInputSelect0 (1<<14)
181#define HDSP_SPDIFInputSelect1 (1<<15)
182#define HDSP_SyncRef0 (1<<16)
183#define HDSP_SyncRef1 (1<<17)
184#define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
185#define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
186#define HDSP_Midi0InterruptEnable (1<<22)
187#define HDSP_Midi1InterruptEnable (1<<23)
188#define HDSP_LineOut (1<<24)
189#define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
190#define HDSP_ADGain1 (1<<26)
191#define HDSP_DAGain0 (1<<27)
192#define HDSP_DAGain1 (1<<28)
193#define HDSP_PhoneGain0 (1<<29)
194#define HDSP_PhoneGain1 (1<<30)
195#define HDSP_QuadSpeed (1<<31)
196
197#define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
198#define HDSP_ADGainMinus10dBV HDSP_ADGainMask
199#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
200#define HDSP_ADGainLowGain 0
201
202#define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
203#define HDSP_DAGainHighGain HDSP_DAGainMask
204#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
205#define HDSP_DAGainMinus10dBV 0
206
207#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
208#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
209#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
210#define HDSP_PhoneGainMinus12dB 0
211
212#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
213#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
214
215#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
216#define HDSP_SPDIFInputADAT1 0
217#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
218#define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
219#define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
220
221#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
222#define HDSP_SyncRef_ADAT1 0
223#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
224#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
225#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
226#define HDSP_SyncRef_WORD (HDSP_SyncRef2)
227#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
228
229/* Sample Clock Sources */
230
231#define HDSP_CLOCK_SOURCE_AUTOSYNC 0
232#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
233#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
234#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
235#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
236#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
237#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
238#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
239#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
240#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
241
242/* Preferred sync reference choices - used by "pref_sync_ref" control switch */
243
244#define HDSP_SYNC_FROM_WORD 0
245#define HDSP_SYNC_FROM_SPDIF 1
246#define HDSP_SYNC_FROM_ADAT1 2
247#define HDSP_SYNC_FROM_ADAT_SYNC 3
248#define HDSP_SYNC_FROM_ADAT2 4
249#define HDSP_SYNC_FROM_ADAT3 5
250
251/* SyncCheck status */
252
253#define HDSP_SYNC_CHECK_NO_LOCK 0
254#define HDSP_SYNC_CHECK_LOCK 1
255#define HDSP_SYNC_CHECK_SYNC 2
256
257/* AutoSync references - used by "autosync_ref" control switch */
258
259#define HDSP_AUTOSYNC_FROM_WORD 0
260#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
261#define HDSP_AUTOSYNC_FROM_SPDIF 2
262#define HDSP_AUTOSYNC_FROM_NONE 3
263#define HDSP_AUTOSYNC_FROM_ADAT1 4
264#define HDSP_AUTOSYNC_FROM_ADAT2 5
265#define HDSP_AUTOSYNC_FROM_ADAT3 6
266
267/* Possible sources of S/PDIF input */
268
269#define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
270#define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
271#define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
272#define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
273
274#define HDSP_Frequency32KHz HDSP_Frequency0
275#define HDSP_Frequency44_1KHz HDSP_Frequency1
276#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
277#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
278#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
279#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
280/* For H9632 cards */
281#define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
282#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
283#define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
e4b6088c
JC
284/* RME says n = 104857600000000, but in the windows MADI driver, I see:
285 return 104857600000000 / rate; // 100 MHz
286 return 110100480000000 / rate; // 105 MHz
287*/
288#define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
1da177e4
LT
289
290#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
291#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
292
293#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
294#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
295
296/* Status Register bits */
297
298#define HDSP_audioIRQPending (1<<0)
299#define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
300#define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
301#define HDSP_Lock1 (1<<2)
302#define HDSP_Lock0 (1<<3)
303#define HDSP_SPDIFSync (1<<4)
304#define HDSP_TimecodeLock (1<<5)
305#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
306#define HDSP_Sync2 (1<<16)
307#define HDSP_Sync1 (1<<17)
308#define HDSP_Sync0 (1<<18)
309#define HDSP_DoubleSpeedStatus (1<<19)
310#define HDSP_ConfigError (1<<20)
311#define HDSP_DllError (1<<21)
312#define HDSP_spdifFrequency0 (1<<22)
313#define HDSP_spdifFrequency1 (1<<23)
314#define HDSP_spdifFrequency2 (1<<24)
315#define HDSP_SPDIFErrorFlag (1<<25)
316#define HDSP_BufferID (1<<26)
317#define HDSP_TimecodeSync (1<<27)
318#define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
319#define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
320#define HDSP_midi0IRQPending (1<<30)
321#define HDSP_midi1IRQPending (1<<31)
322
323#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
324
325#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
326#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
327#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
328
329#define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
330#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
331#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
332
333/* This is for H9632 cards */
334#define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
335#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
336#define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
337
338/* Status2 Register bits */
339
340#define HDSP_version0 (1<<0)
341#define HDSP_version1 (1<<1)
342#define HDSP_version2 (1<<2)
343#define HDSP_wc_lock (1<<3)
344#define HDSP_wc_sync (1<<4)
345#define HDSP_inp_freq0 (1<<5)
346#define HDSP_inp_freq1 (1<<6)
347#define HDSP_inp_freq2 (1<<7)
348#define HDSP_SelSyncRef0 (1<<8)
349#define HDSP_SelSyncRef1 (1<<9)
350#define HDSP_SelSyncRef2 (1<<10)
351
352#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
353
354#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
355#define HDSP_systemFrequency32 (HDSP_inp_freq0)
356#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
357#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
358#define HDSP_systemFrequency64 (HDSP_inp_freq2)
359#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
360#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
361/* FIXME : more values for 9632 cards ? */
362
363#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
364#define HDSP_SelSyncRef_ADAT1 0
365#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
366#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
367#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
368#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
369#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
370
371/* Card state flags */
372
373#define HDSP_InitializationComplete (1<<0)
374#define HDSP_FirmwareLoaded (1<<1)
375#define HDSP_FirmwareCached (1<<2)
376
377/* FIFO wait times, defined in terms of 1/10ths of msecs */
378
379#define HDSP_LONG_WAIT 5000
380#define HDSP_SHORT_WAIT 30
381
382#define UNITY_GAIN 32768
383#define MINUS_INFINITY_GAIN 0
384
1da177e4
LT
385/* the size of a substream (1 mono data stream) */
386
387#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
388#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
389
390/* the size of the area we need to allocate for DMA transfers. the
391 size is the same regardless of the number of channels - the
392 Multiface still uses the same memory area.
393
394 Note that we allocate 1 more channel than is apparently needed
395 because the h/w seems to write 1 byte beyond the end of the last
396 page. Sigh.
397*/
398
399#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
400#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
401
402/* use hotplug firmeare loader? */
403#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
140432fd 404#if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP)
1da177e4
LT
405#define HDSP_FW_LOADER
406#endif
407#endif
408
55e957d8 409struct hdsp_9632_meters {
1da177e4
LT
410 u32 input_peak[16];
411 u32 playback_peak[16];
412 u32 output_peak[16];
413 u32 xxx_peak[16];
414 u32 padding[64];
415 u32 input_rms_low[16];
416 u32 playback_rms_low[16];
417 u32 output_rms_low[16];
418 u32 xxx_rms_low[16];
419 u32 input_rms_high[16];
420 u32 playback_rms_high[16];
421 u32 output_rms_high[16];
422 u32 xxx_rms_high[16];
423};
424
55e957d8
TI
425struct hdsp_midi {
426 struct hdsp *hdsp;
1da177e4 427 int id;
55e957d8
TI
428 struct snd_rawmidi *rmidi;
429 struct snd_rawmidi_substream *input;
430 struct snd_rawmidi_substream *output;
1da177e4
LT
431 char istimer; /* timer in use */
432 struct timer_list timer;
433 spinlock_t lock;
434 int pending;
435};
436
55e957d8 437struct hdsp {
1da177e4 438 spinlock_t lock;
55e957d8
TI
439 struct snd_pcm_substream *capture_substream;
440 struct snd_pcm_substream *playback_substream;
441 struct hdsp_midi midi[2];
1da177e4
LT
442 struct tasklet_struct midi_tasklet;
443 int use_midi_tasklet;
444 int precise_ptr;
445 u32 control_register; /* cached value */
446 u32 control2_register; /* cached value */
447 u32 creg_spdif;
448 u32 creg_spdif_stream;
e3ea4d89 449 int clock_source_locked;
1da177e4 450 char *card_name; /* digiface/multiface */
55e957d8 451 enum HDSP_IO_Type io_type; /* ditto, but for code use */
1da177e4
LT
452 unsigned short firmware_rev;
453 unsigned short state; /* stores state bits */
454 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
455 size_t period_bytes; /* guess what this is */
456 unsigned char max_channels;
457 unsigned char qs_in_channels; /* quad speed mode for H9632 */
458 unsigned char ds_in_channels;
459 unsigned char ss_in_channels; /* different for multiface/digiface */
460 unsigned char qs_out_channels;
461 unsigned char ds_out_channels;
462 unsigned char ss_out_channels;
463
464 struct snd_dma_buffer capture_dma_buf;
465 struct snd_dma_buffer playback_dma_buf;
466 unsigned char *capture_buffer; /* suitably aligned address */
467 unsigned char *playback_buffer; /* suitably aligned address */
468
469 pid_t capture_pid;
470 pid_t playback_pid;
471 int running;
472 int system_sample_rate;
473 char *channel_map;
474 int dev;
475 int irq;
476 unsigned long port;
477 void __iomem *iobase;
55e957d8
TI
478 struct snd_card *card;
479 struct snd_pcm *pcm;
480 struct snd_hwdep *hwdep;
1da177e4 481 struct pci_dev *pci;
55e957d8 482 struct snd_kcontrol *spdif_ctl;
1da177e4 483 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
d7923b2a 484 unsigned int dds_value; /* last value written to freq register */
1da177e4
LT
485};
486
487/* These tables map the ALSA channels 1..N to the channels that we
488 need to use in order to find the relevant channel buffer. RME
489 refer to this kind of mapping as between "the ADAT channel and
490 the DMA channel." We index it using the logical audio channel,
491 and the value is the DMA channel (i.e. channel buffer number)
492 where the data for that channel can be read/written from/to.
493*/
494
495static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
496 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
497 18, 19, 20, 21, 22, 23, 24, 25
498};
499
500static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
501 /* Analog */
502 0, 1, 2, 3, 4, 5, 6, 7,
503 /* ADAT 2 */
504 16, 17, 18, 19, 20, 21, 22, 23,
505 /* SPDIF */
506 24, 25,
507 -1, -1, -1, -1, -1, -1, -1, -1
508};
509
510static char channel_map_ds[HDSP_MAX_CHANNELS] = {
511 /* ADAT channels are remapped */
512 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
513 /* channels 12 and 13 are S/PDIF */
514 24, 25,
515 /* others don't exist */
516 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
517};
518
519static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
520 /* ADAT channels */
521 0, 1, 2, 3, 4, 5, 6, 7,
522 /* SPDIF */
523 8, 9,
524 /* Analog */
525 10, 11,
526 /* AO4S-192 and AI4S-192 extension boards */
527 12, 13, 14, 15,
528 /* others don't exist */
529 -1, -1, -1, -1, -1, -1, -1, -1,
530 -1, -1
531};
532
533static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
534 /* ADAT */
535 1, 3, 5, 7,
536 /* SPDIF */
537 8, 9,
538 /* Analog */
539 10, 11,
540 /* AO4S-192 and AI4S-192 extension boards */
541 12, 13, 14, 15,
542 /* others don't exist */
543 -1, -1, -1, -1, -1, -1, -1, -1,
544 -1, -1, -1, -1, -1, -1
545};
546
547static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
548 /* ADAT is disabled in this mode */
549 /* SPDIF */
550 8, 9,
551 /* Analog */
552 10, 11,
553 /* AO4S-192 and AI4S-192 extension boards */
554 12, 13, 14, 15,
555 /* others don't exist */
556 -1, -1, -1, -1, -1, -1, -1, -1,
557 -1, -1, -1, -1, -1, -1, -1, -1,
558 -1, -1
559};
560
561static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
562{
563 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
564 dmab->dev.dev = snd_dma_pci_data(pci);
b6a96915
TI
565 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
566 if (dmab->bytes >= size)
567 return 0;
1da177e4 568 }
b6a96915
TI
569 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
570 size, dmab) < 0)
571 return -ENOMEM;
1da177e4
LT
572 return 0;
573}
574
575static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
576{
b6a96915
TI
577 if (dmab->area) {
578 dmab->dev.dev = NULL; /* make it anonymous */
1da177e4 579 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
b6a96915 580 }
1da177e4
LT
581}
582
583
f40b6890 584static struct pci_device_id snd_hdsp_ids[] = {
1da177e4
LT
585 {
586 .vendor = PCI_VENDOR_ID_XILINX,
587 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
588 .subvendor = PCI_ANY_ID,
589 .subdevice = PCI_ANY_ID,
590 }, /* RME Hammerfall-DSP */
591 { 0, },
592};
593
594MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
595
596/* prototypes */
55e957d8
TI
597static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
598static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
599static int snd_hdsp_enable_io (struct hdsp *hdsp);
600static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
601static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
602static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
603static int hdsp_autosync_ref(struct hdsp *hdsp);
604static int snd_hdsp_set_defaults(struct hdsp *hdsp);
605static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
606
607static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
1da177e4
LT
608{
609 switch (hdsp->firmware_rev) {
610 case 0xa:
611 return (64 * out) + (32 + (in));
612 case 0x96:
613 case 0x97:
6add0f42 614 case 0x98:
1da177e4
LT
615 return (32 * out) + (16 + (in));
616 default:
617 return (52 * out) + (26 + (in));
618 }
619}
620
55e957d8 621static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
1da177e4
LT
622{
623 switch (hdsp->firmware_rev) {
624 case 0xa:
625 return (64 * out) + in;
626 case 0x96:
627 case 0x97:
6add0f42 628 case 0x98:
1da177e4
LT
629 return (32 * out) + in;
630 default:
631 return (52 * out) + in;
632 }
633}
634
55e957d8 635static void hdsp_write(struct hdsp *hdsp, int reg, int val)
1da177e4
LT
636{
637 writel(val, hdsp->iobase + reg);
638}
639
55e957d8 640static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
1da177e4
LT
641{
642 return readl (hdsp->iobase + reg);
643}
644
55e957d8 645static int hdsp_check_for_iobox (struct hdsp *hdsp)
1da177e4
LT
646{
647
648 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
649 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
650 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
651 hdsp->state &= ~HDSP_FirmwareLoaded;
652 return -EIO;
653 }
654 return 0;
655
656}
657
55e957d8 658static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
1da177e4
LT
659
660 int i;
661 unsigned long flags;
662
663 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
664
665 snd_printk ("Hammerfall-DSP: loading firmware\n");
666
667 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
668 hdsp_write (hdsp, HDSP_fifoData, 0);
669
670 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
671 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
672 return -EIO;
673 }
674
675 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
676
677 for (i = 0; i < 24413; ++i) {
678 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
679 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
680 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
681 return -EIO;
682 }
683 }
684
b0b98119 685 ssleep(3);
1da177e4
LT
686
687 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
688 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
689 return -EIO;
690 }
691
692#ifdef SNDRV_BIG_ENDIAN
693 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
694#else
695 hdsp->control2_register = 0;
696#endif
697 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
698 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
699
700 }
701 if (hdsp->state & HDSP_InitializationComplete) {
b0b98119 702 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
1da177e4
LT
703 spin_lock_irqsave(&hdsp->lock, flags);
704 snd_hdsp_set_defaults(hdsp);
705 spin_unlock_irqrestore(&hdsp->lock, flags);
706 }
707
708 hdsp->state |= HDSP_FirmwareLoaded;
709
710 return 0;
711}
712
55e957d8 713static int hdsp_get_iobox_version (struct hdsp *hdsp)
1da177e4
LT
714{
715 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
716
717 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
718 hdsp_write (hdsp, HDSP_fifoData, 0);
b0b98119 719 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0)
1da177e4 720 return -EIO;
1da177e4
LT
721
722 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
723 hdsp_write (hdsp, HDSP_fifoData, 0);
724
725 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
726 hdsp->io_type = Multiface;
727 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
728 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
729 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
730 } else {
731 hdsp->io_type = Digiface;
732 }
733 } else {
734 /* firmware was already loaded, get iobox type */
b0b98119 735 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
1da177e4 736 hdsp->io_type = Multiface;
b0b98119 737 else
1da177e4 738 hdsp->io_type = Digiface;
1da177e4
LT
739 }
740 return 0;
741}
742
743
311e70a4
TI
744#ifdef HDSP_FW_LOADER
745static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp);
746#endif
747
748static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
1da177e4 749{
311e70a4
TI
750 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
751 return 0;
1da177e4 752 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
1da177e4 753 hdsp->state &= ~HDSP_FirmwareLoaded;
311e70a4 754 if (! load_on_demand)
b0b98119 755 return -EIO;
311e70a4 756 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
b0b98119 757 /* try to load firmware */
311e70a4
TI
758 if (! (hdsp->state & HDSP_FirmwareCached)) {
759#ifdef HDSP_FW_LOADER
760 if (! hdsp_request_fw_loader(hdsp))
761 return 0;
762#endif
763 snd_printk(KERN_ERR
764 "Hammerfall-DSP: No firmware loaded nor "
765 "cached, please upload firmware.\n");
766 return -EIO;
767 }
768 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
769 snd_printk(KERN_ERR
770 "Hammerfall-DSP: Firmware loading from "
771 "cache failed, please upload manually.\n");
772 return -EIO;
b0b98119 773 }
1da177e4
LT
774 }
775 return 0;
776}
777
778
55e957d8 779static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
1da177e4
LT
780{
781 int i;
782
783 /* the fifoStatus registers reports on how many words
784 are available in the command FIFO.
785 */
786
787 for (i = 0; i < timeout; i++) {
788
789 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
790 return 0;
791
792 /* not very friendly, but we only do this during a firmware
793 load and changing the mixer, so we just put up with it.
794 */
795
796 udelay (100);
797 }
798
799 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
800 count, timeout);
801 return -1;
802}
803
55e957d8 804static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
1da177e4 805{
b0b98119 806 if (addr >= HDSP_MATRIX_MIXER_SIZE)
1da177e4 807 return 0;
b0b98119 808
1da177e4
LT
809 return hdsp->mixer_matrix[addr];
810}
811
55e957d8 812static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
1da177e4
LT
813{
814 unsigned int ad;
815
816 if (addr >= HDSP_MATRIX_MIXER_SIZE)
817 return -1;
818
819 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
820
821 /* from martin bjornsen:
822
823 "You can only write dwords to the
824 mixer memory which contain two
825 mixer values in the low and high
826 word. So if you want to change
827 value 0 you have to read value 1
828 from the cache and write both to
829 the first dword in the mixer
830 memory."
831 */
832
b0b98119 833 if (hdsp->io_type == H9632 && addr >= 512)
1da177e4 834 return 0;
1da177e4 835
b0b98119 836 if (hdsp->io_type == H9652 && addr >= 1352)
1da177e4 837 return 0;
1da177e4
LT
838
839 hdsp->mixer_matrix[addr] = data;
840
841
842 /* `addr' addresses a 16-bit wide address, but
843 the address space accessed via hdsp_write
844 uses byte offsets. put another way, addr
845 varies from 0 to 1351, but to access the
846 corresponding memory location, we need
847 to access 0 to 2703 ...
848 */
849 ad = addr/2;
850
851 hdsp_write (hdsp, 4096 + (ad*4),
852 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
853 hdsp->mixer_matrix[addr&0x7fe]);
854
855 return 0;
856
857 } else {
858
859 ad = (addr << 16) + data;
860
b0b98119 861 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
1da177e4 862 return -1;
1da177e4
LT
863
864 hdsp_write (hdsp, HDSP_fifoData, ad);
865 hdsp->mixer_matrix[addr] = data;
866
867 }
868
869 return 0;
870}
871
55e957d8 872static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
1da177e4
LT
873{
874 unsigned long flags;
875 int ret = 1;
876
877 spin_lock_irqsave(&hdsp->lock, flags);
878 if ((hdsp->playback_pid != hdsp->capture_pid) &&
b0b98119 879 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
1da177e4 880 ret = 0;
1da177e4
LT
881 spin_unlock_irqrestore(&hdsp->lock, flags);
882 return ret;
883}
884
55e957d8 885static int hdsp_external_sample_rate (struct hdsp *hdsp)
1da177e4
LT
886{
887 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
888 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
889
890 switch (rate_bits) {
891 case HDSP_systemFrequency32: return 32000;
892 case HDSP_systemFrequency44_1: return 44100;
893 case HDSP_systemFrequency48: return 48000;
894 case HDSP_systemFrequency64: return 64000;
895 case HDSP_systemFrequency88_2: return 88200;
896 case HDSP_systemFrequency96: return 96000;
897 default:
898 return 0;
899 }
900}
901
55e957d8 902static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
1da177e4
LT
903{
904 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
905 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
906
b0b98119 907 if (status & HDSP_SPDIFErrorFlag)
1da177e4 908 return 0;
1da177e4
LT
909
910 switch (rate_bits) {
911 case HDSP_spdifFrequency32KHz: return 32000;
912 case HDSP_spdifFrequency44_1KHz: return 44100;
913 case HDSP_spdifFrequency48KHz: return 48000;
914 case HDSP_spdifFrequency64KHz: return 64000;
915 case HDSP_spdifFrequency88_2KHz: return 88200;
916 case HDSP_spdifFrequency96KHz: return 96000;
917 case HDSP_spdifFrequency128KHz:
918 if (hdsp->io_type == H9632) return 128000;
919 break;
920 case HDSP_spdifFrequency176_4KHz:
921 if (hdsp->io_type == H9632) return 176400;
922 break;
923 case HDSP_spdifFrequency192KHz:
924 if (hdsp->io_type == H9632) return 192000;
925 break;
926 default:
927 break;
928 }
929 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
930 return 0;
931}
932
55e957d8 933static void hdsp_compute_period_size(struct hdsp *hdsp)
1da177e4
LT
934{
935 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
936}
937
55e957d8 938static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1da177e4
LT
939{
940 int position;
941
942 position = hdsp_read(hdsp, HDSP_statusRegister);
943
b0b98119 944 if (!hdsp->precise_ptr)
1da177e4 945 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1da177e4
LT
946
947 position &= HDSP_BufferPositionMask;
948 position /= 4;
949 position &= (hdsp->period_bytes/2) - 1;
950 return position;
951}
952
55e957d8 953static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1da177e4
LT
954{
955 hdsp_write (hdsp, HDSP_resetPointer, 0);
d7923b2a
RB
956 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
957 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
958 * requires (?) to write again DDS value after a reset pointer
959 * (at least, it works like this) */
960 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1da177e4
LT
961}
962
55e957d8 963static void hdsp_start_audio(struct hdsp *s)
1da177e4
LT
964{
965 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
966 hdsp_write(s, HDSP_controlRegister, s->control_register);
967}
968
55e957d8 969static void hdsp_stop_audio(struct hdsp *s)
1da177e4
LT
970{
971 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
972 hdsp_write(s, HDSP_controlRegister, s->control_register);
973}
974
55e957d8 975static void hdsp_silence_playback(struct hdsp *hdsp)
1da177e4
LT
976{
977 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
978}
979
55e957d8 980static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1da177e4
LT
981{
982 int n;
983
984 spin_lock_irq(&s->lock);
985
986 frames >>= 7;
987 n = 0;
988 while (frames) {
989 n++;
990 frames >>= 1;
991 }
992
993 s->control_register &= ~HDSP_LatencyMask;
994 s->control_register |= hdsp_encode_latency(n);
995
996 hdsp_write(s, HDSP_controlRegister, s->control_register);
997
998 hdsp_compute_period_size(s);
999
1000 spin_unlock_irq(&s->lock);
1001
1002 return 0;
1003}
1004
d7923b2a
RB
1005static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1006{
1007 u64 n;
1008 u32 r;
1009
1010 if (rate >= 112000)
1011 rate /= 4;
1012 else if (rate >= 56000)
1013 rate /= 2;
1014
e4b6088c 1015 n = DDS_NUMERATOR;
d7923b2a
RB
1016 div64_32(&n, rate, &r);
1017 /* n should be less than 2^32 for being written to FREQ register */
1018 snd_assert((n >> 32) == 0);
1019 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1020 value to write it after a reset */
1021 hdsp->dds_value = n;
1022 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1023}
1024
55e957d8 1025static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1da177e4
LT
1026{
1027 int reject_if_open = 0;
1028 int current_rate;
1029 int rate_bits;
1030
1031 /* ASSUMPTION: hdsp->lock is either held, or
1032 there is no need for it (e.g. during module
1033 initialization).
1034 */
1035
1036 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1037 if (called_internally) {
1038 /* request from ctl or card initialization */
b0b98119 1039 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1da177e4
LT
1040 return -1;
1041 } else {
1042 /* hw_param request while in AutoSync mode */
1043 int external_freq = hdsp_external_sample_rate(hdsp);
1044 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1045
b0b98119
TI
1046 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1047 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1048 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1049 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1050 else if (rate != external_freq) {
1051 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1da177e4
LT
1052 return -1;
1053 }
1054 }
1055 }
1056
1057 current_rate = hdsp->system_sample_rate;
1058
1059 /* Changing from a "single speed" to a "double speed" rate is
1060 not allowed if any substreams are open. This is because
1061 such a change causes a shift in the location of
1062 the DMA buffers and a reduction in the number of available
1063 buffers.
1064
1065 Note that a similar but essentially insoluble problem
1066 exists for externally-driven rate changes. All we can do
1067 is to flag rate changes in the read/write routines. */
1068
b0b98119 1069 if (rate > 96000 && hdsp->io_type != H9632)
1da177e4 1070 return -EINVAL;
1da177e4
LT
1071
1072 switch (rate) {
1073 case 32000:
b0b98119 1074 if (current_rate > 48000)
1da177e4 1075 reject_if_open = 1;
1da177e4
LT
1076 rate_bits = HDSP_Frequency32KHz;
1077 break;
1078 case 44100:
b0b98119 1079 if (current_rate > 48000)
1da177e4 1080 reject_if_open = 1;
1da177e4
LT
1081 rate_bits = HDSP_Frequency44_1KHz;
1082 break;
1083 case 48000:
b0b98119 1084 if (current_rate > 48000)
1da177e4 1085 reject_if_open = 1;
1da177e4
LT
1086 rate_bits = HDSP_Frequency48KHz;
1087 break;
1088 case 64000:
b0b98119 1089 if (current_rate <= 48000 || current_rate > 96000)
1da177e4 1090 reject_if_open = 1;
1da177e4
LT
1091 rate_bits = HDSP_Frequency64KHz;
1092 break;
1093 case 88200:
b0b98119 1094 if (current_rate <= 48000 || current_rate > 96000)
1da177e4 1095 reject_if_open = 1;
1da177e4
LT
1096 rate_bits = HDSP_Frequency88_2KHz;
1097 break;
1098 case 96000:
b0b98119 1099 if (current_rate <= 48000 || current_rate > 96000)
1da177e4 1100 reject_if_open = 1;
1da177e4
LT
1101 rate_bits = HDSP_Frequency96KHz;
1102 break;
1103 case 128000:
b0b98119 1104 if (current_rate < 128000)
1da177e4 1105 reject_if_open = 1;
1da177e4
LT
1106 rate_bits = HDSP_Frequency128KHz;
1107 break;
1108 case 176400:
b0b98119 1109 if (current_rate < 128000)
1da177e4 1110 reject_if_open = 1;
1da177e4
LT
1111 rate_bits = HDSP_Frequency176_4KHz;
1112 break;
1113 case 192000:
b0b98119 1114 if (current_rate < 128000)
1da177e4 1115 reject_if_open = 1;
1da177e4
LT
1116 rate_bits = HDSP_Frequency192KHz;
1117 break;
1118 default:
1119 return -EINVAL;
1120 }
1121
1122 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1123 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1124 hdsp->capture_pid,
1125 hdsp->playback_pid);
1126 return -EBUSY;
1127 }
1128
1129 hdsp->control_register &= ~HDSP_FrequencyMask;
1130 hdsp->control_register |= rate_bits;
1131 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1132
d7923b2a
RB
1133 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1134 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1135 hdsp_set_dds_value(hdsp, rate);
1136
1da177e4
LT
1137 if (rate >= 128000) {
1138 hdsp->channel_map = channel_map_H9632_qs;
1139 } else if (rate > 48000) {
b0b98119 1140 if (hdsp->io_type == H9632)
1da177e4 1141 hdsp->channel_map = channel_map_H9632_ds;
b0b98119 1142 else
1da177e4 1143 hdsp->channel_map = channel_map_ds;
1da177e4
LT
1144 } else {
1145 switch (hdsp->io_type) {
1146 case Multiface:
1147 hdsp->channel_map = channel_map_mf_ss;
1148 break;
1149 case Digiface:
1150 case H9652:
1151 hdsp->channel_map = channel_map_df_ss;
1152 break;
1153 case H9632:
1154 hdsp->channel_map = channel_map_H9632_ss;
1155 break;
1156 default:
1157 /* should never happen */
1158 break;
1159 }
1160 }
1161
1162 hdsp->system_sample_rate = rate;
1163
1164 return 0;
1165}
1166
1167/*----------------------------------------------------------------------------
1168 MIDI
1169 ----------------------------------------------------------------------------*/
1170
55e957d8 1171static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1da177e4
LT
1172{
1173 /* the hardware already does the relevant bit-mask with 0xff */
b0b98119 1174 if (id)
1da177e4 1175 return hdsp_read(hdsp, HDSP_midiDataIn1);
b0b98119 1176 else
1da177e4 1177 return hdsp_read(hdsp, HDSP_midiDataIn0);
1da177e4
LT
1178}
1179
55e957d8 1180static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1da177e4
LT
1181{
1182 /* the hardware already does the relevant bit-mask with 0xff */
b0b98119 1183 if (id)
1da177e4 1184 hdsp_write(hdsp, HDSP_midiDataOut1, val);
b0b98119 1185 else
1da177e4 1186 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1da177e4
LT
1187}
1188
55e957d8 1189static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1da177e4 1190{
b0b98119 1191 if (id)
1da177e4 1192 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
b0b98119 1193 else
1da177e4 1194 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1da177e4
LT
1195}
1196
55e957d8 1197static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1da177e4
LT
1198{
1199 int fifo_bytes_used;
1200
b0b98119 1201 if (id)
1da177e4 1202 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
b0b98119 1203 else
1da177e4 1204 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1da177e4 1205
b0b98119 1206 if (fifo_bytes_used < 128)
1da177e4 1207 return 128 - fifo_bytes_used;
b0b98119 1208 else
1da177e4 1209 return 0;
1da177e4
LT
1210}
1211
55e957d8 1212static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1da177e4 1213{
b0b98119 1214 while (snd_hdsp_midi_input_available (hdsp, id))
1da177e4 1215 snd_hdsp_midi_read_byte (hdsp, id);
1da177e4
LT
1216}
1217
55e957d8 1218static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1da177e4
LT
1219{
1220 unsigned long flags;
1221 int n_pending;
1222 int to_write;
1223 int i;
1224 unsigned char buf[128];
1225
1226 /* Output is not interrupt driven */
1227
1228 spin_lock_irqsave (&hmidi->lock, flags);
1229 if (hmidi->output) {
1230 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1231 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1232 if (n_pending > (int)sizeof (buf))
1233 n_pending = sizeof (buf);
1234
1235 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1236 for (i = 0; i < to_write; ++i)
1237 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1238 }
1239 }
1240 }
1241 }
1242 spin_unlock_irqrestore (&hmidi->lock, flags);
1243 return 0;
1244}
1245
55e957d8 1246static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1da177e4
LT
1247{
1248 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1249 unsigned long flags;
1250 int n_pending;
1251 int i;
1252
1253 spin_lock_irqsave (&hmidi->lock, flags);
1254 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1255 if (hmidi->input) {
b0b98119 1256 if (n_pending > (int)sizeof (buf))
1da177e4 1257 n_pending = sizeof (buf);
b0b98119 1258 for (i = 0; i < n_pending; ++i)
1da177e4 1259 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
b0b98119 1260 if (n_pending)
1da177e4 1261 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1da177e4
LT
1262 } else {
1263 /* flush the MIDI input FIFO */
b0b98119 1264 while (--n_pending)
1da177e4 1265 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1da177e4
LT
1266 }
1267 }
1268 hmidi->pending = 0;
b0b98119 1269 if (hmidi->id)
1da177e4 1270 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
b0b98119 1271 else
1da177e4 1272 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1da177e4
LT
1273 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1274 spin_unlock_irqrestore (&hmidi->lock, flags);
1275 return snd_hdsp_midi_output_write (hmidi);
1276}
1277
55e957d8 1278static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4 1279{
55e957d8
TI
1280 struct hdsp *hdsp;
1281 struct hdsp_midi *hmidi;
1da177e4
LT
1282 unsigned long flags;
1283 u32 ie;
1284
55e957d8 1285 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1da177e4
LT
1286 hdsp = hmidi->hdsp;
1287 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1288 spin_lock_irqsave (&hdsp->lock, flags);
1289 if (up) {
1290 if (!(hdsp->control_register & ie)) {
1291 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1292 hdsp->control_register |= ie;
1293 }
1294 } else {
1295 hdsp->control_register &= ~ie;
1296 tasklet_kill(&hdsp->midi_tasklet);
1297 }
1298
1299 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1300 spin_unlock_irqrestore (&hdsp->lock, flags);
1301}
1302
1303static void snd_hdsp_midi_output_timer(unsigned long data)
1304{
55e957d8 1305 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1da177e4
LT
1306 unsigned long flags;
1307
1308 snd_hdsp_midi_output_write(hmidi);
1309 spin_lock_irqsave (&hmidi->lock, flags);
1310
1311 /* this does not bump hmidi->istimer, because the
1312 kernel automatically removed the timer when it
1313 expired, and we are now adding it back, thus
1314 leaving istimer wherever it was set before.
1315 */
1316
1317 if (hmidi->istimer) {
1318 hmidi->timer.expires = 1 + jiffies;
1319 add_timer(&hmidi->timer);
1320 }
1321
1322 spin_unlock_irqrestore (&hmidi->lock, flags);
1323}
1324
55e957d8 1325static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4 1326{
55e957d8 1327 struct hdsp_midi *hmidi;
1da177e4
LT
1328 unsigned long flags;
1329
55e957d8 1330 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1da177e4
LT
1331 spin_lock_irqsave (&hmidi->lock, flags);
1332 if (up) {
1333 if (!hmidi->istimer) {
1334 init_timer(&hmidi->timer);
1335 hmidi->timer.function = snd_hdsp_midi_output_timer;
1336 hmidi->timer.data = (unsigned long) hmidi;
1337 hmidi->timer.expires = 1 + jiffies;
1338 add_timer(&hmidi->timer);
1339 hmidi->istimer++;
1340 }
1341 } else {
b0b98119 1342 if (hmidi->istimer && --hmidi->istimer <= 0)
1da177e4 1343 del_timer (&hmidi->timer);
1da177e4
LT
1344 }
1345 spin_unlock_irqrestore (&hmidi->lock, flags);
1346 if (up)
1347 snd_hdsp_midi_output_write(hmidi);
1348}
1349
55e957d8 1350static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 1351{
55e957d8 1352 struct hdsp_midi *hmidi;
1da177e4 1353
55e957d8 1354 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1da177e4
LT
1355 spin_lock_irq (&hmidi->lock);
1356 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1357 hmidi->input = substream;
1358 spin_unlock_irq (&hmidi->lock);
1359
1360 return 0;
1361}
1362
55e957d8 1363static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 1364{
55e957d8 1365 struct hdsp_midi *hmidi;
1da177e4 1366
55e957d8 1367 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1da177e4
LT
1368 spin_lock_irq (&hmidi->lock);
1369 hmidi->output = substream;
1370 spin_unlock_irq (&hmidi->lock);
1371
1372 return 0;
1373}
1374
55e957d8 1375static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 1376{
55e957d8 1377 struct hdsp_midi *hmidi;
1da177e4
LT
1378
1379 snd_hdsp_midi_input_trigger (substream, 0);
1380
55e957d8 1381 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1da177e4
LT
1382 spin_lock_irq (&hmidi->lock);
1383 hmidi->input = NULL;
1384 spin_unlock_irq (&hmidi->lock);
1385
1386 return 0;
1387}
1388
55e957d8 1389static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 1390{
55e957d8 1391 struct hdsp_midi *hmidi;
1da177e4
LT
1392
1393 snd_hdsp_midi_output_trigger (substream, 0);
1394
55e957d8 1395 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1da177e4
LT
1396 spin_lock_irq (&hmidi->lock);
1397 hmidi->output = NULL;
1398 spin_unlock_irq (&hmidi->lock);
1399
1400 return 0;
1401}
1402
55e957d8 1403static struct snd_rawmidi_ops snd_hdsp_midi_output =
1da177e4
LT
1404{
1405 .open = snd_hdsp_midi_output_open,
1406 .close = snd_hdsp_midi_output_close,
1407 .trigger = snd_hdsp_midi_output_trigger,
1408};
1409
55e957d8 1410static struct snd_rawmidi_ops snd_hdsp_midi_input =
1da177e4
LT
1411{
1412 .open = snd_hdsp_midi_input_open,
1413 .close = snd_hdsp_midi_input_close,
1414 .trigger = snd_hdsp_midi_input_trigger,
1415};
1416
f40b6890 1417static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1da177e4
LT
1418{
1419 char buf[32];
1420
1421 hdsp->midi[id].id = id;
1422 hdsp->midi[id].rmidi = NULL;
1423 hdsp->midi[id].input = NULL;
1424 hdsp->midi[id].output = NULL;
1425 hdsp->midi[id].hdsp = hdsp;
1426 hdsp->midi[id].istimer = 0;
1427 hdsp->midi[id].pending = 0;
1428 spin_lock_init (&hdsp->midi[id].lock);
1429
1430 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
b0b98119 1431 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1da177e4 1432 return -1;
1da177e4
LT
1433
1434 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1435 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1436
1437 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1438 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1439
1440 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1441 SNDRV_RAWMIDI_INFO_INPUT |
1442 SNDRV_RAWMIDI_INFO_DUPLEX;
1443
1444 return 0;
1445}
1446
1447/*-----------------------------------------------------------------------------
1448 Control Interface
1449 ----------------------------------------------------------------------------*/
1450
55e957d8 1451static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT
1452{
1453 u32 val = 0;
1454 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1455 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1456 if (val & HDSP_SPDIFProfessional)
1457 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1458 else
1459 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1460 return val;
1461}
1462
55e957d8 1463static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT
1464{
1465 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1466 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1467 if (val & HDSP_SPDIFProfessional)
1468 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1469 else
1470 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1471}
1472
55e957d8 1473static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1474{
1475 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1476 uinfo->count = 1;
1477 return 0;
1478}
1479
55e957d8 1480static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1481{
55e957d8 1482 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1483
1484 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1485 return 0;
1486}
1487
55e957d8 1488static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1489{
55e957d8 1490 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1491 int change;
1492 u32 val;
1493
1494 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1495 spin_lock_irq(&hdsp->lock);
1496 change = val != hdsp->creg_spdif;
1497 hdsp->creg_spdif = val;
1498 spin_unlock_irq(&hdsp->lock);
1499 return change;
1500}
1501
55e957d8 1502static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1503{
1504 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1505 uinfo->count = 1;
1506 return 0;
1507}
1508
55e957d8 1509static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1510{
55e957d8 1511 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1512
1513 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1514 return 0;
1515}
1516
55e957d8 1517static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1518{
55e957d8 1519 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1520 int change;
1521 u32 val;
1522
1523 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1524 spin_lock_irq(&hdsp->lock);
1525 change = val != hdsp->creg_spdif_stream;
1526 hdsp->creg_spdif_stream = val;
1527 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1528 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1529 spin_unlock_irq(&hdsp->lock);
1530 return change;
1531}
1532
55e957d8 1533static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1534{
1535 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1536 uinfo->count = 1;
1537 return 0;
1538}
1539
55e957d8 1540static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT
1541{
1542 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1543 return 0;
1544}
1545
1546#define HDSP_SPDIF_IN(xname, xindex) \
67ed4161 1547{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
1548 .name = xname, \
1549 .index = xindex, \
1550 .info = snd_hdsp_info_spdif_in, \
1551 .get = snd_hdsp_get_spdif_in, \
1552 .put = snd_hdsp_put_spdif_in }
1553
55e957d8 1554static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1da177e4
LT
1555{
1556 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1557}
1558
55e957d8 1559static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1da177e4
LT
1560{
1561 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1562 hdsp->control_register |= hdsp_encode_spdif_in(in);
1563 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1564 return 0;
1565}
1566
55e957d8 1567static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1568{
1569 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
55e957d8 1570 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1571
1572 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1573 uinfo->count = 1;
1574 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1575 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1576 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1577 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1578 return 0;
1579}
1580
55e957d8 1581static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1582{
55e957d8 1583 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1584
1585 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1586 return 0;
1587}
1588
55e957d8 1589static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1590{
55e957d8 1591 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1592 int change;
1593 unsigned int val;
1594
1595 if (!snd_hdsp_use_is_exclusive(hdsp))
1596 return -EBUSY;
1597 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1598 spin_lock_irq(&hdsp->lock);
1599 change = val != hdsp_spdif_in(hdsp);
1600 if (change)
1601 hdsp_set_spdif_input(hdsp, val);
1602 spin_unlock_irq(&hdsp->lock);
1603 return change;
1604}
1605
1606#define HDSP_SPDIF_OUT(xname, xindex) \
67ed4161 1607{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1da177e4
LT
1608 .info = snd_hdsp_info_spdif_bits, \
1609 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1610
55e957d8 1611static int hdsp_spdif_out(struct hdsp *hdsp)
1da177e4
LT
1612{
1613 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1614}
1615
55e957d8 1616static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
1da177e4 1617{
b0b98119 1618 if (out)
1da177e4 1619 hdsp->control_register |= HDSP_SPDIFOpticalOut;
b0b98119 1620 else
1da177e4 1621 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1da177e4
LT
1622 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1623 return 0;
1624}
1625
a5ce8890 1626#define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info
1da177e4 1627
55e957d8 1628static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1629{
55e957d8 1630 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1631
1632 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1633 return 0;
1634}
1635
55e957d8 1636static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1637{
55e957d8 1638 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1639 int change;
1640 unsigned int val;
1641
1642 if (!snd_hdsp_use_is_exclusive(hdsp))
1643 return -EBUSY;
1644 val = ucontrol->value.integer.value[0] & 1;
1645 spin_lock_irq(&hdsp->lock);
1646 change = (int)val != hdsp_spdif_out(hdsp);
1647 hdsp_set_spdif_output(hdsp, val);
1648 spin_unlock_irq(&hdsp->lock);
1649 return change;
1650}
1651
1652#define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
67ed4161 1653{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1da177e4
LT
1654 .info = snd_hdsp_info_spdif_bits, \
1655 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1656
55e957d8 1657static int hdsp_spdif_professional(struct hdsp *hdsp)
1da177e4
LT
1658{
1659 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1660}
1661
55e957d8 1662static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
1da177e4 1663{
b0b98119 1664 if (val)
1da177e4 1665 hdsp->control_register |= HDSP_SPDIFProfessional;
b0b98119 1666 else
1da177e4 1667 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1da177e4
LT
1668 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1669 return 0;
1670}
1671
55e957d8 1672static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1673{
55e957d8 1674 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1675
1676 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1677 return 0;
1678}
1679
55e957d8 1680static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1681{
55e957d8 1682 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1683 int change;
1684 unsigned int val;
1685
1686 if (!snd_hdsp_use_is_exclusive(hdsp))
1687 return -EBUSY;
1688 val = ucontrol->value.integer.value[0] & 1;
1689 spin_lock_irq(&hdsp->lock);
1690 change = (int)val != hdsp_spdif_professional(hdsp);
1691 hdsp_set_spdif_professional(hdsp, val);
1692 spin_unlock_irq(&hdsp->lock);
1693 return change;
1694}
1695
1696#define HDSP_SPDIF_EMPHASIS(xname, xindex) \
67ed4161 1697{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1da177e4
LT
1698 .info = snd_hdsp_info_spdif_bits, \
1699 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1700
55e957d8 1701static int hdsp_spdif_emphasis(struct hdsp *hdsp)
1da177e4
LT
1702{
1703 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1704}
1705
55e957d8 1706static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
1da177e4 1707{
b0b98119 1708 if (val)
1da177e4 1709 hdsp->control_register |= HDSP_SPDIFEmphasis;
b0b98119 1710 else
1da177e4 1711 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1da177e4
LT
1712 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1713 return 0;
1714}
1715
55e957d8 1716static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1717{
55e957d8 1718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1719
1720 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1721 return 0;
1722}
1723
55e957d8 1724static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1725{
55e957d8 1726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1727 int change;
1728 unsigned int val;
1729
1730 if (!snd_hdsp_use_is_exclusive(hdsp))
1731 return -EBUSY;
1732 val = ucontrol->value.integer.value[0] & 1;
1733 spin_lock_irq(&hdsp->lock);
1734 change = (int)val != hdsp_spdif_emphasis(hdsp);
1735 hdsp_set_spdif_emphasis(hdsp, val);
1736 spin_unlock_irq(&hdsp->lock);
1737 return change;
1738}
1739
1740#define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
67ed4161 1741{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1da177e4
LT
1742 .info = snd_hdsp_info_spdif_bits, \
1743 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1744
55e957d8 1745static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
1da177e4
LT
1746{
1747 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1748}
1749
55e957d8 1750static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
1da177e4 1751{
b0b98119 1752 if (val)
1da177e4 1753 hdsp->control_register |= HDSP_SPDIFNonAudio;
b0b98119 1754 else
1da177e4 1755 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1da177e4
LT
1756 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1757 return 0;
1758}
1759
55e957d8 1760static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1761{
55e957d8 1762 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1763
1764 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1765 return 0;
1766}
1767
55e957d8 1768static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1769{
55e957d8 1770 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1771 int change;
1772 unsigned int val;
1773
1774 if (!snd_hdsp_use_is_exclusive(hdsp))
1775 return -EBUSY;
1776 val = ucontrol->value.integer.value[0] & 1;
1777 spin_lock_irq(&hdsp->lock);
1778 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1779 hdsp_set_spdif_nonaudio(hdsp, val);
1780 spin_unlock_irq(&hdsp->lock);
1781 return change;
1782}
1783
1784#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
67ed4161 1785{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
1786 .name = xname, \
1787 .index = xindex, \
1788 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1789 .info = snd_hdsp_info_spdif_sample_rate, \
1790 .get = snd_hdsp_get_spdif_sample_rate \
1791}
1792
55e957d8 1793static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1794{
1795 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
55e957d8 1796 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1797
1798 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1799 uinfo->count = 1;
1800 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1801 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1802 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1803 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1804 return 0;
1805}
1806
55e957d8 1807static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1808{
55e957d8 1809 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1810
1811 switch (hdsp_spdif_sample_rate(hdsp)) {
1812 case 32000:
1813 ucontrol->value.enumerated.item[0] = 0;
1814 break;
1815 case 44100:
1816 ucontrol->value.enumerated.item[0] = 1;
1817 break;
1818 case 48000:
1819 ucontrol->value.enumerated.item[0] = 2;
1820 break;
1821 case 64000:
1822 ucontrol->value.enumerated.item[0] = 3;
1823 break;
1824 case 88200:
1825 ucontrol->value.enumerated.item[0] = 4;
1826 break;
1827 case 96000:
1828 ucontrol->value.enumerated.item[0] = 5;
1829 break;
1830 case 128000:
1831 ucontrol->value.enumerated.item[0] = 7;
1832 break;
1833 case 176400:
1834 ucontrol->value.enumerated.item[0] = 8;
1835 break;
1836 case 192000:
1837 ucontrol->value.enumerated.item[0] = 9;
1838 break;
1839 default:
1840 ucontrol->value.enumerated.item[0] = 6;
1841 }
1842 return 0;
1843}
1844
1845#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
67ed4161 1846{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
1847 .name = xname, \
1848 .index = xindex, \
1849 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1850 .info = snd_hdsp_info_system_sample_rate, \
1851 .get = snd_hdsp_get_system_sample_rate \
1852}
1853
55e957d8 1854static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1855{
1856 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1857 uinfo->count = 1;
1858 return 0;
1859}
1860
55e957d8 1861static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1862{
55e957d8 1863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1864
1865 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1866 return 0;
1867}
1868
1869#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
67ed4161 1870{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
1871 .name = xname, \
1872 .index = xindex, \
1873 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1874 .info = snd_hdsp_info_autosync_sample_rate, \
1875 .get = snd_hdsp_get_autosync_sample_rate \
1876}
1877
55e957d8 1878static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 1879{
55e957d8 1880 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1881 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1882 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1883 uinfo->count = 1;
1884 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1885 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1886 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1887 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1888 return 0;
1889}
1890
55e957d8 1891static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1892{
55e957d8 1893 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1894
1895 switch (hdsp_external_sample_rate(hdsp)) {
1896 case 32000:
1897 ucontrol->value.enumerated.item[0] = 0;
1898 break;
1899 case 44100:
1900 ucontrol->value.enumerated.item[0] = 1;
1901 break;
1902 case 48000:
1903 ucontrol->value.enumerated.item[0] = 2;
1904 break;
1905 case 64000:
1906 ucontrol->value.enumerated.item[0] = 3;
1907 break;
1908 case 88200:
1909 ucontrol->value.enumerated.item[0] = 4;
1910 break;
1911 case 96000:
1912 ucontrol->value.enumerated.item[0] = 5;
1913 break;
1914 case 128000:
1915 ucontrol->value.enumerated.item[0] = 7;
1916 break;
1917 case 176400:
1918 ucontrol->value.enumerated.item[0] = 8;
1919 break;
1920 case 192000:
1921 ucontrol->value.enumerated.item[0] = 9;
1922 break;
1923 default:
1924 ucontrol->value.enumerated.item[0] = 6;
1925 }
1926 return 0;
1927}
1928
1929#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
67ed4161 1930{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
1931 .name = xname, \
1932 .index = xindex, \
1933 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1934 .info = snd_hdsp_info_system_clock_mode, \
1935 .get = snd_hdsp_get_system_clock_mode \
1936}
1937
55e957d8 1938static int hdsp_system_clock_mode(struct hdsp *hdsp)
1da177e4 1939{
b0b98119 1940 if (hdsp->control_register & HDSP_ClockModeMaster)
1da177e4 1941 return 0;
b0b98119 1942 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1da177e4 1943 return 0;
1da177e4
LT
1944 return 1;
1945}
1946
55e957d8 1947static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
1948{
1949 static char *texts[] = {"Master", "Slave" };
1950
1951 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1952 uinfo->count = 1;
1953 uinfo->value.enumerated.items = 2;
1954 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1955 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1956 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1957 return 0;
1958}
1959
55e957d8 1960static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1961{
55e957d8 1962 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
1963
1964 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1965 return 0;
1966}
1967
1968#define HDSP_CLOCK_SOURCE(xname, xindex) \
67ed4161 1969{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
1970 .name = xname, \
1971 .index = xindex, \
1972 .info = snd_hdsp_info_clock_source, \
1973 .get = snd_hdsp_get_clock_source, \
1974 .put = snd_hdsp_put_clock_source \
1975}
1976
55e957d8 1977static int hdsp_clock_source(struct hdsp *hdsp)
1da177e4
LT
1978{
1979 if (hdsp->control_register & HDSP_ClockModeMaster) {
1980 switch (hdsp->system_sample_rate) {
1981 case 32000:
1982 return 1;
1983 case 44100:
1984 return 2;
1985 case 48000:
1986 return 3;
1987 case 64000:
1988 return 4;
1989 case 88200:
1990 return 5;
1991 case 96000:
1992 return 6;
1993 case 128000:
1994 return 7;
1995 case 176400:
1996 return 8;
1997 case 192000:
1998 return 9;
1999 default:
2000 return 3;
2001 }
2002 } else {
2003 return 0;
2004 }
2005}
2006
55e957d8 2007static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1da177e4
LT
2008{
2009 int rate;
2010 switch (mode) {
2011 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2012 if (hdsp_external_sample_rate(hdsp) != 0) {
2013 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2014 hdsp->control_register &= ~HDSP_ClockModeMaster;
2015 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2016 return 0;
2017 }
2018 }
2019 return -1;
2020 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2021 rate = 32000;
2022 break;
2023 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2024 rate = 44100;
2025 break;
2026 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2027 rate = 48000;
2028 break;
2029 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2030 rate = 64000;
2031 break;
2032 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2033 rate = 88200;
2034 break;
2035 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2036 rate = 96000;
2037 break;
2038 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2039 rate = 128000;
2040 break;
2041 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2042 rate = 176400;
2043 break;
2044 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2045 rate = 192000;
2046 break;
2047 default:
2048 rate = 48000;
2049 }
2050 hdsp->control_register |= HDSP_ClockModeMaster;
2051 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2052 hdsp_set_rate(hdsp, rate, 1);
2053 return 0;
2054}
2055
55e957d8 2056static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2057{
2058 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
55e957d8 2059 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2060
2061 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2062 uinfo->count = 1;
2063 if (hdsp->io_type == H9632)
2064 uinfo->value.enumerated.items = 10;
2065 else
2066 uinfo->value.enumerated.items = 7;
2067 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2068 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2069 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2070 return 0;
2071}
2072
55e957d8 2073static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2074{
55e957d8 2075 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2076
2077 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2078 return 0;
2079}
2080
55e957d8 2081static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2082{
55e957d8 2083 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2084 int change;
2085 int val;
2086
2087 if (!snd_hdsp_use_is_exclusive(hdsp))
2088 return -EBUSY;
2089 val = ucontrol->value.enumerated.item[0];
2090 if (val < 0) val = 0;
2091 if (hdsp->io_type == H9632) {
b0b98119
TI
2092 if (val > 9)
2093 val = 9;
1da177e4 2094 } else {
b0b98119
TI
2095 if (val > 6)
2096 val = 6;
1da177e4
LT
2097 }
2098 spin_lock_irq(&hdsp->lock);
b0b98119 2099 if (val != hdsp_clock_source(hdsp))
1da177e4 2100 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
b0b98119 2101 else
1da177e4 2102 change = 0;
1da177e4
LT
2103 spin_unlock_irq(&hdsp->lock);
2104 return change;
2105}
2106
a5ce8890 2107#define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
e3ea4d89 2108
55e957d8 2109static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
e3ea4d89 2110{
55e957d8 2111 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
e3ea4d89
TI
2112
2113 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2114 return 0;
2115}
2116
55e957d8 2117static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
e3ea4d89 2118{
55e957d8 2119 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
e3ea4d89
TI
2120 int change;
2121
2122 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2123 if (change)
2124 hdsp->clock_source_locked = ucontrol->value.integer.value[0];
2125 return change;
2126}
2127
1da177e4 2128#define HDSP_DA_GAIN(xname, xindex) \
67ed4161 2129{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2130 .name = xname, \
2131 .index = xindex, \
2132 .info = snd_hdsp_info_da_gain, \
2133 .get = snd_hdsp_get_da_gain, \
2134 .put = snd_hdsp_put_da_gain \
2135}
2136
55e957d8 2137static int hdsp_da_gain(struct hdsp *hdsp)
1da177e4
LT
2138{
2139 switch (hdsp->control_register & HDSP_DAGainMask) {
2140 case HDSP_DAGainHighGain:
2141 return 0;
2142 case HDSP_DAGainPlus4dBu:
2143 return 1;
2144 case HDSP_DAGainMinus10dBV:
2145 return 2;
2146 default:
2147 return 1;
2148 }
2149}
2150
55e957d8 2151static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
1da177e4
LT
2152{
2153 hdsp->control_register &= ~HDSP_DAGainMask;
2154 switch (mode) {
2155 case 0:
2156 hdsp->control_register |= HDSP_DAGainHighGain;
2157 break;
2158 case 1:
2159 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2160 break;
2161 case 2:
2162 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2163 break;
2164 default:
2165 return -1;
2166
2167 }
2168 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2169 return 0;
2170}
2171
55e957d8 2172static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2173{
2174 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2175
2176 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2177 uinfo->count = 1;
2178 uinfo->value.enumerated.items = 3;
2179 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2180 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2181 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2182 return 0;
2183}
2184
55e957d8 2185static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2186{
55e957d8 2187 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2188
2189 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2190 return 0;
2191}
2192
55e957d8 2193static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2194{
55e957d8 2195 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2196 int change;
2197 int val;
2198
2199 if (!snd_hdsp_use_is_exclusive(hdsp))
2200 return -EBUSY;
2201 val = ucontrol->value.enumerated.item[0];
2202 if (val < 0) val = 0;
2203 if (val > 2) val = 2;
2204 spin_lock_irq(&hdsp->lock);
b0b98119 2205 if (val != hdsp_da_gain(hdsp))
1da177e4 2206 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
b0b98119 2207 else
1da177e4 2208 change = 0;
1da177e4
LT
2209 spin_unlock_irq(&hdsp->lock);
2210 return change;
2211}
2212
2213#define HDSP_AD_GAIN(xname, xindex) \
67ed4161 2214{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2215 .name = xname, \
2216 .index = xindex, \
2217 .info = snd_hdsp_info_ad_gain, \
2218 .get = snd_hdsp_get_ad_gain, \
2219 .put = snd_hdsp_put_ad_gain \
2220}
2221
55e957d8 2222static int hdsp_ad_gain(struct hdsp *hdsp)
1da177e4
LT
2223{
2224 switch (hdsp->control_register & HDSP_ADGainMask) {
2225 case HDSP_ADGainMinus10dBV:
2226 return 0;
2227 case HDSP_ADGainPlus4dBu:
2228 return 1;
2229 case HDSP_ADGainLowGain:
2230 return 2;
2231 default:
2232 return 1;
2233 }
2234}
2235
55e957d8 2236static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
1da177e4
LT
2237{
2238 hdsp->control_register &= ~HDSP_ADGainMask;
2239 switch (mode) {
2240 case 0:
2241 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2242 break;
2243 case 1:
2244 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2245 break;
2246 case 2:
2247 hdsp->control_register |= HDSP_ADGainLowGain;
2248 break;
2249 default:
2250 return -1;
2251
2252 }
2253 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2254 return 0;
2255}
2256
55e957d8 2257static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2258{
2259 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2260
2261 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2262 uinfo->count = 1;
2263 uinfo->value.enumerated.items = 3;
2264 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2265 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2266 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2267 return 0;
2268}
2269
55e957d8 2270static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2271{
55e957d8 2272 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2273
2274 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2275 return 0;
2276}
2277
55e957d8 2278static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2279{
55e957d8 2280 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2281 int change;
2282 int val;
2283
2284 if (!snd_hdsp_use_is_exclusive(hdsp))
2285 return -EBUSY;
2286 val = ucontrol->value.enumerated.item[0];
2287 if (val < 0) val = 0;
2288 if (val > 2) val = 2;
2289 spin_lock_irq(&hdsp->lock);
b0b98119 2290 if (val != hdsp_ad_gain(hdsp))
1da177e4 2291 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
b0b98119 2292 else
1da177e4 2293 change = 0;
1da177e4
LT
2294 spin_unlock_irq(&hdsp->lock);
2295 return change;
2296}
2297
2298#define HDSP_PHONE_GAIN(xname, xindex) \
67ed4161 2299{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2300 .name = xname, \
2301 .index = xindex, \
2302 .info = snd_hdsp_info_phone_gain, \
2303 .get = snd_hdsp_get_phone_gain, \
2304 .put = snd_hdsp_put_phone_gain \
2305}
2306
55e957d8 2307static int hdsp_phone_gain(struct hdsp *hdsp)
1da177e4
LT
2308{
2309 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2310 case HDSP_PhoneGain0dB:
2311 return 0;
2312 case HDSP_PhoneGainMinus6dB:
2313 return 1;
2314 case HDSP_PhoneGainMinus12dB:
2315 return 2;
2316 default:
2317 return 0;
2318 }
2319}
2320
55e957d8 2321static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
1da177e4
LT
2322{
2323 hdsp->control_register &= ~HDSP_PhoneGainMask;
2324 switch (mode) {
2325 case 0:
2326 hdsp->control_register |= HDSP_PhoneGain0dB;
2327 break;
2328 case 1:
2329 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2330 break;
2331 case 2:
2332 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2333 break;
2334 default:
2335 return -1;
2336
2337 }
2338 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2339 return 0;
2340}
2341
55e957d8 2342static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2343{
2344 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2345
2346 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2347 uinfo->count = 1;
2348 uinfo->value.enumerated.items = 3;
2349 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2350 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2351 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2352 return 0;
2353}
2354
55e957d8 2355static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2356{
55e957d8 2357 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2358
2359 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2360 return 0;
2361}
2362
55e957d8 2363static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2364{
55e957d8 2365 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2366 int change;
2367 int val;
2368
2369 if (!snd_hdsp_use_is_exclusive(hdsp))
2370 return -EBUSY;
2371 val = ucontrol->value.enumerated.item[0];
2372 if (val < 0) val = 0;
2373 if (val > 2) val = 2;
2374 spin_lock_irq(&hdsp->lock);
b0b98119 2375 if (val != hdsp_phone_gain(hdsp))
1da177e4 2376 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
b0b98119 2377 else
1da177e4 2378 change = 0;
1da177e4
LT
2379 spin_unlock_irq(&hdsp->lock);
2380 return change;
2381}
2382
2383#define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
67ed4161 2384{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2385 .name = xname, \
2386 .index = xindex, \
2387 .info = snd_hdsp_info_xlr_breakout_cable, \
2388 .get = snd_hdsp_get_xlr_breakout_cable, \
2389 .put = snd_hdsp_put_xlr_breakout_cable \
2390}
2391
55e957d8 2392static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
1da177e4 2393{
b0b98119 2394 if (hdsp->control_register & HDSP_XLRBreakoutCable)
1da177e4 2395 return 1;
1da177e4
LT
2396 return 0;
2397}
2398
55e957d8 2399static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
1da177e4 2400{
b0b98119 2401 if (mode)
1da177e4 2402 hdsp->control_register |= HDSP_XLRBreakoutCable;
b0b98119 2403 else
1da177e4 2404 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
1da177e4
LT
2405 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2406 return 0;
2407}
2408
a5ce8890 2409#define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info
1da177e4 2410
55e957d8 2411static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2412{
55e957d8 2413 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2414
2415 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2416 return 0;
2417}
2418
55e957d8 2419static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2420{
55e957d8 2421 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2422 int change;
2423 int val;
2424
2425 if (!snd_hdsp_use_is_exclusive(hdsp))
2426 return -EBUSY;
2427 val = ucontrol->value.integer.value[0] & 1;
2428 spin_lock_irq(&hdsp->lock);
2429 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2430 hdsp_set_xlr_breakout_cable(hdsp, val);
2431 spin_unlock_irq(&hdsp->lock);
2432 return change;
2433}
2434
2435/* (De)activates old RME Analog Extension Board
2436 These are connected to the internal ADAT connector
2437 Switching this on desactivates external ADAT
2438*/
2439#define HDSP_AEB(xname, xindex) \
67ed4161 2440{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2441 .name = xname, \
2442 .index = xindex, \
2443 .info = snd_hdsp_info_aeb, \
2444 .get = snd_hdsp_get_aeb, \
2445 .put = snd_hdsp_put_aeb \
2446}
2447
55e957d8 2448static int hdsp_aeb(struct hdsp *hdsp)
1da177e4 2449{
b0b98119 2450 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
1da177e4 2451 return 1;
1da177e4
LT
2452 return 0;
2453}
2454
55e957d8 2455static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
1da177e4 2456{
b0b98119 2457 if (mode)
1da177e4 2458 hdsp->control_register |= HDSP_AnalogExtensionBoard;
b0b98119 2459 else
1da177e4 2460 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
1da177e4
LT
2461 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2462 return 0;
2463}
2464
a5ce8890 2465#define snd_hdsp_info_aeb snd_ctl_boolean_mono_info
1da177e4 2466
55e957d8 2467static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2468{
55e957d8 2469 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2470
2471 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2472 return 0;
2473}
2474
55e957d8 2475static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2476{
55e957d8 2477 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2478 int change;
2479 int val;
2480
2481 if (!snd_hdsp_use_is_exclusive(hdsp))
2482 return -EBUSY;
2483 val = ucontrol->value.integer.value[0] & 1;
2484 spin_lock_irq(&hdsp->lock);
2485 change = (int)val != hdsp_aeb(hdsp);
2486 hdsp_set_aeb(hdsp, val);
2487 spin_unlock_irq(&hdsp->lock);
2488 return change;
2489}
2490
2491#define HDSP_PREF_SYNC_REF(xname, xindex) \
67ed4161 2492{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2493 .name = xname, \
2494 .index = xindex, \
2495 .info = snd_hdsp_info_pref_sync_ref, \
2496 .get = snd_hdsp_get_pref_sync_ref, \
2497 .put = snd_hdsp_put_pref_sync_ref \
2498}
2499
55e957d8 2500static int hdsp_pref_sync_ref(struct hdsp *hdsp)
1da177e4
LT
2501{
2502 /* Notice that this looks at the requested sync source,
2503 not the one actually in use.
2504 */
2505
2506 switch (hdsp->control_register & HDSP_SyncRefMask) {
2507 case HDSP_SyncRef_ADAT1:
2508 return HDSP_SYNC_FROM_ADAT1;
2509 case HDSP_SyncRef_ADAT2:
2510 return HDSP_SYNC_FROM_ADAT2;
2511 case HDSP_SyncRef_ADAT3:
2512 return HDSP_SYNC_FROM_ADAT3;
2513 case HDSP_SyncRef_SPDIF:
2514 return HDSP_SYNC_FROM_SPDIF;
2515 case HDSP_SyncRef_WORD:
2516 return HDSP_SYNC_FROM_WORD;
2517 case HDSP_SyncRef_ADAT_SYNC:
2518 return HDSP_SYNC_FROM_ADAT_SYNC;
2519 default:
2520 return HDSP_SYNC_FROM_WORD;
2521 }
2522 return 0;
2523}
2524
55e957d8 2525static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
1da177e4
LT
2526{
2527 hdsp->control_register &= ~HDSP_SyncRefMask;
2528 switch (pref) {
2529 case HDSP_SYNC_FROM_ADAT1:
2530 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2531 break;
2532 case HDSP_SYNC_FROM_ADAT2:
2533 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2534 break;
2535 case HDSP_SYNC_FROM_ADAT3:
2536 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2537 break;
2538 case HDSP_SYNC_FROM_SPDIF:
2539 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2540 break;
2541 case HDSP_SYNC_FROM_WORD:
2542 hdsp->control_register |= HDSP_SyncRef_WORD;
2543 break;
2544 case HDSP_SYNC_FROM_ADAT_SYNC:
2545 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2546 break;
2547 default:
2548 return -1;
2549 }
2550 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2551 return 0;
2552}
2553
55e957d8 2554static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2555{
2556 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
55e957d8 2557 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2558
2559 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2560 uinfo->count = 1;
2561
2562 switch (hdsp->io_type) {
2563 case Digiface:
2564 case H9652:
2565 uinfo->value.enumerated.items = 6;
2566 break;
2567 case Multiface:
2568 uinfo->value.enumerated.items = 4;
2569 break;
2570 case H9632:
2571 uinfo->value.enumerated.items = 3;
2572 break;
2573 default:
2574 uinfo->value.enumerated.items = 0;
2575 break;
2576 }
2577
2578 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2579 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2580 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2581 return 0;
2582}
2583
55e957d8 2584static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2585{
55e957d8 2586 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2587
2588 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2589 return 0;
2590}
2591
55e957d8 2592static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2593{
55e957d8 2594 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2595 int change, max;
2596 unsigned int val;
2597
2598 if (!snd_hdsp_use_is_exclusive(hdsp))
2599 return -EBUSY;
2600
2601 switch (hdsp->io_type) {
2602 case Digiface:
2603 case H9652:
2604 max = 6;
2605 break;
2606 case Multiface:
2607 max = 4;
2608 break;
2609 case H9632:
2610 max = 3;
2611 break;
2612 default:
2613 return -EIO;
2614 }
2615
2616 val = ucontrol->value.enumerated.item[0] % max;
2617 spin_lock_irq(&hdsp->lock);
2618 change = (int)val != hdsp_pref_sync_ref(hdsp);
2619 hdsp_set_pref_sync_ref(hdsp, val);
2620 spin_unlock_irq(&hdsp->lock);
2621 return change;
2622}
2623
2624#define HDSP_AUTOSYNC_REF(xname, xindex) \
67ed4161 2625{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2626 .name = xname, \
2627 .index = xindex, \
2628 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2629 .info = snd_hdsp_info_autosync_ref, \
2630 .get = snd_hdsp_get_autosync_ref, \
2631}
2632
55e957d8 2633static int hdsp_autosync_ref(struct hdsp *hdsp)
1da177e4
LT
2634{
2635 /* This looks at the autosync selected sync reference */
2636 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2637
2638 switch (status2 & HDSP_SelSyncRefMask) {
2639 case HDSP_SelSyncRef_WORD:
2640 return HDSP_AUTOSYNC_FROM_WORD;
2641 case HDSP_SelSyncRef_ADAT_SYNC:
2642 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2643 case HDSP_SelSyncRef_SPDIF:
2644 return HDSP_AUTOSYNC_FROM_SPDIF;
2645 case HDSP_SelSyncRefMask:
2646 return HDSP_AUTOSYNC_FROM_NONE;
2647 case HDSP_SelSyncRef_ADAT1:
2648 return HDSP_AUTOSYNC_FROM_ADAT1;
2649 case HDSP_SelSyncRef_ADAT2:
2650 return HDSP_AUTOSYNC_FROM_ADAT2;
2651 case HDSP_SelSyncRef_ADAT3:
2652 return HDSP_AUTOSYNC_FROM_ADAT3;
2653 default:
2654 return HDSP_AUTOSYNC_FROM_WORD;
2655 }
2656 return 0;
2657}
2658
55e957d8 2659static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2660{
2661 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2662
2663 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2664 uinfo->count = 1;
2665 uinfo->value.enumerated.items = 7;
2666 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2667 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2668 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2669 return 0;
2670}
2671
55e957d8 2672static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2673{
55e957d8 2674 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2675
2676 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2677 return 0;
2678}
2679
2680#define HDSP_LINE_OUT(xname, xindex) \
67ed4161 2681{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2682 .name = xname, \
2683 .index = xindex, \
2684 .info = snd_hdsp_info_line_out, \
2685 .get = snd_hdsp_get_line_out, \
2686 .put = snd_hdsp_put_line_out \
2687}
2688
55e957d8 2689static int hdsp_line_out(struct hdsp *hdsp)
1da177e4
LT
2690{
2691 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2692}
2693
55e957d8 2694static int hdsp_set_line_output(struct hdsp *hdsp, int out)
1da177e4 2695{
b0b98119 2696 if (out)
1da177e4 2697 hdsp->control_register |= HDSP_LineOut;
b0b98119 2698 else
1da177e4 2699 hdsp->control_register &= ~HDSP_LineOut;
1da177e4
LT
2700 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2701 return 0;
2702}
2703
a5ce8890 2704#define snd_hdsp_info_line_out snd_ctl_boolean_mono_info
1da177e4 2705
55e957d8 2706static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2707{
55e957d8 2708 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2709
2710 spin_lock_irq(&hdsp->lock);
2711 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2712 spin_unlock_irq(&hdsp->lock);
2713 return 0;
2714}
2715
55e957d8 2716static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2717{
55e957d8 2718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2719 int change;
2720 unsigned int val;
2721
2722 if (!snd_hdsp_use_is_exclusive(hdsp))
2723 return -EBUSY;
2724 val = ucontrol->value.integer.value[0] & 1;
2725 spin_lock_irq(&hdsp->lock);
2726 change = (int)val != hdsp_line_out(hdsp);
2727 hdsp_set_line_output(hdsp, val);
2728 spin_unlock_irq(&hdsp->lock);
2729 return change;
2730}
2731
2732#define HDSP_PRECISE_POINTER(xname, xindex) \
67ed4161 2733{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
1da177e4
LT
2734 .name = xname, \
2735 .index = xindex, \
2736 .info = snd_hdsp_info_precise_pointer, \
2737 .get = snd_hdsp_get_precise_pointer, \
2738 .put = snd_hdsp_put_precise_pointer \
2739}
2740
55e957d8 2741static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
1da177e4 2742{
b0b98119 2743 if (precise)
1da177e4 2744 hdsp->precise_ptr = 1;
b0b98119 2745 else
1da177e4 2746 hdsp->precise_ptr = 0;
1da177e4
LT
2747 return 0;
2748}
2749
a5ce8890 2750#define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
1da177e4 2751
55e957d8 2752static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2753{
55e957d8 2754 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2755
2756 spin_lock_irq(&hdsp->lock);
2757 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2758 spin_unlock_irq(&hdsp->lock);
2759 return 0;
2760}
2761
55e957d8 2762static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2763{
55e957d8 2764 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2765 int change;
2766 unsigned int val;
2767
2768 if (!snd_hdsp_use_is_exclusive(hdsp))
2769 return -EBUSY;
2770 val = ucontrol->value.integer.value[0] & 1;
2771 spin_lock_irq(&hdsp->lock);
2772 change = (int)val != hdsp->precise_ptr;
2773 hdsp_set_precise_pointer(hdsp, val);
2774 spin_unlock_irq(&hdsp->lock);
2775 return change;
2776}
2777
2778#define HDSP_USE_MIDI_TASKLET(xname, xindex) \
67ed4161 2779{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
1da177e4
LT
2780 .name = xname, \
2781 .index = xindex, \
2782 .info = snd_hdsp_info_use_midi_tasklet, \
2783 .get = snd_hdsp_get_use_midi_tasklet, \
2784 .put = snd_hdsp_put_use_midi_tasklet \
2785}
2786
55e957d8 2787static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
1da177e4 2788{
b0b98119 2789 if (use_tasklet)
1da177e4 2790 hdsp->use_midi_tasklet = 1;
b0b98119 2791 else
1da177e4 2792 hdsp->use_midi_tasklet = 0;
1da177e4
LT
2793 return 0;
2794}
2795
a5ce8890 2796#define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
1da177e4 2797
55e957d8 2798static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2799{
55e957d8 2800 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2801
2802 spin_lock_irq(&hdsp->lock);
2803 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2804 spin_unlock_irq(&hdsp->lock);
2805 return 0;
2806}
2807
55e957d8 2808static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2809{
55e957d8 2810 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2811 int change;
2812 unsigned int val;
2813
2814 if (!snd_hdsp_use_is_exclusive(hdsp))
2815 return -EBUSY;
2816 val = ucontrol->value.integer.value[0] & 1;
2817 spin_lock_irq(&hdsp->lock);
2818 change = (int)val != hdsp->use_midi_tasklet;
2819 hdsp_set_use_midi_tasklet(hdsp, val);
2820 spin_unlock_irq(&hdsp->lock);
2821 return change;
2822}
2823
2824#define HDSP_MIXER(xname, xindex) \
2825{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2826 .name = xname, \
2827 .index = xindex, \
67ed4161 2828 .device = 0, \
1da177e4
LT
2829 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2830 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2831 .info = snd_hdsp_info_mixer, \
2832 .get = snd_hdsp_get_mixer, \
2833 .put = snd_hdsp_put_mixer \
2834}
2835
55e957d8 2836static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2837{
2838 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2839 uinfo->count = 3;
2840 uinfo->value.integer.min = 0;
2841 uinfo->value.integer.max = 65536;
2842 uinfo->value.integer.step = 1;
2843 return 0;
2844}
2845
55e957d8 2846static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2847{
55e957d8 2848 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2849 int source;
2850 int destination;
2851 int addr;
2852
2853 source = ucontrol->value.integer.value[0];
2854 destination = ucontrol->value.integer.value[1];
2855
b0b98119 2856 if (source >= hdsp->max_channels)
1da177e4 2857 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
b0b98119 2858 else
1da177e4 2859 addr = hdsp_input_to_output_key(hdsp,source, destination);
1da177e4
LT
2860
2861 spin_lock_irq(&hdsp->lock);
2862 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2863 spin_unlock_irq(&hdsp->lock);
2864 return 0;
2865}
2866
55e957d8 2867static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2868{
55e957d8 2869 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2870 int change;
2871 int source;
2872 int destination;
2873 int gain;
2874 int addr;
2875
2876 if (!snd_hdsp_use_is_exclusive(hdsp))
2877 return -EBUSY;
2878
2879 source = ucontrol->value.integer.value[0];
2880 destination = ucontrol->value.integer.value[1];
2881
b0b98119 2882 if (source >= hdsp->max_channels)
1da177e4 2883 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
b0b98119 2884 else
1da177e4 2885 addr = hdsp_input_to_output_key(hdsp,source, destination);
1da177e4
LT
2886
2887 gain = ucontrol->value.integer.value[2];
2888
2889 spin_lock_irq(&hdsp->lock);
2890 change = gain != hdsp_read_gain(hdsp, addr);
2891 if (change)
2892 hdsp_write_gain(hdsp, addr, gain);
2893 spin_unlock_irq(&hdsp->lock);
2894 return change;
2895}
2896
2897#define HDSP_WC_SYNC_CHECK(xname, xindex) \
67ed4161 2898{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2899 .name = xname, \
2900 .index = xindex, \
2901 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2902 .info = snd_hdsp_info_sync_check, \
2903 .get = snd_hdsp_get_wc_sync_check \
2904}
2905
55e957d8 2906static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT
2907{
2908 static char *texts[] = {"No Lock", "Lock", "Sync" };
2909 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2910 uinfo->count = 1;
2911 uinfo->value.enumerated.items = 3;
2912 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2913 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2914 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2915 return 0;
2916}
2917
55e957d8 2918static int hdsp_wc_sync_check(struct hdsp *hdsp)
1da177e4
LT
2919{
2920 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2921 if (status2 & HDSP_wc_lock) {
b0b98119 2922 if (status2 & HDSP_wc_sync)
1da177e4 2923 return 2;
b0b98119 2924 else
1da177e4 2925 return 1;
b0b98119 2926 } else
1da177e4 2927 return 0;
1da177e4
LT
2928 return 0;
2929}
2930
55e957d8 2931static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2932{
55e957d8 2933 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2934
2935 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2936 return 0;
2937}
2938
2939#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
67ed4161 2940{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2941 .name = xname, \
2942 .index = xindex, \
2943 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2944 .info = snd_hdsp_info_sync_check, \
2945 .get = snd_hdsp_get_spdif_sync_check \
2946}
2947
55e957d8 2948static int hdsp_spdif_sync_check(struct hdsp *hdsp)
1da177e4
LT
2949{
2950 int status = hdsp_read(hdsp, HDSP_statusRegister);
b0b98119 2951 if (status & HDSP_SPDIFErrorFlag)
1da177e4 2952 return 0;
b0b98119
TI
2953 else {
2954 if (status & HDSP_SPDIFSync)
1da177e4 2955 return 2;
b0b98119 2956 else
1da177e4 2957 return 1;
1da177e4
LT
2958 }
2959 return 0;
2960}
2961
55e957d8 2962static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2963{
55e957d8 2964 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2965
2966 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2967 return 0;
2968}
2969
2970#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
67ed4161 2971{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
2972 .name = xname, \
2973 .index = xindex, \
2974 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2975 .info = snd_hdsp_info_sync_check, \
2976 .get = snd_hdsp_get_adatsync_sync_check \
2977}
2978
55e957d8 2979static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
1da177e4
LT
2980{
2981 int status = hdsp_read(hdsp, HDSP_statusRegister);
2982 if (status & HDSP_TimecodeLock) {
b0b98119 2983 if (status & HDSP_TimecodeSync)
1da177e4 2984 return 2;
b0b98119 2985 else
1da177e4 2986 return 1;
b0b98119 2987 } else
1da177e4 2988 return 0;
1da177e4
LT
2989}
2990
55e957d8 2991static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2992{
55e957d8 2993 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
2994
2995 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2996 return 0;
2997}
2998
2999#define HDSP_ADAT_SYNC_CHECK \
67ed4161 3000{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1da177e4
LT
3001 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3002 .info = snd_hdsp_info_sync_check, \
3003 .get = snd_hdsp_get_adat_sync_check \
3004}
3005
55e957d8 3006static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
1da177e4
LT
3007{
3008 int status = hdsp_read(hdsp, HDSP_statusRegister);
3009
3010 if (status & (HDSP_Lock0>>idx)) {
b0b98119 3011 if (status & (HDSP_Sync0>>idx))
1da177e4 3012 return 2;
b0b98119 3013 else
1da177e4 3014 return 1;
b0b98119 3015 } else
1da177e4 3016 return 0;
1da177e4
LT
3017}
3018
55e957d8 3019static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT
3020{
3021 int offset;
55e957d8 3022 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1da177e4
LT
3023
3024 offset = ucontrol->id.index - 1;
3025 snd_assert(offset >= 0);
3026
3027 switch (hdsp->io_type) {
3028 case Digiface:
3029 case H9652:
3030 if (offset >= 3)
3031 return -EINVAL;
3032 break;
3033 case Multiface:
3034 case H9632:
3035 if (offset >= 1)
3036 return -EINVAL;
3037 break;
3038 default:
3039 return -EIO;
3040 }
3041
3042 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3043 return 0;
3044}
3045
e4b6088c
JC
3046#define HDSP_DDS_OFFSET(xname, xindex) \
3047{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3048 .name = xname, \
3049 .index = xindex, \
3050 .info = snd_hdsp_info_dds_offset, \
3051 .get = snd_hdsp_get_dds_offset, \
3052 .put = snd_hdsp_put_dds_offset \
3053}
3054
3055static int hdsp_dds_offset(struct hdsp *hdsp)
3056{
3057 u64 n;
3058 u32 r;
3059 unsigned int dds_value = hdsp->dds_value;
3060 int system_sample_rate = hdsp->system_sample_rate;
3061
3062 n = DDS_NUMERATOR;
3063 /*
3064 * dds_value = n / rate
3065 * rate = n / dds_value
3066 */
3067 div64_32(&n, dds_value, &r);
3068 if (system_sample_rate >= 112000)
3069 n *= 4;
3070 else if (system_sample_rate >= 56000)
3071 n *= 2;
3072 return ((int)n) - system_sample_rate;
3073}
3074
3075static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
3076{
3077 int rate = hdsp->system_sample_rate + offset_hz;
3078 hdsp_set_dds_value(hdsp, rate);
3079 return 0;
3080}
3081
3082static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3083{
3084 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3085 uinfo->count = 1;
3086 uinfo->value.integer.min = -5000;
3087 uinfo->value.integer.max = 5000;
3088 return 0;
3089}
3090
3091static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3092{
3093 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3094
3095 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
3096 return 0;
3097}
3098
3099static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3100{
3101 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3102 int change;
3103 int val;
3104
3105 if (!snd_hdsp_use_is_exclusive(hdsp))
3106 return -EBUSY;
3107 val = ucontrol->value.enumerated.item[0];
3108 spin_lock_irq(&hdsp->lock);
3109 if (val != hdsp_dds_offset(hdsp))
3110 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
3111 else
3112 change = 0;
3113 spin_unlock_irq(&hdsp->lock);
3114 return change;
3115}
3116
55e957d8 3117static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
1da177e4
LT
3118HDSP_DA_GAIN("DA Gain", 0),
3119HDSP_AD_GAIN("AD Gain", 0),
3120HDSP_PHONE_GAIN("Phones Gain", 0),
e4b6088c
JC
3121HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0),
3122HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
1da177e4
LT
3123};
3124
55e957d8 3125static struct snd_kcontrol_new snd_hdsp_controls[] = {
1da177e4 3126{
5549d549 3127 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT
3128 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3129 .info = snd_hdsp_control_spdif_info,
3130 .get = snd_hdsp_control_spdif_get,
3131 .put = snd_hdsp_control_spdif_put,
3132},
3133{
3134 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
5549d549 3135 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT
3136 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3137 .info = snd_hdsp_control_spdif_stream_info,
3138 .get = snd_hdsp_control_spdif_stream_get,
3139 .put = snd_hdsp_control_spdif_stream_put,
3140},
3141{
3142 .access = SNDRV_CTL_ELEM_ACCESS_READ,
5549d549 3143 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT
3144 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3145 .info = snd_hdsp_control_spdif_mask_info,
3146 .get = snd_hdsp_control_spdif_mask_get,
3147 .private_value = IEC958_AES0_NONAUDIO |
3148 IEC958_AES0_PROFESSIONAL |
3149 IEC958_AES0_CON_EMPHASIS,
3150},
3151{
3152 .access = SNDRV_CTL_ELEM_ACCESS_READ,
5549d549 3153 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT
3154 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3155 .info = snd_hdsp_control_spdif_mask_info,
3156 .get = snd_hdsp_control_spdif_mask_get,
3157 .private_value = IEC958_AES0_NONAUDIO |
3158 IEC958_AES0_PROFESSIONAL |
3159 IEC958_AES0_PRO_EMPHASIS,
3160},
3161HDSP_MIXER("Mixer", 0),
3162HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3163HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3164HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3165HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3166HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3167/* 'Sample Clock Source' complies with the alsa control naming scheme */
3168HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
e3ea4d89 3169{
e3ea4d89
TI
3170 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3171 .name = "Sample Clock Source Locking",
3172 .info = snd_hdsp_info_clock_source_lock,
3173 .get = snd_hdsp_get_clock_source_lock,
3174 .put = snd_hdsp_put_clock_source_lock,
3175},
1da177e4
LT
3176HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3177HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3178HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3179HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3180HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3181/* 'External Rate' complies with the alsa control naming scheme */
3182HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3183HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3184HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3185HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3186HDSP_LINE_OUT("Line Out", 0),
3187HDSP_PRECISE_POINTER("Precise Pointer", 0),
3188HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3189};
3190
55e957d8
TI
3191static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3192static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
1da177e4 3193
55e957d8 3194static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
1da177e4
LT
3195{
3196 unsigned int idx;
3197 int err;
55e957d8 3198 struct snd_kcontrol *kctl;
1da177e4
LT
3199
3200 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
b0b98119 3201 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
1da177e4 3202 return err;
1da177e4
LT
3203 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3204 hdsp->spdif_ctl = kctl;
3205 }
3206
3207 /* ADAT SyncCheck status */
3208 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3209 snd_hdsp_adat_sync_check.index = 1;
b0b98119 3210 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
1da177e4 3211 return err;
1da177e4
LT
3212 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3213 for (idx = 1; idx < 3; ++idx) {
3214 snd_hdsp_adat_sync_check.index = idx+1;
b0b98119 3215 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
1da177e4 3216 return err;
1da177e4
LT
3217 }
3218 }
3219
3220 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3221 if (hdsp->io_type == H9632) {
3222 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
b0b98119 3223 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
1da177e4 3224 return err;
1da177e4
LT
3225 }
3226 }
3227
3228 /* AEB control for H96xx card */
3229 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
b0b98119 3230 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
1da177e4 3231 return err;
1da177e4
LT
3232 }
3233
3234 return 0;
3235}
3236
3237/*------------------------------------------------------------
3238 /proc interface
3239 ------------------------------------------------------------*/
3240
3241static void
55e957d8 3242snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4 3243{
55e957d8 3244 struct hdsp *hdsp = (struct hdsp *) entry->private_data;
1da177e4
LT
3245 unsigned int status;
3246 unsigned int status2;
3247 char *pref_sync_ref;
3248 char *autosync_ref;
3249 char *system_clock_mode;
3250 char *clock_source;
3251 int x;
3252
ecb594e6 3253 if (hdsp_check_for_iobox (hdsp)) {
1da177e4
LT
3254 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3255 return;
ecb594e6 3256 }
1da177e4 3257
b0b98119 3258 if (hdsp_check_for_firmware(hdsp, 0)) {
1da177e4
LT
3259 if (hdsp->state & HDSP_FirmwareCached) {
3260 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3261 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3262 return;
3263 }
3264 } else {
311e70a4
TI
3265 int err = -EINVAL;
3266#ifdef HDSP_FW_LOADER
3267 err = hdsp_request_fw_loader(hdsp);
3268#endif
3269 if (err < 0) {
3270 snd_iprintf(buffer,
3271 "No firmware loaded nor cached, "
3272 "please upload firmware.\n");
3273 return;
3274 }
1da177e4
LT
3275 }
3276 }
3277
3278 status = hdsp_read(hdsp, HDSP_statusRegister);
3279 status2 = hdsp_read(hdsp, HDSP_status2Register);
3280
3281 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3282 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3283 hdsp->capture_buffer, hdsp->playback_buffer);
3284 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3285 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3286 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3287 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3288 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3289 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3290 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3291 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3292 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3293 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3294 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3295 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3296
3297 snd_iprintf(buffer, "\n");
3298
3299 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3300
3301 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3302 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3303 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3304 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3305
3306 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3307
3308 snd_iprintf(buffer, "\n");
3309
3310
3311 switch (hdsp_clock_source(hdsp)) {
3312 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3313 clock_source = "AutoSync";
3314 break;
3315 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3316 clock_source = "Internal 32 kHz";
3317 break;
3318 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3319 clock_source = "Internal 44.1 kHz";
3320 break;
3321 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3322 clock_source = "Internal 48 kHz";
3323 break;
3324 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3325 clock_source = "Internal 64 kHz";
3326 break;
3327 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3328 clock_source = "Internal 88.2 kHz";
3329 break;
3330 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3331 clock_source = "Internal 96 kHz";
3332 break;
3333 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3334 clock_source = "Internal 128 kHz";
3335 break;
3336 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3337 clock_source = "Internal 176.4 kHz";
3338 break;
3339 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3340 clock_source = "Internal 192 kHz";
3341 break;
3342 default:
3343 clock_source = "Error";
3344 }
3345 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3346
b0b98119 3347 if (hdsp_system_clock_mode(hdsp))
1da177e4 3348 system_clock_mode = "Slave";
b0b98119 3349 else
1da177e4 3350 system_clock_mode = "Master";
1da177e4
LT
3351
3352 switch (hdsp_pref_sync_ref (hdsp)) {
3353 case HDSP_SYNC_FROM_WORD:
3354 pref_sync_ref = "Word Clock";
3355 break;
3356 case HDSP_SYNC_FROM_ADAT_SYNC:
3357 pref_sync_ref = "ADAT Sync";
3358 break;
3359 case HDSP_SYNC_FROM_SPDIF:
3360 pref_sync_ref = "SPDIF";
3361 break;
3362 case HDSP_SYNC_FROM_ADAT1:
3363 pref_sync_ref = "ADAT1";
3364 break;
3365 case HDSP_SYNC_FROM_ADAT2:
3366 pref_sync_ref = "ADAT2";
3367 break;
3368 case HDSP_SYNC_FROM_ADAT3:
3369 pref_sync_ref = "ADAT3";
3370 break;
3371 default:
3372 pref_sync_ref = "Word Clock";
3373 break;
3374 }
3375 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3376
3377 switch (hdsp_autosync_ref (hdsp)) {
3378 case HDSP_AUTOSYNC_FROM_WORD:
3379 autosync_ref = "Word Clock";
3380 break;
3381 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3382 autosync_ref = "ADAT Sync";
3383 break;
3384 case HDSP_AUTOSYNC_FROM_SPDIF:
3385 autosync_ref = "SPDIF";
3386 break;
3387 case HDSP_AUTOSYNC_FROM_NONE:
3388 autosync_ref = "None";
3389 break;
3390 case HDSP_AUTOSYNC_FROM_ADAT1:
3391 autosync_ref = "ADAT1";
3392 break;
3393 case HDSP_AUTOSYNC_FROM_ADAT2:
3394 autosync_ref = "ADAT2";
3395 break;
3396 case HDSP_AUTOSYNC_FROM_ADAT3:
3397 autosync_ref = "ADAT3";
3398 break;
3399 default:
3400 autosync_ref = "---";
3401 break;
3402 }
3403 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3404
3405 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3406
3407 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3408
3409 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
e3ea4d89 3410 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
1da177e4
LT
3411
3412 snd_iprintf(buffer, "\n");
3413
3414 switch (hdsp_spdif_in(hdsp)) {
3415 case HDSP_SPDIFIN_OPTICAL:
3416 snd_iprintf(buffer, "IEC958 input: Optical\n");
3417 break;
3418 case HDSP_SPDIFIN_COAXIAL:
3419 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3420 break;
3421 case HDSP_SPDIFIN_INTERNAL:
3422 snd_iprintf(buffer, "IEC958 input: Internal\n");
3423 break;
3424 case HDSP_SPDIFIN_AES:
3425 snd_iprintf(buffer, "IEC958 input: AES\n");
3426 break;
3427 default:
3428 snd_iprintf(buffer, "IEC958 input: ???\n");
3429 break;
3430 }
3431
b0b98119 3432 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
1da177e4 3433 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
b0b98119 3434 else
1da177e4 3435 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
1da177e4 3436
b0b98119 3437 if (hdsp->control_register & HDSP_SPDIFProfessional)
1da177e4 3438 snd_iprintf(buffer, "IEC958 quality: Professional\n");
b0b98119 3439 else
1da177e4 3440 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
1da177e4 3441
b0b98119 3442 if (hdsp->control_register & HDSP_SPDIFEmphasis)
1da177e4 3443 snd_iprintf(buffer, "IEC958 emphasis: on\n");
b0b98119 3444 else
1da177e4 3445 snd_iprintf(buffer, "IEC958 emphasis: off\n");
1da177e4 3446
b0b98119 3447 if (hdsp->control_register & HDSP_SPDIFNonAudio)
1da177e4 3448 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
b0b98119 3449 else
1da177e4 3450 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
b0b98119 3451 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0)
1da177e4 3452 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
b0b98119 3453 else
1da177e4 3454 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
1da177e4
LT
3455
3456 snd_iprintf(buffer, "\n");
3457
3458 /* Sync Check */
3459 x = status & HDSP_Sync0;
b0b98119 3460 if (status & HDSP_Lock0)
1da177e4 3461 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
b0b98119 3462 else
1da177e4 3463 snd_iprintf(buffer, "ADAT1: No Lock\n");
1da177e4
LT
3464
3465 switch (hdsp->io_type) {
3466 case Digiface:
3467 case H9652:
3468 x = status & HDSP_Sync1;
b0b98119 3469 if (status & HDSP_Lock1)
1da177e4 3470 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
b0b98119 3471 else
1da177e4 3472 snd_iprintf(buffer, "ADAT2: No Lock\n");
1da177e4 3473 x = status & HDSP_Sync2;
b0b98119 3474 if (status & HDSP_Lock2)
1da177e4 3475 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
b0b98119 3476 else
1da177e4 3477 snd_iprintf(buffer, "ADAT3: No Lock\n");
b0b98119 3478 break;
1da177e4
LT
3479 default:
3480 /* relax */
3481 break;
3482 }
3483
3484 x = status & HDSP_SPDIFSync;
b0b98119 3485 if (status & HDSP_SPDIFErrorFlag)
1da177e4 3486 snd_iprintf (buffer, "SPDIF: No Lock\n");
b0b98119 3487 else
1da177e4 3488 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
1da177e4
LT
3489
3490 x = status2 & HDSP_wc_sync;
b0b98119 3491 if (status2 & HDSP_wc_lock)
1da177e4 3492 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
b0b98119 3493 else
1da177e4 3494 snd_iprintf (buffer, "Word Clock: No Lock\n");
1da177e4
LT
3495
3496 x = status & HDSP_TimecodeSync;
b0b98119 3497 if (status & HDSP_TimecodeLock)
1da177e4 3498 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
b0b98119 3499 else
1da177e4 3500 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
1da177e4
LT
3501
3502 snd_iprintf(buffer, "\n");
3503
3504 /* Informations about H9632 specific controls */
3505 if (hdsp->io_type == H9632) {
3506 char *tmp;
3507
3508 switch (hdsp_ad_gain(hdsp)) {
3509 case 0:
3510 tmp = "-10 dBV";
3511 break;
3512 case 1:
3513 tmp = "+4 dBu";
3514 break;
3515 default:
3516 tmp = "Lo Gain";
3517 break;
3518 }
3519 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3520
3521 switch (hdsp_da_gain(hdsp)) {
3522 case 0:
3523 tmp = "Hi Gain";
3524 break;
3525 case 1:
3526 tmp = "+4 dBu";
3527 break;
3528 default:
3529 tmp = "-10 dBV";
3530 break;
3531 }
3532 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3533
3534 switch (hdsp_phone_gain(hdsp)) {
3535 case 0:
3536 tmp = "0 dB";
3537 break;
3538 case 1:
3539 tmp = "-6 dB";
3540 break;
3541 default:
3542 tmp = "-12 dB";
3543 break;
3544 }
3545 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3546
3547 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3548
b0b98119 3549 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
1da177e4 3550 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
b0b98119 3551 else
1da177e4 3552 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
1da177e4
LT
3553 snd_iprintf(buffer, "\n");
3554 }
3555
3556}
3557
55e957d8 3558static void __devinit snd_hdsp_proc_init(struct hdsp *hdsp)
1da177e4 3559{
55e957d8 3560 struct snd_info_entry *entry;
1da177e4
LT
3561
3562 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
bf850204 3563 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
1da177e4
LT
3564}
3565
55e957d8 3566static void snd_hdsp_free_buffers(struct hdsp *hdsp)
1da177e4
LT
3567{
3568 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3569 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3570}
3571
55e957d8 3572static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp)
1da177e4
LT
3573{
3574 unsigned long pb_bus, cb_bus;
3575
3576 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3577 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3578 if (hdsp->capture_dma_buf.area)
3579 snd_dma_free_pages(&hdsp->capture_dma_buf);
3580 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3581 return -ENOMEM;
3582 }
3583
3584 /* Align to bus-space 64K boundary */
3585
7ab39926
CL
3586 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3587 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
1da177e4
LT
3588
3589 /* Tell the card where it is */
3590
3591 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3592 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3593
3594 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3595 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3596
3597 return 0;
3598}
3599
55e957d8 3600static int snd_hdsp_set_defaults(struct hdsp *hdsp)
1da177e4
LT
3601{
3602 unsigned int i;
3603
3604 /* ASSUMPTION: hdsp->lock is either held, or
3605 there is no need to hold it (e.g. during module
3606 initalization).
3607 */
3608
3609 /* set defaults:
3610
3611 SPDIF Input via Coax
3612 Master clock mode
3613 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3614 which implies 2 4096 sample, 32Kbyte periods).
3615 Enable line out.
3616 */
3617
3618 hdsp->control_register = HDSP_ClockModeMaster |
3619 HDSP_SPDIFInputCoaxial |
3620 hdsp_encode_latency(7) |
3621 HDSP_LineOut;
3622
3623
3624 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3625
3626#ifdef SNDRV_BIG_ENDIAN
3627 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3628#else
3629 hdsp->control2_register = 0;
3630#endif
b0b98119 3631 if (hdsp->io_type == H9652)
1da177e4 3632 snd_hdsp_9652_enable_mixer (hdsp);
b0b98119
TI
3633 else
3634 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
1da177e4
LT
3635
3636 hdsp_reset_hw_pointer(hdsp);
3637 hdsp_compute_period_size(hdsp);
3638
3639 /* silence everything */
3640
b0b98119 3641 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
1da177e4 3642 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
1da177e4
LT
3643
3644 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
b0b98119 3645 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
1da177e4 3646 return -EIO;
1da177e4
LT
3647 }
3648
3649 /* H9632 specific defaults */
3650 if (hdsp->io_type == H9632) {
3651 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3652 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3653 }
3654
3655 /* set a default rate so that the channel map is set up.
3656 */
3657
3658 hdsp_set_rate(hdsp, 48000, 1);
3659
3660 return 0;
3661}
3662
3663static void hdsp_midi_tasklet(unsigned long arg)
3664{
55e957d8 3665 struct hdsp *hdsp = (struct hdsp *)arg;
1da177e4 3666
b0b98119 3667 if (hdsp->midi[0].pending)
1da177e4 3668 snd_hdsp_midi_input_read (&hdsp->midi[0]);
b0b98119 3669 if (hdsp->midi[1].pending)
1da177e4 3670 snd_hdsp_midi_input_read (&hdsp->midi[1]);
1da177e4
LT
3671}
3672
7d12e780 3673static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
1da177e4 3674{
55e957d8 3675 struct hdsp *hdsp = (struct hdsp *) dev_id;
1da177e4
LT
3676 unsigned int status;
3677 int audio;
3678 int midi0;
3679 int midi1;
3680 unsigned int midi0status;
3681 unsigned int midi1status;
3682 int schedule = 0;
3683
3684 status = hdsp_read(hdsp, HDSP_statusRegister);
3685
3686 audio = status & HDSP_audioIRQPending;
3687 midi0 = status & HDSP_midi0IRQPending;
3688 midi1 = status & HDSP_midi1IRQPending;
3689
b0b98119 3690 if (!audio && !midi0 && !midi1)
1da177e4 3691 return IRQ_NONE;
1da177e4
LT
3692
3693 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3694
3695 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3696 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3697
3698 if (audio) {
b0b98119 3699 if (hdsp->capture_substream)
1da177e4 3700 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
1da177e4 3701
b0b98119 3702 if (hdsp->playback_substream)
1da177e4 3703 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
1da177e4
LT
3704 }
3705
3706 if (midi0 && midi0status) {
3707 if (hdsp->use_midi_tasklet) {
3708 /* we disable interrupts for this input until processing is done */
3709 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3710 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3711 hdsp->midi[0].pending = 1;
3712 schedule = 1;
3713 } else {
3714 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3715 }
3716 }
3717 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3718 if (hdsp->use_midi_tasklet) {
3719 /* we disable interrupts for this input until processing is done */
3720 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3721 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3722 hdsp->midi[1].pending = 1;
3723 schedule = 1;
3724 } else {
3725 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3726 }
3727 }
3728 if (hdsp->use_midi_tasklet && schedule)
3729 tasklet_hi_schedule(&hdsp->midi_tasklet);
3730 return IRQ_HANDLED;
3731}
3732
55e957d8 3733static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
1da177e4 3734{
55e957d8 3735 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
3736 return hdsp_hw_pointer(hdsp);
3737}
3738
55e957d8 3739static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
1da177e4
LT
3740 int stream,
3741 int channel)
3742
3743{
3744 int mapped_channel;
3745
3746 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3747
b0b98119 3748 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
1da177e4 3749 return NULL;
1da177e4 3750
b0b98119 3751 if (stream == SNDRV_PCM_STREAM_CAPTURE)
1da177e4 3752 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
b0b98119 3753 else
1da177e4 3754 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
1da177e4
LT
3755}
3756
55e957d8 3757static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
1da177e4
LT
3758 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3759{
55e957d8 3760 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
3761 char *channel_buf;
3762
3763 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3764
3765 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3766 snd_assert(channel_buf != NULL, return -EIO);
3767 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3768 return -EFAULT;
3769 return count;
3770}
3771
55e957d8 3772static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
1da177e4
LT
3773 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3774{
55e957d8 3775 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
3776 char *channel_buf;
3777
3778 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3779
3780 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3781 snd_assert(channel_buf != NULL, return -EIO);
3782 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3783 return -EFAULT;
3784 return count;
3785}
3786
55e957d8 3787static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
1da177e4
LT
3788 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3789{
55e957d8 3790 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
3791 char *channel_buf;
3792
3793 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3794 snd_assert(channel_buf != NULL, return -EIO);
3795 memset(channel_buf + pos * 4, 0, count * 4);
3796 return count;
3797}
3798
55e957d8 3799static int snd_hdsp_reset(struct snd_pcm_substream *substream)
1da177e4 3800{
55e957d8
TI
3801 struct snd_pcm_runtime *runtime = substream->runtime;
3802 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3803 struct snd_pcm_substream *other;
1da177e4
LT
3804 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3805 other = hdsp->capture_substream;
3806 else
3807 other = hdsp->playback_substream;
3808 if (hdsp->running)
3809 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3810 else
3811 runtime->status->hw_ptr = 0;
3812 if (other) {
55e957d8
TI
3813 struct snd_pcm_substream *s;
3814 struct snd_pcm_runtime *oruntime = other->runtime;
ef991b95 3815 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT
3816 if (s == other) {
3817 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3818 break;
3819 }
3820 }
3821 }
3822 return 0;
3823}
3824
55e957d8
TI
3825static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3826 struct snd_pcm_hw_params *params)
1da177e4 3827{
55e957d8 3828 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
3829 int err;
3830 pid_t this_pid;
3831 pid_t other_pid;
3832
b0b98119 3833 if (hdsp_check_for_iobox (hdsp))
1da177e4 3834 return -EIO;
1da177e4 3835
b0b98119 3836 if (hdsp_check_for_firmware(hdsp, 1))
1da177e4 3837 return -EIO;
1da177e4
LT
3838
3839 spin_lock_irq(&hdsp->lock);
3840
3841 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3842 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3843 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3844 this_pid = hdsp->playback_pid;
3845 other_pid = hdsp->capture_pid;
3846 } else {
3847 this_pid = hdsp->capture_pid;
3848 other_pid = hdsp->playback_pid;
3849 }
3850
3851 if ((other_pid > 0) && (this_pid != other_pid)) {
3852
3853 /* The other stream is open, and not by the same
3854 task as this one. Make sure that the parameters
3855 that matter are the same.
3856 */
3857
3858 if (params_rate(params) != hdsp->system_sample_rate) {
3859 spin_unlock_irq(&hdsp->lock);
3860 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3861 return -EBUSY;
3862 }
3863
3864 if (params_period_size(params) != hdsp->period_bytes / 4) {
3865 spin_unlock_irq(&hdsp->lock);
3866 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3867 return -EBUSY;
3868 }
3869
3870 /* We're fine. */
3871
3872 spin_unlock_irq(&hdsp->lock);
3873 return 0;
3874
3875 } else {
3876 spin_unlock_irq(&hdsp->lock);
3877 }
3878
3879 /* how to make sure that the rate matches an externally-set one ?
3880 */
3881
3882 spin_lock_irq(&hdsp->lock);
e3ea4d89
TI
3883 if (! hdsp->clock_source_locked) {
3884 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3885 spin_unlock_irq(&hdsp->lock);
3886 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3887 return err;
3888 }
1da177e4 3889 }
e3ea4d89 3890 spin_unlock_irq(&hdsp->lock);
1da177e4
LT
3891
3892 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3893 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3894 return err;
3895 }
3896
3897 return 0;
3898}
3899
55e957d8
TI
3900static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
3901 struct snd_pcm_channel_info *info)
1da177e4 3902{
55e957d8 3903 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
3904 int mapped_channel;
3905
3906 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3907
b0b98119 3908 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
1da177e4 3909 return -EINVAL;
1da177e4
LT
3910
3911 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3912 info->first = 0;
3913 info->step = 32;
3914 return 0;
3915}
3916
55e957d8 3917static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
1da177e4
LT
3918 unsigned int cmd, void *arg)
3919{
3920 switch (cmd) {
3921 case SNDRV_PCM_IOCTL1_RESET:
1da177e4 3922 return snd_hdsp_reset(substream);
1da177e4 3923 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
b0b98119 3924 return snd_hdsp_channel_info(substream, arg);
1da177e4
LT
3925 default:
3926 break;
3927 }
3928
3929 return snd_pcm_lib_ioctl(substream, cmd, arg);
3930}
3931
55e957d8 3932static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 3933{
55e957d8
TI
3934 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3935 struct snd_pcm_substream *other;
1da177e4
LT
3936 int running;
3937
b0b98119 3938 if (hdsp_check_for_iobox (hdsp))
1da177e4 3939 return -EIO;
1da177e4 3940
311e70a4 3941 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
1da177e4 3942 return -EIO;
1da177e4
LT
3943
3944 spin_lock(&hdsp->lock);
3945 running = hdsp->running;
3946 switch (cmd) {
3947 case SNDRV_PCM_TRIGGER_START:
3948 running |= 1 << substream->stream;
3949 break;
3950 case SNDRV_PCM_TRIGGER_STOP:
3951 running &= ~(1 << substream->stream);
3952 break;
3953 default:
3954 snd_BUG();
3955 spin_unlock(&hdsp->lock);
3956 return -EINVAL;
3957 }
3958 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3959 other = hdsp->capture_substream;
3960 else
3961 other = hdsp->playback_substream;
3962
3963 if (other) {
55e957d8 3964 struct snd_pcm_substream *s;
ef991b95 3965 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT
3966 if (s == other) {
3967 snd_pcm_trigger_done(s, substream);
3968 if (cmd == SNDRV_PCM_TRIGGER_START)
3969 running |= 1 << s->stream;
3970 else
3971 running &= ~(1 << s->stream);
3972 goto _ok;
3973 }
3974 }
3975 if (cmd == SNDRV_PCM_TRIGGER_START) {
3976 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3977 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3978 hdsp_silence_playback(hdsp);
3979 } else {
3980 if (running &&
3981 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3982 hdsp_silence_playback(hdsp);
3983 }
3984 } else {
3985 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3986 hdsp_silence_playback(hdsp);
3987 }
3988 _ok:
3989 snd_pcm_trigger_done(substream, substream);
3990 if (!hdsp->running && running)
3991 hdsp_start_audio(hdsp);
3992 else if (hdsp->running && !running)
3993 hdsp_stop_audio(hdsp);
3994 hdsp->running = running;
3995 spin_unlock(&hdsp->lock);
3996
3997 return 0;
3998}
3999
55e957d8 4000static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
1da177e4 4001{
55e957d8 4002 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
4003 int result = 0;
4004
b0b98119 4005 if (hdsp_check_for_iobox (hdsp))
1da177e4 4006 return -EIO;
1da177e4 4007
b0b98119 4008 if (hdsp_check_for_firmware(hdsp, 1))
1da177e4 4009 return -EIO;
1da177e4
LT
4010
4011 spin_lock_irq(&hdsp->lock);
4012 if (!hdsp->running)
4013 hdsp_reset_hw_pointer(hdsp);
4014 spin_unlock_irq(&hdsp->lock);
4015 return result;
4016}
4017
55e957d8 4018static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
1da177e4
LT
4019{
4020 .info = (SNDRV_PCM_INFO_MMAP |
4021 SNDRV_PCM_INFO_MMAP_VALID |
4022 SNDRV_PCM_INFO_NONINTERLEAVED |
4023 SNDRV_PCM_INFO_SYNC_START |
4024 SNDRV_PCM_INFO_DOUBLE),
4025#ifdef SNDRV_BIG_ENDIAN
4026 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4027#else
4028 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4029#endif
4030 .rates = (SNDRV_PCM_RATE_32000 |
4031 SNDRV_PCM_RATE_44100 |
4032 SNDRV_PCM_RATE_48000 |
4033 SNDRV_PCM_RATE_64000 |
4034 SNDRV_PCM_RATE_88200 |
4035 SNDRV_PCM_RATE_96000),
4036 .rate_min = 32000,
4037 .rate_max = 96000,
4038 .channels_min = 14,
4039 .channels_max = HDSP_MAX_CHANNELS,
4040 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4041 .period_bytes_min = (64 * 4) * 10,
4042 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4043 .periods_min = 2,
4044 .periods_max = 2,
4045 .fifo_size = 0
4046};
4047
55e957d8 4048static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
1da177e4
LT
4049{
4050 .info = (SNDRV_PCM_INFO_MMAP |
4051 SNDRV_PCM_INFO_MMAP_VALID |
4052 SNDRV_PCM_INFO_NONINTERLEAVED |
4053 SNDRV_PCM_INFO_SYNC_START),
4054#ifdef SNDRV_BIG_ENDIAN
4055 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4056#else
4057 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4058#endif
4059 .rates = (SNDRV_PCM_RATE_32000 |
4060 SNDRV_PCM_RATE_44100 |
4061 SNDRV_PCM_RATE_48000 |
4062 SNDRV_PCM_RATE_64000 |
4063 SNDRV_PCM_RATE_88200 |
4064 SNDRV_PCM_RATE_96000),
4065 .rate_min = 32000,
4066 .rate_max = 96000,
4067 .channels_min = 14,
4068 .channels_max = HDSP_MAX_CHANNELS,
4069 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4070 .period_bytes_min = (64 * 4) * 10,
4071 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4072 .periods_min = 2,
4073 .periods_max = 2,
4074 .fifo_size = 0
4075};
4076
4077static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4078
55e957d8 4079static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
1da177e4
LT
4080 .count = ARRAY_SIZE(hdsp_period_sizes),
4081 .list = hdsp_period_sizes,
4082 .mask = 0
4083};
4084
4085static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4086
55e957d8 4087static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
1da177e4
LT
4088 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4089 .list = hdsp_9632_sample_rates,
4090 .mask = 0
4091};
4092
55e957d8
TI
4093static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4094 struct snd_pcm_hw_rule *rule)
1da177e4 4095{
55e957d8
TI
4096 struct hdsp *hdsp = rule->private;
4097 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
1da177e4
LT
4098 if (hdsp->io_type == H9632) {
4099 unsigned int list[3];
4100 list[0] = hdsp->qs_in_channels;
4101 list[1] = hdsp->ds_in_channels;
4102 list[2] = hdsp->ss_in_channels;
4103 return snd_interval_list(c, 3, list, 0);
4104 } else {
4105 unsigned int list[2];
4106 list[0] = hdsp->ds_in_channels;
4107 list[1] = hdsp->ss_in_channels;
4108 return snd_interval_list(c, 2, list, 0);
4109 }
4110}
4111
55e957d8
TI
4112static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4113 struct snd_pcm_hw_rule *rule)
1da177e4
LT
4114{
4115 unsigned int list[3];
55e957d8
TI
4116 struct hdsp *hdsp = rule->private;
4117 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
1da177e4
LT
4118 if (hdsp->io_type == H9632) {
4119 list[0] = hdsp->qs_out_channels;
4120 list[1] = hdsp->ds_out_channels;
4121 list[2] = hdsp->ss_out_channels;
4122 return snd_interval_list(c, 3, list, 0);
4123 } else {
4124 list[0] = hdsp->ds_out_channels;
4125 list[1] = hdsp->ss_out_channels;
4126 }
4127 return snd_interval_list(c, 2, list, 0);
4128}
4129
55e957d8
TI
4130static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4131 struct snd_pcm_hw_rule *rule)
1da177e4 4132{
55e957d8
TI
4133 struct hdsp *hdsp = rule->private;
4134 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4135 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1da177e4 4136 if (r->min > 96000 && hdsp->io_type == H9632) {
55e957d8 4137 struct snd_interval t = {
1da177e4
LT
4138 .min = hdsp->qs_in_channels,
4139 .max = hdsp->qs_in_channels,
4140 .integer = 1,
4141 };
4142 return snd_interval_refine(c, &t);
4143 } else if (r->min > 48000 && r->max <= 96000) {
55e957d8 4144 struct snd_interval t = {
1da177e4
LT
4145 .min = hdsp->ds_in_channels,
4146 .max = hdsp->ds_in_channels,
4147 .integer = 1,
4148 };
4149 return snd_interval_refine(c, &t);
4150 } else if (r->max < 64000) {
55e957d8 4151 struct snd_interval t = {
1da177e4
LT
4152 .min = hdsp->ss_in_channels,
4153 .max = hdsp->ss_in_channels,
4154 .integer = 1,
4155 };
4156 return snd_interval_refine(c, &t);
4157 }
4158 return 0;
4159}
4160
55e957d8
TI
4161static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4162 struct snd_pcm_hw_rule *rule)
1da177e4 4163{
55e957d8
TI
4164 struct hdsp *hdsp = rule->private;
4165 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4166 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1da177e4 4167 if (r->min > 96000 && hdsp->io_type == H9632) {
55e957d8 4168 struct snd_interval t = {
1da177e4
LT
4169 .min = hdsp->qs_out_channels,
4170 .max = hdsp->qs_out_channels,
4171 .integer = 1,
4172 };
4173 return snd_interval_refine(c, &t);
4174 } else if (r->min > 48000 && r->max <= 96000) {
55e957d8 4175 struct snd_interval t = {
1da177e4
LT
4176 .min = hdsp->ds_out_channels,
4177 .max = hdsp->ds_out_channels,
4178 .integer = 1,
4179 };
4180 return snd_interval_refine(c, &t);
4181 } else if (r->max < 64000) {
55e957d8 4182 struct snd_interval t = {
1da177e4
LT
4183 .min = hdsp->ss_out_channels,
4184 .max = hdsp->ss_out_channels,
4185 .integer = 1,
4186 };
4187 return snd_interval_refine(c, &t);
4188 }
4189 return 0;
4190}
4191
55e957d8
TI
4192static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4193 struct snd_pcm_hw_rule *rule)
1da177e4 4194{
55e957d8
TI
4195 struct hdsp *hdsp = rule->private;
4196 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4197 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1da177e4 4198 if (c->min >= hdsp->ss_out_channels) {
55e957d8 4199 struct snd_interval t = {
1da177e4
LT
4200 .min = 32000,
4201 .max = 48000,
4202 .integer = 1,
4203 };
4204 return snd_interval_refine(r, &t);
4205 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
55e957d8 4206 struct snd_interval t = {
1da177e4
LT
4207 .min = 128000,
4208 .max = 192000,
4209 .integer = 1,
4210 };
4211 return snd_interval_refine(r, &t);
4212 } else if (c->max <= hdsp->ds_out_channels) {
55e957d8 4213 struct snd_interval t = {
1da177e4
LT
4214 .min = 64000,
4215 .max = 96000,
4216 .integer = 1,
4217 };
4218 return snd_interval_refine(r, &t);
4219 }
4220 return 0;
4221}
4222
55e957d8
TI
4223static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4224 struct snd_pcm_hw_rule *rule)
1da177e4 4225{
55e957d8
TI
4226 struct hdsp *hdsp = rule->private;
4227 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4228 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1da177e4 4229 if (c->min >= hdsp->ss_in_channels) {
55e957d8 4230 struct snd_interval t = {
1da177e4
LT
4231 .min = 32000,
4232 .max = 48000,
4233 .integer = 1,
4234 };
4235 return snd_interval_refine(r, &t);
4236 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
55e957d8 4237 struct snd_interval t = {
1da177e4
LT
4238 .min = 128000,
4239 .max = 192000,
4240 .integer = 1,
4241 };
4242 return snd_interval_refine(r, &t);
4243 } else if (c->max <= hdsp->ds_in_channels) {
55e957d8 4244 struct snd_interval t = {
1da177e4
LT
4245 .min = 64000,
4246 .max = 96000,
4247 .integer = 1,
4248 };
4249 return snd_interval_refine(r, &t);
4250 }
4251 return 0;
4252}
4253
55e957d8 4254static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
1da177e4 4255{
55e957d8
TI
4256 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4257 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 4258
b0b98119 4259 if (hdsp_check_for_iobox (hdsp))
1da177e4 4260 return -EIO;
1da177e4 4261
b0b98119 4262 if (hdsp_check_for_firmware(hdsp, 1))
1da177e4 4263 return -EIO;
1da177e4
LT
4264
4265 spin_lock_irq(&hdsp->lock);
4266
4267 snd_pcm_set_sync(substream);
4268
4269 runtime->hw = snd_hdsp_playback_subinfo;
4270 runtime->dma_area = hdsp->playback_buffer;
4271 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4272
4273 hdsp->playback_pid = current->pid;
4274 hdsp->playback_substream = substream;
4275
4276 spin_unlock_irq(&hdsp->lock);
4277
4278 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4279 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
e3ea4d89
TI
4280 if (hdsp->clock_source_locked) {
4281 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4282 } else if (hdsp->io_type == H9632) {
1da177e4
LT
4283 runtime->hw.rate_max = 192000;
4284 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4285 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4286 }
e3ea4d89
TI
4287 if (hdsp->io_type == H9632) {
4288 runtime->hw.channels_min = hdsp->qs_out_channels;
4289 runtime->hw.channels_max = hdsp->ss_out_channels;
4290 }
1da177e4
LT
4291
4292 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4293 snd_hdsp_hw_rule_out_channels, hdsp,
4294 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4295 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4296 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4297 SNDRV_PCM_HW_PARAM_RATE, -1);
4298 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4299 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4300 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4301
4302 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4303 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4304 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4305 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4306 return 0;
4307}
4308
55e957d8 4309static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
1da177e4 4310{
55e957d8 4311 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
4312
4313 spin_lock_irq(&hdsp->lock);
4314
4315 hdsp->playback_pid = -1;
4316 hdsp->playback_substream = NULL;
4317
4318 spin_unlock_irq(&hdsp->lock);
4319
4320 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4321 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4322 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4323 return 0;
4324}
4325
4326
55e957d8 4327static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
1da177e4 4328{
55e957d8
TI
4329 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4330 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 4331
b0b98119 4332 if (hdsp_check_for_iobox (hdsp))
1da177e4 4333 return -EIO;
1da177e4 4334
b0b98119 4335 if (hdsp_check_for_firmware(hdsp, 1))
1da177e4 4336 return -EIO;
1da177e4
LT
4337
4338 spin_lock_irq(&hdsp->lock);
4339
4340 snd_pcm_set_sync(substream);
4341
4342 runtime->hw = snd_hdsp_capture_subinfo;
4343 runtime->dma_area = hdsp->capture_buffer;
4344 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4345
4346 hdsp->capture_pid = current->pid;
4347 hdsp->capture_substream = substream;
4348
4349 spin_unlock_irq(&hdsp->lock);
4350
4351 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4352 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4353 if (hdsp->io_type == H9632) {
4354 runtime->hw.channels_min = hdsp->qs_in_channels;
4355 runtime->hw.channels_max = hdsp->ss_in_channels;
4356 runtime->hw.rate_max = 192000;
4357 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4358 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4359 }
4360 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4361 snd_hdsp_hw_rule_in_channels, hdsp,
4362 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4363 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4364 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4365 SNDRV_PCM_HW_PARAM_RATE, -1);
4366 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4367 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4368 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4369 return 0;
4370}
4371
55e957d8 4372static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
1da177e4 4373{
55e957d8 4374 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
1da177e4
LT
4375
4376 spin_lock_irq(&hdsp->lock);
4377
4378 hdsp->capture_pid = -1;
4379 hdsp->capture_substream = NULL;
4380
4381 spin_unlock_irq(&hdsp->lock);
4382 return 0;
4383}
4384
55e957d8 4385static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
1da177e4
LT
4386{
4387 /* we have nothing to initialize but the call is required */
4388 return 0;
4389}
4390
4391
4392/* helper functions for copying meter values */
4393static inline int copy_u32_le(void __user *dest, void __iomem *src)
4394{
4395 u32 val = readl(src);
4396 return copy_to_user(dest, &val, 4);
4397}
4398
4399static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4400{
4401 u32 rms_low, rms_high;
4402 u64 rms;
4403 rms_low = readl(src_low);
4404 rms_high = readl(src_high);
4405 rms = ((u64)rms_high << 32) | rms_low;
4406 return copy_to_user(dest, &rms, 8);
4407}
4408
4409static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4410{
4411 u32 rms_low, rms_high;
4412 u64 rms;
4413 rms_low = readl(src_low) & 0xffffff00;
4414 rms_high = readl(src_high) & 0xffffff00;
4415 rms = ((u64)rms_high << 32) | rms_low;
4416 return copy_to_user(dest, &rms, 8);
4417}
4418
55e957d8 4419static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
1da177e4
LT
4420{
4421 int doublespeed = 0;
4422 int i, j, channels, ofs;
4423
4424 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4425 doublespeed = 1;
4426 channels = doublespeed ? 14 : 26;
4427 for (i = 0, j = 0; i < 26; ++i) {
4428 if (doublespeed && (i & 4))
4429 continue;
4430 ofs = HDSP_9652_peakBase - j * 4;
4431 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4432 return -EFAULT;
4433 ofs -= channels * 4;
4434 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4435 return -EFAULT;
4436 ofs -= channels * 4;
4437 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4438 return -EFAULT;
4439 ofs = HDSP_9652_rmsBase + j * 8;
4440 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4441 hdsp->iobase + ofs + 4))
4442 return -EFAULT;
4443 ofs += channels * 8;
4444 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4445 hdsp->iobase + ofs + 4))
4446 return -EFAULT;
4447 ofs += channels * 8;
4448 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4449 hdsp->iobase + ofs + 4))
4450 return -EFAULT;
4451 j++;
4452 }
4453 return 0;
4454}
4455
55e957d8 4456static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
1da177e4
LT
4457{
4458 int i, j;
55e957d8 4459 struct hdsp_9632_meters __iomem *m;
1da177e4
LT
4460 int doublespeed = 0;
4461
4462 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4463 doublespeed = 1;
55e957d8 4464 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
1da177e4
LT
4465 for (i = 0, j = 0; i < 16; ++i, ++j) {
4466 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4467 return -EFAULT;
4468 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4469 return -EFAULT;
4470 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4471 return -EFAULT;
4472 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4473 &m->input_rms_high[j]))
4474 return -EFAULT;
4475 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4476 &m->playback_rms_high[j]))
4477 return -EFAULT;
4478 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4479 &m->output_rms_high[j]))
4480 return -EFAULT;
4481 if (doublespeed && i == 3) i += 4;
4482 }
4483 return 0;
4484}
4485
55e957d8 4486static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
1da177e4
LT
4487{
4488 int i;
4489
4490 for (i = 0; i < 26; i++) {
4491 if (copy_u32_le(&peak_rms->playback_peaks[i],
4492 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4493 return -EFAULT;
4494 if (copy_u32_le(&peak_rms->input_peaks[i],
4495 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4496 return -EFAULT;
4497 }
4498 for (i = 0; i < 28; i++) {
4499 if (copy_u32_le(&peak_rms->output_peaks[i],
4500 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4501 return -EFAULT;
4502 }
4503 for (i = 0; i < 26; ++i) {
4504 if (copy_u64_le(&peak_rms->playback_rms[i],
4505 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4506 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4507 return -EFAULT;
4508 if (copy_u64_le(&peak_rms->input_rms[i],
4509 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4510 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4511 return -EFAULT;
4512 }
4513 return 0;
4514}
4515
55e957d8 4516static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
1da177e4 4517{
55e957d8 4518 struct hdsp *hdsp = (struct hdsp *)hw->private_data;
1da177e4
LT
4519 void __user *argp = (void __user *)arg;
4520
4521 switch (cmd) {
4522 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
55e957d8 4523 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
1da177e4
LT
4524
4525 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4526 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4527 return -EINVAL;
4528 }
4529
4530 switch (hdsp->io_type) {
4531 case H9652:
4532 return hdsp_9652_get_peak(hdsp, peak_rms);
4533 case H9632:
4534 return hdsp_9632_get_peak(hdsp, peak_rms);
4535 default:
4536 return hdsp_get_peak(hdsp, peak_rms);
4537 }
4538 }
4539 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
55e957d8 4540 struct hdsp_config_info info;
1da177e4
LT
4541 unsigned long flags;
4542 int i;
4543
4544 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
b0b98119 4545 snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
1da177e4
LT
4546 return -EINVAL;
4547 }
4548 spin_lock_irqsave(&hdsp->lock, flags);
4549 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4550 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
b0b98119 4551 if (hdsp->io_type != H9632)
1da177e4 4552 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
1da177e4 4553 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
b0b98119 4554 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i)
1da177e4 4555 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
1da177e4
LT
4556 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4557 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4558 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4559 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4560 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4561 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4562 info.system_sample_rate = hdsp->system_sample_rate;
4563 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4564 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4565 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4566 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4567 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4568 if (hdsp->io_type == H9632) {
4569 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4570 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4571 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4572 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4573
4574 }
b0b98119 4575 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
1da177e4 4576 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
1da177e4
LT
4577 spin_unlock_irqrestore(&hdsp->lock, flags);
4578 if (copy_to_user(argp, &info, sizeof(info)))
4579 return -EFAULT;
4580 break;
4581 }
4582 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
55e957d8 4583 struct hdsp_9632_aeb h9632_aeb;
1da177e4
LT
4584
4585 if (hdsp->io_type != H9632) return -EINVAL;
4586 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4587 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4588 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4589 return -EFAULT;
4590 break;
4591 }
4592 case SNDRV_HDSP_IOCTL_GET_VERSION: {
55e957d8 4593 struct hdsp_version hdsp_version;
1da177e4
LT
4594 int err;
4595
4596 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4597 if (hdsp->io_type == Undefined) {
b0b98119 4598 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
1da177e4 4599 return err;
1da177e4
LT
4600 }
4601 hdsp_version.io_type = hdsp->io_type;
4602 hdsp_version.firmware_rev = hdsp->firmware_rev;
b0b98119 4603 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
1da177e4 4604 return -EFAULT;
1da177e4
LT
4605 break;
4606 }
4607 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
55e957d8 4608 struct hdsp_firmware __user *firmware;
1da177e4
LT
4609 u32 __user *firmware_data;
4610 int err;
4611
4612 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4613 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4614 if (hdsp->io_type == Undefined) return -EINVAL;
4615
4616 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4617 return -EBUSY;
4618
b0b98119 4619 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
55e957d8 4620 firmware = (struct hdsp_firmware __user *)argp;
1da177e4 4621
b0b98119 4622 if (get_user(firmware_data, &firmware->firmware_data))
1da177e4 4623 return -EFAULT;
1da177e4 4624
b0b98119 4625 if (hdsp_check_for_iobox (hdsp))
1da177e4 4626 return -EIO;
1da177e4 4627
b0b98119 4628 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0)
1da177e4 4629 return -EFAULT;
1da177e4
LT
4630
4631 hdsp->state |= HDSP_FirmwareCached;
4632
b0b98119 4633 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
1da177e4 4634 return err;
1da177e4
LT
4635
4636 if (!(hdsp->state & HDSP_InitializationComplete)) {
b0b98119 4637 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
1da177e4 4638 return err;
1da177e4
LT
4639
4640 snd_hdsp_initialize_channels(hdsp);
4641 snd_hdsp_initialize_midi_flush(hdsp);
4642
4643 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
b0b98119
TI
4644 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4645 return err;
1da177e4
LT
4646 }
4647 }
4648 break;
4649 }
4650 case SNDRV_HDSP_IOCTL_GET_MIXER: {
55e957d8 4651 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
1da177e4
LT
4652 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4653 return -EFAULT;
4654 break;
4655 }
4656 default:
4657 return -EINVAL;
4658 }
4659 return 0;
4660}
4661
55e957d8 4662static struct snd_pcm_ops snd_hdsp_playback_ops = {
1da177e4
LT
4663 .open = snd_hdsp_playback_open,
4664 .close = snd_hdsp_playback_release,
4665 .ioctl = snd_hdsp_ioctl,
4666 .hw_params = snd_hdsp_hw_params,
4667 .prepare = snd_hdsp_prepare,
4668 .trigger = snd_hdsp_trigger,
4669 .pointer = snd_hdsp_hw_pointer,
4670 .copy = snd_hdsp_playback_copy,
4671 .silence = snd_hdsp_hw_silence,
4672};
4673
55e957d8 4674static struct snd_pcm_ops snd_hdsp_capture_ops = {
1da177e4
LT
4675 .open = snd_hdsp_capture_open,
4676 .close = snd_hdsp_capture_release,
4677 .ioctl = snd_hdsp_ioctl,
4678 .hw_params = snd_hdsp_hw_params,
4679 .prepare = snd_hdsp_prepare,
4680 .trigger = snd_hdsp_trigger,
4681 .pointer = snd_hdsp_hw_pointer,
4682 .copy = snd_hdsp_capture_copy,
4683};
4684
55e957d8
TI
4685static int __devinit snd_hdsp_create_hwdep(struct snd_card *card,
4686 struct hdsp *hdsp)
1da177e4 4687{
55e957d8 4688 struct snd_hwdep *hw;
1da177e4
LT
4689 int err;
4690
4691 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4692 return err;
4693
4694 hdsp->hwdep = hw;
4695 hw->private_data = hdsp;
4696 strcpy(hw->name, "HDSP hwdep interface");
4697
4698 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4699 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4700 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4701
4702 return 0;
4703}
4704
55e957d8 4705static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
1da177e4 4706{
55e957d8 4707 struct snd_pcm *pcm;
1da177e4
LT
4708 int err;
4709
4710 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4711 return err;
4712
4713 hdsp->pcm = pcm;
4714 pcm->private_data = hdsp;
4715 strcpy(pcm->name, hdsp->card_name);
4716
4717 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4718 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4719
4720 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4721
4722 return 0;
4723}
4724
55e957d8 4725static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
1da177e4
LT
4726{
4727 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4728 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4729}
4730
55e957d8 4731static int snd_hdsp_enable_io (struct hdsp *hdsp)
1da177e4
LT
4732{
4733 int i;
4734
4735 if (hdsp_fifo_wait (hdsp, 0, 100)) {
b0b98119 4736 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
1da177e4
LT
4737 return -EIO;
4738 }
4739
4740 for (i = 0; i < hdsp->max_channels; ++i) {
4741 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4742 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4743 }
4744
4745 return 0;
4746}
4747
55e957d8 4748static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
1da177e4
LT
4749{
4750 int status, aebi_channels, aebo_channels;
4751
4752 switch (hdsp->io_type) {
4753 case Digiface:
4754 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4755 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4756 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4757 break;
4758
4759 case H9652:
4760 hdsp->card_name = "RME Hammerfall HDSP 9652";
4761 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4762 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4763 break;
4764
4765 case H9632:
4766 status = hdsp_read(hdsp, HDSP_statusRegister);
4767 /* HDSP_AEBx bits are low when AEB are connected */
4768 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4769 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4770 hdsp->card_name = "RME Hammerfall HDSP 9632";
4771 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4772 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4773 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4774 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4775 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4776 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4777 break;
4778
4779 case Multiface:
4780 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4781 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4782 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4783 break;
4784
4785 default:
4786 /* should never get here */
4787 break;
4788 }
4789}
4790
55e957d8 4791static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
1da177e4
LT
4792{
4793 snd_hdsp_flush_midi_input (hdsp, 0);
4794 snd_hdsp_flush_midi_input (hdsp, 1);
4795}
4796
55e957d8 4797static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
1da177e4
LT
4798{
4799 int err;
4800
4801 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
b0b98119 4802 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
1da177e4
LT
4803 return err;
4804 }
4805
4806
4807 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
b0b98119 4808 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
1da177e4
LT
4809 return err;
4810 }
4811
4812 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4813 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
b0b98119 4814 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
1da177e4
LT
4815 return err;
4816 }
4817 }
4818
4819 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
b0b98119 4820 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
1da177e4
LT
4821 return err;
4822 }
4823
4824 snd_hdsp_proc_init(hdsp);
4825
4826 hdsp->system_sample_rate = -1;
4827 hdsp->playback_pid = -1;
4828 hdsp->capture_pid = -1;
4829 hdsp->capture_substream = NULL;
4830 hdsp->playback_substream = NULL;
4831
4832 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
b0b98119 4833 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
1da177e4
LT
4834 return err;
4835 }
4836
4837 if (!(hdsp->state & HDSP_InitializationComplete)) {
b73c1c12 4838 strcpy(card->shortname, "Hammerfall DSP");
1da177e4
LT
4839 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4840 hdsp->port, hdsp->irq);
4841
4842 if ((err = snd_card_register(card)) < 0) {
b0b98119 4843 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
1da177e4
LT
4844 return err;
4845 }
4846 hdsp->state |= HDSP_InitializationComplete;
4847 }
4848
4849 return 0;
4850}
4851
4852#ifdef HDSP_FW_LOADER
4853/* load firmware via hotplug fw loader */
55e957d8 4854static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp)
1da177e4
LT
4855{
4856 const char *fwfile;
4857 const struct firmware *fw;
4858 int err;
4859
4860 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4861 return 0;
4862 if (hdsp->io_type == Undefined) {
4863 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4864 return err;
4865 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4866 return 0;
4867 }
4868
4869 /* caution: max length of firmware filename is 30! */
4870 switch (hdsp->io_type) {
4871 case Multiface:
4872 if (hdsp->firmware_rev == 0xa)
4873 fwfile = "multiface_firmware.bin";
4874 else
4875 fwfile = "multiface_firmware_rev11.bin";
4876 break;
4877 case Digiface:
4878 if (hdsp->firmware_rev == 0xa)
4879 fwfile = "digiface_firmware.bin";
4880 else
4881 fwfile = "digiface_firmware_rev11.bin";
4882 break;
4883 default:
4884 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4885 return -EINVAL;
4886 }
4887
4888 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4889 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4890 return -ENOENT;
4891 }
4892 if (fw->size < sizeof(hdsp->firmware_cache)) {
4893 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4894 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4895 release_firmware(fw);
4896 return -EINVAL;
4897 }
7679a030 4898
1da177e4 4899 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
7679a030 4900
1da177e4
LT
4901 release_firmware(fw);
4902
4903 hdsp->state |= HDSP_FirmwareCached;
4904
4905 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4906 return err;
4907
4908 if (!(hdsp->state & HDSP_InitializationComplete)) {
b0b98119 4909 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
1da177e4 4910 return err;
1da177e4
LT
4911
4912 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
b0b98119 4913 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
1da177e4
LT
4914 return err;
4915 }
4916 snd_hdsp_initialize_channels(hdsp);
4917 snd_hdsp_initialize_midi_flush(hdsp);
4918 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
b0b98119 4919 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
1da177e4
LT
4920 return err;
4921 }
4922 }
4923 return 0;
4924}
4925#endif
4926
55e957d8
TI
4927static int __devinit snd_hdsp_create(struct snd_card *card,
4928 struct hdsp *hdsp)
1da177e4
LT
4929{
4930 struct pci_dev *pci = hdsp->pci;
4931 int err;
4932 int is_9652 = 0;
4933 int is_9632 = 0;
4934
4935 hdsp->irq = -1;
4936 hdsp->state = 0;
4937 hdsp->midi[0].rmidi = NULL;
4938 hdsp->midi[1].rmidi = NULL;
4939 hdsp->midi[0].input = NULL;
4940 hdsp->midi[1].input = NULL;
4941 hdsp->midi[0].output = NULL;
4942 hdsp->midi[1].output = NULL;
4943 hdsp->midi[0].pending = 0;
4944 hdsp->midi[1].pending = 0;
4945 spin_lock_init(&hdsp->midi[0].lock);
4946 spin_lock_init(&hdsp->midi[1].lock);
4947 hdsp->iobase = NULL;
4948 hdsp->control_register = 0;
4949 hdsp->control2_register = 0;
4950 hdsp->io_type = Undefined;
4951 hdsp->max_channels = 26;
4952
4953 hdsp->card = card;
4954
4955 spin_lock_init(&hdsp->lock);
4956
4957 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4958
4959 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4960 hdsp->firmware_rev &= 0xff;
4961
4962 /* From Martin Bjoernsen :
4963 "It is important that the card's latency timer register in
4964 the PCI configuration space is set to a value much larger
4965 than 0 by the computer's BIOS or the driver.
4966 The windows driver always sets this 8 bit register [...]
4967 to its maximum 255 to avoid problems with some computers."
4968 */
4969 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4970
4971 strcpy(card->driver, "H-DSP");
4972 strcpy(card->mixername, "Xilinx FPGA");
4973
b0b98119 4974 if (hdsp->firmware_rev < 0xa)
1da177e4 4975 return -ENODEV;
b0b98119 4976 else if (hdsp->firmware_rev < 0x64)
1da177e4 4977 hdsp->card_name = "RME Hammerfall DSP";
b0b98119 4978 else if (hdsp->firmware_rev < 0x96) {
1da177e4
LT
4979 hdsp->card_name = "RME HDSP 9652";
4980 is_9652 = 1;
4981 } else {
4982 hdsp->card_name = "RME HDSP 9632";
4983 hdsp->max_channels = 16;
4984 is_9632 = 1;
4985 }
4986
b0b98119 4987 if ((err = pci_enable_device(pci)) < 0)
1da177e4 4988 return err;
1da177e4
LT
4989
4990 pci_set_master(hdsp->pci);
4991
4992 if ((err = pci_request_regions(pci, "hdsp")) < 0)
4993 return err;
4994 hdsp->port = pci_resource_start(pci, 0);
4995 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
b0b98119 4996 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
1da177e4
LT
4997 return -EBUSY;
4998 }
4999
437a5a46
TI
5000 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5001 "hdsp", hdsp)) {
b0b98119 5002 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
1da177e4
LT
5003 return -EBUSY;
5004 }
5005
5006 hdsp->irq = pci->irq;
176546ab 5007 hdsp->precise_ptr = 0;
1da177e4 5008 hdsp->use_midi_tasklet = 1;
d7923b2a 5009 hdsp->dds_value = 0;
1da177e4 5010
b0b98119 5011 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
1da177e4 5012 return err;
1da177e4
LT
5013
5014 if (!is_9652 && !is_9632) {
5015 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
b0b98119 5016 ssleep(2);
1da177e4
LT
5017
5018 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5019#ifdef HDSP_FW_LOADER
b0b98119 5020 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
1da177e4
LT
5021 /* we don't fail as this can happen
5022 if userspace is not ready for
5023 firmware upload
5024 */
b0b98119
TI
5025 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5026 else
1da177e4
LT
5027 /* init is complete, we return */
5028 return 0;
1da177e4
LT
5029#endif
5030 /* no iobox connected, we defer initialization */
b0b98119
TI
5031 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5032 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
1da177e4 5033 return err;
1da177e4
LT
5034 return 0;
5035 } else {
b0b98119
TI
5036 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5037 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
1da177e4 5038 hdsp->io_type = Multiface;
b0b98119 5039 else
1da177e4 5040 hdsp->io_type = Digiface;
1da177e4
LT
5041 }
5042 }
5043
b0b98119 5044 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
1da177e4 5045 return err;
1da177e4 5046
b0b98119 5047 if (is_9652)
1da177e4 5048 hdsp->io_type = H9652;
1da177e4 5049
b0b98119 5050 if (is_9632)
1da177e4 5051 hdsp->io_type = H9632;
1da177e4 5052
b0b98119 5053 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
1da177e4 5054 return err;
1da177e4
LT
5055
5056 snd_hdsp_initialize_channels(hdsp);
5057 snd_hdsp_initialize_midi_flush(hdsp);
5058
5059 hdsp->state |= HDSP_FirmwareLoaded;
5060
b0b98119 5061 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
1da177e4 5062 return err;
1da177e4
LT
5063
5064 return 0;
5065}
5066
55e957d8 5067static int snd_hdsp_free(struct hdsp *hdsp)
1da177e4
LT
5068{
5069 if (hdsp->port) {
5070 /* stop the audio, and cancel all interrupts */
5071 tasklet_kill(&hdsp->midi_tasklet);
5072 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5073 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5074 }
5075
5076 if (hdsp->irq >= 0)
5077 free_irq(hdsp->irq, (void *)hdsp);
5078
5079 snd_hdsp_free_buffers(hdsp);
5080
5081 if (hdsp->iobase)
5082 iounmap(hdsp->iobase);
5083
5084 if (hdsp->port)
5085 pci_release_regions(hdsp->pci);
5086
5087 pci_disable_device(hdsp->pci);
5088 return 0;
5089}
5090
55e957d8 5091static void snd_hdsp_card_free(struct snd_card *card)
1da177e4 5092{
55e957d8 5093 struct hdsp *hdsp = (struct hdsp *) card->private_data;
1da177e4
LT
5094
5095 if (hdsp)
5096 snd_hdsp_free(hdsp);
5097}
5098
5099static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5100 const struct pci_device_id *pci_id)
5101{
5102 static int dev;
55e957d8
TI
5103 struct hdsp *hdsp;
5104 struct snd_card *card;
1da177e4
LT
5105 int err;
5106
5107 if (dev >= SNDRV_CARDS)
5108 return -ENODEV;
5109 if (!enable[dev]) {
5110 dev++;
5111 return -ENOENT;
5112 }
5113
55e957d8 5114 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp))))
1da177e4
LT
5115 return -ENOMEM;
5116
55e957d8 5117 hdsp = (struct hdsp *) card->private_data;
1da177e4
LT
5118 card->private_free = snd_hdsp_card_free;
5119 hdsp->dev = dev;
5120 hdsp->pci = pci;
5121 snd_card_set_dev(card, &pci->dev);
5122
5123 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5124 snd_card_free(card);
5125 return err;
5126 }
5127
5128 strcpy(card->shortname, "Hammerfall DSP");
5129 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5130 hdsp->port, hdsp->irq);
5131
5132 if ((err = snd_card_register(card)) < 0) {
5133 snd_card_free(card);
5134 return err;
5135 }
5136 pci_set_drvdata(pci, card);
5137 dev++;
5138 return 0;
5139}
5140
5141static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5142{
5143 snd_card_free(pci_get_drvdata(pci));
5144 pci_set_drvdata(pci, NULL);
5145}
5146
5147static struct pci_driver driver = {
5148 .name = "RME Hammerfall DSP",
5149 .id_table = snd_hdsp_ids,
5150 .probe = snd_hdsp_probe,
5151 .remove = __devexit_p(snd_hdsp_remove),
5152};
5153
5154static int __init alsa_card_hdsp_init(void)
5155{
01d25d46 5156 return pci_register_driver(&driver);
1da177e4
LT
5157}
5158
5159static void __exit alsa_card_hdsp_exit(void)
5160{
5161 pci_unregister_driver(&driver);
5162}
5163
5164module_init(alsa_card_hdsp_init)
5165module_exit(alsa_card_hdsp_exit)
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