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1da177e4 LT |
1 | /* |
2 | * ALSA driver for RME Hammerfall DSP audio interface(s) | |
3 | * | |
4 | * Copyright (c) 2002 Paul Davis | |
5 | * Marcus Andersson | |
6 | * Thomas Charbonnel | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
1da177e4 LT |
24 | #include <linux/init.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/interrupt.h> | |
1da177e4 LT |
27 | #include <linux/pci.h> |
28 | #include <linux/firmware.h> | |
65a77217 | 29 | #include <linux/module.h> |
3f7440a6 | 30 | #include <linux/math64.h> |
8232932d | 31 | #include <linux/vmalloc.h> |
1da177e4 LT |
32 | |
33 | #include <sound/core.h> | |
34 | #include <sound/control.h> | |
35 | #include <sound/pcm.h> | |
36 | #include <sound/info.h> | |
37 | #include <sound/asoundef.h> | |
38 | #include <sound/rawmidi.h> | |
39 | #include <sound/hwdep.h> | |
40 | #include <sound/initval.h> | |
41 | #include <sound/hdsp.h> | |
42 | ||
43 | #include <asm/byteorder.h> | |
44 | #include <asm/current.h> | |
45 | #include <asm/io.h> | |
46 | ||
47 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
48 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 | 49 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
1da177e4 LT |
50 | |
51 | module_param_array(index, int, NULL, 0444); | |
52 | MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); | |
53 | module_param_array(id, charp, NULL, 0444); | |
54 | MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); | |
55 | module_param_array(enable, bool, NULL, 0444); | |
56 | MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); | |
57 | MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); | |
58 | MODULE_DESCRIPTION("RME Hammerfall DSP"); | |
59 | MODULE_LICENSE("GPL"); | |
60 | MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP}," | |
61 | "{RME HDSP-9652}," | |
62 | "{RME HDSP-9632}}"); | |
28b26e15 | 63 | MODULE_FIRMWARE("rpm_firmware.bin"); |
7e0af29d CL |
64 | MODULE_FIRMWARE("multiface_firmware.bin"); |
65 | MODULE_FIRMWARE("multiface_firmware_rev11.bin"); | |
66 | MODULE_FIRMWARE("digiface_firmware.bin"); | |
67 | MODULE_FIRMWARE("digiface_firmware_rev11.bin"); | |
1da177e4 LT |
68 | |
69 | #define HDSP_MAX_CHANNELS 26 | |
70 | #define HDSP_MAX_DS_CHANNELS 14 | |
71 | #define HDSP_MAX_QS_CHANNELS 8 | |
72 | #define DIGIFACE_SS_CHANNELS 26 | |
73 | #define DIGIFACE_DS_CHANNELS 14 | |
74 | #define MULTIFACE_SS_CHANNELS 18 | |
75 | #define MULTIFACE_DS_CHANNELS 14 | |
76 | #define H9652_SS_CHANNELS 26 | |
77 | #define H9652_DS_CHANNELS 14 | |
78 | /* This does not include possible Analog Extension Boards | |
79 | AEBs are detected at card initialization | |
80 | */ | |
81 | #define H9632_SS_CHANNELS 12 | |
82 | #define H9632_DS_CHANNELS 8 | |
83 | #define H9632_QS_CHANNELS 4 | |
28b26e15 | 84 | #define RPM_CHANNELS 6 |
1da177e4 LT |
85 | |
86 | /* Write registers. These are defined as byte-offsets from the iobase value. | |
87 | */ | |
88 | #define HDSP_resetPointer 0 | |
d7923b2a | 89 | #define HDSP_freqReg 0 |
1da177e4 LT |
90 | #define HDSP_outputBufferAddress 32 |
91 | #define HDSP_inputBufferAddress 36 | |
92 | #define HDSP_controlRegister 64 | |
93 | #define HDSP_interruptConfirmation 96 | |
94 | #define HDSP_outputEnable 128 | |
95 | #define HDSP_control2Reg 256 | |
96 | #define HDSP_midiDataOut0 352 | |
97 | #define HDSP_midiDataOut1 356 | |
98 | #define HDSP_fifoData 368 | |
99 | #define HDSP_inputEnable 384 | |
100 | ||
101 | /* Read registers. These are defined as byte-offsets from the iobase value | |
102 | */ | |
103 | ||
104 | #define HDSP_statusRegister 0 | |
105 | #define HDSP_timecode 128 | |
106 | #define HDSP_status2Register 192 | |
1da177e4 LT |
107 | #define HDSP_midiDataIn0 360 |
108 | #define HDSP_midiDataIn1 364 | |
109 | #define HDSP_midiStatusOut0 384 | |
110 | #define HDSP_midiStatusOut1 388 | |
111 | #define HDSP_midiStatusIn0 392 | |
112 | #define HDSP_midiStatusIn1 396 | |
113 | #define HDSP_fifoStatus 400 | |
114 | ||
115 | /* the meters are regular i/o-mapped registers, but offset | |
116 | considerably from the rest. the peak registers are reset | |
f9ffc5d6 | 117 | when read; the least-significant 4 bits are full-scale counters; |
1da177e4 LT |
118 | the actual peak value is in the most-significant 24 bits. |
119 | */ | |
120 | ||
121 | #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ | |
122 | #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ | |
123 | #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ | |
124 | #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ | |
125 | #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ | |
126 | ||
127 | ||
128 | /* This is for H9652 cards | |
129 | Peak values are read downward from the base | |
130 | Rms values are read upward | |
131 | There are rms values for the outputs too | |
132 | 26*3 values are read in ss mode | |
133 | 14*3 in ds mode, with no gap between values | |
134 | */ | |
f9ffc5d6 | 135 | #define HDSP_9652_peakBase 7164 |
1da177e4 LT |
136 | #define HDSP_9652_rmsBase 4096 |
137 | ||
138 | /* c.f. the hdsp_9632_meters_t struct */ | |
139 | #define HDSP_9632_metersBase 4096 | |
140 | ||
141 | #define HDSP_IO_EXTENT 7168 | |
142 | ||
143 | /* control2 register bits */ | |
144 | ||
145 | #define HDSP_TMS 0x01 | |
146 | #define HDSP_TCK 0x02 | |
147 | #define HDSP_TDI 0x04 | |
148 | #define HDSP_JTAG 0x08 | |
149 | #define HDSP_PWDN 0x10 | |
150 | #define HDSP_PROGRAM 0x020 | |
151 | #define HDSP_CONFIG_MODE_0 0x040 | |
152 | #define HDSP_CONFIG_MODE_1 0x080 | |
a3466865 | 153 | #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD) |
1da177e4 LT |
154 | #define HDSP_BIGENDIAN_MODE 0x200 |
155 | #define HDSP_RD_MULTIPLE 0x400 | |
156 | #define HDSP_9652_ENABLE_MIXER 0x800 | |
0c2bc7c7 AK |
157 | #define HDSP_S200 0x800 |
158 | #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */ | |
159 | #define HDSP_CYCLIC_MODE 0x1000 | |
1da177e4 LT |
160 | #define HDSP_TDO 0x10000000 |
161 | ||
0c2bc7c7 AK |
162 | #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0) |
163 | #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1) | |
1da177e4 LT |
164 | |
165 | /* Control Register bits */ | |
166 | ||
167 | #define HDSP_Start (1<<0) /* start engine */ | |
168 | #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ | |
169 | #define HDSP_Latency1 (1<<2) /* [ see above ] */ | |
170 | #define HDSP_Latency2 (1<<3) /* [ see above ] */ | |
171 | #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ | |
172 | #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ | |
173 | #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ | |
174 | #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ | |
175 | #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ | |
176 | #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ | |
177 | #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ | |
178 | #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ | |
179 | #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ | |
f9ffc5d6 TB |
180 | #define HDSP_SyncRef2 (1<<13) |
181 | #define HDSP_SPDIFInputSelect0 (1<<14) | |
182 | #define HDSP_SPDIFInputSelect1 (1<<15) | |
183 | #define HDSP_SyncRef0 (1<<16) | |
1da177e4 | 184 | #define HDSP_SyncRef1 (1<<17) |
f9ffc5d6 | 185 | #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ |
1da177e4 LT |
186 | #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ |
187 | #define HDSP_Midi0InterruptEnable (1<<22) | |
188 | #define HDSP_Midi1InterruptEnable (1<<23) | |
189 | #define HDSP_LineOut (1<<24) | |
190 | #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ | |
191 | #define HDSP_ADGain1 (1<<26) | |
192 | #define HDSP_DAGain0 (1<<27) | |
193 | #define HDSP_DAGain1 (1<<28) | |
194 | #define HDSP_PhoneGain0 (1<<29) | |
195 | #define HDSP_PhoneGain1 (1<<30) | |
196 | #define HDSP_QuadSpeed (1<<31) | |
197 | ||
28b26e15 FF |
198 | /* RPM uses some of the registers for special purposes */ |
199 | #define HDSP_RPM_Inp12 0x04A00 | |
200 | #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */ | |
201 | #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */ | |
202 | #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */ | |
203 | #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */ | |
204 | #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */ | |
205 | ||
206 | #define HDSP_RPM_Inp34 0x32000 | |
207 | #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */ | |
208 | #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */ | |
209 | #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */ | |
210 | #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */ | |
211 | #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */ | |
212 | ||
213 | #define HDSP_RPM_Bypass 0x01000 | |
214 | ||
215 | #define HDSP_RPM_Disconnect 0x00001 | |
216 | ||
1da177e4 LT |
217 | #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) |
218 | #define HDSP_ADGainMinus10dBV HDSP_ADGainMask | |
219 | #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) | |
220 | #define HDSP_ADGainLowGain 0 | |
221 | ||
222 | #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) | |
223 | #define HDSP_DAGainHighGain HDSP_DAGainMask | |
224 | #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) | |
225 | #define HDSP_DAGainMinus10dBV 0 | |
226 | ||
227 | #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) | |
228 | #define HDSP_PhoneGain0dB HDSP_PhoneGainMask | |
229 | #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) | |
230 | #define HDSP_PhoneGainMinus12dB 0 | |
231 | ||
232 | #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) | |
233 | #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) | |
234 | ||
235 | #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) | |
236 | #define HDSP_SPDIFInputADAT1 0 | |
237 | #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) | |
238 | #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) | |
239 | #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) | |
240 | ||
241 | #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) | |
242 | #define HDSP_SyncRef_ADAT1 0 | |
243 | #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) | |
244 | #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) | |
245 | #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) | |
246 | #define HDSP_SyncRef_WORD (HDSP_SyncRef2) | |
247 | #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) | |
248 | ||
249 | /* Sample Clock Sources */ | |
250 | ||
251 | #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 | |
252 | #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 | |
253 | #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 | |
254 | #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 | |
255 | #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 | |
256 | #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 | |
257 | #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 | |
258 | #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 | |
259 | #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 | |
260 | #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 | |
261 | ||
262 | /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ | |
263 | ||
264 | #define HDSP_SYNC_FROM_WORD 0 | |
265 | #define HDSP_SYNC_FROM_SPDIF 1 | |
266 | #define HDSP_SYNC_FROM_ADAT1 2 | |
267 | #define HDSP_SYNC_FROM_ADAT_SYNC 3 | |
268 | #define HDSP_SYNC_FROM_ADAT2 4 | |
269 | #define HDSP_SYNC_FROM_ADAT3 5 | |
270 | ||
271 | /* SyncCheck status */ | |
272 | ||
273 | #define HDSP_SYNC_CHECK_NO_LOCK 0 | |
274 | #define HDSP_SYNC_CHECK_LOCK 1 | |
275 | #define HDSP_SYNC_CHECK_SYNC 2 | |
276 | ||
277 | /* AutoSync references - used by "autosync_ref" control switch */ | |
278 | ||
279 | #define HDSP_AUTOSYNC_FROM_WORD 0 | |
280 | #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 | |
281 | #define HDSP_AUTOSYNC_FROM_SPDIF 2 | |
282 | #define HDSP_AUTOSYNC_FROM_NONE 3 | |
283 | #define HDSP_AUTOSYNC_FROM_ADAT1 4 | |
284 | #define HDSP_AUTOSYNC_FROM_ADAT2 5 | |
285 | #define HDSP_AUTOSYNC_FROM_ADAT3 6 | |
286 | ||
287 | /* Possible sources of S/PDIF input */ | |
288 | ||
289 | #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ | |
290 | #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ | |
291 | #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ | |
292 | #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ | |
293 | ||
294 | #define HDSP_Frequency32KHz HDSP_Frequency0 | |
295 | #define HDSP_Frequency44_1KHz HDSP_Frequency1 | |
296 | #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) | |
297 | #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) | |
298 | #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) | |
299 | #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) | |
300 | /* For H9632 cards */ | |
301 | #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) | |
302 | #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) | |
303 | #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) | |
e4b6088c JC |
304 | /* RME says n = 104857600000000, but in the windows MADI driver, I see: |
305 | return 104857600000000 / rate; // 100 MHz | |
306 | return 110100480000000 / rate; // 105 MHz | |
307 | */ | |
308 | #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */ | |
1da177e4 LT |
309 | |
310 | #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) | |
311 | #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) | |
312 | ||
313 | #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) | |
314 | #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) | |
315 | ||
316 | /* Status Register bits */ | |
317 | ||
318 | #define HDSP_audioIRQPending (1<<0) | |
319 | #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ | |
320 | #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ | |
321 | #define HDSP_Lock1 (1<<2) | |
322 | #define HDSP_Lock0 (1<<3) | |
323 | #define HDSP_SPDIFSync (1<<4) | |
324 | #define HDSP_TimecodeLock (1<<5) | |
325 | #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ | |
326 | #define HDSP_Sync2 (1<<16) | |
327 | #define HDSP_Sync1 (1<<17) | |
328 | #define HDSP_Sync0 (1<<18) | |
329 | #define HDSP_DoubleSpeedStatus (1<<19) | |
330 | #define HDSP_ConfigError (1<<20) | |
331 | #define HDSP_DllError (1<<21) | |
332 | #define HDSP_spdifFrequency0 (1<<22) | |
333 | #define HDSP_spdifFrequency1 (1<<23) | |
334 | #define HDSP_spdifFrequency2 (1<<24) | |
335 | #define HDSP_SPDIFErrorFlag (1<<25) | |
336 | #define HDSP_BufferID (1<<26) | |
337 | #define HDSP_TimecodeSync (1<<27) | |
338 | #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ | |
339 | #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ | |
f9ffc5d6 | 340 | #define HDSP_midi0IRQPending (1<<30) |
1da177e4 LT |
341 | #define HDSP_midi1IRQPending (1<<31) |
342 | ||
343 | #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) | |
47ba97f8 RB |
344 | #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\ |
345 | HDSP_spdifFrequency1|\ | |
346 | HDSP_spdifFrequency2|\ | |
347 | HDSP_spdifFrequency3) | |
1da177e4 LT |
348 | |
349 | #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) | |
350 | #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) | |
351 | #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) | |
352 | ||
353 | #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) | |
354 | #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) | |
355 | #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) | |
356 | ||
357 | /* This is for H9632 cards */ | |
47ba97f8 RB |
358 | #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\ |
359 | HDSP_spdifFrequency1|\ | |
360 | HDSP_spdifFrequency2) | |
1da177e4 LT |
361 | #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 |
362 | #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) | |
363 | ||
364 | /* Status2 Register bits */ | |
365 | ||
366 | #define HDSP_version0 (1<<0) | |
367 | #define HDSP_version1 (1<<1) | |
368 | #define HDSP_version2 (1<<2) | |
369 | #define HDSP_wc_lock (1<<3) | |
370 | #define HDSP_wc_sync (1<<4) | |
371 | #define HDSP_inp_freq0 (1<<5) | |
372 | #define HDSP_inp_freq1 (1<<6) | |
373 | #define HDSP_inp_freq2 (1<<7) | |
374 | #define HDSP_SelSyncRef0 (1<<8) | |
375 | #define HDSP_SelSyncRef1 (1<<9) | |
376 | #define HDSP_SelSyncRef2 (1<<10) | |
377 | ||
378 | #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) | |
379 | ||
380 | #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) | |
381 | #define HDSP_systemFrequency32 (HDSP_inp_freq0) | |
382 | #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) | |
383 | #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) | |
384 | #define HDSP_systemFrequency64 (HDSP_inp_freq2) | |
385 | #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) | |
386 | #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) | |
387 | /* FIXME : more values for 9632 cards ? */ | |
388 | ||
389 | #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) | |
390 | #define HDSP_SelSyncRef_ADAT1 0 | |
391 | #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) | |
392 | #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) | |
393 | #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) | |
394 | #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) | |
395 | #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) | |
396 | ||
397 | /* Card state flags */ | |
398 | ||
399 | #define HDSP_InitializationComplete (1<<0) | |
400 | #define HDSP_FirmwareLoaded (1<<1) | |
401 | #define HDSP_FirmwareCached (1<<2) | |
402 | ||
403 | /* FIFO wait times, defined in terms of 1/10ths of msecs */ | |
404 | ||
405 | #define HDSP_LONG_WAIT 5000 | |
406 | #define HDSP_SHORT_WAIT 30 | |
407 | ||
408 | #define UNITY_GAIN 32768 | |
409 | #define MINUS_INFINITY_GAIN 0 | |
410 | ||
1da177e4 LT |
411 | /* the size of a substream (1 mono data stream) */ |
412 | ||
413 | #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) | |
414 | #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) | |
415 | ||
416 | /* the size of the area we need to allocate for DMA transfers. the | |
f9ffc5d6 | 417 | size is the same regardless of the number of channels - the |
1da177e4 LT |
418 | Multiface still uses the same memory area. |
419 | ||
420 | Note that we allocate 1 more channel than is apparently needed | |
421 | because the h/w seems to write 1 byte beyond the end of the last | |
422 | page. Sigh. | |
423 | */ | |
424 | ||
425 | #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) | |
426 | #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) | |
427 | ||
90caaef6 | 428 | #define HDSP_FIRMWARE_SIZE (24413 * 4) |
1da177e4 | 429 | |
55e957d8 | 430 | struct hdsp_9632_meters { |
1da177e4 LT |
431 | u32 input_peak[16]; |
432 | u32 playback_peak[16]; | |
433 | u32 output_peak[16]; | |
434 | u32 xxx_peak[16]; | |
435 | u32 padding[64]; | |
436 | u32 input_rms_low[16]; | |
437 | u32 playback_rms_low[16]; | |
438 | u32 output_rms_low[16]; | |
439 | u32 xxx_rms_low[16]; | |
440 | u32 input_rms_high[16]; | |
441 | u32 playback_rms_high[16]; | |
442 | u32 output_rms_high[16]; | |
443 | u32 xxx_rms_high[16]; | |
444 | }; | |
445 | ||
55e957d8 TI |
446 | struct hdsp_midi { |
447 | struct hdsp *hdsp; | |
1da177e4 | 448 | int id; |
55e957d8 TI |
449 | struct snd_rawmidi *rmidi; |
450 | struct snd_rawmidi_substream *input; | |
451 | struct snd_rawmidi_substream *output; | |
1da177e4 LT |
452 | char istimer; /* timer in use */ |
453 | struct timer_list timer; | |
454 | spinlock_t lock; | |
455 | int pending; | |
456 | }; | |
457 | ||
55e957d8 | 458 | struct hdsp { |
1da177e4 | 459 | spinlock_t lock; |
55e957d8 TI |
460 | struct snd_pcm_substream *capture_substream; |
461 | struct snd_pcm_substream *playback_substream; | |
462 | struct hdsp_midi midi[2]; | |
1da177e4 LT |
463 | struct tasklet_struct midi_tasklet; |
464 | int use_midi_tasklet; | |
465 | int precise_ptr; | |
466 | u32 control_register; /* cached value */ | |
467 | u32 control2_register; /* cached value */ | |
468 | u32 creg_spdif; | |
469 | u32 creg_spdif_stream; | |
e3ea4d89 | 470 | int clock_source_locked; |
28b26e15 | 471 | char *card_name; /* digiface/multiface/rpm */ |
55e957d8 | 472 | enum HDSP_IO_Type io_type; /* ditto, but for code use */ |
1da177e4 LT |
473 | unsigned short firmware_rev; |
474 | unsigned short state; /* stores state bits */ | |
90caaef6 TI |
475 | const struct firmware *firmware; |
476 | u32 *fw_uploaded; | |
1da177e4 LT |
477 | size_t period_bytes; /* guess what this is */ |
478 | unsigned char max_channels; | |
479 | unsigned char qs_in_channels; /* quad speed mode for H9632 */ | |
480 | unsigned char ds_in_channels; | |
481 | unsigned char ss_in_channels; /* different for multiface/digiface */ | |
f9ffc5d6 | 482 | unsigned char qs_out_channels; |
1da177e4 LT |
483 | unsigned char ds_out_channels; |
484 | unsigned char ss_out_channels; | |
485 | ||
486 | struct snd_dma_buffer capture_dma_buf; | |
487 | struct snd_dma_buffer playback_dma_buf; | |
488 | unsigned char *capture_buffer; /* suitably aligned address */ | |
489 | unsigned char *playback_buffer; /* suitably aligned address */ | |
490 | ||
491 | pid_t capture_pid; | |
492 | pid_t playback_pid; | |
493 | int running; | |
494 | int system_sample_rate; | |
495 | char *channel_map; | |
496 | int dev; | |
497 | int irq; | |
498 | unsigned long port; | |
499 | void __iomem *iobase; | |
55e957d8 TI |
500 | struct snd_card *card; |
501 | struct snd_pcm *pcm; | |
502 | struct snd_hwdep *hwdep; | |
1da177e4 | 503 | struct pci_dev *pci; |
55e957d8 | 504 | struct snd_kcontrol *spdif_ctl; |
1da177e4 | 505 | unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; |
d7923b2a | 506 | unsigned int dds_value; /* last value written to freq register */ |
1da177e4 LT |
507 | }; |
508 | ||
509 | /* These tables map the ALSA channels 1..N to the channels that we | |
510 | need to use in order to find the relevant channel buffer. RME | |
511 | refer to this kind of mapping as between "the ADAT channel and | |
512 | the DMA channel." We index it using the logical audio channel, | |
513 | and the value is the DMA channel (i.e. channel buffer number) | |
514 | where the data for that channel can be read/written from/to. | |
515 | */ | |
516 | ||
517 | static char channel_map_df_ss[HDSP_MAX_CHANNELS] = { | |
518 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
519 | 18, 19, 20, 21, 22, 23, 24, 25 | |
520 | }; | |
521 | ||
522 | static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ | |
523 | /* Analog */ | |
f9ffc5d6 | 524 | 0, 1, 2, 3, 4, 5, 6, 7, |
1da177e4 | 525 | /* ADAT 2 */ |
f9ffc5d6 | 526 | 16, 17, 18, 19, 20, 21, 22, 23, |
1da177e4 LT |
527 | /* SPDIF */ |
528 | 24, 25, | |
529 | -1, -1, -1, -1, -1, -1, -1, -1 | |
530 | }; | |
531 | ||
532 | static char channel_map_ds[HDSP_MAX_CHANNELS] = { | |
533 | /* ADAT channels are remapped */ | |
534 | 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, | |
535 | /* channels 12 and 13 are S/PDIF */ | |
536 | 24, 25, | |
537 | /* others don't exist */ | |
538 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 | |
539 | }; | |
540 | ||
541 | static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { | |
542 | /* ADAT channels */ | |
543 | 0, 1, 2, 3, 4, 5, 6, 7, | |
544 | /* SPDIF */ | |
545 | 8, 9, | |
546 | /* Analog */ | |
f9ffc5d6 | 547 | 10, 11, |
1da177e4 LT |
548 | /* AO4S-192 and AI4S-192 extension boards */ |
549 | 12, 13, 14, 15, | |
550 | /* others don't exist */ | |
f9ffc5d6 | 551 | -1, -1, -1, -1, -1, -1, -1, -1, |
1da177e4 LT |
552 | -1, -1 |
553 | }; | |
554 | ||
555 | static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { | |
556 | /* ADAT */ | |
557 | 1, 3, 5, 7, | |
558 | /* SPDIF */ | |
559 | 8, 9, | |
560 | /* Analog */ | |
f9ffc5d6 | 561 | 10, 11, |
1da177e4 LT |
562 | /* AO4S-192 and AI4S-192 extension boards */ |
563 | 12, 13, 14, 15, | |
564 | /* others don't exist */ | |
565 | -1, -1, -1, -1, -1, -1, -1, -1, | |
566 | -1, -1, -1, -1, -1, -1 | |
567 | }; | |
568 | ||
569 | static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { | |
570 | /* ADAT is disabled in this mode */ | |
571 | /* SPDIF */ | |
572 | 8, 9, | |
573 | /* Analog */ | |
574 | 10, 11, | |
575 | /* AO4S-192 and AI4S-192 extension boards */ | |
576 | 12, 13, 14, 15, | |
577 | /* others don't exist */ | |
578 | -1, -1, -1, -1, -1, -1, -1, -1, | |
579 | -1, -1, -1, -1, -1, -1, -1, -1, | |
580 | -1, -1 | |
581 | }; | |
582 | ||
583 | static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) | |
584 | { | |
585 | dmab->dev.type = SNDRV_DMA_TYPE_DEV; | |
586 | dmab->dev.dev = snd_dma_pci_data(pci); | |
b6a96915 TI |
587 | if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) { |
588 | if (dmab->bytes >= size) | |
589 | return 0; | |
1da177e4 | 590 | } |
b6a96915 TI |
591 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), |
592 | size, dmab) < 0) | |
593 | return -ENOMEM; | |
1da177e4 LT |
594 | return 0; |
595 | } | |
596 | ||
597 | static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) | |
598 | { | |
b6a96915 TI |
599 | if (dmab->area) { |
600 | dmab->dev.dev = NULL; /* make it anonymous */ | |
1da177e4 | 601 | snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci)); |
b6a96915 | 602 | } |
1da177e4 LT |
603 | } |
604 | ||
605 | ||
cebe41d4 | 606 | static DEFINE_PCI_DEVICE_TABLE(snd_hdsp_ids) = { |
1da177e4 LT |
607 | { |
608 | .vendor = PCI_VENDOR_ID_XILINX, | |
f9ffc5d6 | 609 | .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, |
1da177e4 LT |
610 | .subvendor = PCI_ANY_ID, |
611 | .subdevice = PCI_ANY_ID, | |
612 | }, /* RME Hammerfall-DSP */ | |
613 | { 0, }, | |
614 | }; | |
615 | ||
616 | MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); | |
617 | ||
618 | /* prototypes */ | |
55e957d8 TI |
619 | static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); |
620 | static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); | |
621 | static int snd_hdsp_enable_io (struct hdsp *hdsp); | |
622 | static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); | |
623 | static void snd_hdsp_initialize_channels (struct hdsp *hdsp); | |
624 | static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); | |
625 | static int hdsp_autosync_ref(struct hdsp *hdsp); | |
626 | static int snd_hdsp_set_defaults(struct hdsp *hdsp); | |
627 | static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); | |
628 | ||
629 | static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) | |
1da177e4 | 630 | { |
a3a68c85 RB |
631 | switch (hdsp->io_type) { |
632 | case Multiface: | |
633 | case Digiface: | |
28b26e15 | 634 | case RPM: |
a3a68c85 | 635 | default: |
192b8e39 AD |
636 | if (hdsp->firmware_rev == 0xa) |
637 | return (64 * out) + (32 + (in)); | |
638 | else | |
639 | return (52 * out) + (26 + (in)); | |
a3a68c85 | 640 | case H9632: |
1da177e4 | 641 | return (32 * out) + (16 + (in)); |
a3a68c85 | 642 | case H9652: |
1da177e4 LT |
643 | return (52 * out) + (26 + (in)); |
644 | } | |
645 | } | |
646 | ||
55e957d8 | 647 | static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) |
1da177e4 | 648 | { |
a3a68c85 RB |
649 | switch (hdsp->io_type) { |
650 | case Multiface: | |
651 | case Digiface: | |
28b26e15 | 652 | case RPM: |
a3a68c85 | 653 | default: |
192b8e39 AD |
654 | if (hdsp->firmware_rev == 0xa) |
655 | return (64 * out) + in; | |
656 | else | |
657 | return (52 * out) + in; | |
a3a68c85 | 658 | case H9632: |
1da177e4 | 659 | return (32 * out) + in; |
a3a68c85 | 660 | case H9652: |
1da177e4 LT |
661 | return (52 * out) + in; |
662 | } | |
663 | } | |
664 | ||
55e957d8 | 665 | static void hdsp_write(struct hdsp *hdsp, int reg, int val) |
1da177e4 LT |
666 | { |
667 | writel(val, hdsp->iobase + reg); | |
668 | } | |
669 | ||
55e957d8 | 670 | static unsigned int hdsp_read(struct hdsp *hdsp, int reg) |
1da177e4 LT |
671 | { |
672 | return readl (hdsp->iobase + reg); | |
673 | } | |
674 | ||
55e957d8 | 675 | static int hdsp_check_for_iobox (struct hdsp *hdsp) |
1da177e4 | 676 | { |
0c2bc7c7 AK |
677 | int i; |
678 | ||
1da177e4 | 679 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; |
0c2bc7c7 AK |
680 | for (i = 0; i < 500; i++) { |
681 | if (0 == (hdsp_read(hdsp, HDSP_statusRegister) & | |
682 | HDSP_ConfigError)) { | |
683 | if (i) { | |
684 | snd_printd("Hammerfall-DSP: IO box found after %d ms\n", | |
685 | (20 * i)); | |
686 | } | |
687 | return 0; | |
688 | } | |
689 | msleep(20); | |
1da177e4 | 690 | } |
0c2bc7c7 AK |
691 | snd_printk(KERN_ERR "Hammerfall-DSP: no IO box connected!\n"); |
692 | hdsp->state &= ~HDSP_FirmwareLoaded; | |
693 | return -EIO; | |
e588ed83 | 694 | } |
1da177e4 | 695 | |
e588ed83 TB |
696 | static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops, |
697 | unsigned int delay) | |
698 | { | |
699 | unsigned int i; | |
700 | ||
701 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) | |
702 | return 0; | |
703 | ||
704 | for (i = 0; i != loops; ++i) { | |
705 | if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError) | |
706 | msleep(delay); | |
707 | else { | |
708 | snd_printd("Hammerfall-DSP: iobox found after %ums!\n", | |
709 | i * delay); | |
710 | return 0; | |
711 | } | |
712 | } | |
713 | ||
28b26e15 | 714 | snd_printk("Hammerfall-DSP: no IO box connected!\n"); |
e588ed83 TB |
715 | hdsp->state &= ~HDSP_FirmwareLoaded; |
716 | return -EIO; | |
1da177e4 LT |
717 | } |
718 | ||
55e957d8 | 719 | static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { |
1da177e4 LT |
720 | |
721 | int i; | |
722 | unsigned long flags; | |
90caaef6 TI |
723 | const u32 *cache; |
724 | ||
725 | if (hdsp->fw_uploaded) | |
726 | cache = hdsp->fw_uploaded; | |
727 | else { | |
728 | if (!hdsp->firmware) | |
729 | return -ENODEV; | |
730 | cache = (u32 *)hdsp->firmware->data; | |
731 | if (!cache) | |
732 | return -ENODEV; | |
733 | } | |
1da177e4 LT |
734 | |
735 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
f9ffc5d6 | 736 | |
1da177e4 LT |
737 | snd_printk ("Hammerfall-DSP: loading firmware\n"); |
738 | ||
739 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); | |
740 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
f9ffc5d6 | 741 | |
1da177e4 LT |
742 | if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { |
743 | snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n"); | |
0c2bc7c7 | 744 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); |
1da177e4 LT |
745 | return -EIO; |
746 | } | |
f9ffc5d6 | 747 | |
1da177e4 | 748 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); |
f9ffc5d6 | 749 | |
90caaef6 TI |
750 | for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) { |
751 | hdsp_write(hdsp, HDSP_fifoData, cache[i]); | |
1da177e4 LT |
752 | if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { |
753 | snd_printk ("Hammerfall-DSP: timeout during firmware loading\n"); | |
0c2bc7c7 | 754 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); |
1da177e4 LT |
755 | return -EIO; |
756 | } | |
757 | } | |
758 | ||
0c2bc7c7 AK |
759 | hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT); |
760 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); | |
1da177e4 | 761 | |
0c2bc7c7 | 762 | ssleep(3); |
1da177e4 LT |
763 | #ifdef SNDRV_BIG_ENDIAN |
764 | hdsp->control2_register = HDSP_BIGENDIAN_MODE; | |
765 | #else | |
766 | hdsp->control2_register = 0; | |
767 | #endif | |
768 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
769 | snd_printk ("Hammerfall-DSP: finished firmware loading\n"); | |
f9ffc5d6 | 770 | |
1da177e4 LT |
771 | } |
772 | if (hdsp->state & HDSP_InitializationComplete) { | |
b0b98119 | 773 | snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n"); |
1da177e4 LT |
774 | spin_lock_irqsave(&hdsp->lock, flags); |
775 | snd_hdsp_set_defaults(hdsp); | |
f9ffc5d6 | 776 | spin_unlock_irqrestore(&hdsp->lock, flags); |
1da177e4 | 777 | } |
f9ffc5d6 | 778 | |
1da177e4 LT |
779 | hdsp->state |= HDSP_FirmwareLoaded; |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
55e957d8 | 784 | static int hdsp_get_iobox_version (struct hdsp *hdsp) |
1da177e4 LT |
785 | { |
786 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
f9ffc5d6 | 787 | |
0c2bc7c7 AK |
788 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); |
789 | hdsp_write(hdsp, HDSP_fifoData, 0); | |
1da177e4 | 790 | |
0c2bc7c7 AK |
791 | if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) { |
792 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); | |
793 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
794 | } | |
795 | ||
796 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM); | |
1da177e4 | 797 | hdsp_write (hdsp, HDSP_fifoData, 0); |
0c2bc7c7 AK |
798 | if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) { |
799 | hdsp->io_type = Multiface; | |
800 | snd_printk("Hammerfall-DSP: Multiface found\n"); | |
801 | return 0; | |
802 | } | |
1da177e4 | 803 | |
0c2bc7c7 AK |
804 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); |
805 | hdsp_write(hdsp, HDSP_fifoData, 0); | |
806 | if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) { | |
1da177e4 | 807 | hdsp->io_type = Digiface; |
0c2bc7c7 AK |
808 | snd_printk("Hammerfall-DSP: Digiface found\n"); |
809 | return 0; | |
f9ffc5d6 | 810 | } |
0c2bc7c7 AK |
811 | |
812 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); | |
813 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
814 | hdsp_write(hdsp, HDSP_fifoData, 0); | |
815 | if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) { | |
816 | hdsp->io_type = Multiface; | |
817 | snd_printk("Hammerfall-DSP: Multiface found\n"); | |
818 | return 0; | |
819 | } | |
820 | ||
821 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); | |
822 | hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
823 | hdsp_write(hdsp, HDSP_fifoData, 0); | |
824 | if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) { | |
825 | hdsp->io_type = Multiface; | |
826 | snd_printk("Hammerfall-DSP: Multiface found\n"); | |
827 | return 0; | |
828 | } | |
829 | ||
830 | hdsp->io_type = RPM; | |
831 | snd_printk("Hammerfall-DSP: RPM found\n"); | |
832 | return 0; | |
1da177e4 LT |
833 | } else { |
834 | /* firmware was already loaded, get iobox type */ | |
28b26e15 FF |
835 | if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2) |
836 | hdsp->io_type = RPM; | |
837 | else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) | |
1da177e4 | 838 | hdsp->io_type = Multiface; |
b0b98119 | 839 | else |
1da177e4 | 840 | hdsp->io_type = Digiface; |
1da177e4 LT |
841 | } |
842 | return 0; | |
843 | } | |
844 | ||
845 | ||
92eed66d | 846 | static int hdsp_request_fw_loader(struct hdsp *hdsp); |
311e70a4 TI |
847 | |
848 | static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) | |
1da177e4 | 849 | { |
311e70a4 TI |
850 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) |
851 | return 0; | |
1da177e4 | 852 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { |
1da177e4 | 853 | hdsp->state &= ~HDSP_FirmwareLoaded; |
311e70a4 | 854 | if (! load_on_demand) |
b0b98119 | 855 | return -EIO; |
311e70a4 | 856 | snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n"); |
b0b98119 | 857 | /* try to load firmware */ |
311e70a4 | 858 | if (! (hdsp->state & HDSP_FirmwareCached)) { |
311e70a4 TI |
859 | if (! hdsp_request_fw_loader(hdsp)) |
860 | return 0; | |
311e70a4 TI |
861 | snd_printk(KERN_ERR |
862 | "Hammerfall-DSP: No firmware loaded nor " | |
863 | "cached, please upload firmware.\n"); | |
864 | return -EIO; | |
865 | } | |
866 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
867 | snd_printk(KERN_ERR | |
868 | "Hammerfall-DSP: Firmware loading from " | |
869 | "cache failed, please upload manually.\n"); | |
870 | return -EIO; | |
b0b98119 | 871 | } |
1da177e4 LT |
872 | } |
873 | return 0; | |
874 | } | |
875 | ||
876 | ||
55e957d8 | 877 | static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) |
f9ffc5d6 | 878 | { |
1da177e4 LT |
879 | int i; |
880 | ||
881 | /* the fifoStatus registers reports on how many words | |
882 | are available in the command FIFO. | |
883 | */ | |
f9ffc5d6 | 884 | |
1da177e4 LT |
885 | for (i = 0; i < timeout; i++) { |
886 | ||
887 | if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) | |
888 | return 0; | |
889 | ||
890 | /* not very friendly, but we only do this during a firmware | |
891 | load and changing the mixer, so we just put up with it. | |
892 | */ | |
893 | ||
894 | udelay (100); | |
895 | } | |
896 | ||
897 | snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n", | |
898 | count, timeout); | |
899 | return -1; | |
900 | } | |
901 | ||
55e957d8 | 902 | static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) |
1da177e4 | 903 | { |
b0b98119 | 904 | if (addr >= HDSP_MATRIX_MIXER_SIZE) |
1da177e4 | 905 | return 0; |
b0b98119 | 906 | |
1da177e4 LT |
907 | return hdsp->mixer_matrix[addr]; |
908 | } | |
909 | ||
55e957d8 | 910 | static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) |
1da177e4 LT |
911 | { |
912 | unsigned int ad; | |
913 | ||
914 | if (addr >= HDSP_MATRIX_MIXER_SIZE) | |
915 | return -1; | |
f9ffc5d6 | 916 | |
1da177e4 LT |
917 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { |
918 | ||
919 | /* from martin bjornsen: | |
f9ffc5d6 | 920 | |
1da177e4 LT |
921 | "You can only write dwords to the |
922 | mixer memory which contain two | |
923 | mixer values in the low and high | |
924 | word. So if you want to change | |
925 | value 0 you have to read value 1 | |
926 | from the cache and write both to | |
927 | the first dword in the mixer | |
928 | memory." | |
929 | */ | |
930 | ||
b0b98119 | 931 | if (hdsp->io_type == H9632 && addr >= 512) |
1da177e4 | 932 | return 0; |
1da177e4 | 933 | |
b0b98119 | 934 | if (hdsp->io_type == H9652 && addr >= 1352) |
1da177e4 | 935 | return 0; |
1da177e4 LT |
936 | |
937 | hdsp->mixer_matrix[addr] = data; | |
938 | ||
f9ffc5d6 | 939 | |
1da177e4 LT |
940 | /* `addr' addresses a 16-bit wide address, but |
941 | the address space accessed via hdsp_write | |
942 | uses byte offsets. put another way, addr | |
943 | varies from 0 to 1351, but to access the | |
944 | corresponding memory location, we need | |
945 | to access 0 to 2703 ... | |
946 | */ | |
947 | ad = addr/2; | |
f9ffc5d6 TB |
948 | |
949 | hdsp_write (hdsp, 4096 + (ad*4), | |
950 | (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + | |
1da177e4 | 951 | hdsp->mixer_matrix[addr&0x7fe]); |
f9ffc5d6 | 952 | |
1da177e4 LT |
953 | return 0; |
954 | ||
955 | } else { | |
956 | ||
957 | ad = (addr << 16) + data; | |
f9ffc5d6 | 958 | |
b0b98119 | 959 | if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) |
1da177e4 | 960 | return -1; |
1da177e4 LT |
961 | |
962 | hdsp_write (hdsp, HDSP_fifoData, ad); | |
963 | hdsp->mixer_matrix[addr] = data; | |
964 | ||
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
55e957d8 | 970 | static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) |
1da177e4 LT |
971 | { |
972 | unsigned long flags; | |
973 | int ret = 1; | |
974 | ||
975 | spin_lock_irqsave(&hdsp->lock, flags); | |
976 | if ((hdsp->playback_pid != hdsp->capture_pid) && | |
b0b98119 | 977 | (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) |
1da177e4 | 978 | ret = 0; |
1da177e4 LT |
979 | spin_unlock_irqrestore(&hdsp->lock, flags); |
980 | return ret; | |
981 | } | |
982 | ||
55e957d8 | 983 | static int hdsp_spdif_sample_rate(struct hdsp *hdsp) |
1da177e4 LT |
984 | { |
985 | unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); | |
986 | unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); | |
987 | ||
47ba97f8 RB |
988 | /* For the 9632, the mask is different */ |
989 | if (hdsp->io_type == H9632) | |
990 | rate_bits = (status & HDSP_spdifFrequencyMask_9632); | |
991 | ||
b0b98119 | 992 | if (status & HDSP_SPDIFErrorFlag) |
1da177e4 | 993 | return 0; |
f9ffc5d6 | 994 | |
1da177e4 LT |
995 | switch (rate_bits) { |
996 | case HDSP_spdifFrequency32KHz: return 32000; | |
997 | case HDSP_spdifFrequency44_1KHz: return 44100; | |
998 | case HDSP_spdifFrequency48KHz: return 48000; | |
999 | case HDSP_spdifFrequency64KHz: return 64000; | |
1000 | case HDSP_spdifFrequency88_2KHz: return 88200; | |
1001 | case HDSP_spdifFrequency96KHz: return 96000; | |
f9ffc5d6 | 1002 | case HDSP_spdifFrequency128KHz: |
1da177e4 LT |
1003 | if (hdsp->io_type == H9632) return 128000; |
1004 | break; | |
f9ffc5d6 | 1005 | case HDSP_spdifFrequency176_4KHz: |
1da177e4 LT |
1006 | if (hdsp->io_type == H9632) return 176400; |
1007 | break; | |
f9ffc5d6 | 1008 | case HDSP_spdifFrequency192KHz: |
1da177e4 LT |
1009 | if (hdsp->io_type == H9632) return 192000; |
1010 | break; | |
1011 | default: | |
1012 | break; | |
1013 | } | |
1014 | snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); | |
1015 | return 0; | |
1016 | } | |
1017 | ||
47ba97f8 RB |
1018 | static int hdsp_external_sample_rate(struct hdsp *hdsp) |
1019 | { | |
1020 | unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
1021 | unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; | |
1022 | ||
1023 | /* For the 9632 card, there seems to be no bit for indicating external | |
1024 | * sample rate greater than 96kHz. The card reports the corresponding | |
1025 | * single speed. So the best means seems to get spdif rate when | |
1026 | * autosync reference is spdif */ | |
1027 | if (hdsp->io_type == H9632 && | |
1028 | hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF) | |
1029 | return hdsp_spdif_sample_rate(hdsp); | |
1030 | ||
1031 | switch (rate_bits) { | |
1032 | case HDSP_systemFrequency32: return 32000; | |
1033 | case HDSP_systemFrequency44_1: return 44100; | |
1034 | case HDSP_systemFrequency48: return 48000; | |
1035 | case HDSP_systemFrequency64: return 64000; | |
1036 | case HDSP_systemFrequency88_2: return 88200; | |
1037 | case HDSP_systemFrequency96: return 96000; | |
1038 | default: | |
1039 | return 0; | |
1040 | } | |
1041 | } | |
1042 | ||
55e957d8 | 1043 | static void hdsp_compute_period_size(struct hdsp *hdsp) |
1da177e4 LT |
1044 | { |
1045 | hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); | |
1046 | } | |
1047 | ||
55e957d8 | 1048 | static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) |
1da177e4 LT |
1049 | { |
1050 | int position; | |
1051 | ||
1052 | position = hdsp_read(hdsp, HDSP_statusRegister); | |
1053 | ||
b0b98119 | 1054 | if (!hdsp->precise_ptr) |
1da177e4 | 1055 | return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; |
1da177e4 LT |
1056 | |
1057 | position &= HDSP_BufferPositionMask; | |
1058 | position /= 4; | |
1059 | position &= (hdsp->period_bytes/2) - 1; | |
1060 | return position; | |
1061 | } | |
1062 | ||
55e957d8 | 1063 | static void hdsp_reset_hw_pointer(struct hdsp *hdsp) |
1da177e4 LT |
1064 | { |
1065 | hdsp_write (hdsp, HDSP_resetPointer, 0); | |
d7923b2a RB |
1066 | if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) |
1067 | /* HDSP_resetPointer = HDSP_freqReg, which is strange and | |
1068 | * requires (?) to write again DDS value after a reset pointer | |
1069 | * (at least, it works like this) */ | |
1070 | hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); | |
1da177e4 LT |
1071 | } |
1072 | ||
55e957d8 | 1073 | static void hdsp_start_audio(struct hdsp *s) |
1da177e4 LT |
1074 | { |
1075 | s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); | |
1076 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
1077 | } | |
1078 | ||
55e957d8 | 1079 | static void hdsp_stop_audio(struct hdsp *s) |
1da177e4 LT |
1080 | { |
1081 | s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); | |
1082 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
1083 | } | |
1084 | ||
55e957d8 | 1085 | static void hdsp_silence_playback(struct hdsp *hdsp) |
1da177e4 LT |
1086 | { |
1087 | memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); | |
1088 | } | |
1089 | ||
55e957d8 | 1090 | static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) |
1da177e4 LT |
1091 | { |
1092 | int n; | |
1093 | ||
1094 | spin_lock_irq(&s->lock); | |
1095 | ||
1096 | frames >>= 7; | |
1097 | n = 0; | |
1098 | while (frames) { | |
1099 | n++; | |
1100 | frames >>= 1; | |
1101 | } | |
1102 | ||
1103 | s->control_register &= ~HDSP_LatencyMask; | |
1104 | s->control_register |= hdsp_encode_latency(n); | |
1105 | ||
1106 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
1107 | ||
1108 | hdsp_compute_period_size(s); | |
1109 | ||
1110 | spin_unlock_irq(&s->lock); | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
d7923b2a RB |
1115 | static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) |
1116 | { | |
1117 | u64 n; | |
f9ffc5d6 | 1118 | |
d7923b2a RB |
1119 | if (rate >= 112000) |
1120 | rate /= 4; | |
1121 | else if (rate >= 56000) | |
1122 | rate /= 2; | |
1123 | ||
e4b6088c | 1124 | n = DDS_NUMERATOR; |
3f7440a6 | 1125 | n = div_u64(n, rate); |
d7923b2a | 1126 | /* n should be less than 2^32 for being written to FREQ register */ |
da3cec35 | 1127 | snd_BUG_ON(n >> 32); |
d7923b2a RB |
1128 | /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS |
1129 | value to write it after a reset */ | |
1130 | hdsp->dds_value = n; | |
1131 | hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); | |
1132 | } | |
1133 | ||
55e957d8 | 1134 | static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) |
1da177e4 LT |
1135 | { |
1136 | int reject_if_open = 0; | |
1137 | int current_rate; | |
1138 | int rate_bits; | |
1139 | ||
1140 | /* ASSUMPTION: hdsp->lock is either held, or | |
1141 | there is no need for it (e.g. during module | |
1142 | initialization). | |
1143 | */ | |
f9ffc5d6 TB |
1144 | |
1145 | if (!(hdsp->control_register & HDSP_ClockModeMaster)) { | |
1da177e4 LT |
1146 | if (called_internally) { |
1147 | /* request from ctl or card initialization */ | |
b0b98119 | 1148 | snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n"); |
1da177e4 | 1149 | return -1; |
f9ffc5d6 | 1150 | } else { |
1da177e4 LT |
1151 | /* hw_param request while in AutoSync mode */ |
1152 | int external_freq = hdsp_external_sample_rate(hdsp); | |
1153 | int spdif_freq = hdsp_spdif_sample_rate(hdsp); | |
f9ffc5d6 | 1154 | |
b0b98119 TI |
1155 | if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) |
1156 | snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n"); | |
1157 | else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) | |
f9ffc5d6 | 1158 | snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n"); |
b0b98119 TI |
1159 | else if (rate != external_freq) { |
1160 | snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n"); | |
1da177e4 | 1161 | return -1; |
f9ffc5d6 TB |
1162 | } |
1163 | } | |
1da177e4 LT |
1164 | } |
1165 | ||
1166 | current_rate = hdsp->system_sample_rate; | |
1167 | ||
1168 | /* Changing from a "single speed" to a "double speed" rate is | |
1169 | not allowed if any substreams are open. This is because | |
f9ffc5d6 | 1170 | such a change causes a shift in the location of |
1da177e4 | 1171 | the DMA buffers and a reduction in the number of available |
f9ffc5d6 | 1172 | buffers. |
1da177e4 LT |
1173 | |
1174 | Note that a similar but essentially insoluble problem | |
1175 | exists for externally-driven rate changes. All we can do | |
1176 | is to flag rate changes in the read/write routines. */ | |
1177 | ||
b0b98119 | 1178 | if (rate > 96000 && hdsp->io_type != H9632) |
1da177e4 | 1179 | return -EINVAL; |
f9ffc5d6 | 1180 | |
1da177e4 LT |
1181 | switch (rate) { |
1182 | case 32000: | |
b0b98119 | 1183 | if (current_rate > 48000) |
1da177e4 | 1184 | reject_if_open = 1; |
1da177e4 LT |
1185 | rate_bits = HDSP_Frequency32KHz; |
1186 | break; | |
1187 | case 44100: | |
b0b98119 | 1188 | if (current_rate > 48000) |
1da177e4 | 1189 | reject_if_open = 1; |
1da177e4 LT |
1190 | rate_bits = HDSP_Frequency44_1KHz; |
1191 | break; | |
1192 | case 48000: | |
b0b98119 | 1193 | if (current_rate > 48000) |
1da177e4 | 1194 | reject_if_open = 1; |
1da177e4 LT |
1195 | rate_bits = HDSP_Frequency48KHz; |
1196 | break; | |
1197 | case 64000: | |
b0b98119 | 1198 | if (current_rate <= 48000 || current_rate > 96000) |
1da177e4 | 1199 | reject_if_open = 1; |
1da177e4 LT |
1200 | rate_bits = HDSP_Frequency64KHz; |
1201 | break; | |
1202 | case 88200: | |
b0b98119 | 1203 | if (current_rate <= 48000 || current_rate > 96000) |
1da177e4 | 1204 | reject_if_open = 1; |
1da177e4 LT |
1205 | rate_bits = HDSP_Frequency88_2KHz; |
1206 | break; | |
1207 | case 96000: | |
b0b98119 | 1208 | if (current_rate <= 48000 || current_rate > 96000) |
1da177e4 | 1209 | reject_if_open = 1; |
1da177e4 LT |
1210 | rate_bits = HDSP_Frequency96KHz; |
1211 | break; | |
1212 | case 128000: | |
b0b98119 | 1213 | if (current_rate < 128000) |
1da177e4 | 1214 | reject_if_open = 1; |
1da177e4 LT |
1215 | rate_bits = HDSP_Frequency128KHz; |
1216 | break; | |
1217 | case 176400: | |
b0b98119 | 1218 | if (current_rate < 128000) |
1da177e4 | 1219 | reject_if_open = 1; |
1da177e4 LT |
1220 | rate_bits = HDSP_Frequency176_4KHz; |
1221 | break; | |
1222 | case 192000: | |
b0b98119 | 1223 | if (current_rate < 128000) |
1da177e4 | 1224 | reject_if_open = 1; |
1da177e4 LT |
1225 | rate_bits = HDSP_Frequency192KHz; |
1226 | break; | |
1227 | default: | |
1228 | return -EINVAL; | |
1229 | } | |
1230 | ||
1231 | if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { | |
1232 | snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n", | |
1233 | hdsp->capture_pid, | |
1234 | hdsp->playback_pid); | |
1235 | return -EBUSY; | |
1236 | } | |
1237 | ||
1238 | hdsp->control_register &= ~HDSP_FrequencyMask; | |
1239 | hdsp->control_register |= rate_bits; | |
1240 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1241 | ||
d7923b2a RB |
1242 | /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ |
1243 | if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) | |
1244 | hdsp_set_dds_value(hdsp, rate); | |
1245 | ||
1da177e4 LT |
1246 | if (rate >= 128000) { |
1247 | hdsp->channel_map = channel_map_H9632_qs; | |
1248 | } else if (rate > 48000) { | |
b0b98119 | 1249 | if (hdsp->io_type == H9632) |
1da177e4 | 1250 | hdsp->channel_map = channel_map_H9632_ds; |
b0b98119 | 1251 | else |
1da177e4 | 1252 | hdsp->channel_map = channel_map_ds; |
1da177e4 LT |
1253 | } else { |
1254 | switch (hdsp->io_type) { | |
28b26e15 | 1255 | case RPM: |
1da177e4 LT |
1256 | case Multiface: |
1257 | hdsp->channel_map = channel_map_mf_ss; | |
1258 | break; | |
1259 | case Digiface: | |
1260 | case H9652: | |
1261 | hdsp->channel_map = channel_map_df_ss; | |
1262 | break; | |
1263 | case H9632: | |
1264 | hdsp->channel_map = channel_map_H9632_ss; | |
1265 | break; | |
1266 | default: | |
1267 | /* should never happen */ | |
1268 | break; | |
1269 | } | |
1270 | } | |
f9ffc5d6 | 1271 | |
1da177e4 LT |
1272 | hdsp->system_sample_rate = rate; |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | /*---------------------------------------------------------------------------- | |
1278 | MIDI | |
1279 | ----------------------------------------------------------------------------*/ | |
1280 | ||
55e957d8 | 1281 | static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) |
1da177e4 LT |
1282 | { |
1283 | /* the hardware already does the relevant bit-mask with 0xff */ | |
b0b98119 | 1284 | if (id) |
1da177e4 | 1285 | return hdsp_read(hdsp, HDSP_midiDataIn1); |
b0b98119 | 1286 | else |
1da177e4 | 1287 | return hdsp_read(hdsp, HDSP_midiDataIn0); |
1da177e4 LT |
1288 | } |
1289 | ||
55e957d8 | 1290 | static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) |
1da177e4 LT |
1291 | { |
1292 | /* the hardware already does the relevant bit-mask with 0xff */ | |
b0b98119 | 1293 | if (id) |
1da177e4 | 1294 | hdsp_write(hdsp, HDSP_midiDataOut1, val); |
b0b98119 | 1295 | else |
1da177e4 | 1296 | hdsp_write(hdsp, HDSP_midiDataOut0, val); |
1da177e4 LT |
1297 | } |
1298 | ||
55e957d8 | 1299 | static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) |
1da177e4 | 1300 | { |
b0b98119 | 1301 | if (id) |
1da177e4 | 1302 | return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); |
b0b98119 | 1303 | else |
1da177e4 | 1304 | return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); |
1da177e4 LT |
1305 | } |
1306 | ||
55e957d8 | 1307 | static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) |
1da177e4 LT |
1308 | { |
1309 | int fifo_bytes_used; | |
1310 | ||
b0b98119 | 1311 | if (id) |
1da177e4 | 1312 | fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; |
b0b98119 | 1313 | else |
1da177e4 | 1314 | fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; |
1da177e4 | 1315 | |
b0b98119 | 1316 | if (fifo_bytes_used < 128) |
1da177e4 | 1317 | return 128 - fifo_bytes_used; |
b0b98119 | 1318 | else |
1da177e4 | 1319 | return 0; |
1da177e4 LT |
1320 | } |
1321 | ||
55e957d8 | 1322 | static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) |
1da177e4 | 1323 | { |
b0b98119 | 1324 | while (snd_hdsp_midi_input_available (hdsp, id)) |
1da177e4 | 1325 | snd_hdsp_midi_read_byte (hdsp, id); |
1da177e4 LT |
1326 | } |
1327 | ||
55e957d8 | 1328 | static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) |
1da177e4 LT |
1329 | { |
1330 | unsigned long flags; | |
1331 | int n_pending; | |
1332 | int to_write; | |
1333 | int i; | |
1334 | unsigned char buf[128]; | |
1335 | ||
1336 | /* Output is not interrupt driven */ | |
f9ffc5d6 | 1337 | |
1da177e4 LT |
1338 | spin_lock_irqsave (&hmidi->lock, flags); |
1339 | if (hmidi->output) { | |
1340 | if (!snd_rawmidi_transmit_empty (hmidi->output)) { | |
1341 | if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) { | |
1342 | if (n_pending > (int)sizeof (buf)) | |
1343 | n_pending = sizeof (buf); | |
f9ffc5d6 | 1344 | |
1da177e4 | 1345 | if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) { |
f9ffc5d6 | 1346 | for (i = 0; i < to_write; ++i) |
1da177e4 LT |
1347 | snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); |
1348 | } | |
1349 | } | |
1350 | } | |
1351 | } | |
1352 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1353 | return 0; | |
1354 | } | |
1355 | ||
55e957d8 | 1356 | static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) |
1da177e4 LT |
1357 | { |
1358 | unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ | |
1359 | unsigned long flags; | |
1360 | int n_pending; | |
1361 | int i; | |
1362 | ||
1363 | spin_lock_irqsave (&hmidi->lock, flags); | |
1364 | if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { | |
1365 | if (hmidi->input) { | |
b0b98119 | 1366 | if (n_pending > (int)sizeof (buf)) |
1da177e4 | 1367 | n_pending = sizeof (buf); |
b0b98119 | 1368 | for (i = 0; i < n_pending; ++i) |
1da177e4 | 1369 | buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); |
b0b98119 | 1370 | if (n_pending) |
1da177e4 | 1371 | snd_rawmidi_receive (hmidi->input, buf, n_pending); |
1da177e4 LT |
1372 | } else { |
1373 | /* flush the MIDI input FIFO */ | |
b0b98119 | 1374 | while (--n_pending) |
1da177e4 | 1375 | snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); |
1da177e4 LT |
1376 | } |
1377 | } | |
1378 | hmidi->pending = 0; | |
b0b98119 | 1379 | if (hmidi->id) |
1da177e4 | 1380 | hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; |
b0b98119 | 1381 | else |
1da177e4 | 1382 | hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; |
1da177e4 LT |
1383 | hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); |
1384 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1385 | return snd_hdsp_midi_output_write (hmidi); | |
1386 | } | |
1387 | ||
55e957d8 | 1388 | static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 | 1389 | { |
55e957d8 TI |
1390 | struct hdsp *hdsp; |
1391 | struct hdsp_midi *hmidi; | |
1da177e4 LT |
1392 | unsigned long flags; |
1393 | u32 ie; | |
1394 | ||
55e957d8 | 1395 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1396 | hdsp = hmidi->hdsp; |
1397 | ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; | |
1398 | spin_lock_irqsave (&hdsp->lock, flags); | |
1399 | if (up) { | |
1400 | if (!(hdsp->control_register & ie)) { | |
1401 | snd_hdsp_flush_midi_input (hdsp, hmidi->id); | |
1402 | hdsp->control_register |= ie; | |
1403 | } | |
1404 | } else { | |
1405 | hdsp->control_register &= ~ie; | |
1406 | tasklet_kill(&hdsp->midi_tasklet); | |
1407 | } | |
1408 | ||
1409 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1410 | spin_unlock_irqrestore (&hdsp->lock, flags); | |
1411 | } | |
1412 | ||
1413 | static void snd_hdsp_midi_output_timer(unsigned long data) | |
1414 | { | |
55e957d8 | 1415 | struct hdsp_midi *hmidi = (struct hdsp_midi *) data; |
1da177e4 | 1416 | unsigned long flags; |
f9ffc5d6 | 1417 | |
1da177e4 LT |
1418 | snd_hdsp_midi_output_write(hmidi); |
1419 | spin_lock_irqsave (&hmidi->lock, flags); | |
1420 | ||
1421 | /* this does not bump hmidi->istimer, because the | |
1422 | kernel automatically removed the timer when it | |
1423 | expired, and we are now adding it back, thus | |
f9ffc5d6 | 1424 | leaving istimer wherever it was set before. |
1da177e4 LT |
1425 | */ |
1426 | ||
1427 | if (hmidi->istimer) { | |
1428 | hmidi->timer.expires = 1 + jiffies; | |
1429 | add_timer(&hmidi->timer); | |
1430 | } | |
1431 | ||
1432 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1433 | } | |
1434 | ||
55e957d8 | 1435 | static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 | 1436 | { |
55e957d8 | 1437 | struct hdsp_midi *hmidi; |
1da177e4 LT |
1438 | unsigned long flags; |
1439 | ||
55e957d8 | 1440 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1441 | spin_lock_irqsave (&hmidi->lock, flags); |
1442 | if (up) { | |
1443 | if (!hmidi->istimer) { | |
1444 | init_timer(&hmidi->timer); | |
1445 | hmidi->timer.function = snd_hdsp_midi_output_timer; | |
1446 | hmidi->timer.data = (unsigned long) hmidi; | |
1447 | hmidi->timer.expires = 1 + jiffies; | |
1448 | add_timer(&hmidi->timer); | |
1449 | hmidi->istimer++; | |
1450 | } | |
1451 | } else { | |
b0b98119 | 1452 | if (hmidi->istimer && --hmidi->istimer <= 0) |
1da177e4 | 1453 | del_timer (&hmidi->timer); |
1da177e4 LT |
1454 | } |
1455 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1456 | if (up) | |
1457 | snd_hdsp_midi_output_write(hmidi); | |
1458 | } | |
1459 | ||
55e957d8 | 1460 | static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 1461 | { |
55e957d8 | 1462 | struct hdsp_midi *hmidi; |
1da177e4 | 1463 | |
55e957d8 | 1464 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1465 | spin_lock_irq (&hmidi->lock); |
1466 | snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); | |
1467 | hmidi->input = substream; | |
1468 | spin_unlock_irq (&hmidi->lock); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
55e957d8 | 1473 | static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 1474 | { |
55e957d8 | 1475 | struct hdsp_midi *hmidi; |
1da177e4 | 1476 | |
55e957d8 | 1477 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1478 | spin_lock_irq (&hmidi->lock); |
1479 | hmidi->output = substream; | |
1480 | spin_unlock_irq (&hmidi->lock); | |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
55e957d8 | 1485 | static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 1486 | { |
55e957d8 | 1487 | struct hdsp_midi *hmidi; |
1da177e4 LT |
1488 | |
1489 | snd_hdsp_midi_input_trigger (substream, 0); | |
1490 | ||
55e957d8 | 1491 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1492 | spin_lock_irq (&hmidi->lock); |
1493 | hmidi->input = NULL; | |
1494 | spin_unlock_irq (&hmidi->lock); | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
55e957d8 | 1499 | static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 1500 | { |
55e957d8 | 1501 | struct hdsp_midi *hmidi; |
1da177e4 LT |
1502 | |
1503 | snd_hdsp_midi_output_trigger (substream, 0); | |
1504 | ||
55e957d8 | 1505 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1506 | spin_lock_irq (&hmidi->lock); |
1507 | hmidi->output = NULL; | |
1508 | spin_unlock_irq (&hmidi->lock); | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
55e957d8 | 1513 | static struct snd_rawmidi_ops snd_hdsp_midi_output = |
1da177e4 LT |
1514 | { |
1515 | .open = snd_hdsp_midi_output_open, | |
1516 | .close = snd_hdsp_midi_output_close, | |
1517 | .trigger = snd_hdsp_midi_output_trigger, | |
1518 | }; | |
1519 | ||
55e957d8 | 1520 | static struct snd_rawmidi_ops snd_hdsp_midi_input = |
1da177e4 LT |
1521 | { |
1522 | .open = snd_hdsp_midi_input_open, | |
1523 | .close = snd_hdsp_midi_input_close, | |
1524 | .trigger = snd_hdsp_midi_input_trigger, | |
1525 | }; | |
1526 | ||
f40b6890 | 1527 | static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) |
1da177e4 LT |
1528 | { |
1529 | char buf[32]; | |
1530 | ||
1531 | hdsp->midi[id].id = id; | |
1532 | hdsp->midi[id].rmidi = NULL; | |
1533 | hdsp->midi[id].input = NULL; | |
1534 | hdsp->midi[id].output = NULL; | |
1535 | hdsp->midi[id].hdsp = hdsp; | |
1536 | hdsp->midi[id].istimer = 0; | |
1537 | hdsp->midi[id].pending = 0; | |
1538 | spin_lock_init (&hdsp->midi[id].lock); | |
1539 | ||
1540 | sprintf (buf, "%s MIDI %d", card->shortname, id+1); | |
b0b98119 | 1541 | if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) |
1da177e4 | 1542 | return -1; |
1da177e4 | 1543 | |
972d4c50 | 1544 | sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1); |
1da177e4 LT |
1545 | hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; |
1546 | ||
1547 | snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); | |
1548 | snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); | |
1549 | ||
1550 | hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | | |
1551 | SNDRV_RAWMIDI_INFO_INPUT | | |
1552 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1553 | ||
1554 | return 0; | |
1555 | } | |
1556 | ||
1557 | /*----------------------------------------------------------------------------- | |
1558 | Control Interface | |
1559 | ----------------------------------------------------------------------------*/ | |
1560 | ||
55e957d8 | 1561 | static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) |
1da177e4 LT |
1562 | { |
1563 | u32 val = 0; | |
1564 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; | |
1565 | val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; | |
1566 | if (val & HDSP_SPDIFProfessional) | |
1567 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; | |
1568 | else | |
1569 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; | |
1570 | return val; | |
1571 | } | |
1572 | ||
55e957d8 | 1573 | static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) |
1da177e4 LT |
1574 | { |
1575 | aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | | |
1576 | ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); | |
1577 | if (val & HDSP_SPDIFProfessional) | |
1578 | aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; | |
1579 | else | |
1580 | aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; | |
1581 | } | |
1582 | ||
55e957d8 | 1583 | static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1584 | { |
1585 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1586 | uinfo->count = 1; | |
1587 | return 0; | |
1588 | } | |
1589 | ||
55e957d8 | 1590 | static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1591 | { |
55e957d8 | 1592 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1593 | |
1da177e4 LT |
1594 | snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); |
1595 | return 0; | |
1596 | } | |
1597 | ||
55e957d8 | 1598 | static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1599 | { |
55e957d8 | 1600 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1601 | int change; |
1602 | u32 val; | |
f9ffc5d6 | 1603 | |
1da177e4 LT |
1604 | val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); |
1605 | spin_lock_irq(&hdsp->lock); | |
1606 | change = val != hdsp->creg_spdif; | |
1607 | hdsp->creg_spdif = val; | |
1608 | spin_unlock_irq(&hdsp->lock); | |
1609 | return change; | |
1610 | } | |
1611 | ||
55e957d8 | 1612 | static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1613 | { |
1614 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1615 | uinfo->count = 1; | |
1616 | return 0; | |
1617 | } | |
1618 | ||
55e957d8 | 1619 | static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1620 | { |
55e957d8 | 1621 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1622 | |
1da177e4 LT |
1623 | snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); |
1624 | return 0; | |
1625 | } | |
1626 | ||
55e957d8 | 1627 | static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1628 | { |
55e957d8 | 1629 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1630 | int change; |
1631 | u32 val; | |
f9ffc5d6 | 1632 | |
1da177e4 LT |
1633 | val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); |
1634 | spin_lock_irq(&hdsp->lock); | |
1635 | change = val != hdsp->creg_spdif_stream; | |
1636 | hdsp->creg_spdif_stream = val; | |
1637 | hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); | |
1638 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); | |
1639 | spin_unlock_irq(&hdsp->lock); | |
1640 | return change; | |
1641 | } | |
1642 | ||
55e957d8 | 1643 | static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1644 | { |
1645 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1646 | uinfo->count = 1; | |
1647 | return 0; | |
1648 | } | |
1649 | ||
55e957d8 | 1650 | static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 LT |
1651 | { |
1652 | ucontrol->value.iec958.status[0] = kcontrol->private_value; | |
1653 | return 0; | |
1654 | } | |
1655 | ||
1656 | #define HDSP_SPDIF_IN(xname, xindex) \ | |
67ed4161 | 1657 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1658 | .name = xname, \ |
1659 | .index = xindex, \ | |
1660 | .info = snd_hdsp_info_spdif_in, \ | |
1661 | .get = snd_hdsp_get_spdif_in, \ | |
1662 | .put = snd_hdsp_put_spdif_in } | |
1663 | ||
55e957d8 | 1664 | static unsigned int hdsp_spdif_in(struct hdsp *hdsp) |
1da177e4 LT |
1665 | { |
1666 | return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); | |
1667 | } | |
1668 | ||
55e957d8 | 1669 | static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) |
1da177e4 LT |
1670 | { |
1671 | hdsp->control_register &= ~HDSP_SPDIFInputMask; | |
1672 | hdsp->control_register |= hdsp_encode_spdif_in(in); | |
1673 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1674 | return 0; | |
1675 | } | |
1676 | ||
55e957d8 | 1677 | static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1678 | { |
1679 | static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; | |
55e957d8 | 1680 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1681 | |
1682 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1683 | uinfo->count = 1; | |
1684 | uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); | |
1685 | if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) | |
1686 | uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); | |
1687 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1688 | return 0; | |
1689 | } | |
1690 | ||
55e957d8 | 1691 | static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1692 | { |
55e957d8 | 1693 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1694 | |
1da177e4 LT |
1695 | ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); |
1696 | return 0; | |
1697 | } | |
1698 | ||
55e957d8 | 1699 | static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1700 | { |
55e957d8 | 1701 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1702 | int change; |
1703 | unsigned int val; | |
f9ffc5d6 | 1704 | |
1da177e4 LT |
1705 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
1706 | return -EBUSY; | |
1707 | val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); | |
1708 | spin_lock_irq(&hdsp->lock); | |
1709 | change = val != hdsp_spdif_in(hdsp); | |
1710 | if (change) | |
1711 | hdsp_set_spdif_input(hdsp, val); | |
1712 | spin_unlock_irq(&hdsp->lock); | |
1713 | return change; | |
1714 | } | |
1715 | ||
66d9244e AK |
1716 | #define HDSP_TOGGLE_SETTING(xname, xindex) \ |
1717 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
1718 | .name = xname, \ | |
1719 | .private_value = xindex, \ | |
1720 | .info = snd_hdsp_info_toggle_setting, \ | |
1721 | .get = snd_hdsp_get_toggle_setting, \ | |
1722 | .put = snd_hdsp_put_toggle_setting \ | |
1723 | } | |
1724 | ||
1725 | static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask) | |
1726 | { | |
1727 | return (hdsp->control_register & regmask) ? 1 : 0; | |
1728 | } | |
1729 | ||
1730 | static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out) | |
1731 | { | |
1732 | if (out) | |
1733 | hdsp->control_register |= regmask; | |
1734 | else | |
1735 | hdsp->control_register &= ~regmask; | |
1736 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1737 | ||
1738 | return 0; | |
1739 | } | |
1740 | ||
1741 | #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info | |
1742 | ||
1743 | static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol, | |
1744 | struct snd_ctl_elem_value *ucontrol) | |
1745 | { | |
1746 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
1747 | u32 regmask = kcontrol->private_value; | |
1748 | ||
1749 | spin_lock_irq(&hdsp->lock); | |
1750 | ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask); | |
1751 | spin_unlock_irq(&hdsp->lock); | |
1752 | return 0; | |
1753 | } | |
1754 | ||
1755 | static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol, | |
1756 | struct snd_ctl_elem_value *ucontrol) | |
1757 | { | |
1758 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
1759 | u32 regmask = kcontrol->private_value; | |
1760 | int change; | |
1761 | unsigned int val; | |
1762 | ||
1763 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1764 | return -EBUSY; | |
1765 | val = ucontrol->value.integer.value[0] & 1; | |
1766 | spin_lock_irq(&hdsp->lock); | |
1767 | change = (int) val != hdsp_toggle_setting(hdsp, regmask); | |
1768 | if (change) | |
1769 | hdsp_set_toggle_setting(hdsp, regmask, val); | |
1770 | spin_unlock_irq(&hdsp->lock); | |
1771 | return change; | |
1772 | } | |
1773 | ||
1774 | ||
1da177e4 | 1775 | #define HDSP_SPDIF_OUT(xname, xindex) \ |
67ed4161 | 1776 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1777 | .info = snd_hdsp_info_spdif_bits, \ |
1778 | .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } | |
1779 | ||
55e957d8 | 1780 | static int hdsp_spdif_out(struct hdsp *hdsp) |
1da177e4 LT |
1781 | { |
1782 | return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0; | |
1783 | } | |
1784 | ||
55e957d8 | 1785 | static int hdsp_set_spdif_output(struct hdsp *hdsp, int out) |
1da177e4 | 1786 | { |
b0b98119 | 1787 | if (out) |
1da177e4 | 1788 | hdsp->control_register |= HDSP_SPDIFOpticalOut; |
b0b98119 | 1789 | else |
1da177e4 | 1790 | hdsp->control_register &= ~HDSP_SPDIFOpticalOut; |
1da177e4 LT |
1791 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1792 | return 0; | |
1793 | } | |
1794 | ||
a5ce8890 | 1795 | #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info |
1da177e4 | 1796 | |
55e957d8 | 1797 | static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1798 | { |
55e957d8 | 1799 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1800 | |
1da177e4 LT |
1801 | ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); |
1802 | return 0; | |
1803 | } | |
1804 | ||
55e957d8 | 1805 | static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1806 | { |
55e957d8 | 1807 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1808 | int change; |
1809 | unsigned int val; | |
f9ffc5d6 | 1810 | |
1da177e4 LT |
1811 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
1812 | return -EBUSY; | |
1813 | val = ucontrol->value.integer.value[0] & 1; | |
1814 | spin_lock_irq(&hdsp->lock); | |
1815 | change = (int)val != hdsp_spdif_out(hdsp); | |
1816 | hdsp_set_spdif_output(hdsp, val); | |
1817 | spin_unlock_irq(&hdsp->lock); | |
1818 | return change; | |
1819 | } | |
1820 | ||
1821 | #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ | |
67ed4161 | 1822 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1823 | .info = snd_hdsp_info_spdif_bits, \ |
1824 | .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } | |
1825 | ||
55e957d8 | 1826 | static int hdsp_spdif_professional(struct hdsp *hdsp) |
1da177e4 LT |
1827 | { |
1828 | return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; | |
1829 | } | |
1830 | ||
55e957d8 | 1831 | static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val) |
1da177e4 | 1832 | { |
b0b98119 | 1833 | if (val) |
1da177e4 | 1834 | hdsp->control_register |= HDSP_SPDIFProfessional; |
b0b98119 | 1835 | else |
1da177e4 | 1836 | hdsp->control_register &= ~HDSP_SPDIFProfessional; |
1da177e4 LT |
1837 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1838 | return 0; | |
1839 | } | |
1840 | ||
55e957d8 | 1841 | static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1842 | { |
55e957d8 | 1843 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1844 | |
1da177e4 LT |
1845 | ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); |
1846 | return 0; | |
1847 | } | |
1848 | ||
55e957d8 | 1849 | static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1850 | { |
55e957d8 | 1851 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1852 | int change; |
1853 | unsigned int val; | |
f9ffc5d6 | 1854 | |
1da177e4 LT |
1855 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
1856 | return -EBUSY; | |
1857 | val = ucontrol->value.integer.value[0] & 1; | |
1858 | spin_lock_irq(&hdsp->lock); | |
1859 | change = (int)val != hdsp_spdif_professional(hdsp); | |
1860 | hdsp_set_spdif_professional(hdsp, val); | |
1861 | spin_unlock_irq(&hdsp->lock); | |
1862 | return change; | |
1863 | } | |
1864 | ||
1865 | #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ | |
67ed4161 | 1866 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1867 | .info = snd_hdsp_info_spdif_bits, \ |
1868 | .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } | |
1869 | ||
55e957d8 | 1870 | static int hdsp_spdif_emphasis(struct hdsp *hdsp) |
1da177e4 LT |
1871 | { |
1872 | return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; | |
1873 | } | |
1874 | ||
55e957d8 | 1875 | static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val) |
1da177e4 | 1876 | { |
b0b98119 | 1877 | if (val) |
1da177e4 | 1878 | hdsp->control_register |= HDSP_SPDIFEmphasis; |
b0b98119 | 1879 | else |
1da177e4 | 1880 | hdsp->control_register &= ~HDSP_SPDIFEmphasis; |
1da177e4 LT |
1881 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1882 | return 0; | |
1883 | } | |
1884 | ||
55e957d8 | 1885 | static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1886 | { |
55e957d8 | 1887 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1888 | |
1da177e4 LT |
1889 | ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); |
1890 | return 0; | |
1891 | } | |
1892 | ||
55e957d8 | 1893 | static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1894 | { |
55e957d8 | 1895 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1896 | int change; |
1897 | unsigned int val; | |
f9ffc5d6 | 1898 | |
1da177e4 LT |
1899 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
1900 | return -EBUSY; | |
1901 | val = ucontrol->value.integer.value[0] & 1; | |
1902 | spin_lock_irq(&hdsp->lock); | |
1903 | change = (int)val != hdsp_spdif_emphasis(hdsp); | |
1904 | hdsp_set_spdif_emphasis(hdsp, val); | |
1905 | spin_unlock_irq(&hdsp->lock); | |
1906 | return change; | |
1907 | } | |
1908 | ||
1909 | #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ | |
67ed4161 | 1910 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1911 | .info = snd_hdsp_info_spdif_bits, \ |
1912 | .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } | |
1913 | ||
55e957d8 | 1914 | static int hdsp_spdif_nonaudio(struct hdsp *hdsp) |
1da177e4 LT |
1915 | { |
1916 | return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; | |
1917 | } | |
1918 | ||
55e957d8 | 1919 | static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val) |
1da177e4 | 1920 | { |
b0b98119 | 1921 | if (val) |
1da177e4 | 1922 | hdsp->control_register |= HDSP_SPDIFNonAudio; |
b0b98119 | 1923 | else |
1da177e4 | 1924 | hdsp->control_register &= ~HDSP_SPDIFNonAudio; |
1da177e4 LT |
1925 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1926 | return 0; | |
1927 | } | |
1928 | ||
55e957d8 | 1929 | static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1930 | { |
55e957d8 | 1931 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1932 | |
1da177e4 LT |
1933 | ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); |
1934 | return 0; | |
1935 | } | |
1936 | ||
55e957d8 | 1937 | static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1938 | { |
55e957d8 | 1939 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1940 | int change; |
1941 | unsigned int val; | |
f9ffc5d6 | 1942 | |
1da177e4 LT |
1943 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
1944 | return -EBUSY; | |
1945 | val = ucontrol->value.integer.value[0] & 1; | |
1946 | spin_lock_irq(&hdsp->lock); | |
1947 | change = (int)val != hdsp_spdif_nonaudio(hdsp); | |
1948 | hdsp_set_spdif_nonaudio(hdsp, val); | |
1949 | spin_unlock_irq(&hdsp->lock); | |
1950 | return change; | |
1951 | } | |
1952 | ||
1953 | #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 1954 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1955 | .name = xname, \ |
1956 | .index = xindex, \ | |
1957 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1958 | .info = snd_hdsp_info_spdif_sample_rate, \ | |
1959 | .get = snd_hdsp_get_spdif_sample_rate \ | |
1960 | } | |
1961 | ||
55e957d8 | 1962 | static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1963 | { |
1964 | static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; | |
55e957d8 | 1965 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1966 | |
1967 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1968 | uinfo->count = 1; | |
1969 | uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; | |
1970 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1971 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1972 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1973 | return 0; | |
1974 | } | |
1975 | ||
55e957d8 | 1976 | static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1977 | { |
55e957d8 | 1978 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 1979 | |
1da177e4 LT |
1980 | switch (hdsp_spdif_sample_rate(hdsp)) { |
1981 | case 32000: | |
1982 | ucontrol->value.enumerated.item[0] = 0; | |
1983 | break; | |
1984 | case 44100: | |
1985 | ucontrol->value.enumerated.item[0] = 1; | |
1986 | break; | |
1987 | case 48000: | |
1988 | ucontrol->value.enumerated.item[0] = 2; | |
1989 | break; | |
1990 | case 64000: | |
1991 | ucontrol->value.enumerated.item[0] = 3; | |
1992 | break; | |
1993 | case 88200: | |
1994 | ucontrol->value.enumerated.item[0] = 4; | |
1995 | break; | |
1996 | case 96000: | |
1997 | ucontrol->value.enumerated.item[0] = 5; | |
1998 | break; | |
1999 | case 128000: | |
2000 | ucontrol->value.enumerated.item[0] = 7; | |
2001 | break; | |
2002 | case 176400: | |
2003 | ucontrol->value.enumerated.item[0] = 8; | |
2004 | break; | |
2005 | case 192000: | |
2006 | ucontrol->value.enumerated.item[0] = 9; | |
2007 | break; | |
2008 | default: | |
f9ffc5d6 | 2009 | ucontrol->value.enumerated.item[0] = 6; |
1da177e4 LT |
2010 | } |
2011 | return 0; | |
2012 | } | |
2013 | ||
2014 | #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 2015 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2016 | .name = xname, \ |
2017 | .index = xindex, \ | |
2018 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2019 | .info = snd_hdsp_info_system_sample_rate, \ | |
2020 | .get = snd_hdsp_get_system_sample_rate \ | |
2021 | } | |
2022 | ||
55e957d8 | 2023 | static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2024 | { |
2025 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2026 | uinfo->count = 1; | |
2027 | return 0; | |
2028 | } | |
2029 | ||
55e957d8 | 2030 | static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2031 | { |
55e957d8 | 2032 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2033 | |
1da177e4 LT |
2034 | ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; |
2035 | return 0; | |
2036 | } | |
2037 | ||
2038 | #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 2039 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2040 | .name = xname, \ |
2041 | .index = xindex, \ | |
2042 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2043 | .info = snd_hdsp_info_autosync_sample_rate, \ | |
2044 | .get = snd_hdsp_get_autosync_sample_rate \ | |
2045 | } | |
2046 | ||
55e957d8 | 2047 | static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 2048 | { |
55e957d8 | 2049 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2050 | static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; |
1da177e4 LT |
2051 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2052 | uinfo->count = 1; | |
2053 | uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; | |
2054 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2055 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2056 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2057 | return 0; | |
2058 | } | |
2059 | ||
55e957d8 | 2060 | static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2061 | { |
55e957d8 | 2062 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2063 | |
1da177e4 LT |
2064 | switch (hdsp_external_sample_rate(hdsp)) { |
2065 | case 32000: | |
2066 | ucontrol->value.enumerated.item[0] = 0; | |
2067 | break; | |
2068 | case 44100: | |
2069 | ucontrol->value.enumerated.item[0] = 1; | |
2070 | break; | |
2071 | case 48000: | |
2072 | ucontrol->value.enumerated.item[0] = 2; | |
2073 | break; | |
2074 | case 64000: | |
2075 | ucontrol->value.enumerated.item[0] = 3; | |
2076 | break; | |
2077 | case 88200: | |
2078 | ucontrol->value.enumerated.item[0] = 4; | |
2079 | break; | |
2080 | case 96000: | |
2081 | ucontrol->value.enumerated.item[0] = 5; | |
2082 | break; | |
2083 | case 128000: | |
2084 | ucontrol->value.enumerated.item[0] = 7; | |
2085 | break; | |
2086 | case 176400: | |
2087 | ucontrol->value.enumerated.item[0] = 8; | |
2088 | break; | |
2089 | case 192000: | |
2090 | ucontrol->value.enumerated.item[0] = 9; | |
f9ffc5d6 | 2091 | break; |
1da177e4 | 2092 | default: |
f9ffc5d6 | 2093 | ucontrol->value.enumerated.item[0] = 6; |
1da177e4 LT |
2094 | } |
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ | |
67ed4161 | 2099 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2100 | .name = xname, \ |
2101 | .index = xindex, \ | |
2102 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2103 | .info = snd_hdsp_info_system_clock_mode, \ | |
2104 | .get = snd_hdsp_get_system_clock_mode \ | |
2105 | } | |
2106 | ||
55e957d8 | 2107 | static int hdsp_system_clock_mode(struct hdsp *hdsp) |
1da177e4 | 2108 | { |
b0b98119 | 2109 | if (hdsp->control_register & HDSP_ClockModeMaster) |
1da177e4 | 2110 | return 0; |
b0b98119 | 2111 | else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) |
1da177e4 | 2112 | return 0; |
1da177e4 LT |
2113 | return 1; |
2114 | } | |
2115 | ||
55e957d8 | 2116 | static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2117 | { |
2118 | static char *texts[] = {"Master", "Slave" }; | |
f9ffc5d6 | 2119 | |
1da177e4 LT |
2120 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2121 | uinfo->count = 1; | |
2122 | uinfo->value.enumerated.items = 2; | |
2123 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2124 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2125 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2126 | return 0; | |
2127 | } | |
2128 | ||
55e957d8 | 2129 | static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2130 | { |
55e957d8 | 2131 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2132 | |
1da177e4 LT |
2133 | ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); |
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | #define HDSP_CLOCK_SOURCE(xname, xindex) \ | |
67ed4161 | 2138 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2139 | .name = xname, \ |
2140 | .index = xindex, \ | |
2141 | .info = snd_hdsp_info_clock_source, \ | |
2142 | .get = snd_hdsp_get_clock_source, \ | |
2143 | .put = snd_hdsp_put_clock_source \ | |
2144 | } | |
2145 | ||
55e957d8 | 2146 | static int hdsp_clock_source(struct hdsp *hdsp) |
1da177e4 LT |
2147 | { |
2148 | if (hdsp->control_register & HDSP_ClockModeMaster) { | |
2149 | switch (hdsp->system_sample_rate) { | |
2150 | case 32000: | |
2151 | return 1; | |
2152 | case 44100: | |
2153 | return 2; | |
2154 | case 48000: | |
2155 | return 3; | |
2156 | case 64000: | |
2157 | return 4; | |
2158 | case 88200: | |
2159 | return 5; | |
2160 | case 96000: | |
2161 | return 6; | |
2162 | case 128000: | |
2163 | return 7; | |
2164 | case 176400: | |
2165 | return 8; | |
2166 | case 192000: | |
2167 | return 9; | |
2168 | default: | |
f9ffc5d6 | 2169 | return 3; |
1da177e4 LT |
2170 | } |
2171 | } else { | |
2172 | return 0; | |
2173 | } | |
2174 | } | |
2175 | ||
55e957d8 | 2176 | static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2177 | { |
2178 | int rate; | |
2179 | switch (mode) { | |
2180 | case HDSP_CLOCK_SOURCE_AUTOSYNC: | |
2181 | if (hdsp_external_sample_rate(hdsp) != 0) { | |
2182 | if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { | |
f9ffc5d6 | 2183 | hdsp->control_register &= ~HDSP_ClockModeMaster; |
1da177e4 LT |
2184 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2185 | return 0; | |
2186 | } | |
2187 | } | |
2188 | return -1; | |
2189 | case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: | |
2190 | rate = 32000; | |
2191 | break; | |
2192 | case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
2193 | rate = 44100; | |
f9ffc5d6 | 2194 | break; |
1da177e4 LT |
2195 | case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: |
2196 | rate = 48000; | |
2197 | break; | |
2198 | case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: | |
2199 | rate = 64000; | |
2200 | break; | |
2201 | case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
2202 | rate = 88200; | |
2203 | break; | |
2204 | case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: | |
2205 | rate = 96000; | |
2206 | break; | |
2207 | case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: | |
2208 | rate = 128000; | |
2209 | break; | |
2210 | case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
2211 | rate = 176400; | |
2212 | break; | |
2213 | case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: | |
2214 | rate = 192000; | |
2215 | break; | |
2216 | default: | |
2217 | rate = 48000; | |
2218 | } | |
2219 | hdsp->control_register |= HDSP_ClockModeMaster; | |
2220 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2221 | hdsp_set_rate(hdsp, rate, 1); | |
2222 | return 0; | |
2223 | } | |
2224 | ||
55e957d8 | 2225 | static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2226 | { |
2227 | static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; | |
55e957d8 | 2228 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2229 | |
1da177e4 LT |
2230 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2231 | uinfo->count = 1; | |
2232 | if (hdsp->io_type == H9632) | |
2233 | uinfo->value.enumerated.items = 10; | |
2234 | else | |
f9ffc5d6 | 2235 | uinfo->value.enumerated.items = 7; |
1da177e4 LT |
2236 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
2237 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2238 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2239 | return 0; | |
2240 | } | |
2241 | ||
55e957d8 | 2242 | static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2243 | { |
55e957d8 | 2244 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2245 | |
1da177e4 LT |
2246 | ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); |
2247 | return 0; | |
2248 | } | |
2249 | ||
55e957d8 | 2250 | static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2251 | { |
55e957d8 | 2252 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2253 | int change; |
2254 | int val; | |
f9ffc5d6 | 2255 | |
1da177e4 LT |
2256 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2257 | return -EBUSY; | |
2258 | val = ucontrol->value.enumerated.item[0]; | |
2259 | if (val < 0) val = 0; | |
2260 | if (hdsp->io_type == H9632) { | |
b0b98119 TI |
2261 | if (val > 9) |
2262 | val = 9; | |
1da177e4 | 2263 | } else { |
b0b98119 TI |
2264 | if (val > 6) |
2265 | val = 6; | |
1da177e4 LT |
2266 | } |
2267 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2268 | if (val != hdsp_clock_source(hdsp)) |
1da177e4 | 2269 | change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2270 | else |
1da177e4 | 2271 | change = 0; |
1da177e4 LT |
2272 | spin_unlock_irq(&hdsp->lock); |
2273 | return change; | |
2274 | } | |
2275 | ||
a5ce8890 | 2276 | #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info |
e3ea4d89 | 2277 | |
55e957d8 | 2278 | static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
e3ea4d89 | 2279 | { |
55e957d8 | 2280 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2281 | |
e3ea4d89 TI |
2282 | ucontrol->value.integer.value[0] = hdsp->clock_source_locked; |
2283 | return 0; | |
2284 | } | |
2285 | ||
55e957d8 | 2286 | static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
e3ea4d89 | 2287 | { |
55e957d8 | 2288 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
e3ea4d89 TI |
2289 | int change; |
2290 | ||
2291 | change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; | |
2292 | if (change) | |
4e98d6a7 | 2293 | hdsp->clock_source_locked = !!ucontrol->value.integer.value[0]; |
e3ea4d89 TI |
2294 | return change; |
2295 | } | |
2296 | ||
1da177e4 | 2297 | #define HDSP_DA_GAIN(xname, xindex) \ |
67ed4161 | 2298 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2299 | .name = xname, \ |
2300 | .index = xindex, \ | |
2301 | .info = snd_hdsp_info_da_gain, \ | |
2302 | .get = snd_hdsp_get_da_gain, \ | |
2303 | .put = snd_hdsp_put_da_gain \ | |
2304 | } | |
2305 | ||
55e957d8 | 2306 | static int hdsp_da_gain(struct hdsp *hdsp) |
1da177e4 LT |
2307 | { |
2308 | switch (hdsp->control_register & HDSP_DAGainMask) { | |
2309 | case HDSP_DAGainHighGain: | |
2310 | return 0; | |
2311 | case HDSP_DAGainPlus4dBu: | |
2312 | return 1; | |
2313 | case HDSP_DAGainMinus10dBV: | |
2314 | return 2; | |
2315 | default: | |
f9ffc5d6 | 2316 | return 1; |
1da177e4 LT |
2317 | } |
2318 | } | |
2319 | ||
55e957d8 | 2320 | static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2321 | { |
2322 | hdsp->control_register &= ~HDSP_DAGainMask; | |
2323 | switch (mode) { | |
2324 | case 0: | |
2325 | hdsp->control_register |= HDSP_DAGainHighGain; | |
2326 | break; | |
2327 | case 1: | |
2328 | hdsp->control_register |= HDSP_DAGainPlus4dBu; | |
2329 | break; | |
2330 | case 2: | |
f9ffc5d6 TB |
2331 | hdsp->control_register |= HDSP_DAGainMinus10dBV; |
2332 | break; | |
1da177e4 LT |
2333 | default: |
2334 | return -1; | |
2335 | ||
2336 | } | |
2337 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2338 | return 0; | |
2339 | } | |
2340 | ||
55e957d8 | 2341 | static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2342 | { |
2343 | static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; | |
f9ffc5d6 | 2344 | |
1da177e4 LT |
2345 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2346 | uinfo->count = 1; | |
2347 | uinfo->value.enumerated.items = 3; | |
2348 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2349 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2350 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2351 | return 0; | |
2352 | } | |
2353 | ||
55e957d8 | 2354 | static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2355 | { |
55e957d8 | 2356 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2357 | |
1da177e4 LT |
2358 | ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); |
2359 | return 0; | |
2360 | } | |
2361 | ||
55e957d8 | 2362 | static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2363 | { |
55e957d8 | 2364 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2365 | int change; |
2366 | int val; | |
f9ffc5d6 | 2367 | |
1da177e4 LT |
2368 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2369 | return -EBUSY; | |
2370 | val = ucontrol->value.enumerated.item[0]; | |
2371 | if (val < 0) val = 0; | |
2372 | if (val > 2) val = 2; | |
2373 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2374 | if (val != hdsp_da_gain(hdsp)) |
1da177e4 | 2375 | change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2376 | else |
1da177e4 | 2377 | change = 0; |
1da177e4 LT |
2378 | spin_unlock_irq(&hdsp->lock); |
2379 | return change; | |
2380 | } | |
2381 | ||
2382 | #define HDSP_AD_GAIN(xname, xindex) \ | |
67ed4161 | 2383 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2384 | .name = xname, \ |
2385 | .index = xindex, \ | |
2386 | .info = snd_hdsp_info_ad_gain, \ | |
2387 | .get = snd_hdsp_get_ad_gain, \ | |
2388 | .put = snd_hdsp_put_ad_gain \ | |
2389 | } | |
2390 | ||
55e957d8 | 2391 | static int hdsp_ad_gain(struct hdsp *hdsp) |
1da177e4 LT |
2392 | { |
2393 | switch (hdsp->control_register & HDSP_ADGainMask) { | |
2394 | case HDSP_ADGainMinus10dBV: | |
2395 | return 0; | |
2396 | case HDSP_ADGainPlus4dBu: | |
2397 | return 1; | |
2398 | case HDSP_ADGainLowGain: | |
2399 | return 2; | |
2400 | default: | |
f9ffc5d6 | 2401 | return 1; |
1da177e4 LT |
2402 | } |
2403 | } | |
2404 | ||
55e957d8 | 2405 | static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2406 | { |
2407 | hdsp->control_register &= ~HDSP_ADGainMask; | |
2408 | switch (mode) { | |
2409 | case 0: | |
2410 | hdsp->control_register |= HDSP_ADGainMinus10dBV; | |
2411 | break; | |
2412 | case 1: | |
f9ffc5d6 | 2413 | hdsp->control_register |= HDSP_ADGainPlus4dBu; |
1da177e4 LT |
2414 | break; |
2415 | case 2: | |
f9ffc5d6 TB |
2416 | hdsp->control_register |= HDSP_ADGainLowGain; |
2417 | break; | |
1da177e4 LT |
2418 | default: |
2419 | return -1; | |
2420 | ||
2421 | } | |
2422 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2423 | return 0; | |
2424 | } | |
2425 | ||
55e957d8 | 2426 | static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2427 | { |
2428 | static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; | |
f9ffc5d6 | 2429 | |
1da177e4 LT |
2430 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2431 | uinfo->count = 1; | |
2432 | uinfo->value.enumerated.items = 3; | |
2433 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2434 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2435 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2436 | return 0; | |
2437 | } | |
2438 | ||
55e957d8 | 2439 | static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2440 | { |
55e957d8 | 2441 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2442 | |
1da177e4 LT |
2443 | ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); |
2444 | return 0; | |
2445 | } | |
2446 | ||
55e957d8 | 2447 | static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2448 | { |
55e957d8 | 2449 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2450 | int change; |
2451 | int val; | |
f9ffc5d6 | 2452 | |
1da177e4 LT |
2453 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2454 | return -EBUSY; | |
2455 | val = ucontrol->value.enumerated.item[0]; | |
2456 | if (val < 0) val = 0; | |
2457 | if (val > 2) val = 2; | |
2458 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2459 | if (val != hdsp_ad_gain(hdsp)) |
1da177e4 | 2460 | change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2461 | else |
1da177e4 | 2462 | change = 0; |
1da177e4 LT |
2463 | spin_unlock_irq(&hdsp->lock); |
2464 | return change; | |
2465 | } | |
2466 | ||
2467 | #define HDSP_PHONE_GAIN(xname, xindex) \ | |
67ed4161 | 2468 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2469 | .name = xname, \ |
2470 | .index = xindex, \ | |
2471 | .info = snd_hdsp_info_phone_gain, \ | |
2472 | .get = snd_hdsp_get_phone_gain, \ | |
2473 | .put = snd_hdsp_put_phone_gain \ | |
2474 | } | |
2475 | ||
55e957d8 | 2476 | static int hdsp_phone_gain(struct hdsp *hdsp) |
1da177e4 LT |
2477 | { |
2478 | switch (hdsp->control_register & HDSP_PhoneGainMask) { | |
2479 | case HDSP_PhoneGain0dB: | |
2480 | return 0; | |
2481 | case HDSP_PhoneGainMinus6dB: | |
2482 | return 1; | |
2483 | case HDSP_PhoneGainMinus12dB: | |
2484 | return 2; | |
2485 | default: | |
f9ffc5d6 | 2486 | return 0; |
1da177e4 LT |
2487 | } |
2488 | } | |
2489 | ||
55e957d8 | 2490 | static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2491 | { |
2492 | hdsp->control_register &= ~HDSP_PhoneGainMask; | |
2493 | switch (mode) { | |
2494 | case 0: | |
2495 | hdsp->control_register |= HDSP_PhoneGain0dB; | |
2496 | break; | |
2497 | case 1: | |
f9ffc5d6 | 2498 | hdsp->control_register |= HDSP_PhoneGainMinus6dB; |
1da177e4 LT |
2499 | break; |
2500 | case 2: | |
f9ffc5d6 TB |
2501 | hdsp->control_register |= HDSP_PhoneGainMinus12dB; |
2502 | break; | |
1da177e4 LT |
2503 | default: |
2504 | return -1; | |
2505 | ||
2506 | } | |
2507 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2508 | return 0; | |
2509 | } | |
2510 | ||
55e957d8 | 2511 | static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2512 | { |
2513 | static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; | |
f9ffc5d6 | 2514 | |
1da177e4 LT |
2515 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2516 | uinfo->count = 1; | |
2517 | uinfo->value.enumerated.items = 3; | |
2518 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2519 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2520 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2521 | return 0; | |
2522 | } | |
2523 | ||
55e957d8 | 2524 | static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2525 | { |
55e957d8 | 2526 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2527 | |
1da177e4 LT |
2528 | ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); |
2529 | return 0; | |
2530 | } | |
2531 | ||
55e957d8 | 2532 | static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2533 | { |
55e957d8 | 2534 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2535 | int change; |
2536 | int val; | |
f9ffc5d6 | 2537 | |
1da177e4 LT |
2538 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2539 | return -EBUSY; | |
2540 | val = ucontrol->value.enumerated.item[0]; | |
2541 | if (val < 0) val = 0; | |
2542 | if (val > 2) val = 2; | |
2543 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2544 | if (val != hdsp_phone_gain(hdsp)) |
1da177e4 | 2545 | change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2546 | else |
1da177e4 | 2547 | change = 0; |
1da177e4 LT |
2548 | spin_unlock_irq(&hdsp->lock); |
2549 | return change; | |
2550 | } | |
2551 | ||
2552 | #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ | |
67ed4161 | 2553 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2554 | .name = xname, \ |
2555 | .index = xindex, \ | |
2556 | .info = snd_hdsp_info_xlr_breakout_cable, \ | |
2557 | .get = snd_hdsp_get_xlr_breakout_cable, \ | |
2558 | .put = snd_hdsp_put_xlr_breakout_cable \ | |
2559 | } | |
2560 | ||
55e957d8 | 2561 | static int hdsp_xlr_breakout_cable(struct hdsp *hdsp) |
1da177e4 | 2562 | { |
b0b98119 | 2563 | if (hdsp->control_register & HDSP_XLRBreakoutCable) |
1da177e4 | 2564 | return 1; |
1da177e4 LT |
2565 | return 0; |
2566 | } | |
2567 | ||
55e957d8 | 2568 | static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode) |
1da177e4 | 2569 | { |
b0b98119 | 2570 | if (mode) |
1da177e4 | 2571 | hdsp->control_register |= HDSP_XLRBreakoutCable; |
b0b98119 | 2572 | else |
1da177e4 | 2573 | hdsp->control_register &= ~HDSP_XLRBreakoutCable; |
1da177e4 LT |
2574 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2575 | return 0; | |
2576 | } | |
2577 | ||
a5ce8890 | 2578 | #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info |
1da177e4 | 2579 | |
55e957d8 | 2580 | static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2581 | { |
55e957d8 | 2582 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2583 | |
1da177e4 LT |
2584 | ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); |
2585 | return 0; | |
2586 | } | |
2587 | ||
55e957d8 | 2588 | static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2589 | { |
55e957d8 | 2590 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2591 | int change; |
2592 | int val; | |
f9ffc5d6 | 2593 | |
1da177e4 LT |
2594 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2595 | return -EBUSY; | |
2596 | val = ucontrol->value.integer.value[0] & 1; | |
2597 | spin_lock_irq(&hdsp->lock); | |
2598 | change = (int)val != hdsp_xlr_breakout_cable(hdsp); | |
2599 | hdsp_set_xlr_breakout_cable(hdsp, val); | |
2600 | spin_unlock_irq(&hdsp->lock); | |
2601 | return change; | |
2602 | } | |
2603 | ||
2604 | /* (De)activates old RME Analog Extension Board | |
2605 | These are connected to the internal ADAT connector | |
2606 | Switching this on desactivates external ADAT | |
2607 | */ | |
2608 | #define HDSP_AEB(xname, xindex) \ | |
67ed4161 | 2609 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2610 | .name = xname, \ |
2611 | .index = xindex, \ | |
2612 | .info = snd_hdsp_info_aeb, \ | |
2613 | .get = snd_hdsp_get_aeb, \ | |
2614 | .put = snd_hdsp_put_aeb \ | |
2615 | } | |
2616 | ||
55e957d8 | 2617 | static int hdsp_aeb(struct hdsp *hdsp) |
1da177e4 | 2618 | { |
b0b98119 | 2619 | if (hdsp->control_register & HDSP_AnalogExtensionBoard) |
1da177e4 | 2620 | return 1; |
1da177e4 LT |
2621 | return 0; |
2622 | } | |
2623 | ||
55e957d8 | 2624 | static int hdsp_set_aeb(struct hdsp *hdsp, int mode) |
1da177e4 | 2625 | { |
b0b98119 | 2626 | if (mode) |
1da177e4 | 2627 | hdsp->control_register |= HDSP_AnalogExtensionBoard; |
b0b98119 | 2628 | else |
1da177e4 | 2629 | hdsp->control_register &= ~HDSP_AnalogExtensionBoard; |
1da177e4 LT |
2630 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2631 | return 0; | |
2632 | } | |
2633 | ||
a5ce8890 | 2634 | #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info |
1da177e4 | 2635 | |
55e957d8 | 2636 | static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2637 | { |
55e957d8 | 2638 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2639 | |
1da177e4 LT |
2640 | ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); |
2641 | return 0; | |
2642 | } | |
2643 | ||
55e957d8 | 2644 | static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2645 | { |
55e957d8 | 2646 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2647 | int change; |
2648 | int val; | |
f9ffc5d6 | 2649 | |
1da177e4 LT |
2650 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2651 | return -EBUSY; | |
2652 | val = ucontrol->value.integer.value[0] & 1; | |
2653 | spin_lock_irq(&hdsp->lock); | |
2654 | change = (int)val != hdsp_aeb(hdsp); | |
2655 | hdsp_set_aeb(hdsp, val); | |
2656 | spin_unlock_irq(&hdsp->lock); | |
2657 | return change; | |
2658 | } | |
2659 | ||
2660 | #define HDSP_PREF_SYNC_REF(xname, xindex) \ | |
67ed4161 | 2661 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2662 | .name = xname, \ |
2663 | .index = xindex, \ | |
2664 | .info = snd_hdsp_info_pref_sync_ref, \ | |
2665 | .get = snd_hdsp_get_pref_sync_ref, \ | |
2666 | .put = snd_hdsp_put_pref_sync_ref \ | |
2667 | } | |
2668 | ||
55e957d8 | 2669 | static int hdsp_pref_sync_ref(struct hdsp *hdsp) |
1da177e4 LT |
2670 | { |
2671 | /* Notice that this looks at the requested sync source, | |
2672 | not the one actually in use. | |
2673 | */ | |
2674 | ||
2675 | switch (hdsp->control_register & HDSP_SyncRefMask) { | |
2676 | case HDSP_SyncRef_ADAT1: | |
2677 | return HDSP_SYNC_FROM_ADAT1; | |
2678 | case HDSP_SyncRef_ADAT2: | |
2679 | return HDSP_SYNC_FROM_ADAT2; | |
2680 | case HDSP_SyncRef_ADAT3: | |
2681 | return HDSP_SYNC_FROM_ADAT3; | |
2682 | case HDSP_SyncRef_SPDIF: | |
2683 | return HDSP_SYNC_FROM_SPDIF; | |
2684 | case HDSP_SyncRef_WORD: | |
2685 | return HDSP_SYNC_FROM_WORD; | |
2686 | case HDSP_SyncRef_ADAT_SYNC: | |
2687 | return HDSP_SYNC_FROM_ADAT_SYNC; | |
2688 | default: | |
2689 | return HDSP_SYNC_FROM_WORD; | |
2690 | } | |
2691 | return 0; | |
2692 | } | |
2693 | ||
55e957d8 | 2694 | static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) |
1da177e4 LT |
2695 | { |
2696 | hdsp->control_register &= ~HDSP_SyncRefMask; | |
2697 | switch (pref) { | |
2698 | case HDSP_SYNC_FROM_ADAT1: | |
2699 | hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ | |
2700 | break; | |
2701 | case HDSP_SYNC_FROM_ADAT2: | |
2702 | hdsp->control_register |= HDSP_SyncRef_ADAT2; | |
2703 | break; | |
2704 | case HDSP_SYNC_FROM_ADAT3: | |
2705 | hdsp->control_register |= HDSP_SyncRef_ADAT3; | |
2706 | break; | |
2707 | case HDSP_SYNC_FROM_SPDIF: | |
2708 | hdsp->control_register |= HDSP_SyncRef_SPDIF; | |
2709 | break; | |
2710 | case HDSP_SYNC_FROM_WORD: | |
2711 | hdsp->control_register |= HDSP_SyncRef_WORD; | |
2712 | break; | |
2713 | case HDSP_SYNC_FROM_ADAT_SYNC: | |
2714 | hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; | |
2715 | break; | |
2716 | default: | |
2717 | return -1; | |
2718 | } | |
2719 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2720 | return 0; | |
2721 | } | |
2722 | ||
55e957d8 | 2723 | static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2724 | { |
2725 | static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; | |
55e957d8 | 2726 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2727 | |
1da177e4 LT |
2728 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2729 | uinfo->count = 1; | |
2730 | ||
2731 | switch (hdsp->io_type) { | |
2732 | case Digiface: | |
2733 | case H9652: | |
2734 | uinfo->value.enumerated.items = 6; | |
2735 | break; | |
2736 | case Multiface: | |
2737 | uinfo->value.enumerated.items = 4; | |
2738 | break; | |
2739 | case H9632: | |
2740 | uinfo->value.enumerated.items = 3; | |
2741 | break; | |
2742 | default: | |
9badda0a | 2743 | return -EINVAL; |
1da177e4 | 2744 | } |
f9ffc5d6 | 2745 | |
1da177e4 LT |
2746 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
2747 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2748 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2749 | return 0; | |
2750 | } | |
2751 | ||
55e957d8 | 2752 | static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2753 | { |
55e957d8 | 2754 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2755 | |
1da177e4 LT |
2756 | ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); |
2757 | return 0; | |
2758 | } | |
2759 | ||
55e957d8 | 2760 | static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2761 | { |
55e957d8 | 2762 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2763 | int change, max; |
2764 | unsigned int val; | |
f9ffc5d6 | 2765 | |
1da177e4 LT |
2766 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2767 | return -EBUSY; | |
2768 | ||
2769 | switch (hdsp->io_type) { | |
2770 | case Digiface: | |
2771 | case H9652: | |
2772 | max = 6; | |
2773 | break; | |
2774 | case Multiface: | |
2775 | max = 4; | |
2776 | break; | |
2777 | case H9632: | |
2778 | max = 3; | |
2779 | break; | |
2780 | default: | |
2781 | return -EIO; | |
2782 | } | |
2783 | ||
2784 | val = ucontrol->value.enumerated.item[0] % max; | |
2785 | spin_lock_irq(&hdsp->lock); | |
2786 | change = (int)val != hdsp_pref_sync_ref(hdsp); | |
2787 | hdsp_set_pref_sync_ref(hdsp, val); | |
2788 | spin_unlock_irq(&hdsp->lock); | |
2789 | return change; | |
2790 | } | |
2791 | ||
2792 | #define HDSP_AUTOSYNC_REF(xname, xindex) \ | |
67ed4161 | 2793 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2794 | .name = xname, \ |
2795 | .index = xindex, \ | |
2796 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2797 | .info = snd_hdsp_info_autosync_ref, \ | |
2798 | .get = snd_hdsp_get_autosync_ref, \ | |
2799 | } | |
2800 | ||
55e957d8 | 2801 | static int hdsp_autosync_ref(struct hdsp *hdsp) |
1da177e4 LT |
2802 | { |
2803 | /* This looks at the autosync selected sync reference */ | |
2804 | unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
2805 | ||
2806 | switch (status2 & HDSP_SelSyncRefMask) { | |
2807 | case HDSP_SelSyncRef_WORD: | |
2808 | return HDSP_AUTOSYNC_FROM_WORD; | |
2809 | case HDSP_SelSyncRef_ADAT_SYNC: | |
2810 | return HDSP_AUTOSYNC_FROM_ADAT_SYNC; | |
2811 | case HDSP_SelSyncRef_SPDIF: | |
2812 | return HDSP_AUTOSYNC_FROM_SPDIF; | |
2813 | case HDSP_SelSyncRefMask: | |
f9ffc5d6 | 2814 | return HDSP_AUTOSYNC_FROM_NONE; |
1da177e4 LT |
2815 | case HDSP_SelSyncRef_ADAT1: |
2816 | return HDSP_AUTOSYNC_FROM_ADAT1; | |
2817 | case HDSP_SelSyncRef_ADAT2: | |
2818 | return HDSP_AUTOSYNC_FROM_ADAT2; | |
2819 | case HDSP_SelSyncRef_ADAT3: | |
2820 | return HDSP_AUTOSYNC_FROM_ADAT3; | |
2821 | default: | |
2822 | return HDSP_AUTOSYNC_FROM_WORD; | |
2823 | } | |
2824 | return 0; | |
2825 | } | |
2826 | ||
55e957d8 | 2827 | static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2828 | { |
2829 | static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; | |
f9ffc5d6 | 2830 | |
1da177e4 LT |
2831 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2832 | uinfo->count = 1; | |
2833 | uinfo->value.enumerated.items = 7; | |
2834 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2835 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2836 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2837 | return 0; | |
2838 | } | |
2839 | ||
55e957d8 | 2840 | static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2841 | { |
55e957d8 | 2842 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2843 | |
1da177e4 LT |
2844 | ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); |
2845 | return 0; | |
2846 | } | |
2847 | ||
2848 | #define HDSP_LINE_OUT(xname, xindex) \ | |
67ed4161 | 2849 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2850 | .name = xname, \ |
2851 | .index = xindex, \ | |
2852 | .info = snd_hdsp_info_line_out, \ | |
2853 | .get = snd_hdsp_get_line_out, \ | |
2854 | .put = snd_hdsp_put_line_out \ | |
2855 | } | |
2856 | ||
55e957d8 | 2857 | static int hdsp_line_out(struct hdsp *hdsp) |
1da177e4 LT |
2858 | { |
2859 | return (hdsp->control_register & HDSP_LineOut) ? 1 : 0; | |
2860 | } | |
2861 | ||
55e957d8 | 2862 | static int hdsp_set_line_output(struct hdsp *hdsp, int out) |
1da177e4 | 2863 | { |
b0b98119 | 2864 | if (out) |
1da177e4 | 2865 | hdsp->control_register |= HDSP_LineOut; |
b0b98119 | 2866 | else |
1da177e4 | 2867 | hdsp->control_register &= ~HDSP_LineOut; |
1da177e4 LT |
2868 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2869 | return 0; | |
2870 | } | |
2871 | ||
a5ce8890 | 2872 | #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info |
1da177e4 | 2873 | |
55e957d8 | 2874 | static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2875 | { |
55e957d8 | 2876 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2877 | |
1da177e4 LT |
2878 | spin_lock_irq(&hdsp->lock); |
2879 | ucontrol->value.integer.value[0] = hdsp_line_out(hdsp); | |
2880 | spin_unlock_irq(&hdsp->lock); | |
2881 | return 0; | |
2882 | } | |
2883 | ||
55e957d8 | 2884 | static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2885 | { |
55e957d8 | 2886 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2887 | int change; |
2888 | unsigned int val; | |
f9ffc5d6 | 2889 | |
1da177e4 LT |
2890 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2891 | return -EBUSY; | |
2892 | val = ucontrol->value.integer.value[0] & 1; | |
2893 | spin_lock_irq(&hdsp->lock); | |
2894 | change = (int)val != hdsp_line_out(hdsp); | |
2895 | hdsp_set_line_output(hdsp, val); | |
2896 | spin_unlock_irq(&hdsp->lock); | |
2897 | return change; | |
2898 | } | |
2899 | ||
2900 | #define HDSP_PRECISE_POINTER(xname, xindex) \ | |
67ed4161 | 2901 | { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ |
1da177e4 LT |
2902 | .name = xname, \ |
2903 | .index = xindex, \ | |
2904 | .info = snd_hdsp_info_precise_pointer, \ | |
2905 | .get = snd_hdsp_get_precise_pointer, \ | |
2906 | .put = snd_hdsp_put_precise_pointer \ | |
2907 | } | |
2908 | ||
55e957d8 | 2909 | static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) |
1da177e4 | 2910 | { |
b0b98119 | 2911 | if (precise) |
1da177e4 | 2912 | hdsp->precise_ptr = 1; |
b0b98119 | 2913 | else |
1da177e4 | 2914 | hdsp->precise_ptr = 0; |
1da177e4 LT |
2915 | return 0; |
2916 | } | |
2917 | ||
a5ce8890 | 2918 | #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info |
1da177e4 | 2919 | |
55e957d8 | 2920 | static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2921 | { |
55e957d8 | 2922 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2923 | |
1da177e4 LT |
2924 | spin_lock_irq(&hdsp->lock); |
2925 | ucontrol->value.integer.value[0] = hdsp->precise_ptr; | |
2926 | spin_unlock_irq(&hdsp->lock); | |
2927 | return 0; | |
2928 | } | |
2929 | ||
55e957d8 | 2930 | static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2931 | { |
55e957d8 | 2932 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2933 | int change; |
2934 | unsigned int val; | |
f9ffc5d6 | 2935 | |
1da177e4 LT |
2936 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2937 | return -EBUSY; | |
2938 | val = ucontrol->value.integer.value[0] & 1; | |
2939 | spin_lock_irq(&hdsp->lock); | |
2940 | change = (int)val != hdsp->precise_ptr; | |
2941 | hdsp_set_precise_pointer(hdsp, val); | |
2942 | spin_unlock_irq(&hdsp->lock); | |
2943 | return change; | |
2944 | } | |
2945 | ||
2946 | #define HDSP_USE_MIDI_TASKLET(xname, xindex) \ | |
67ed4161 | 2947 | { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ |
1da177e4 LT |
2948 | .name = xname, \ |
2949 | .index = xindex, \ | |
2950 | .info = snd_hdsp_info_use_midi_tasklet, \ | |
2951 | .get = snd_hdsp_get_use_midi_tasklet, \ | |
2952 | .put = snd_hdsp_put_use_midi_tasklet \ | |
2953 | } | |
2954 | ||
55e957d8 | 2955 | static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet) |
1da177e4 | 2956 | { |
b0b98119 | 2957 | if (use_tasklet) |
1da177e4 | 2958 | hdsp->use_midi_tasklet = 1; |
b0b98119 | 2959 | else |
1da177e4 | 2960 | hdsp->use_midi_tasklet = 0; |
1da177e4 LT |
2961 | return 0; |
2962 | } | |
2963 | ||
a5ce8890 | 2964 | #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info |
1da177e4 | 2965 | |
55e957d8 | 2966 | static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2967 | { |
55e957d8 | 2968 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
f9ffc5d6 | 2969 | |
1da177e4 LT |
2970 | spin_lock_irq(&hdsp->lock); |
2971 | ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet; | |
2972 | spin_unlock_irq(&hdsp->lock); | |
2973 | return 0; | |
2974 | } | |
2975 | ||
55e957d8 | 2976 | static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2977 | { |
55e957d8 | 2978 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2979 | int change; |
2980 | unsigned int val; | |
f9ffc5d6 | 2981 | |
1da177e4 LT |
2982 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
2983 | return -EBUSY; | |
2984 | val = ucontrol->value.integer.value[0] & 1; | |
2985 | spin_lock_irq(&hdsp->lock); | |
2986 | change = (int)val != hdsp->use_midi_tasklet; | |
2987 | hdsp_set_use_midi_tasklet(hdsp, val); | |
2988 | spin_unlock_irq(&hdsp->lock); | |
2989 | return change; | |
2990 | } | |
2991 | ||
2992 | #define HDSP_MIXER(xname, xindex) \ | |
2993 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2994 | .name = xname, \ | |
2995 | .index = xindex, \ | |
67ed4161 | 2996 | .device = 0, \ |
1da177e4 LT |
2997 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ |
2998 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2999 | .info = snd_hdsp_info_mixer, \ | |
3000 | .get = snd_hdsp_get_mixer, \ | |
3001 | .put = snd_hdsp_put_mixer \ | |
3002 | } | |
3003 | ||
55e957d8 | 3004 | static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
3005 | { |
3006 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3007 | uinfo->count = 3; | |
3008 | uinfo->value.integer.min = 0; | |
3009 | uinfo->value.integer.max = 65536; | |
3010 | uinfo->value.integer.step = 1; | |
3011 | return 0; | |
3012 | } | |
3013 | ||
55e957d8 | 3014 | static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 3015 | { |
55e957d8 | 3016 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3017 | int source; |
3018 | int destination; | |
3019 | int addr; | |
3020 | ||
3021 | source = ucontrol->value.integer.value[0]; | |
3022 | destination = ucontrol->value.integer.value[1]; | |
f9ffc5d6 | 3023 | |
b0b98119 | 3024 | if (source >= hdsp->max_channels) |
1da177e4 | 3025 | addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); |
b0b98119 | 3026 | else |
1da177e4 | 3027 | addr = hdsp_input_to_output_key(hdsp,source, destination); |
f9ffc5d6 | 3028 | |
1da177e4 LT |
3029 | spin_lock_irq(&hdsp->lock); |
3030 | ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); | |
3031 | spin_unlock_irq(&hdsp->lock); | |
3032 | return 0; | |
3033 | } | |
3034 | ||
55e957d8 | 3035 | static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 3036 | { |
55e957d8 | 3037 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3038 | int change; |
3039 | int source; | |
3040 | int destination; | |
3041 | int gain; | |
3042 | int addr; | |
3043 | ||
3044 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
3045 | return -EBUSY; | |
3046 | ||
3047 | source = ucontrol->value.integer.value[0]; | |
3048 | destination = ucontrol->value.integer.value[1]; | |
3049 | ||
b0b98119 | 3050 | if (source >= hdsp->max_channels) |
1da177e4 | 3051 | addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); |
b0b98119 | 3052 | else |
1da177e4 | 3053 | addr = hdsp_input_to_output_key(hdsp,source, destination); |
1da177e4 LT |
3054 | |
3055 | gain = ucontrol->value.integer.value[2]; | |
3056 | ||
3057 | spin_lock_irq(&hdsp->lock); | |
3058 | change = gain != hdsp_read_gain(hdsp, addr); | |
3059 | if (change) | |
3060 | hdsp_write_gain(hdsp, addr, gain); | |
3061 | spin_unlock_irq(&hdsp->lock); | |
3062 | return change; | |
3063 | } | |
3064 | ||
3065 | #define HDSP_WC_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 3066 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
3067 | .name = xname, \ |
3068 | .index = xindex, \ | |
3069 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3070 | .info = snd_hdsp_info_sync_check, \ | |
3071 | .get = snd_hdsp_get_wc_sync_check \ | |
3072 | } | |
3073 | ||
55e957d8 | 3074 | static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 3075 | { |
f9ffc5d6 | 3076 | static char *texts[] = {"No Lock", "Lock", "Sync" }; |
1da177e4 LT |
3077 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
3078 | uinfo->count = 1; | |
3079 | uinfo->value.enumerated.items = 3; | |
3080 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3081 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
3082 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
3083 | return 0; | |
3084 | } | |
3085 | ||
55e957d8 | 3086 | static int hdsp_wc_sync_check(struct hdsp *hdsp) |
1da177e4 LT |
3087 | { |
3088 | int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
3089 | if (status2 & HDSP_wc_lock) { | |
b0b98119 | 3090 | if (status2 & HDSP_wc_sync) |
1da177e4 | 3091 | return 2; |
b0b98119 | 3092 | else |
1da177e4 | 3093 | return 1; |
b0b98119 | 3094 | } else |
1da177e4 | 3095 | return 0; |
1da177e4 LT |
3096 | return 0; |
3097 | } | |
3098 | ||
55e957d8 | 3099 | static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 3100 | { |
55e957d8 | 3101 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3102 | |
3103 | ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); | |
3104 | return 0; | |
3105 | } | |
3106 | ||
3107 | #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 3108 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
3109 | .name = xname, \ |
3110 | .index = xindex, \ | |
3111 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3112 | .info = snd_hdsp_info_sync_check, \ | |
3113 | .get = snd_hdsp_get_spdif_sync_check \ | |
3114 | } | |
3115 | ||
55e957d8 | 3116 | static int hdsp_spdif_sync_check(struct hdsp *hdsp) |
1da177e4 LT |
3117 | { |
3118 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
b0b98119 | 3119 | if (status & HDSP_SPDIFErrorFlag) |
1da177e4 | 3120 | return 0; |
f9ffc5d6 | 3121 | else { |
b0b98119 | 3122 | if (status & HDSP_SPDIFSync) |
1da177e4 | 3123 | return 2; |
b0b98119 | 3124 | else |
1da177e4 | 3125 | return 1; |
1da177e4 LT |
3126 | } |
3127 | return 0; | |
3128 | } | |
3129 | ||
55e957d8 | 3130 | static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 3131 | { |
55e957d8 | 3132 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3133 | |
3134 | ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); | |
3135 | return 0; | |
3136 | } | |
3137 | ||
3138 | #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 3139 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
3140 | .name = xname, \ |
3141 | .index = xindex, \ | |
3142 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3143 | .info = snd_hdsp_info_sync_check, \ | |
3144 | .get = snd_hdsp_get_adatsync_sync_check \ | |
3145 | } | |
3146 | ||
55e957d8 | 3147 | static int hdsp_adatsync_sync_check(struct hdsp *hdsp) |
1da177e4 LT |
3148 | { |
3149 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
3150 | if (status & HDSP_TimecodeLock) { | |
b0b98119 | 3151 | if (status & HDSP_TimecodeSync) |
1da177e4 | 3152 | return 2; |
b0b98119 | 3153 | else |
1da177e4 | 3154 | return 1; |
b0b98119 | 3155 | } else |
1da177e4 | 3156 | return 0; |
f9ffc5d6 | 3157 | } |
1da177e4 | 3158 | |
55e957d8 | 3159 | static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 3160 | { |
55e957d8 | 3161 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3162 | |
3163 | ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); | |
3164 | return 0; | |
3165 | } | |
3166 | ||
3167 | #define HDSP_ADAT_SYNC_CHECK \ | |
67ed4161 | 3168 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
3169 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ |
3170 | .info = snd_hdsp_info_sync_check, \ | |
3171 | .get = snd_hdsp_get_adat_sync_check \ | |
3172 | } | |
3173 | ||
55e957d8 | 3174 | static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) |
f9ffc5d6 | 3175 | { |
1da177e4 | 3176 | int status = hdsp_read(hdsp, HDSP_statusRegister); |
f9ffc5d6 | 3177 | |
1da177e4 | 3178 | if (status & (HDSP_Lock0>>idx)) { |
b0b98119 | 3179 | if (status & (HDSP_Sync0>>idx)) |
1da177e4 | 3180 | return 2; |
b0b98119 | 3181 | else |
f9ffc5d6 | 3182 | return 1; |
b0b98119 | 3183 | } else |
1da177e4 | 3184 | return 0; |
f9ffc5d6 | 3185 | } |
1da177e4 | 3186 | |
55e957d8 | 3187 | static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 LT |
3188 | { |
3189 | int offset; | |
55e957d8 | 3190 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3191 | |
3192 | offset = ucontrol->id.index - 1; | |
da3cec35 | 3193 | snd_BUG_ON(offset < 0); |
1da177e4 LT |
3194 | |
3195 | switch (hdsp->io_type) { | |
3196 | case Digiface: | |
3197 | case H9652: | |
3198 | if (offset >= 3) | |
3199 | return -EINVAL; | |
3200 | break; | |
3201 | case Multiface: | |
3202 | case H9632: | |
f9ffc5d6 | 3203 | if (offset >= 1) |
1da177e4 LT |
3204 | return -EINVAL; |
3205 | break; | |
3206 | default: | |
3207 | return -EIO; | |
3208 | } | |
3209 | ||
3210 | ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); | |
3211 | return 0; | |
3212 | } | |
3213 | ||
e4b6088c JC |
3214 | #define HDSP_DDS_OFFSET(xname, xindex) \ |
3215 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3216 | .name = xname, \ | |
3217 | .index = xindex, \ | |
3218 | .info = snd_hdsp_info_dds_offset, \ | |
3219 | .get = snd_hdsp_get_dds_offset, \ | |
3220 | .put = snd_hdsp_put_dds_offset \ | |
3221 | } | |
3222 | ||
3223 | static int hdsp_dds_offset(struct hdsp *hdsp) | |
3224 | { | |
3225 | u64 n; | |
e4b6088c JC |
3226 | unsigned int dds_value = hdsp->dds_value; |
3227 | int system_sample_rate = hdsp->system_sample_rate; | |
3228 | ||
2a3988f6 TI |
3229 | if (!dds_value) |
3230 | return 0; | |
3231 | ||
e4b6088c JC |
3232 | n = DDS_NUMERATOR; |
3233 | /* | |
3234 | * dds_value = n / rate | |
3235 | * rate = n / dds_value | |
3236 | */ | |
3f7440a6 | 3237 | n = div_u64(n, dds_value); |
e4b6088c JC |
3238 | if (system_sample_rate >= 112000) |
3239 | n *= 4; | |
3240 | else if (system_sample_rate >= 56000) | |
3241 | n *= 2; | |
3242 | return ((int)n) - system_sample_rate; | |
3243 | } | |
3244 | ||
3245 | static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) | |
3246 | { | |
3247 | int rate = hdsp->system_sample_rate + offset_hz; | |
3248 | hdsp_set_dds_value(hdsp, rate); | |
3249 | return 0; | |
3250 | } | |
3251 | ||
3252 | static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) | |
3253 | { | |
3254 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3255 | uinfo->count = 1; | |
3256 | uinfo->value.integer.min = -5000; | |
3257 | uinfo->value.integer.max = 5000; | |
3258 | return 0; | |
3259 | } | |
3260 | ||
3261 | static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3262 | { | |
3263 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
f9ffc5d6 | 3264 | |
e4b6088c JC |
3265 | ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp); |
3266 | return 0; | |
3267 | } | |
3268 | ||
3269 | static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3270 | { | |
3271 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3272 | int change; | |
3273 | int val; | |
f9ffc5d6 | 3274 | |
e4b6088c JC |
3275 | if (!snd_hdsp_use_is_exclusive(hdsp)) |
3276 | return -EBUSY; | |
3277 | val = ucontrol->value.enumerated.item[0]; | |
3278 | spin_lock_irq(&hdsp->lock); | |
3279 | if (val != hdsp_dds_offset(hdsp)) | |
3280 | change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; | |
3281 | else | |
3282 | change = 0; | |
3283 | spin_unlock_irq(&hdsp->lock); | |
3284 | return change; | |
3285 | } | |
3286 | ||
55e957d8 | 3287 | static struct snd_kcontrol_new snd_hdsp_9632_controls[] = { |
1da177e4 LT |
3288 | HDSP_DA_GAIN("DA Gain", 0), |
3289 | HDSP_AD_GAIN("AD Gain", 0), | |
3290 | HDSP_PHONE_GAIN("Phones Gain", 0), | |
e4b6088c JC |
3291 | HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0), |
3292 | HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) | |
1da177e4 LT |
3293 | }; |
3294 | ||
55e957d8 | 3295 | static struct snd_kcontrol_new snd_hdsp_controls[] = { |
1da177e4 | 3296 | { |
5549d549 | 3297 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3298 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), |
3299 | .info = snd_hdsp_control_spdif_info, | |
3300 | .get = snd_hdsp_control_spdif_get, | |
3301 | .put = snd_hdsp_control_spdif_put, | |
3302 | }, | |
3303 | { | |
3304 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
5549d549 | 3305 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3306 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), |
3307 | .info = snd_hdsp_control_spdif_stream_info, | |
3308 | .get = snd_hdsp_control_spdif_stream_get, | |
3309 | .put = snd_hdsp_control_spdif_stream_put, | |
3310 | }, | |
3311 | { | |
3312 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
5549d549 | 3313 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3314 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), |
3315 | .info = snd_hdsp_control_spdif_mask_info, | |
3316 | .get = snd_hdsp_control_spdif_mask_get, | |
3317 | .private_value = IEC958_AES0_NONAUDIO | | |
3318 | IEC958_AES0_PROFESSIONAL | | |
f9ffc5d6 | 3319 | IEC958_AES0_CON_EMPHASIS, |
1da177e4 LT |
3320 | }, |
3321 | { | |
3322 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
5549d549 | 3323 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3324 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), |
3325 | .info = snd_hdsp_control_spdif_mask_info, | |
3326 | .get = snd_hdsp_control_spdif_mask_get, | |
3327 | .private_value = IEC958_AES0_NONAUDIO | | |
3328 | IEC958_AES0_PROFESSIONAL | | |
3329 | IEC958_AES0_PRO_EMPHASIS, | |
3330 | }, | |
3331 | HDSP_MIXER("Mixer", 0), | |
3332 | HDSP_SPDIF_IN("IEC958 Input Connector", 0), | |
3333 | HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), | |
3334 | HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), | |
3335 | HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), | |
3336 | HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), | |
f9ffc5d6 | 3337 | /* 'Sample Clock Source' complies with the alsa control naming scheme */ |
1da177e4 | 3338 | HDSP_CLOCK_SOURCE("Sample Clock Source", 0), |
e3ea4d89 | 3339 | { |
e3ea4d89 TI |
3340 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
3341 | .name = "Sample Clock Source Locking", | |
3342 | .info = snd_hdsp_info_clock_source_lock, | |
3343 | .get = snd_hdsp_get_clock_source_lock, | |
3344 | .put = snd_hdsp_put_clock_source_lock, | |
3345 | }, | |
1da177e4 LT |
3346 | HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), |
3347 | HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
3348 | HDSP_AUTOSYNC_REF("AutoSync Reference", 0), | |
3349 | HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), | |
3350 | HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
3351 | /* 'External Rate' complies with the alsa control naming scheme */ | |
3352 | HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
3353 | HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), | |
3354 | HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), | |
3355 | HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), | |
3356 | HDSP_LINE_OUT("Line Out", 0), | |
3357 | HDSP_PRECISE_POINTER("Precise Pointer", 0), | |
3358 | HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0), | |
3359 | }; | |
3360 | ||
28b26e15 FF |
3361 | |
3362 | static int hdsp_rpm_input12(struct hdsp *hdsp) | |
3363 | { | |
3364 | switch (hdsp->control_register & HDSP_RPM_Inp12) { | |
3365 | case HDSP_RPM_Inp12_Phon_6dB: | |
3366 | return 0; | |
3367 | case HDSP_RPM_Inp12_Phon_n6dB: | |
3368 | return 2; | |
3369 | case HDSP_RPM_Inp12_Line_0dB: | |
3370 | return 3; | |
3371 | case HDSP_RPM_Inp12_Line_n6dB: | |
3372 | return 4; | |
3373 | } | |
3374 | return 1; | |
3375 | } | |
3376 | ||
3377 | ||
3378 | static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3379 | { | |
3380 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3381 | ||
3382 | ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp); | |
3383 | return 0; | |
3384 | } | |
3385 | ||
3386 | ||
3387 | static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode) | |
3388 | { | |
3389 | hdsp->control_register &= ~HDSP_RPM_Inp12; | |
3390 | switch (mode) { | |
3391 | case 0: | |
3392 | hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB; | |
3393 | break; | |
3394 | case 1: | |
3395 | break; | |
3396 | case 2: | |
3397 | hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB; | |
3398 | break; | |
3399 | case 3: | |
3400 | hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB; | |
3401 | break; | |
3402 | case 4: | |
3403 | hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB; | |
3404 | break; | |
3405 | default: | |
3406 | return -1; | |
3407 | } | |
3408 | ||
3409 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3410 | return 0; | |
3411 | } | |
3412 | ||
3413 | ||
3414 | static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3415 | { | |
3416 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3417 | int change; | |
3418 | int val; | |
3419 | ||
3420 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
3421 | return -EBUSY; | |
3422 | val = ucontrol->value.enumerated.item[0]; | |
3423 | if (val < 0) | |
3424 | val = 0; | |
3425 | if (val > 4) | |
3426 | val = 4; | |
3427 | spin_lock_irq(&hdsp->lock); | |
3428 | if (val != hdsp_rpm_input12(hdsp)) | |
3429 | change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0; | |
3430 | else | |
3431 | change = 0; | |
3432 | spin_unlock_irq(&hdsp->lock); | |
3433 | return change; | |
3434 | } | |
3435 | ||
3436 | ||
3437 | static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) | |
3438 | { | |
3439 | static char *texts[] = {"Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"}; | |
3440 | ||
3441 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3442 | uinfo->count = 1; | |
3443 | uinfo->value.enumerated.items = 5; | |
3444 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3445 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
3446 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
3447 | return 0; | |
3448 | } | |
3449 | ||
3450 | ||
3451 | static int hdsp_rpm_input34(struct hdsp *hdsp) | |
3452 | { | |
3453 | switch (hdsp->control_register & HDSP_RPM_Inp34) { | |
3454 | case HDSP_RPM_Inp34_Phon_6dB: | |
3455 | return 0; | |
3456 | case HDSP_RPM_Inp34_Phon_n6dB: | |
3457 | return 2; | |
3458 | case HDSP_RPM_Inp34_Line_0dB: | |
3459 | return 3; | |
3460 | case HDSP_RPM_Inp34_Line_n6dB: | |
3461 | return 4; | |
3462 | } | |
3463 | return 1; | |
3464 | } | |
3465 | ||
3466 | ||
3467 | static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3468 | { | |
3469 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3470 | ||
3471 | ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp); | |
3472 | return 0; | |
3473 | } | |
3474 | ||
3475 | ||
3476 | static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode) | |
3477 | { | |
3478 | hdsp->control_register &= ~HDSP_RPM_Inp34; | |
3479 | switch (mode) { | |
3480 | case 0: | |
3481 | hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB; | |
3482 | break; | |
3483 | case 1: | |
3484 | break; | |
3485 | case 2: | |
3486 | hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB; | |
3487 | break; | |
3488 | case 3: | |
3489 | hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB; | |
3490 | break; | |
3491 | case 4: | |
3492 | hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB; | |
3493 | break; | |
3494 | default: | |
3495 | return -1; | |
3496 | } | |
3497 | ||
3498 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3499 | return 0; | |
3500 | } | |
3501 | ||
3502 | ||
3503 | static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3504 | { | |
3505 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3506 | int change; | |
3507 | int val; | |
3508 | ||
3509 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
3510 | return -EBUSY; | |
3511 | val = ucontrol->value.enumerated.item[0]; | |
3512 | if (val < 0) | |
3513 | val = 0; | |
3514 | if (val > 4) | |
3515 | val = 4; | |
3516 | spin_lock_irq(&hdsp->lock); | |
3517 | if (val != hdsp_rpm_input34(hdsp)) | |
3518 | change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0; | |
3519 | else | |
3520 | change = 0; | |
3521 | spin_unlock_irq(&hdsp->lock); | |
3522 | return change; | |
3523 | } | |
3524 | ||
3525 | ||
3526 | /* RPM Bypass switch */ | |
3527 | static int hdsp_rpm_bypass(struct hdsp *hdsp) | |
3528 | { | |
3529 | return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0; | |
3530 | } | |
3531 | ||
3532 | ||
3533 | static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3534 | { | |
3535 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3536 | ||
3537 | ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp); | |
3538 | return 0; | |
3539 | } | |
3540 | ||
3541 | ||
3542 | static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on) | |
3543 | { | |
3544 | if (on) | |
3545 | hdsp->control_register |= HDSP_RPM_Bypass; | |
3546 | else | |
3547 | hdsp->control_register &= ~HDSP_RPM_Bypass; | |
3548 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3549 | return 0; | |
3550 | } | |
3551 | ||
3552 | ||
3553 | static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3554 | { | |
3555 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3556 | int change; | |
3557 | unsigned int val; | |
3558 | ||
3559 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
3560 | return -EBUSY; | |
3561 | val = ucontrol->value.integer.value[0] & 1; | |
3562 | spin_lock_irq(&hdsp->lock); | |
3563 | change = (int)val != hdsp_rpm_bypass(hdsp); | |
3564 | hdsp_set_rpm_bypass(hdsp, val); | |
3565 | spin_unlock_irq(&hdsp->lock); | |
3566 | return change; | |
3567 | } | |
3568 | ||
3569 | ||
3570 | static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) | |
3571 | { | |
3572 | static char *texts[] = {"On", "Off"}; | |
3573 | ||
3574 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3575 | uinfo->count = 1; | |
3576 | uinfo->value.enumerated.items = 2; | |
3577 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3578 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
3579 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
3580 | return 0; | |
3581 | } | |
3582 | ||
3583 | ||
3584 | /* RPM Disconnect switch */ | |
3585 | static int hdsp_rpm_disconnect(struct hdsp *hdsp) | |
3586 | { | |
3587 | return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0; | |
3588 | } | |
3589 | ||
3590 | ||
3591 | static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3592 | { | |
3593 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3594 | ||
3595 | ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp); | |
3596 | return 0; | |
3597 | } | |
3598 | ||
3599 | ||
3600 | static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on) | |
3601 | { | |
3602 | if (on) | |
3603 | hdsp->control_register |= HDSP_RPM_Disconnect; | |
3604 | else | |
3605 | hdsp->control_register &= ~HDSP_RPM_Disconnect; | |
3606 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3607 | return 0; | |
3608 | } | |
3609 | ||
3610 | ||
3611 | static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3612 | { | |
3613 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3614 | int change; | |
3615 | unsigned int val; | |
3616 | ||
3617 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
3618 | return -EBUSY; | |
3619 | val = ucontrol->value.integer.value[0] & 1; | |
3620 | spin_lock_irq(&hdsp->lock); | |
3621 | change = (int)val != hdsp_rpm_disconnect(hdsp); | |
3622 | hdsp_set_rpm_disconnect(hdsp, val); | |
3623 | spin_unlock_irq(&hdsp->lock); | |
3624 | return change; | |
3625 | } | |
3626 | ||
3627 | static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) | |
3628 | { | |
3629 | static char *texts[] = {"On", "Off"}; | |
3630 | ||
3631 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3632 | uinfo->count = 1; | |
3633 | uinfo->value.enumerated.items = 2; | |
3634 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3635 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
3636 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
3637 | return 0; | |
3638 | } | |
3639 | ||
3640 | static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = { | |
3641 | { | |
3642 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
3643 | .name = "RPM Bypass", | |
3644 | .get = snd_hdsp_get_rpm_bypass, | |
3645 | .put = snd_hdsp_put_rpm_bypass, | |
3646 | .info = snd_hdsp_info_rpm_bypass | |
3647 | }, | |
3648 | { | |
3649 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
3650 | .name = "RPM Disconnect", | |
3651 | .get = snd_hdsp_get_rpm_disconnect, | |
3652 | .put = snd_hdsp_put_rpm_disconnect, | |
3653 | .info = snd_hdsp_info_rpm_disconnect | |
3654 | }, | |
3655 | { | |
3656 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
3657 | .name = "Input 1/2", | |
3658 | .get = snd_hdsp_get_rpm_input12, | |
3659 | .put = snd_hdsp_put_rpm_input12, | |
3660 | .info = snd_hdsp_info_rpm_input | |
3661 | }, | |
3662 | { | |
3663 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
3664 | .name = "Input 3/4", | |
3665 | .get = snd_hdsp_get_rpm_input34, | |
3666 | .put = snd_hdsp_put_rpm_input34, | |
3667 | .info = snd_hdsp_info_rpm_input | |
3668 | }, | |
3669 | HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
3670 | HDSP_MIXER("Mixer", 0) | |
3671 | }; | |
3672 | ||
55e957d8 TI |
3673 | static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); |
3674 | static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; | |
1da177e4 | 3675 | |
55e957d8 | 3676 | static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 LT |
3677 | { |
3678 | unsigned int idx; | |
3679 | int err; | |
55e957d8 | 3680 | struct snd_kcontrol *kctl; |
1da177e4 | 3681 | |
28b26e15 FF |
3682 | if (hdsp->io_type == RPM) { |
3683 | /* RPM Bypass, Disconnect and Input switches */ | |
3684 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) { | |
3685 | err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp)); | |
3686 | if (err < 0) | |
3687 | return err; | |
3688 | } | |
3689 | return 0; | |
3690 | } | |
3691 | ||
1da177e4 | 3692 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { |
b0b98119 | 3693 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) |
1da177e4 | 3694 | return err; |
1da177e4 LT |
3695 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ |
3696 | hdsp->spdif_ctl = kctl; | |
3697 | } | |
3698 | ||
3699 | /* ADAT SyncCheck status */ | |
3700 | snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; | |
3701 | snd_hdsp_adat_sync_check.index = 1; | |
b0b98119 | 3702 | if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) |
1da177e4 | 3703 | return err; |
1da177e4 LT |
3704 | if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { |
3705 | for (idx = 1; idx < 3; ++idx) { | |
3706 | snd_hdsp_adat_sync_check.index = idx+1; | |
b0b98119 | 3707 | if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) |
1da177e4 | 3708 | return err; |
1da177e4 LT |
3709 | } |
3710 | } | |
f9ffc5d6 | 3711 | |
1da177e4 LT |
3712 | /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ |
3713 | if (hdsp->io_type == H9632) { | |
3714 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { | |
b0b98119 | 3715 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) |
1da177e4 | 3716 | return err; |
1da177e4 LT |
3717 | } |
3718 | } | |
3719 | ||
3720 | /* AEB control for H96xx card */ | |
3721 | if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { | |
b0b98119 | 3722 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) |
1da177e4 | 3723 | return err; |
1da177e4 LT |
3724 | } |
3725 | ||
3726 | return 0; | |
3727 | } | |
3728 | ||
3729 | /*------------------------------------------------------------ | |
f9ffc5d6 | 3730 | /proc interface |
1da177e4 LT |
3731 | ------------------------------------------------------------*/ |
3732 | ||
3733 | static void | |
55e957d8 | 3734 | snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) |
1da177e4 | 3735 | { |
9fe856e4 | 3736 | struct hdsp *hdsp = entry->private_data; |
1da177e4 LT |
3737 | unsigned int status; |
3738 | unsigned int status2; | |
3739 | char *pref_sync_ref; | |
3740 | char *autosync_ref; | |
3741 | char *system_clock_mode; | |
3742 | char *clock_source; | |
3743 | int x; | |
3744 | ||
c18bc9b9 TB |
3745 | status = hdsp_read(hdsp, HDSP_statusRegister); |
3746 | status2 = hdsp_read(hdsp, HDSP_status2Register); | |
3747 | ||
3748 | snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, | |
3749 | hdsp->card->number + 1); | |
3750 | snd_iprintf(buffer, "Buffers: capture %p playback %p\n", | |
3751 | hdsp->capture_buffer, hdsp->playback_buffer); | |
3752 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
3753 | hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); | |
3754 | snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); | |
3755 | snd_iprintf(buffer, "Control2 register: 0x%x\n", | |
3756 | hdsp->control2_register); | |
3757 | snd_iprintf(buffer, "Status register: 0x%x\n", status); | |
3758 | snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); | |
3759 | ||
3760 | if (hdsp_check_for_iobox(hdsp)) { | |
3761 | snd_iprintf(buffer, "No I/O box connected.\n" | |
3762 | "Please connect one and upload firmware.\n"); | |
1da177e4 | 3763 | return; |
c18bc9b9 | 3764 | } |
1da177e4 | 3765 | |
b0b98119 | 3766 | if (hdsp_check_for_firmware(hdsp, 0)) { |
1da177e4 LT |
3767 | if (hdsp->state & HDSP_FirmwareCached) { |
3768 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
c18bc9b9 TB |
3769 | snd_iprintf(buffer, "Firmware loading from " |
3770 | "cache failed, " | |
3771 | "please upload manually.\n"); | |
1da177e4 LT |
3772 | return; |
3773 | } | |
3774 | } else { | |
311e70a4 | 3775 | int err = -EINVAL; |
311e70a4 | 3776 | err = hdsp_request_fw_loader(hdsp); |
311e70a4 TI |
3777 | if (err < 0) { |
3778 | snd_iprintf(buffer, | |
3779 | "No firmware loaded nor cached, " | |
3780 | "please upload firmware.\n"); | |
3781 | return; | |
3782 | } | |
1da177e4 LT |
3783 | } |
3784 | } | |
f9ffc5d6 | 3785 | |
1da177e4 LT |
3786 | snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); |
3787 | snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); | |
3788 | snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); | |
3789 | snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); | |
3790 | snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); | |
3791 | snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off"); | |
3792 | ||
3793 | snd_iprintf(buffer, "\n"); | |
3794 | ||
3795 | x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); | |
3796 | ||
3797 | snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); | |
3798 | snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); | |
3799 | snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); | |
3800 | snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); | |
3801 | ||
3802 | snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); | |
3803 | ||
3804 | snd_iprintf(buffer, "\n"); | |
3805 | ||
1da177e4 LT |
3806 | switch (hdsp_clock_source(hdsp)) { |
3807 | case HDSP_CLOCK_SOURCE_AUTOSYNC: | |
3808 | clock_source = "AutoSync"; | |
3809 | break; | |
3810 | case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: | |
3811 | clock_source = "Internal 32 kHz"; | |
3812 | break; | |
3813 | case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
3814 | clock_source = "Internal 44.1 kHz"; | |
3815 | break; | |
3816 | case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: | |
3817 | clock_source = "Internal 48 kHz"; | |
3818 | break; | |
3819 | case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: | |
3820 | clock_source = "Internal 64 kHz"; | |
3821 | break; | |
3822 | case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
3823 | clock_source = "Internal 88.2 kHz"; | |
3824 | break; | |
3825 | case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: | |
3826 | clock_source = "Internal 96 kHz"; | |
3827 | break; | |
3828 | case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: | |
3829 | clock_source = "Internal 128 kHz"; | |
3830 | break; | |
3831 | case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
3832 | clock_source = "Internal 176.4 kHz"; | |
3833 | break; | |
3834 | case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: | |
3835 | clock_source = "Internal 192 kHz"; | |
f9ffc5d6 | 3836 | break; |
1da177e4 | 3837 | default: |
f9ffc5d6 | 3838 | clock_source = "Error"; |
1da177e4 LT |
3839 | } |
3840 | snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); | |
f9ffc5d6 | 3841 | |
b0b98119 | 3842 | if (hdsp_system_clock_mode(hdsp)) |
1da177e4 | 3843 | system_clock_mode = "Slave"; |
b0b98119 | 3844 | else |
1da177e4 | 3845 | system_clock_mode = "Master"; |
f9ffc5d6 | 3846 | |
1da177e4 LT |
3847 | switch (hdsp_pref_sync_ref (hdsp)) { |
3848 | case HDSP_SYNC_FROM_WORD: | |
3849 | pref_sync_ref = "Word Clock"; | |
3850 | break; | |
3851 | case HDSP_SYNC_FROM_ADAT_SYNC: | |
3852 | pref_sync_ref = "ADAT Sync"; | |
3853 | break; | |
3854 | case HDSP_SYNC_FROM_SPDIF: | |
3855 | pref_sync_ref = "SPDIF"; | |
3856 | break; | |
3857 | case HDSP_SYNC_FROM_ADAT1: | |
3858 | pref_sync_ref = "ADAT1"; | |
3859 | break; | |
3860 | case HDSP_SYNC_FROM_ADAT2: | |
3861 | pref_sync_ref = "ADAT2"; | |
3862 | break; | |
3863 | case HDSP_SYNC_FROM_ADAT3: | |
3864 | pref_sync_ref = "ADAT3"; | |
3865 | break; | |
3866 | default: | |
3867 | pref_sync_ref = "Word Clock"; | |
3868 | break; | |
3869 | } | |
3870 | snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); | |
f9ffc5d6 | 3871 | |
1da177e4 LT |
3872 | switch (hdsp_autosync_ref (hdsp)) { |
3873 | case HDSP_AUTOSYNC_FROM_WORD: | |
3874 | autosync_ref = "Word Clock"; | |
3875 | break; | |
3876 | case HDSP_AUTOSYNC_FROM_ADAT_SYNC: | |
3877 | autosync_ref = "ADAT Sync"; | |
3878 | break; | |
3879 | case HDSP_AUTOSYNC_FROM_SPDIF: | |
3880 | autosync_ref = "SPDIF"; | |
3881 | break; | |
3882 | case HDSP_AUTOSYNC_FROM_NONE: | |
3883 | autosync_ref = "None"; | |
f9ffc5d6 | 3884 | break; |
1da177e4 LT |
3885 | case HDSP_AUTOSYNC_FROM_ADAT1: |
3886 | autosync_ref = "ADAT1"; | |
3887 | break; | |
3888 | case HDSP_AUTOSYNC_FROM_ADAT2: | |
3889 | autosync_ref = "ADAT2"; | |
3890 | break; | |
3891 | case HDSP_AUTOSYNC_FROM_ADAT3: | |
3892 | autosync_ref = "ADAT3"; | |
3893 | break; | |
3894 | default: | |
3895 | autosync_ref = "---"; | |
3896 | break; | |
3897 | } | |
3898 | snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); | |
f9ffc5d6 | 3899 | |
1da177e4 | 3900 | snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); |
f9ffc5d6 | 3901 | |
1da177e4 LT |
3902 | snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); |
3903 | ||
3904 | snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); | |
e3ea4d89 | 3905 | snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); |
f9ffc5d6 | 3906 | |
1da177e4 LT |
3907 | snd_iprintf(buffer, "\n"); |
3908 | ||
28b26e15 FF |
3909 | if (hdsp->io_type != RPM) { |
3910 | switch (hdsp_spdif_in(hdsp)) { | |
3911 | case HDSP_SPDIFIN_OPTICAL: | |
3912 | snd_iprintf(buffer, "IEC958 input: Optical\n"); | |
3913 | break; | |
3914 | case HDSP_SPDIFIN_COAXIAL: | |
3915 | snd_iprintf(buffer, "IEC958 input: Coaxial\n"); | |
3916 | break; | |
3917 | case HDSP_SPDIFIN_INTERNAL: | |
3918 | snd_iprintf(buffer, "IEC958 input: Internal\n"); | |
3919 | break; | |
3920 | case HDSP_SPDIFIN_AES: | |
3921 | snd_iprintf(buffer, "IEC958 input: AES\n"); | |
3922 | break; | |
3923 | default: | |
3924 | snd_iprintf(buffer, "IEC958 input: ???\n"); | |
3925 | break; | |
3926 | } | |
1da177e4 | 3927 | } |
f9ffc5d6 | 3928 | |
28b26e15 FF |
3929 | if (RPM == hdsp->io_type) { |
3930 | if (hdsp->control_register & HDSP_RPM_Bypass) | |
3931 | snd_iprintf(buffer, "RPM Bypass: disabled\n"); | |
3932 | else | |
3933 | snd_iprintf(buffer, "RPM Bypass: enabled\n"); | |
3934 | if (hdsp->control_register & HDSP_RPM_Disconnect) | |
3935 | snd_iprintf(buffer, "RPM disconnected\n"); | |
3936 | else | |
3937 | snd_iprintf(buffer, "RPM connected\n"); | |
1da177e4 | 3938 | |
28b26e15 FF |
3939 | switch (hdsp->control_register & HDSP_RPM_Inp12) { |
3940 | case HDSP_RPM_Inp12_Phon_6dB: | |
3941 | snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n"); | |
3942 | break; | |
3943 | case HDSP_RPM_Inp12_Phon_0dB: | |
3944 | snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n"); | |
3945 | break; | |
3946 | case HDSP_RPM_Inp12_Phon_n6dB: | |
3947 | snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n"); | |
3948 | break; | |
3949 | case HDSP_RPM_Inp12_Line_0dB: | |
3950 | snd_iprintf(buffer, "Input 1/2: Line, 0dB\n"); | |
3951 | break; | |
3952 | case HDSP_RPM_Inp12_Line_n6dB: | |
3953 | snd_iprintf(buffer, "Input 1/2: Line, -6dB\n"); | |
3954 | break; | |
3955 | default: | |
3956 | snd_iprintf(buffer, "Input 1/2: ???\n"); | |
3957 | } | |
1da177e4 | 3958 | |
28b26e15 FF |
3959 | switch (hdsp->control_register & HDSP_RPM_Inp34) { |
3960 | case HDSP_RPM_Inp34_Phon_6dB: | |
3961 | snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n"); | |
3962 | break; | |
3963 | case HDSP_RPM_Inp34_Phon_0dB: | |
3964 | snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n"); | |
3965 | break; | |
3966 | case HDSP_RPM_Inp34_Phon_n6dB: | |
3967 | snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n"); | |
3968 | break; | |
3969 | case HDSP_RPM_Inp34_Line_0dB: | |
3970 | snd_iprintf(buffer, "Input 3/4: Line, 0dB\n"); | |
3971 | break; | |
3972 | case HDSP_RPM_Inp34_Line_n6dB: | |
3973 | snd_iprintf(buffer, "Input 3/4: Line, -6dB\n"); | |
3974 | break; | |
3975 | default: | |
3976 | snd_iprintf(buffer, "Input 3/4: ???\n"); | |
3977 | } | |
1da177e4 | 3978 | |
28b26e15 FF |
3979 | } else { |
3980 | if (hdsp->control_register & HDSP_SPDIFOpticalOut) | |
3981 | snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); | |
3982 | else | |
3983 | snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); | |
3984 | ||
3985 | if (hdsp->control_register & HDSP_SPDIFProfessional) | |
3986 | snd_iprintf(buffer, "IEC958 quality: Professional\n"); | |
3987 | else | |
3988 | snd_iprintf(buffer, "IEC958 quality: Consumer\n"); | |
3989 | ||
3990 | if (hdsp->control_register & HDSP_SPDIFEmphasis) | |
3991 | snd_iprintf(buffer, "IEC958 emphasis: on\n"); | |
3992 | else | |
3993 | snd_iprintf(buffer, "IEC958 emphasis: off\n"); | |
1da177e4 | 3994 | |
28b26e15 FF |
3995 | if (hdsp->control_register & HDSP_SPDIFNonAudio) |
3996 | snd_iprintf(buffer, "IEC958 NonAudio: on\n"); | |
3997 | else | |
3998 | snd_iprintf(buffer, "IEC958 NonAudio: off\n"); | |
3999 | x = hdsp_spdif_sample_rate(hdsp); | |
4000 | if (x != 0) | |
4001 | snd_iprintf(buffer, "IEC958 sample rate: %d\n", x); | |
4002 | else | |
4003 | snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n"); | |
4004 | } | |
1da177e4 LT |
4005 | snd_iprintf(buffer, "\n"); |
4006 | ||
4007 | /* Sync Check */ | |
4008 | x = status & HDSP_Sync0; | |
b0b98119 | 4009 | if (status & HDSP_Lock0) |
1da177e4 | 4010 | snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 4011 | else |
1da177e4 | 4012 | snd_iprintf(buffer, "ADAT1: No Lock\n"); |
1da177e4 LT |
4013 | |
4014 | switch (hdsp->io_type) { | |
4015 | case Digiface: | |
4016 | case H9652: | |
4017 | x = status & HDSP_Sync1; | |
b0b98119 | 4018 | if (status & HDSP_Lock1) |
1da177e4 | 4019 | snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 4020 | else |
1da177e4 | 4021 | snd_iprintf(buffer, "ADAT2: No Lock\n"); |
1da177e4 | 4022 | x = status & HDSP_Sync2; |
b0b98119 | 4023 | if (status & HDSP_Lock2) |
1da177e4 | 4024 | snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 4025 | else |
1da177e4 | 4026 | snd_iprintf(buffer, "ADAT3: No Lock\n"); |
b0b98119 | 4027 | break; |
1da177e4 LT |
4028 | default: |
4029 | /* relax */ | |
4030 | break; | |
4031 | } | |
4032 | ||
4033 | x = status & HDSP_SPDIFSync; | |
b0b98119 | 4034 | if (status & HDSP_SPDIFErrorFlag) |
1da177e4 | 4035 | snd_iprintf (buffer, "SPDIF: No Lock\n"); |
b0b98119 | 4036 | else |
1da177e4 | 4037 | snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); |
f9ffc5d6 | 4038 | |
1da177e4 | 4039 | x = status2 & HDSP_wc_sync; |
b0b98119 | 4040 | if (status2 & HDSP_wc_lock) |
1da177e4 | 4041 | snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 4042 | else |
1da177e4 | 4043 | snd_iprintf (buffer, "Word Clock: No Lock\n"); |
f9ffc5d6 | 4044 | |
1da177e4 | 4045 | x = status & HDSP_TimecodeSync; |
b0b98119 | 4046 | if (status & HDSP_TimecodeLock) |
1da177e4 | 4047 | snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 4048 | else |
1da177e4 | 4049 | snd_iprintf(buffer, "ADAT Sync: No Lock\n"); |
1da177e4 LT |
4050 | |
4051 | snd_iprintf(buffer, "\n"); | |
f9ffc5d6 | 4052 | |
1da177e4 LT |
4053 | /* Informations about H9632 specific controls */ |
4054 | if (hdsp->io_type == H9632) { | |
4055 | char *tmp; | |
f9ffc5d6 | 4056 | |
1da177e4 LT |
4057 | switch (hdsp_ad_gain(hdsp)) { |
4058 | case 0: | |
4059 | tmp = "-10 dBV"; | |
4060 | break; | |
4061 | case 1: | |
4062 | tmp = "+4 dBu"; | |
4063 | break; | |
4064 | default: | |
4065 | tmp = "Lo Gain"; | |
4066 | break; | |
4067 | } | |
4068 | snd_iprintf(buffer, "AD Gain : %s\n", tmp); | |
4069 | ||
4070 | switch (hdsp_da_gain(hdsp)) { | |
4071 | case 0: | |
4072 | tmp = "Hi Gain"; | |
4073 | break; | |
4074 | case 1: | |
4075 | tmp = "+4 dBu"; | |
4076 | break; | |
4077 | default: | |
4078 | tmp = "-10 dBV"; | |
4079 | break; | |
4080 | } | |
4081 | snd_iprintf(buffer, "DA Gain : %s\n", tmp); | |
f9ffc5d6 | 4082 | |
1da177e4 LT |
4083 | switch (hdsp_phone_gain(hdsp)) { |
4084 | case 0: | |
4085 | tmp = "0 dB"; | |
4086 | break; | |
4087 | case 1: | |
4088 | tmp = "-6 dB"; | |
4089 | break; | |
4090 | default: | |
4091 | tmp = "-12 dB"; | |
4092 | break; | |
4093 | } | |
4094 | snd_iprintf(buffer, "Phones Gain : %s\n", tmp); | |
4095 | ||
f9ffc5d6 TB |
4096 | snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); |
4097 | ||
b0b98119 | 4098 | if (hdsp->control_register & HDSP_AnalogExtensionBoard) |
1da177e4 | 4099 | snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); |
b0b98119 | 4100 | else |
1da177e4 | 4101 | snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); |
1da177e4 LT |
4102 | snd_iprintf(buffer, "\n"); |
4103 | } | |
4104 | ||
4105 | } | |
4106 | ||
1374f8ce | 4107 | static void snd_hdsp_proc_init(struct hdsp *hdsp) |
1da177e4 | 4108 | { |
55e957d8 | 4109 | struct snd_info_entry *entry; |
1da177e4 LT |
4110 | |
4111 | if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) | |
bf850204 | 4112 | snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read); |
1da177e4 LT |
4113 | } |
4114 | ||
55e957d8 | 4115 | static void snd_hdsp_free_buffers(struct hdsp *hdsp) |
1da177e4 LT |
4116 | { |
4117 | snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); | |
4118 | snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); | |
4119 | } | |
4120 | ||
e23e7a14 | 4121 | static int snd_hdsp_initialize_memory(struct hdsp *hdsp) |
1da177e4 LT |
4122 | { |
4123 | unsigned long pb_bus, cb_bus; | |
4124 | ||
4125 | if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || | |
4126 | snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { | |
4127 | if (hdsp->capture_dma_buf.area) | |
4128 | snd_dma_free_pages(&hdsp->capture_dma_buf); | |
4129 | printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name); | |
4130 | return -ENOMEM; | |
4131 | } | |
4132 | ||
4133 | /* Align to bus-space 64K boundary */ | |
4134 | ||
7ab39926 CL |
4135 | cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul); |
4136 | pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul); | |
1da177e4 LT |
4137 | |
4138 | /* Tell the card where it is */ | |
4139 | ||
4140 | hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); | |
4141 | hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); | |
4142 | ||
4143 | hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); | |
4144 | hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); | |
4145 | ||
4146 | return 0; | |
4147 | } | |
4148 | ||
55e957d8 | 4149 | static int snd_hdsp_set_defaults(struct hdsp *hdsp) |
1da177e4 LT |
4150 | { |
4151 | unsigned int i; | |
4152 | ||
4153 | /* ASSUMPTION: hdsp->lock is either held, or | |
4154 | there is no need to hold it (e.g. during module | |
561de31a | 4155 | initialization). |
1da177e4 LT |
4156 | */ |
4157 | ||
4158 | /* set defaults: | |
4159 | ||
f9ffc5d6 | 4160 | SPDIF Input via Coax |
1da177e4 LT |
4161 | Master clock mode |
4162 | maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, | |
4163 | which implies 2 4096 sample, 32Kbyte periods). | |
f9ffc5d6 | 4164 | Enable line out. |
1da177e4 LT |
4165 | */ |
4166 | ||
f9ffc5d6 TB |
4167 | hdsp->control_register = HDSP_ClockModeMaster | |
4168 | HDSP_SPDIFInputCoaxial | | |
4169 | hdsp_encode_latency(7) | | |
1da177e4 | 4170 | HDSP_LineOut; |
f9ffc5d6 | 4171 | |
1da177e4 LT |
4172 | |
4173 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
4174 | ||
4175 | #ifdef SNDRV_BIG_ENDIAN | |
4176 | hdsp->control2_register = HDSP_BIGENDIAN_MODE; | |
4177 | #else | |
4178 | hdsp->control2_register = 0; | |
4179 | #endif | |
b0b98119 | 4180 | if (hdsp->io_type == H9652) |
1da177e4 | 4181 | snd_hdsp_9652_enable_mixer (hdsp); |
b0b98119 TI |
4182 | else |
4183 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
1da177e4 LT |
4184 | |
4185 | hdsp_reset_hw_pointer(hdsp); | |
4186 | hdsp_compute_period_size(hdsp); | |
4187 | ||
4188 | /* silence everything */ | |
f9ffc5d6 | 4189 | |
b0b98119 | 4190 | for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) |
1da177e4 | 4191 | hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; |
1da177e4 LT |
4192 | |
4193 | for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { | |
b0b98119 | 4194 | if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) |
1da177e4 | 4195 | return -EIO; |
1da177e4 | 4196 | } |
f9ffc5d6 | 4197 | |
1da177e4 LT |
4198 | /* H9632 specific defaults */ |
4199 | if (hdsp->io_type == H9632) { | |
4200 | hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); | |
4201 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
4202 | } | |
4203 | ||
4204 | /* set a default rate so that the channel map is set up. | |
4205 | */ | |
4206 | ||
4207 | hdsp_set_rate(hdsp, 48000, 1); | |
4208 | ||
4209 | return 0; | |
4210 | } | |
4211 | ||
4212 | static void hdsp_midi_tasklet(unsigned long arg) | |
4213 | { | |
55e957d8 | 4214 | struct hdsp *hdsp = (struct hdsp *)arg; |
f9ffc5d6 | 4215 | |
b0b98119 | 4216 | if (hdsp->midi[0].pending) |
1da177e4 | 4217 | snd_hdsp_midi_input_read (&hdsp->midi[0]); |
b0b98119 | 4218 | if (hdsp->midi[1].pending) |
1da177e4 | 4219 | snd_hdsp_midi_input_read (&hdsp->midi[1]); |
f9ffc5d6 | 4220 | } |
1da177e4 | 4221 | |
7d12e780 | 4222 | static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) |
1da177e4 | 4223 | { |
55e957d8 | 4224 | struct hdsp *hdsp = (struct hdsp *) dev_id; |
1da177e4 LT |
4225 | unsigned int status; |
4226 | int audio; | |
4227 | int midi0; | |
4228 | int midi1; | |
4229 | unsigned int midi0status; | |
4230 | unsigned int midi1status; | |
4231 | int schedule = 0; | |
f9ffc5d6 | 4232 | |
1da177e4 LT |
4233 | status = hdsp_read(hdsp, HDSP_statusRegister); |
4234 | ||
4235 | audio = status & HDSP_audioIRQPending; | |
4236 | midi0 = status & HDSP_midi0IRQPending; | |
4237 | midi1 = status & HDSP_midi1IRQPending; | |
4238 | ||
b0b98119 | 4239 | if (!audio && !midi0 && !midi1) |
1da177e4 | 4240 | return IRQ_NONE; |
1da177e4 LT |
4241 | |
4242 | hdsp_write(hdsp, HDSP_interruptConfirmation, 0); | |
4243 | ||
4244 | midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; | |
4245 | midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; | |
f9ffc5d6 | 4246 | |
c2503cd3 TI |
4247 | if (!(hdsp->state & HDSP_InitializationComplete)) |
4248 | return IRQ_HANDLED; | |
4249 | ||
1da177e4 | 4250 | if (audio) { |
b0b98119 | 4251 | if (hdsp->capture_substream) |
1da177e4 | 4252 | snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); |
f9ffc5d6 | 4253 | |
b0b98119 | 4254 | if (hdsp->playback_substream) |
1da177e4 | 4255 | snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); |
1da177e4 | 4256 | } |
f9ffc5d6 | 4257 | |
1da177e4 LT |
4258 | if (midi0 && midi0status) { |
4259 | if (hdsp->use_midi_tasklet) { | |
4260 | /* we disable interrupts for this input until processing is done */ | |
4261 | hdsp->control_register &= ~HDSP_Midi0InterruptEnable; | |
4262 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
4263 | hdsp->midi[0].pending = 1; | |
4264 | schedule = 1; | |
4265 | } else { | |
4266 | snd_hdsp_midi_input_read (&hdsp->midi[0]); | |
4267 | } | |
4268 | } | |
28b26e15 | 4269 | if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) { |
1da177e4 LT |
4270 | if (hdsp->use_midi_tasklet) { |
4271 | /* we disable interrupts for this input until processing is done */ | |
4272 | hdsp->control_register &= ~HDSP_Midi1InterruptEnable; | |
4273 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
4274 | hdsp->midi[1].pending = 1; | |
4275 | schedule = 1; | |
4276 | } else { | |
4277 | snd_hdsp_midi_input_read (&hdsp->midi[1]); | |
4278 | } | |
4279 | } | |
4280 | if (hdsp->use_midi_tasklet && schedule) | |
1f04128a | 4281 | tasklet_schedule(&hdsp->midi_tasklet); |
1da177e4 LT |
4282 | return IRQ_HANDLED; |
4283 | } | |
4284 | ||
55e957d8 | 4285 | static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 4286 | { |
55e957d8 | 4287 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4288 | return hdsp_hw_pointer(hdsp); |
4289 | } | |
4290 | ||
55e957d8 | 4291 | static char *hdsp_channel_buffer_location(struct hdsp *hdsp, |
1da177e4 LT |
4292 | int stream, |
4293 | int channel) | |
4294 | ||
4295 | { | |
4296 | int mapped_channel; | |
4297 | ||
da3cec35 TI |
4298 | if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels)) |
4299 | return NULL; | |
f9ffc5d6 | 4300 | |
b0b98119 | 4301 | if ((mapped_channel = hdsp->channel_map[channel]) < 0) |
1da177e4 | 4302 | return NULL; |
f9ffc5d6 | 4303 | |
b0b98119 | 4304 | if (stream == SNDRV_PCM_STREAM_CAPTURE) |
1da177e4 | 4305 | return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); |
b0b98119 | 4306 | else |
1da177e4 | 4307 | return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); |
1da177e4 LT |
4308 | } |
4309 | ||
55e957d8 | 4310 | static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel, |
1da177e4 LT |
4311 | snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) |
4312 | { | |
55e957d8 | 4313 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4314 | char *channel_buf; |
4315 | ||
da3cec35 TI |
4316 | if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4)) |
4317 | return -EINVAL; | |
1da177e4 LT |
4318 | |
4319 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
da3cec35 TI |
4320 | if (snd_BUG_ON(!channel_buf)) |
4321 | return -EIO; | |
1da177e4 LT |
4322 | if (copy_from_user(channel_buf + pos * 4, src, count * 4)) |
4323 | return -EFAULT; | |
4324 | return count; | |
4325 | } | |
4326 | ||
55e957d8 | 4327 | static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel, |
1da177e4 LT |
4328 | snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) |
4329 | { | |
55e957d8 | 4330 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4331 | char *channel_buf; |
4332 | ||
da3cec35 TI |
4333 | if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4)) |
4334 | return -EINVAL; | |
1da177e4 LT |
4335 | |
4336 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
da3cec35 TI |
4337 | if (snd_BUG_ON(!channel_buf)) |
4338 | return -EIO; | |
1da177e4 LT |
4339 | if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) |
4340 | return -EFAULT; | |
4341 | return count; | |
4342 | } | |
4343 | ||
55e957d8 | 4344 | static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel, |
1da177e4 LT |
4345 | snd_pcm_uframes_t pos, snd_pcm_uframes_t count) |
4346 | { | |
55e957d8 | 4347 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4348 | char *channel_buf; |
4349 | ||
4350 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
da3cec35 TI |
4351 | if (snd_BUG_ON(!channel_buf)) |
4352 | return -EIO; | |
1da177e4 LT |
4353 | memset(channel_buf + pos * 4, 0, count * 4); |
4354 | return count; | |
4355 | } | |
4356 | ||
55e957d8 | 4357 | static int snd_hdsp_reset(struct snd_pcm_substream *substream) |
1da177e4 | 4358 | { |
55e957d8 TI |
4359 | struct snd_pcm_runtime *runtime = substream->runtime; |
4360 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); | |
4361 | struct snd_pcm_substream *other; | |
1da177e4 LT |
4362 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
4363 | other = hdsp->capture_substream; | |
4364 | else | |
4365 | other = hdsp->playback_substream; | |
4366 | if (hdsp->running) | |
4367 | runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); | |
4368 | else | |
4369 | runtime->status->hw_ptr = 0; | |
4370 | if (other) { | |
55e957d8 TI |
4371 | struct snd_pcm_substream *s; |
4372 | struct snd_pcm_runtime *oruntime = other->runtime; | |
ef991b95 | 4373 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
4374 | if (s == other) { |
4375 | oruntime->status->hw_ptr = runtime->status->hw_ptr; | |
4376 | break; | |
4377 | } | |
4378 | } | |
4379 | } | |
4380 | return 0; | |
4381 | } | |
4382 | ||
55e957d8 TI |
4383 | static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, |
4384 | struct snd_pcm_hw_params *params) | |
1da177e4 | 4385 | { |
55e957d8 | 4386 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4387 | int err; |
4388 | pid_t this_pid; | |
4389 | pid_t other_pid; | |
4390 | ||
b0b98119 | 4391 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4392 | return -EIO; |
1da177e4 | 4393 | |
b0b98119 | 4394 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4395 | return -EIO; |
1da177e4 LT |
4396 | |
4397 | spin_lock_irq(&hdsp->lock); | |
4398 | ||
4399 | if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
4400 | hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); | |
4401 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); | |
4402 | this_pid = hdsp->playback_pid; | |
4403 | other_pid = hdsp->capture_pid; | |
4404 | } else { | |
4405 | this_pid = hdsp->capture_pid; | |
4406 | other_pid = hdsp->playback_pid; | |
4407 | } | |
4408 | ||
4409 | if ((other_pid > 0) && (this_pid != other_pid)) { | |
4410 | ||
4411 | /* The other stream is open, and not by the same | |
4412 | task as this one. Make sure that the parameters | |
4413 | that matter are the same. | |
4414 | */ | |
4415 | ||
4416 | if (params_rate(params) != hdsp->system_sample_rate) { | |
4417 | spin_unlock_irq(&hdsp->lock); | |
4418 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); | |
4419 | return -EBUSY; | |
4420 | } | |
4421 | ||
4422 | if (params_period_size(params) != hdsp->period_bytes / 4) { | |
4423 | spin_unlock_irq(&hdsp->lock); | |
4424 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
4425 | return -EBUSY; | |
4426 | } | |
4427 | ||
4428 | /* We're fine. */ | |
4429 | ||
4430 | spin_unlock_irq(&hdsp->lock); | |
4431 | return 0; | |
4432 | ||
4433 | } else { | |
4434 | spin_unlock_irq(&hdsp->lock); | |
4435 | } | |
4436 | ||
4437 | /* how to make sure that the rate matches an externally-set one ? | |
4438 | */ | |
4439 | ||
4440 | spin_lock_irq(&hdsp->lock); | |
e3ea4d89 TI |
4441 | if (! hdsp->clock_source_locked) { |
4442 | if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { | |
4443 | spin_unlock_irq(&hdsp->lock); | |
4444 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); | |
4445 | return err; | |
4446 | } | |
1da177e4 | 4447 | } |
e3ea4d89 | 4448 | spin_unlock_irq(&hdsp->lock); |
1da177e4 LT |
4449 | |
4450 | if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { | |
4451 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
4452 | return err; | |
4453 | } | |
4454 | ||
4455 | return 0; | |
4456 | } | |
4457 | ||
55e957d8 TI |
4458 | static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, |
4459 | struct snd_pcm_channel_info *info) | |
1da177e4 | 4460 | { |
55e957d8 | 4461 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4462 | int mapped_channel; |
4463 | ||
da3cec35 TI |
4464 | if (snd_BUG_ON(info->channel >= hdsp->max_channels)) |
4465 | return -EINVAL; | |
1da177e4 | 4466 | |
b0b98119 | 4467 | if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) |
1da177e4 | 4468 | return -EINVAL; |
1da177e4 LT |
4469 | |
4470 | info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; | |
4471 | info->first = 0; | |
4472 | info->step = 32; | |
4473 | return 0; | |
4474 | } | |
4475 | ||
55e957d8 | 4476 | static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, |
1da177e4 LT |
4477 | unsigned int cmd, void *arg) |
4478 | { | |
4479 | switch (cmd) { | |
4480 | case SNDRV_PCM_IOCTL1_RESET: | |
1da177e4 | 4481 | return snd_hdsp_reset(substream); |
1da177e4 | 4482 | case SNDRV_PCM_IOCTL1_CHANNEL_INFO: |
b0b98119 | 4483 | return snd_hdsp_channel_info(substream, arg); |
1da177e4 LT |
4484 | default: |
4485 | break; | |
4486 | } | |
4487 | ||
4488 | return snd_pcm_lib_ioctl(substream, cmd, arg); | |
4489 | } | |
4490 | ||
55e957d8 | 4491 | static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 4492 | { |
55e957d8 TI |
4493 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
4494 | struct snd_pcm_substream *other; | |
1da177e4 | 4495 | int running; |
f9ffc5d6 | 4496 | |
b0b98119 | 4497 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4498 | return -EIO; |
1da177e4 | 4499 | |
311e70a4 | 4500 | if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ |
1da177e4 | 4501 | return -EIO; |
1da177e4 LT |
4502 | |
4503 | spin_lock(&hdsp->lock); | |
4504 | running = hdsp->running; | |
4505 | switch (cmd) { | |
4506 | case SNDRV_PCM_TRIGGER_START: | |
4507 | running |= 1 << substream->stream; | |
4508 | break; | |
4509 | case SNDRV_PCM_TRIGGER_STOP: | |
4510 | running &= ~(1 << substream->stream); | |
4511 | break; | |
4512 | default: | |
4513 | snd_BUG(); | |
4514 | spin_unlock(&hdsp->lock); | |
4515 | return -EINVAL; | |
4516 | } | |
4517 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
4518 | other = hdsp->capture_substream; | |
4519 | else | |
4520 | other = hdsp->playback_substream; | |
4521 | ||
4522 | if (other) { | |
55e957d8 | 4523 | struct snd_pcm_substream *s; |
ef991b95 | 4524 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
4525 | if (s == other) { |
4526 | snd_pcm_trigger_done(s, substream); | |
4527 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
4528 | running |= 1 << s->stream; | |
4529 | else | |
4530 | running &= ~(1 << s->stream); | |
4531 | goto _ok; | |
4532 | } | |
4533 | } | |
4534 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
4535 | if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && | |
4536 | substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
4537 | hdsp_silence_playback(hdsp); | |
4538 | } else { | |
4539 | if (running && | |
4540 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
4541 | hdsp_silence_playback(hdsp); | |
4542 | } | |
4543 | } else { | |
4544 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
4545 | hdsp_silence_playback(hdsp); | |
4546 | } | |
4547 | _ok: | |
4548 | snd_pcm_trigger_done(substream, substream); | |
4549 | if (!hdsp->running && running) | |
4550 | hdsp_start_audio(hdsp); | |
4551 | else if (hdsp->running && !running) | |
4552 | hdsp_stop_audio(hdsp); | |
4553 | hdsp->running = running; | |
4554 | spin_unlock(&hdsp->lock); | |
4555 | ||
4556 | return 0; | |
4557 | } | |
4558 | ||
55e957d8 | 4559 | static int snd_hdsp_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 4560 | { |
55e957d8 | 4561 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4562 | int result = 0; |
4563 | ||
b0b98119 | 4564 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4565 | return -EIO; |
1da177e4 | 4566 | |
b0b98119 | 4567 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4568 | return -EIO; |
1da177e4 LT |
4569 | |
4570 | spin_lock_irq(&hdsp->lock); | |
4571 | if (!hdsp->running) | |
4572 | hdsp_reset_hw_pointer(hdsp); | |
4573 | spin_unlock_irq(&hdsp->lock); | |
4574 | return result; | |
4575 | } | |
4576 | ||
55e957d8 | 4577 | static struct snd_pcm_hardware snd_hdsp_playback_subinfo = |
1da177e4 LT |
4578 | { |
4579 | .info = (SNDRV_PCM_INFO_MMAP | | |
4580 | SNDRV_PCM_INFO_MMAP_VALID | | |
4581 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
4582 | SNDRV_PCM_INFO_SYNC_START | | |
4583 | SNDRV_PCM_INFO_DOUBLE), | |
4584 | #ifdef SNDRV_BIG_ENDIAN | |
4585 | .formats = SNDRV_PCM_FMTBIT_S32_BE, | |
4586 | #else | |
4587 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
4588 | #endif | |
4589 | .rates = (SNDRV_PCM_RATE_32000 | | |
f9ffc5d6 TB |
4590 | SNDRV_PCM_RATE_44100 | |
4591 | SNDRV_PCM_RATE_48000 | | |
4592 | SNDRV_PCM_RATE_64000 | | |
4593 | SNDRV_PCM_RATE_88200 | | |
1da177e4 LT |
4594 | SNDRV_PCM_RATE_96000), |
4595 | .rate_min = 32000, | |
4596 | .rate_max = 96000, | |
28b26e15 | 4597 | .channels_min = 6, |
1da177e4 LT |
4598 | .channels_max = HDSP_MAX_CHANNELS, |
4599 | .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, | |
4600 | .period_bytes_min = (64 * 4) * 10, | |
4601 | .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, | |
4602 | .periods_min = 2, | |
4603 | .periods_max = 2, | |
4604 | .fifo_size = 0 | |
4605 | }; | |
4606 | ||
55e957d8 | 4607 | static struct snd_pcm_hardware snd_hdsp_capture_subinfo = |
1da177e4 LT |
4608 | { |
4609 | .info = (SNDRV_PCM_INFO_MMAP | | |
4610 | SNDRV_PCM_INFO_MMAP_VALID | | |
4611 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
4612 | SNDRV_PCM_INFO_SYNC_START), | |
4613 | #ifdef SNDRV_BIG_ENDIAN | |
4614 | .formats = SNDRV_PCM_FMTBIT_S32_BE, | |
4615 | #else | |
4616 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
4617 | #endif | |
4618 | .rates = (SNDRV_PCM_RATE_32000 | | |
f9ffc5d6 TB |
4619 | SNDRV_PCM_RATE_44100 | |
4620 | SNDRV_PCM_RATE_48000 | | |
4621 | SNDRV_PCM_RATE_64000 | | |
4622 | SNDRV_PCM_RATE_88200 | | |
1da177e4 LT |
4623 | SNDRV_PCM_RATE_96000), |
4624 | .rate_min = 32000, | |
4625 | .rate_max = 96000, | |
28b26e15 | 4626 | .channels_min = 5, |
1da177e4 LT |
4627 | .channels_max = HDSP_MAX_CHANNELS, |
4628 | .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, | |
4629 | .period_bytes_min = (64 * 4) * 10, | |
4630 | .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, | |
4631 | .periods_min = 2, | |
4632 | .periods_max = 2, | |
4633 | .fifo_size = 0 | |
4634 | }; | |
4635 | ||
4636 | static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; | |
4637 | ||
55e957d8 | 4638 | static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { |
1da177e4 LT |
4639 | .count = ARRAY_SIZE(hdsp_period_sizes), |
4640 | .list = hdsp_period_sizes, | |
4641 | .mask = 0 | |
4642 | }; | |
4643 | ||
4644 | static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; | |
4645 | ||
55e957d8 | 4646 | static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = { |
1da177e4 LT |
4647 | .count = ARRAY_SIZE(hdsp_9632_sample_rates), |
4648 | .list = hdsp_9632_sample_rates, | |
4649 | .mask = 0 | |
4650 | }; | |
4651 | ||
55e957d8 TI |
4652 | static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, |
4653 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4654 | { |
55e957d8 TI |
4655 | struct hdsp *hdsp = rule->private; |
4656 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
1da177e4 LT |
4657 | if (hdsp->io_type == H9632) { |
4658 | unsigned int list[3]; | |
4659 | list[0] = hdsp->qs_in_channels; | |
4660 | list[1] = hdsp->ds_in_channels; | |
4661 | list[2] = hdsp->ss_in_channels; | |
4662 | return snd_interval_list(c, 3, list, 0); | |
4663 | } else { | |
4664 | unsigned int list[2]; | |
4665 | list[0] = hdsp->ds_in_channels; | |
4666 | list[1] = hdsp->ss_in_channels; | |
4667 | return snd_interval_list(c, 2, list, 0); | |
4668 | } | |
4669 | } | |
4670 | ||
55e957d8 TI |
4671 | static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, |
4672 | struct snd_pcm_hw_rule *rule) | |
1da177e4 LT |
4673 | { |
4674 | unsigned int list[3]; | |
55e957d8 TI |
4675 | struct hdsp *hdsp = rule->private; |
4676 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
1da177e4 LT |
4677 | if (hdsp->io_type == H9632) { |
4678 | list[0] = hdsp->qs_out_channels; | |
4679 | list[1] = hdsp->ds_out_channels; | |
4680 | list[2] = hdsp->ss_out_channels; | |
4681 | return snd_interval_list(c, 3, list, 0); | |
4682 | } else { | |
4683 | list[0] = hdsp->ds_out_channels; | |
4684 | list[1] = hdsp->ss_out_channels; | |
4685 | } | |
4686 | return snd_interval_list(c, 2, list, 0); | |
4687 | } | |
4688 | ||
55e957d8 TI |
4689 | static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, |
4690 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4691 | { |
55e957d8 TI |
4692 | struct hdsp *hdsp = rule->private; |
4693 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4694 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4695 | if (r->min > 96000 && hdsp->io_type == H9632) { |
55e957d8 | 4696 | struct snd_interval t = { |
1da177e4 LT |
4697 | .min = hdsp->qs_in_channels, |
4698 | .max = hdsp->qs_in_channels, | |
4699 | .integer = 1, | |
4700 | }; | |
f9ffc5d6 | 4701 | return snd_interval_refine(c, &t); |
1da177e4 | 4702 | } else if (r->min > 48000 && r->max <= 96000) { |
55e957d8 | 4703 | struct snd_interval t = { |
1da177e4 LT |
4704 | .min = hdsp->ds_in_channels, |
4705 | .max = hdsp->ds_in_channels, | |
4706 | .integer = 1, | |
4707 | }; | |
4708 | return snd_interval_refine(c, &t); | |
4709 | } else if (r->max < 64000) { | |
55e957d8 | 4710 | struct snd_interval t = { |
1da177e4 LT |
4711 | .min = hdsp->ss_in_channels, |
4712 | .max = hdsp->ss_in_channels, | |
4713 | .integer = 1, | |
4714 | }; | |
4715 | return snd_interval_refine(c, &t); | |
4716 | } | |
4717 | return 0; | |
4718 | } | |
4719 | ||
55e957d8 TI |
4720 | static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, |
4721 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4722 | { |
55e957d8 TI |
4723 | struct hdsp *hdsp = rule->private; |
4724 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4725 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4726 | if (r->min > 96000 && hdsp->io_type == H9632) { |
55e957d8 | 4727 | struct snd_interval t = { |
1da177e4 LT |
4728 | .min = hdsp->qs_out_channels, |
4729 | .max = hdsp->qs_out_channels, | |
4730 | .integer = 1, | |
4731 | }; | |
f9ffc5d6 | 4732 | return snd_interval_refine(c, &t); |
1da177e4 | 4733 | } else if (r->min > 48000 && r->max <= 96000) { |
55e957d8 | 4734 | struct snd_interval t = { |
1da177e4 LT |
4735 | .min = hdsp->ds_out_channels, |
4736 | .max = hdsp->ds_out_channels, | |
4737 | .integer = 1, | |
4738 | }; | |
4739 | return snd_interval_refine(c, &t); | |
4740 | } else if (r->max < 64000) { | |
55e957d8 | 4741 | struct snd_interval t = { |
1da177e4 LT |
4742 | .min = hdsp->ss_out_channels, |
4743 | .max = hdsp->ss_out_channels, | |
4744 | .integer = 1, | |
4745 | }; | |
4746 | return snd_interval_refine(c, &t); | |
4747 | } | |
4748 | return 0; | |
4749 | } | |
4750 | ||
55e957d8 TI |
4751 | static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, |
4752 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4753 | { |
55e957d8 TI |
4754 | struct hdsp *hdsp = rule->private; |
4755 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4756 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4757 | if (c->min >= hdsp->ss_out_channels) { |
55e957d8 | 4758 | struct snd_interval t = { |
1da177e4 LT |
4759 | .min = 32000, |
4760 | .max = 48000, | |
4761 | .integer = 1, | |
4762 | }; | |
4763 | return snd_interval_refine(r, &t); | |
4764 | } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { | |
55e957d8 | 4765 | struct snd_interval t = { |
1da177e4 LT |
4766 | .min = 128000, |
4767 | .max = 192000, | |
4768 | .integer = 1, | |
4769 | }; | |
4770 | return snd_interval_refine(r, &t); | |
4771 | } else if (c->max <= hdsp->ds_out_channels) { | |
55e957d8 | 4772 | struct snd_interval t = { |
1da177e4 LT |
4773 | .min = 64000, |
4774 | .max = 96000, | |
4775 | .integer = 1, | |
4776 | }; | |
4777 | return snd_interval_refine(r, &t); | |
4778 | } | |
4779 | return 0; | |
4780 | } | |
4781 | ||
55e957d8 TI |
4782 | static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, |
4783 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4784 | { |
55e957d8 TI |
4785 | struct hdsp *hdsp = rule->private; |
4786 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4787 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4788 | if (c->min >= hdsp->ss_in_channels) { |
55e957d8 | 4789 | struct snd_interval t = { |
1da177e4 LT |
4790 | .min = 32000, |
4791 | .max = 48000, | |
4792 | .integer = 1, | |
4793 | }; | |
4794 | return snd_interval_refine(r, &t); | |
4795 | } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { | |
55e957d8 | 4796 | struct snd_interval t = { |
1da177e4 LT |
4797 | .min = 128000, |
4798 | .max = 192000, | |
4799 | .integer = 1, | |
4800 | }; | |
4801 | return snd_interval_refine(r, &t); | |
4802 | } else if (c->max <= hdsp->ds_in_channels) { | |
55e957d8 | 4803 | struct snd_interval t = { |
1da177e4 LT |
4804 | .min = 64000, |
4805 | .max = 96000, | |
4806 | .integer = 1, | |
4807 | }; | |
4808 | return snd_interval_refine(r, &t); | |
4809 | } | |
4810 | return 0; | |
4811 | } | |
4812 | ||
55e957d8 | 4813 | static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 4814 | { |
55e957d8 TI |
4815 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
4816 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 4817 | |
b0b98119 | 4818 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4819 | return -EIO; |
1da177e4 | 4820 | |
b0b98119 | 4821 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4822 | return -EIO; |
1da177e4 LT |
4823 | |
4824 | spin_lock_irq(&hdsp->lock); | |
4825 | ||
4826 | snd_pcm_set_sync(substream); | |
4827 | ||
4828 | runtime->hw = snd_hdsp_playback_subinfo; | |
4829 | runtime->dma_area = hdsp->playback_buffer; | |
4830 | runtime->dma_bytes = HDSP_DMA_AREA_BYTES; | |
4831 | ||
4832 | hdsp->playback_pid = current->pid; | |
4833 | hdsp->playback_substream = substream; | |
4834 | ||
4835 | spin_unlock_irq(&hdsp->lock); | |
4836 | ||
4837 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4838 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); | |
e3ea4d89 TI |
4839 | if (hdsp->clock_source_locked) { |
4840 | runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; | |
4841 | } else if (hdsp->io_type == H9632) { | |
1da177e4 LT |
4842 | runtime->hw.rate_max = 192000; |
4843 | runtime->hw.rates = SNDRV_PCM_RATE_KNOT; | |
4844 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); | |
4845 | } | |
e3ea4d89 TI |
4846 | if (hdsp->io_type == H9632) { |
4847 | runtime->hw.channels_min = hdsp->qs_out_channels; | |
4848 | runtime->hw.channels_max = hdsp->ss_out_channels; | |
f9ffc5d6 TB |
4849 | } |
4850 | ||
1da177e4 LT |
4851 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, |
4852 | snd_hdsp_hw_rule_out_channels, hdsp, | |
4853 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4854 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4855 | snd_hdsp_hw_rule_out_channels_rate, hdsp, | |
4856 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4857 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4858 | snd_hdsp_hw_rule_rate_out_channels, hdsp, | |
4859 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4860 | ||
28b26e15 FF |
4861 | if (RPM != hdsp->io_type) { |
4862 | hdsp->creg_spdif_stream = hdsp->creg_spdif; | |
4863 | hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
4864 | snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
4865 | SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); | |
4866 | } | |
1da177e4 LT |
4867 | return 0; |
4868 | } | |
4869 | ||
55e957d8 | 4870 | static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) |
1da177e4 | 4871 | { |
55e957d8 | 4872 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4873 | |
4874 | spin_lock_irq(&hdsp->lock); | |
4875 | ||
4876 | hdsp->playback_pid = -1; | |
4877 | hdsp->playback_substream = NULL; | |
4878 | ||
4879 | spin_unlock_irq(&hdsp->lock); | |
4880 | ||
28b26e15 FF |
4881 | if (RPM != hdsp->io_type) { |
4882 | hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
4883 | snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
4884 | SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); | |
4885 | } | |
1da177e4 LT |
4886 | return 0; |
4887 | } | |
4888 | ||
4889 | ||
55e957d8 | 4890 | static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 4891 | { |
55e957d8 TI |
4892 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
4893 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 4894 | |
b0b98119 | 4895 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4896 | return -EIO; |
1da177e4 | 4897 | |
b0b98119 | 4898 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4899 | return -EIO; |
1da177e4 LT |
4900 | |
4901 | spin_lock_irq(&hdsp->lock); | |
4902 | ||
4903 | snd_pcm_set_sync(substream); | |
4904 | ||
4905 | runtime->hw = snd_hdsp_capture_subinfo; | |
4906 | runtime->dma_area = hdsp->capture_buffer; | |
4907 | runtime->dma_bytes = HDSP_DMA_AREA_BYTES; | |
4908 | ||
4909 | hdsp->capture_pid = current->pid; | |
4910 | hdsp->capture_substream = substream; | |
4911 | ||
4912 | spin_unlock_irq(&hdsp->lock); | |
4913 | ||
4914 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4915 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); | |
4916 | if (hdsp->io_type == H9632) { | |
4917 | runtime->hw.channels_min = hdsp->qs_in_channels; | |
4918 | runtime->hw.channels_max = hdsp->ss_in_channels; | |
4919 | runtime->hw.rate_max = 192000; | |
4920 | runtime->hw.rates = SNDRV_PCM_RATE_KNOT; | |
4921 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); | |
4922 | } | |
4923 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4924 | snd_hdsp_hw_rule_in_channels, hdsp, | |
4925 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4926 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4927 | snd_hdsp_hw_rule_in_channels_rate, hdsp, | |
4928 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4929 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4930 | snd_hdsp_hw_rule_rate_in_channels, hdsp, | |
4931 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4932 | return 0; | |
4933 | } | |
4934 | ||
55e957d8 | 4935 | static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) |
1da177e4 | 4936 | { |
55e957d8 | 4937 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4938 | |
4939 | spin_lock_irq(&hdsp->lock); | |
4940 | ||
4941 | hdsp->capture_pid = -1; | |
4942 | hdsp->capture_substream = NULL; | |
4943 | ||
4944 | spin_unlock_irq(&hdsp->lock); | |
4945 | return 0; | |
4946 | } | |
4947 | ||
1da177e4 LT |
4948 | /* helper functions for copying meter values */ |
4949 | static inline int copy_u32_le(void __user *dest, void __iomem *src) | |
4950 | { | |
4951 | u32 val = readl(src); | |
4952 | return copy_to_user(dest, &val, 4); | |
4953 | } | |
4954 | ||
4955 | static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) | |
4956 | { | |
4957 | u32 rms_low, rms_high; | |
4958 | u64 rms; | |
4959 | rms_low = readl(src_low); | |
4960 | rms_high = readl(src_high); | |
4961 | rms = ((u64)rms_high << 32) | rms_low; | |
4962 | return copy_to_user(dest, &rms, 8); | |
4963 | } | |
4964 | ||
4965 | static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) | |
4966 | { | |
4967 | u32 rms_low, rms_high; | |
4968 | u64 rms; | |
4969 | rms_low = readl(src_low) & 0xffffff00; | |
4970 | rms_high = readl(src_high) & 0xffffff00; | |
4971 | rms = ((u64)rms_high << 32) | rms_low; | |
4972 | return copy_to_user(dest, &rms, 8); | |
4973 | } | |
4974 | ||
55e957d8 | 4975 | static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) |
1da177e4 LT |
4976 | { |
4977 | int doublespeed = 0; | |
4978 | int i, j, channels, ofs; | |
4979 | ||
4980 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) | |
4981 | doublespeed = 1; | |
4982 | channels = doublespeed ? 14 : 26; | |
4983 | for (i = 0, j = 0; i < 26; ++i) { | |
4984 | if (doublespeed && (i & 4)) | |
4985 | continue; | |
4986 | ofs = HDSP_9652_peakBase - j * 4; | |
4987 | if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) | |
4988 | return -EFAULT; | |
4989 | ofs -= channels * 4; | |
4990 | if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) | |
4991 | return -EFAULT; | |
4992 | ofs -= channels * 4; | |
4993 | if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) | |
4994 | return -EFAULT; | |
4995 | ofs = HDSP_9652_rmsBase + j * 8; | |
4996 | if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, | |
4997 | hdsp->iobase + ofs + 4)) | |
4998 | return -EFAULT; | |
4999 | ofs += channels * 8; | |
5000 | if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, | |
5001 | hdsp->iobase + ofs + 4)) | |
5002 | return -EFAULT; | |
5003 | ofs += channels * 8; | |
5004 | if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, | |
5005 | hdsp->iobase + ofs + 4)) | |
5006 | return -EFAULT; | |
5007 | j++; | |
5008 | } | |
5009 | return 0; | |
5010 | } | |
5011 | ||
55e957d8 | 5012 | static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) |
1da177e4 LT |
5013 | { |
5014 | int i, j; | |
55e957d8 | 5015 | struct hdsp_9632_meters __iomem *m; |
1da177e4 LT |
5016 | int doublespeed = 0; |
5017 | ||
5018 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) | |
5019 | doublespeed = 1; | |
55e957d8 | 5020 | m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); |
1da177e4 LT |
5021 | for (i = 0, j = 0; i < 16; ++i, ++j) { |
5022 | if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) | |
5023 | return -EFAULT; | |
5024 | if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) | |
5025 | return -EFAULT; | |
5026 | if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) | |
5027 | return -EFAULT; | |
5028 | if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], | |
5029 | &m->input_rms_high[j])) | |
5030 | return -EFAULT; | |
5031 | if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], | |
5032 | &m->playback_rms_high[j])) | |
5033 | return -EFAULT; | |
5034 | if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], | |
5035 | &m->output_rms_high[j])) | |
5036 | return -EFAULT; | |
5037 | if (doublespeed && i == 3) i += 4; | |
5038 | } | |
5039 | return 0; | |
5040 | } | |
5041 | ||
55e957d8 | 5042 | static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) |
1da177e4 LT |
5043 | { |
5044 | int i; | |
5045 | ||
5046 | for (i = 0; i < 26; i++) { | |
5047 | if (copy_u32_le(&peak_rms->playback_peaks[i], | |
5048 | hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) | |
5049 | return -EFAULT; | |
5050 | if (copy_u32_le(&peak_rms->input_peaks[i], | |
5051 | hdsp->iobase + HDSP_inputPeakLevel + i * 4)) | |
5052 | return -EFAULT; | |
5053 | } | |
5054 | for (i = 0; i < 28; i++) { | |
5055 | if (copy_u32_le(&peak_rms->output_peaks[i], | |
5056 | hdsp->iobase + HDSP_outputPeakLevel + i * 4)) | |
5057 | return -EFAULT; | |
5058 | } | |
5059 | for (i = 0; i < 26; ++i) { | |
5060 | if (copy_u64_le(&peak_rms->playback_rms[i], | |
5061 | hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, | |
5062 | hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) | |
5063 | return -EFAULT; | |
f9ffc5d6 | 5064 | if (copy_u64_le(&peak_rms->input_rms[i], |
1da177e4 LT |
5065 | hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, |
5066 | hdsp->iobase + HDSP_inputRmsLevel + i * 8)) | |
5067 | return -EFAULT; | |
5068 | } | |
5069 | return 0; | |
5070 | } | |
5071 | ||
55e957d8 | 5072 | static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) |
1da177e4 | 5073 | { |
9fe856e4 | 5074 | struct hdsp *hdsp = hw->private_data; |
1da177e4 | 5075 | void __user *argp = (void __user *)arg; |
3ae7e2e2 | 5076 | int err; |
1da177e4 LT |
5077 | |
5078 | switch (cmd) { | |
5079 | case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { | |
55e957d8 | 5080 | struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; |
1da177e4 | 5081 | |
3ae7e2e2 TB |
5082 | err = hdsp_check_for_iobox(hdsp); |
5083 | if (err < 0) | |
5084 | return err; | |
5085 | ||
5086 | err = hdsp_check_for_firmware(hdsp, 1); | |
5087 | if (err < 0) | |
5088 | return err; | |
5089 | ||
1da177e4 LT |
5090 | if (!(hdsp->state & HDSP_FirmwareLoaded)) { |
5091 | snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); | |
5092 | return -EINVAL; | |
5093 | } | |
5094 | ||
5095 | switch (hdsp->io_type) { | |
5096 | case H9652: | |
5097 | return hdsp_9652_get_peak(hdsp, peak_rms); | |
5098 | case H9632: | |
5099 | return hdsp_9632_get_peak(hdsp, peak_rms); | |
5100 | default: | |
5101 | return hdsp_get_peak(hdsp, peak_rms); | |
5102 | } | |
5103 | } | |
5104 | case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { | |
55e957d8 | 5105 | struct hdsp_config_info info; |
1da177e4 LT |
5106 | unsigned long flags; |
5107 | int i; | |
f9ffc5d6 | 5108 | |
3ae7e2e2 TB |
5109 | err = hdsp_check_for_iobox(hdsp); |
5110 | if (err < 0) | |
5111 | return err; | |
5112 | ||
5113 | err = hdsp_check_for_firmware(hdsp, 1); | |
5114 | if (err < 0) | |
5115 | return err; | |
5116 | ||
e68d3b31 | 5117 | memset(&info, 0, sizeof(info)); |
1da177e4 LT |
5118 | spin_lock_irqsave(&hdsp->lock, flags); |
5119 | info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); | |
5120 | info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); | |
b0b98119 | 5121 | if (hdsp->io_type != H9632) |
1da177e4 | 5122 | info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); |
1da177e4 | 5123 | info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); |
28b26e15 | 5124 | for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i) |
1da177e4 | 5125 | info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); |
1da177e4 LT |
5126 | info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); |
5127 | info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); | |
5128 | info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); | |
5129 | info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); | |
5130 | info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); | |
5131 | info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); | |
5132 | info.system_sample_rate = hdsp->system_sample_rate; | |
5133 | info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); | |
5134 | info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); | |
5135 | info.clock_source = (unsigned char)hdsp_clock_source(hdsp); | |
5136 | info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); | |
5137 | info.line_out = (unsigned char)hdsp_line_out(hdsp); | |
5138 | if (hdsp->io_type == H9632) { | |
5139 | info.da_gain = (unsigned char)hdsp_da_gain(hdsp); | |
5140 | info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); | |
5141 | info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); | |
5142 | info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); | |
f9ffc5d6 | 5143 | |
28b26e15 FF |
5144 | } else if (hdsp->io_type == RPM) { |
5145 | info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp); | |
5146 | info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp); | |
1da177e4 | 5147 | } |
b0b98119 | 5148 | if (hdsp->io_type == H9632 || hdsp->io_type == H9652) |
1da177e4 | 5149 | info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); |
1da177e4 LT |
5150 | spin_unlock_irqrestore(&hdsp->lock, flags); |
5151 | if (copy_to_user(argp, &info, sizeof(info))) | |
5152 | return -EFAULT; | |
5153 | break; | |
5154 | } | |
5155 | case SNDRV_HDSP_IOCTL_GET_9632_AEB: { | |
55e957d8 | 5156 | struct hdsp_9632_aeb h9632_aeb; |
f9ffc5d6 | 5157 | |
1da177e4 LT |
5158 | if (hdsp->io_type != H9632) return -EINVAL; |
5159 | h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; | |
5160 | h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; | |
5161 | if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) | |
5162 | return -EFAULT; | |
5163 | break; | |
5164 | } | |
5165 | case SNDRV_HDSP_IOCTL_GET_VERSION: { | |
55e957d8 | 5166 | struct hdsp_version hdsp_version; |
1da177e4 | 5167 | int err; |
f9ffc5d6 | 5168 | |
1da177e4 LT |
5169 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; |
5170 | if (hdsp->io_type == Undefined) { | |
b0b98119 | 5171 | if ((err = hdsp_get_iobox_version(hdsp)) < 0) |
1da177e4 | 5172 | return err; |
1da177e4 LT |
5173 | } |
5174 | hdsp_version.io_type = hdsp->io_type; | |
5175 | hdsp_version.firmware_rev = hdsp->firmware_rev; | |
b0b98119 | 5176 | if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) |
1da177e4 | 5177 | return -EFAULT; |
1da177e4 LT |
5178 | break; |
5179 | } | |
5180 | case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { | |
55e957d8 | 5181 | struct hdsp_firmware __user *firmware; |
1da177e4 LT |
5182 | u32 __user *firmware_data; |
5183 | int err; | |
f9ffc5d6 | 5184 | |
1da177e4 LT |
5185 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; |
5186 | /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ | |
5187 | if (hdsp->io_type == Undefined) return -EINVAL; | |
5188 | ||
5189 | if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) | |
5190 | return -EBUSY; | |
5191 | ||
b0b98119 | 5192 | snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n"); |
55e957d8 | 5193 | firmware = (struct hdsp_firmware __user *)argp; |
1da177e4 | 5194 | |
b0b98119 | 5195 | if (get_user(firmware_data, &firmware->firmware_data)) |
1da177e4 | 5196 | return -EFAULT; |
f9ffc5d6 | 5197 | |
b0b98119 | 5198 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 5199 | return -EIO; |
1da177e4 | 5200 | |
90caaef6 TI |
5201 | if (!hdsp->fw_uploaded) { |
5202 | hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE); | |
5203 | if (!hdsp->fw_uploaded) | |
5204 | return -ENOMEM; | |
5205 | } | |
5206 | ||
5207 | if (copy_from_user(hdsp->fw_uploaded, firmware_data, | |
5208 | HDSP_FIRMWARE_SIZE)) { | |
5209 | vfree(hdsp->fw_uploaded); | |
5210 | hdsp->fw_uploaded = NULL; | |
1da177e4 | 5211 | return -EFAULT; |
90caaef6 | 5212 | } |
f9ffc5d6 | 5213 | |
1da177e4 LT |
5214 | hdsp->state |= HDSP_FirmwareCached; |
5215 | ||
b0b98119 | 5216 | if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) |
1da177e4 | 5217 | return err; |
f9ffc5d6 | 5218 | |
1da177e4 | 5219 | if (!(hdsp->state & HDSP_InitializationComplete)) { |
b0b98119 | 5220 | if ((err = snd_hdsp_enable_io(hdsp)) < 0) |
1da177e4 | 5221 | return err; |
f9ffc5d6 TB |
5222 | |
5223 | snd_hdsp_initialize_channels(hdsp); | |
1da177e4 | 5224 | snd_hdsp_initialize_midi_flush(hdsp); |
f9ffc5d6 | 5225 | |
1da177e4 | 5226 | if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { |
b0b98119 TI |
5227 | snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); |
5228 | return err; | |
1da177e4 LT |
5229 | } |
5230 | } | |
5231 | break; | |
5232 | } | |
5233 | case SNDRV_HDSP_IOCTL_GET_MIXER: { | |
55e957d8 | 5234 | struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; |
1da177e4 LT |
5235 | if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) |
5236 | return -EFAULT; | |
5237 | break; | |
5238 | } | |
5239 | default: | |
5240 | return -EINVAL; | |
5241 | } | |
5242 | return 0; | |
5243 | } | |
5244 | ||
55e957d8 | 5245 | static struct snd_pcm_ops snd_hdsp_playback_ops = { |
1da177e4 LT |
5246 | .open = snd_hdsp_playback_open, |
5247 | .close = snd_hdsp_playback_release, | |
5248 | .ioctl = snd_hdsp_ioctl, | |
5249 | .hw_params = snd_hdsp_hw_params, | |
5250 | .prepare = snd_hdsp_prepare, | |
5251 | .trigger = snd_hdsp_trigger, | |
5252 | .pointer = snd_hdsp_hw_pointer, | |
5253 | .copy = snd_hdsp_playback_copy, | |
5254 | .silence = snd_hdsp_hw_silence, | |
5255 | }; | |
5256 | ||
55e957d8 | 5257 | static struct snd_pcm_ops snd_hdsp_capture_ops = { |
1da177e4 LT |
5258 | .open = snd_hdsp_capture_open, |
5259 | .close = snd_hdsp_capture_release, | |
5260 | .ioctl = snd_hdsp_ioctl, | |
5261 | .hw_params = snd_hdsp_hw_params, | |
5262 | .prepare = snd_hdsp_prepare, | |
5263 | .trigger = snd_hdsp_trigger, | |
5264 | .pointer = snd_hdsp_hw_pointer, | |
5265 | .copy = snd_hdsp_capture_copy, | |
5266 | }; | |
5267 | ||
92eed66d | 5268 | static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 | 5269 | { |
55e957d8 | 5270 | struct snd_hwdep *hw; |
1da177e4 | 5271 | int err; |
f9ffc5d6 | 5272 | |
1da177e4 LT |
5273 | if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) |
5274 | return err; | |
f9ffc5d6 | 5275 | |
1da177e4 LT |
5276 | hdsp->hwdep = hw; |
5277 | hw->private_data = hdsp; | |
5278 | strcpy(hw->name, "HDSP hwdep interface"); | |
5279 | ||
1da177e4 | 5280 | hw->ops.ioctl = snd_hdsp_hwdep_ioctl; |
42eb9238 | 5281 | hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl; |
f9ffc5d6 | 5282 | |
1da177e4 LT |
5283 | return 0; |
5284 | } | |
5285 | ||
55e957d8 | 5286 | static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 | 5287 | { |
55e957d8 | 5288 | struct snd_pcm *pcm; |
1da177e4 LT |
5289 | int err; |
5290 | ||
5291 | if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0) | |
5292 | return err; | |
5293 | ||
5294 | hdsp->pcm = pcm; | |
5295 | pcm->private_data = hdsp; | |
5296 | strcpy(pcm->name, hdsp->card_name); | |
5297 | ||
5298 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); | |
5299 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); | |
5300 | ||
5301 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
5302 | ||
5303 | return 0; | |
5304 | } | |
5305 | ||
55e957d8 | 5306 | static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) |
1da177e4 LT |
5307 | { |
5308 | hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; | |
5309 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
5310 | } | |
5311 | ||
55e957d8 | 5312 | static int snd_hdsp_enable_io (struct hdsp *hdsp) |
1da177e4 LT |
5313 | { |
5314 | int i; | |
f9ffc5d6 | 5315 | |
1da177e4 | 5316 | if (hdsp_fifo_wait (hdsp, 0, 100)) { |
b0b98119 | 5317 | snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n"); |
1da177e4 LT |
5318 | return -EIO; |
5319 | } | |
f9ffc5d6 | 5320 | |
1da177e4 LT |
5321 | for (i = 0; i < hdsp->max_channels; ++i) { |
5322 | hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); | |
5323 | hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); | |
5324 | } | |
f9ffc5d6 | 5325 | |
1da177e4 LT |
5326 | return 0; |
5327 | } | |
5328 | ||
55e957d8 | 5329 | static void snd_hdsp_initialize_channels(struct hdsp *hdsp) |
1da177e4 LT |
5330 | { |
5331 | int status, aebi_channels, aebo_channels; | |
f9ffc5d6 | 5332 | |
1da177e4 LT |
5333 | switch (hdsp->io_type) { |
5334 | case Digiface: | |
5335 | hdsp->card_name = "RME Hammerfall DSP + Digiface"; | |
5336 | hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; | |
5337 | hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; | |
5338 | break; | |
5339 | ||
5340 | case H9652: | |
5341 | hdsp->card_name = "RME Hammerfall HDSP 9652"; | |
5342 | hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; | |
5343 | hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; | |
5344 | break; | |
f9ffc5d6 | 5345 | |
1da177e4 LT |
5346 | case H9632: |
5347 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
5348 | /* HDSP_AEBx bits are low when AEB are connected */ | |
5349 | aebi_channels = (status & HDSP_AEBI) ? 0 : 4; | |
5350 | aebo_channels = (status & HDSP_AEBO) ? 0 : 4; | |
5351 | hdsp->card_name = "RME Hammerfall HDSP 9632"; | |
5352 | hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; | |
5353 | hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; | |
5354 | hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; | |
5355 | hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; | |
5356 | hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; | |
5357 | hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; | |
5358 | break; | |
5359 | ||
5360 | case Multiface: | |
5361 | hdsp->card_name = "RME Hammerfall DSP + Multiface"; | |
5362 | hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; | |
5363 | hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; | |
5364 | break; | |
f9ffc5d6 | 5365 | |
28b26e15 FF |
5366 | case RPM: |
5367 | hdsp->card_name = "RME Hammerfall DSP + RPM"; | |
5368 | hdsp->ss_in_channels = RPM_CHANNELS-1; | |
5369 | hdsp->ss_out_channels = RPM_CHANNELS; | |
5370 | hdsp->ds_in_channels = RPM_CHANNELS-1; | |
5371 | hdsp->ds_out_channels = RPM_CHANNELS; | |
5372 | break; | |
5373 | ||
1da177e4 LT |
5374 | default: |
5375 | /* should never get here */ | |
5376 | break; | |
5377 | } | |
5378 | } | |
5379 | ||
55e957d8 | 5380 | static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) |
1da177e4 LT |
5381 | { |
5382 | snd_hdsp_flush_midi_input (hdsp, 0); | |
5383 | snd_hdsp_flush_midi_input (hdsp, 1); | |
5384 | } | |
5385 | ||
55e957d8 | 5386 | static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 LT |
5387 | { |
5388 | int err; | |
f9ffc5d6 | 5389 | |
1da177e4 | 5390 | if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { |
b0b98119 | 5391 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n"); |
1da177e4 LT |
5392 | return err; |
5393 | } | |
f9ffc5d6 | 5394 | |
1da177e4 LT |
5395 | |
5396 | if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { | |
b0b98119 | 5397 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n"); |
1da177e4 LT |
5398 | return err; |
5399 | } | |
5400 | ||
5401 | if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { | |
5402 | if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { | |
b0b98119 | 5403 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n"); |
1da177e4 LT |
5404 | return err; |
5405 | } | |
5406 | } | |
5407 | ||
5408 | if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { | |
b0b98119 | 5409 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n"); |
1da177e4 LT |
5410 | return err; |
5411 | } | |
5412 | ||
5413 | snd_hdsp_proc_init(hdsp); | |
5414 | ||
5415 | hdsp->system_sample_rate = -1; | |
5416 | hdsp->playback_pid = -1; | |
5417 | hdsp->capture_pid = -1; | |
5418 | hdsp->capture_substream = NULL; | |
5419 | hdsp->playback_substream = NULL; | |
5420 | ||
5421 | if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { | |
b0b98119 | 5422 | snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n"); |
1da177e4 LT |
5423 | return err; |
5424 | } | |
f9ffc5d6 | 5425 | |
1da177e4 | 5426 | if (!(hdsp->state & HDSP_InitializationComplete)) { |
b73c1c12 | 5427 | strcpy(card->shortname, "Hammerfall DSP"); |
f9ffc5d6 | 5428 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, |
1da177e4 | 5429 | hdsp->port, hdsp->irq); |
f9ffc5d6 | 5430 | |
1da177e4 | 5431 | if ((err = snd_card_register(card)) < 0) { |
b0b98119 | 5432 | snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n"); |
1da177e4 LT |
5433 | return err; |
5434 | } | |
5435 | hdsp->state |= HDSP_InitializationComplete; | |
5436 | } | |
f9ffc5d6 | 5437 | |
1da177e4 LT |
5438 | return 0; |
5439 | } | |
5440 | ||
1da177e4 | 5441 | /* load firmware via hotplug fw loader */ |
92eed66d | 5442 | static int hdsp_request_fw_loader(struct hdsp *hdsp) |
1da177e4 LT |
5443 | { |
5444 | const char *fwfile; | |
5445 | const struct firmware *fw; | |
5446 | int err; | |
f9ffc5d6 | 5447 | |
1da177e4 LT |
5448 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) |
5449 | return 0; | |
5450 | if (hdsp->io_type == Undefined) { | |
5451 | if ((err = hdsp_get_iobox_version(hdsp)) < 0) | |
5452 | return err; | |
5453 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) | |
5454 | return 0; | |
5455 | } | |
f9ffc5d6 | 5456 | |
1da177e4 LT |
5457 | /* caution: max length of firmware filename is 30! */ |
5458 | switch (hdsp->io_type) { | |
28b26e15 FF |
5459 | case RPM: |
5460 | fwfile = "rpm_firmware.bin"; | |
5461 | break; | |
1da177e4 LT |
5462 | case Multiface: |
5463 | if (hdsp->firmware_rev == 0xa) | |
5464 | fwfile = "multiface_firmware.bin"; | |
5465 | else | |
5466 | fwfile = "multiface_firmware_rev11.bin"; | |
5467 | break; | |
5468 | case Digiface: | |
5469 | if (hdsp->firmware_rev == 0xa) | |
5470 | fwfile = "digiface_firmware.bin"; | |
5471 | else | |
5472 | fwfile = "digiface_firmware_rev11.bin"; | |
5473 | break; | |
5474 | default: | |
5475 | snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type); | |
5476 | return -EINVAL; | |
5477 | } | |
5478 | ||
5479 | if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { | |
5480 | snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile); | |
5481 | return -ENOENT; | |
5482 | } | |
90caaef6 | 5483 | if (fw->size < HDSP_FIRMWARE_SIZE) { |
1da177e4 | 5484 | snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", |
90caaef6 | 5485 | (int)fw->size, HDSP_FIRMWARE_SIZE); |
1da177e4 LT |
5486 | return -EINVAL; |
5487 | } | |
7679a030 | 5488 | |
90caaef6 | 5489 | hdsp->firmware = fw; |
f9ffc5d6 | 5490 | |
1da177e4 LT |
5491 | hdsp->state |= HDSP_FirmwareCached; |
5492 | ||
5493 | if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) | |
5494 | return err; | |
f9ffc5d6 | 5495 | |
1da177e4 | 5496 | if (!(hdsp->state & HDSP_InitializationComplete)) { |
b0b98119 | 5497 | if ((err = snd_hdsp_enable_io(hdsp)) < 0) |
1da177e4 | 5498 | return err; |
1da177e4 LT |
5499 | |
5500 | if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) { | |
b0b98119 | 5501 | snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n"); |
1da177e4 LT |
5502 | return err; |
5503 | } | |
5504 | snd_hdsp_initialize_channels(hdsp); | |
5505 | snd_hdsp_initialize_midi_flush(hdsp); | |
5506 | if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { | |
b0b98119 | 5507 | snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); |
1da177e4 LT |
5508 | return err; |
5509 | } | |
5510 | } | |
5511 | return 0; | |
5512 | } | |
1da177e4 | 5513 | |
e23e7a14 BP |
5514 | static int snd_hdsp_create(struct snd_card *card, |
5515 | struct hdsp *hdsp) | |
1da177e4 LT |
5516 | { |
5517 | struct pci_dev *pci = hdsp->pci; | |
5518 | int err; | |
5519 | int is_9652 = 0; | |
5520 | int is_9632 = 0; | |
5521 | ||
5522 | hdsp->irq = -1; | |
5523 | hdsp->state = 0; | |
5524 | hdsp->midi[0].rmidi = NULL; | |
5525 | hdsp->midi[1].rmidi = NULL; | |
5526 | hdsp->midi[0].input = NULL; | |
5527 | hdsp->midi[1].input = NULL; | |
5528 | hdsp->midi[0].output = NULL; | |
5529 | hdsp->midi[1].output = NULL; | |
5530 | hdsp->midi[0].pending = 0; | |
5531 | hdsp->midi[1].pending = 0; | |
5532 | spin_lock_init(&hdsp->midi[0].lock); | |
5533 | spin_lock_init(&hdsp->midi[1].lock); | |
5534 | hdsp->iobase = NULL; | |
5535 | hdsp->control_register = 0; | |
5536 | hdsp->control2_register = 0; | |
5537 | hdsp->io_type = Undefined; | |
5538 | hdsp->max_channels = 26; | |
5539 | ||
5540 | hdsp->card = card; | |
f9ffc5d6 | 5541 | |
1da177e4 LT |
5542 | spin_lock_init(&hdsp->lock); |
5543 | ||
5544 | tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); | |
f9ffc5d6 | 5545 | |
1da177e4 LT |
5546 | pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); |
5547 | hdsp->firmware_rev &= 0xff; | |
f9ffc5d6 | 5548 | |
1da177e4 LT |
5549 | /* From Martin Bjoernsen : |
5550 | "It is important that the card's latency timer register in | |
5551 | the PCI configuration space is set to a value much larger | |
5552 | than 0 by the computer's BIOS or the driver. | |
5553 | The windows driver always sets this 8 bit register [...] | |
5554 | to its maximum 255 to avoid problems with some computers." | |
5555 | */ | |
5556 | pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); | |
f9ffc5d6 | 5557 | |
1da177e4 LT |
5558 | strcpy(card->driver, "H-DSP"); |
5559 | strcpy(card->mixername, "Xilinx FPGA"); | |
5560 | ||
b0b98119 | 5561 | if (hdsp->firmware_rev < 0xa) |
1da177e4 | 5562 | return -ENODEV; |
b0b98119 | 5563 | else if (hdsp->firmware_rev < 0x64) |
1da177e4 | 5564 | hdsp->card_name = "RME Hammerfall DSP"; |
b0b98119 | 5565 | else if (hdsp->firmware_rev < 0x96) { |
1da177e4 LT |
5566 | hdsp->card_name = "RME HDSP 9652"; |
5567 | is_9652 = 1; | |
5568 | } else { | |
5569 | hdsp->card_name = "RME HDSP 9632"; | |
5570 | hdsp->max_channels = 16; | |
f9ffc5d6 | 5571 | is_9632 = 1; |
1da177e4 LT |
5572 | } |
5573 | ||
b0b98119 | 5574 | if ((err = pci_enable_device(pci)) < 0) |
1da177e4 | 5575 | return err; |
1da177e4 LT |
5576 | |
5577 | pci_set_master(hdsp->pci); | |
5578 | ||
5579 | if ((err = pci_request_regions(pci, "hdsp")) < 0) | |
5580 | return err; | |
5581 | hdsp->port = pci_resource_start(pci, 0); | |
5582 | if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) { | |
b0b98119 | 5583 | snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); |
1da177e4 LT |
5584 | return -EBUSY; |
5585 | } | |
5586 | ||
437a5a46 | 5587 | if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED, |
934c2b6d | 5588 | KBUILD_MODNAME, hdsp)) { |
b0b98119 | 5589 | snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq); |
1da177e4 LT |
5590 | return -EBUSY; |
5591 | } | |
5592 | ||
5593 | hdsp->irq = pci->irq; | |
176546ab | 5594 | hdsp->precise_ptr = 0; |
1da177e4 | 5595 | hdsp->use_midi_tasklet = 1; |
d7923b2a | 5596 | hdsp->dds_value = 0; |
1da177e4 | 5597 | |
b0b98119 | 5598 | if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) |
1da177e4 | 5599 | return err; |
f9ffc5d6 | 5600 | |
1da177e4 | 5601 | if (!is_9652 && !is_9632) { |
e588ed83 TB |
5602 | /* we wait a maximum of 10 seconds to let freshly |
5603 | * inserted cardbus cards do their hardware init */ | |
5604 | err = hdsp_wait_for_iobox(hdsp, 1000, 10); | |
1da177e4 | 5605 | |
00c9ddd1 TB |
5606 | if (err < 0) |
5607 | return err; | |
5608 | ||
1da177e4 | 5609 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { |
b0b98119 | 5610 | if ((err = hdsp_request_fw_loader(hdsp)) < 0) |
1da177e4 LT |
5611 | /* we don't fail as this can happen |
5612 | if userspace is not ready for | |
5613 | firmware upload | |
5614 | */ | |
b0b98119 TI |
5615 | snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n"); |
5616 | else | |
1da177e4 LT |
5617 | /* init is complete, we return */ |
5618 | return 0; | |
00c9ddd1 | 5619 | /* we defer initialization */ |
b0b98119 TI |
5620 | snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n"); |
5621 | if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) | |
1da177e4 | 5622 | return err; |
1da177e4 LT |
5623 | return 0; |
5624 | } else { | |
f9ffc5d6 | 5625 | snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n"); |
28b26e15 FF |
5626 | if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2) |
5627 | hdsp->io_type = RPM; | |
5628 | else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) | |
1da177e4 | 5629 | hdsp->io_type = Multiface; |
f9ffc5d6 | 5630 | else |
1da177e4 | 5631 | hdsp->io_type = Digiface; |
1da177e4 LT |
5632 | } |
5633 | } | |
f9ffc5d6 | 5634 | |
b0b98119 | 5635 | if ((err = snd_hdsp_enable_io(hdsp)) != 0) |
1da177e4 | 5636 | return err; |
f9ffc5d6 | 5637 | |
b0b98119 | 5638 | if (is_9652) |
1da177e4 | 5639 | hdsp->io_type = H9652; |
f9ffc5d6 | 5640 | |
b0b98119 | 5641 | if (is_9632) |
1da177e4 | 5642 | hdsp->io_type = H9632; |
1da177e4 | 5643 | |
b0b98119 | 5644 | if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) |
1da177e4 | 5645 | return err; |
f9ffc5d6 | 5646 | |
1da177e4 LT |
5647 | snd_hdsp_initialize_channels(hdsp); |
5648 | snd_hdsp_initialize_midi_flush(hdsp); | |
5649 | ||
f9ffc5d6 | 5650 | hdsp->state |= HDSP_FirmwareLoaded; |
1da177e4 | 5651 | |
b0b98119 | 5652 | if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) |
1da177e4 | 5653 | return err; |
1da177e4 | 5654 | |
f9ffc5d6 | 5655 | return 0; |
1da177e4 LT |
5656 | } |
5657 | ||
55e957d8 | 5658 | static int snd_hdsp_free(struct hdsp *hdsp) |
1da177e4 LT |
5659 | { |
5660 | if (hdsp->port) { | |
5661 | /* stop the audio, and cancel all interrupts */ | |
5662 | tasklet_kill(&hdsp->midi_tasklet); | |
5663 | hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); | |
5664 | hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); | |
5665 | } | |
5666 | ||
5667 | if (hdsp->irq >= 0) | |
5668 | free_irq(hdsp->irq, (void *)hdsp); | |
5669 | ||
5670 | snd_hdsp_free_buffers(hdsp); | |
f9ffc5d6 | 5671 | |
90caaef6 TI |
5672 | if (hdsp->firmware) |
5673 | release_firmware(hdsp->firmware); | |
5674 | vfree(hdsp->fw_uploaded); | |
5675 | ||
1da177e4 LT |
5676 | if (hdsp->iobase) |
5677 | iounmap(hdsp->iobase); | |
5678 | ||
5679 | if (hdsp->port) | |
5680 | pci_release_regions(hdsp->pci); | |
f9ffc5d6 | 5681 | |
1da177e4 LT |
5682 | pci_disable_device(hdsp->pci); |
5683 | return 0; | |
5684 | } | |
5685 | ||
55e957d8 | 5686 | static void snd_hdsp_card_free(struct snd_card *card) |
1da177e4 | 5687 | { |
9fe856e4 | 5688 | struct hdsp *hdsp = card->private_data; |
1da177e4 LT |
5689 | |
5690 | if (hdsp) | |
5691 | snd_hdsp_free(hdsp); | |
5692 | } | |
5693 | ||
e23e7a14 BP |
5694 | static int snd_hdsp_probe(struct pci_dev *pci, |
5695 | const struct pci_device_id *pci_id) | |
1da177e4 LT |
5696 | { |
5697 | static int dev; | |
55e957d8 TI |
5698 | struct hdsp *hdsp; |
5699 | struct snd_card *card; | |
1da177e4 LT |
5700 | int err; |
5701 | ||
5702 | if (dev >= SNDRV_CARDS) | |
5703 | return -ENODEV; | |
5704 | if (!enable[dev]) { | |
5705 | dev++; | |
5706 | return -ENOENT; | |
5707 | } | |
5708 | ||
e58de7ba TI |
5709 | err = snd_card_create(index[dev], id[dev], THIS_MODULE, |
5710 | sizeof(struct hdsp), &card); | |
5711 | if (err < 0) | |
5712 | return err; | |
1da177e4 | 5713 | |
9fe856e4 | 5714 | hdsp = card->private_data; |
1da177e4 LT |
5715 | card->private_free = snd_hdsp_card_free; |
5716 | hdsp->dev = dev; | |
5717 | hdsp->pci = pci; | |
5718 | snd_card_set_dev(card, &pci->dev); | |
5719 | ||
5720 | if ((err = snd_hdsp_create(card, hdsp)) < 0) { | |
5721 | snd_card_free(card); | |
5722 | return err; | |
5723 | } | |
5724 | ||
5725 | strcpy(card->shortname, "Hammerfall DSP"); | |
f9ffc5d6 | 5726 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, |
1da177e4 LT |
5727 | hdsp->port, hdsp->irq); |
5728 | ||
5729 | if ((err = snd_card_register(card)) < 0) { | |
5730 | snd_card_free(card); | |
5731 | return err; | |
5732 | } | |
5733 | pci_set_drvdata(pci, card); | |
5734 | dev++; | |
5735 | return 0; | |
5736 | } | |
5737 | ||
e23e7a14 | 5738 | static void snd_hdsp_remove(struct pci_dev *pci) |
1da177e4 LT |
5739 | { |
5740 | snd_card_free(pci_get_drvdata(pci)); | |
5741 | pci_set_drvdata(pci, NULL); | |
5742 | } | |
5743 | ||
e9f66d9b | 5744 | static struct pci_driver hdsp_driver = { |
3733e424 | 5745 | .name = KBUILD_MODNAME, |
1da177e4 LT |
5746 | .id_table = snd_hdsp_ids, |
5747 | .probe = snd_hdsp_probe, | |
e23e7a14 | 5748 | .remove = snd_hdsp_remove, |
1da177e4 LT |
5749 | }; |
5750 | ||
e9f66d9b | 5751 | module_pci_driver(hdsp_driver); |