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ASoC: mop500: Staticize non exported struct
[deliverable/linux.git] / sound / soc / codecs / ab8500-codec.c
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679d7abd
OL		 1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
6 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
7 * for ST-Ericsson.
8 *
9 * Based on the early work done by:
10 * Mikko J. Lehto <mikko.lehto@symbio.com>,
11 * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
12 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
13 * for ST-Ericsson.
14 *
15 * License terms:
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License version 2 as published
19 * by the Free Software Foundation.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/slab.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <linux/platform_device.h>
31#include <linux/mutex.h>
32#include <linux/mfd/abx500/ab8500.h>
33#include <linux/mfd/abx500.h>
34#include <linux/mfd/abx500/ab8500-sysctrl.h>
35#include <linux/mfd/abx500/ab8500-codec.h>
36#include <linux/regulator/consumer.h>
db5c811d 37#include <linux/of.h>
679d7abd
OL		 38
39#include <sound/core.h>
40#include <sound/pcm.h>
41#include <sound/pcm_params.h>
42#include <sound/initval.h>
43#include <sound/soc.h>
44#include <sound/soc-dapm.h>
45#include <sound/tlv.h>
46
47#include "ab8500-codec.h"
48
49/* Macrocell value definitions */
50#define CLK_32K_OUT2_DISABLE 0x01
51#define INACTIVE_RESET_AUDIO 0x02
52#define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
53#define ENABLE_VINTCORE12_SUPPLY 0x04
54#define GPIO27_DIR_OUTPUT 0x04
55#define GPIO29_DIR_OUTPUT 0x10
56#define GPIO31_DIR_OUTPUT 0x40
57
58/* Macrocell register definitions */
59#define AB8500_CTRL3_REG 0x0200
60#define AB8500_GPIO_DIR4_REG 0x1013
61
62/* Nr of FIR/IIR-coeff banks in ANC-block */
63#define AB8500_NR_OF_ANC_COEFF_BANKS 2
64
65/* Minimum duration to keep ANC IIR Init bit high or
66low before proceeding with the configuration sequence */
67#define AB8500_ANC_SM_DELAY 2000
68
69#define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
70{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
71 .info = filter_control_info, \
72 .get = filter_control_get, .put = filter_control_put, \
73 .private_value = (unsigned long)&(struct filter_control) \
74 {.count = xcount, .min = xmin, .max = xmax} }
75
76struct filter_control {
77 long min, max;
78 unsigned int count;
79 long value[128];
80};
81
82/* Sidetone states */
83static const char * const enum_sid_state[] = {
84 "Unconfigured",
85 "Apply FIR",
86 "FIR is configured",
87};
88enum sid_state {
89 SID_UNCONFIGURED = 0,
90 SID_APPLY_FIR = 1,
91 SID_FIR_CONFIGURED = 2,
92};
93
94static const char * const enum_anc_state[] = {
95 "Unconfigured",
96 "Apply FIR and IIR",
97 "FIR and IIR are configured",
98 "Apply FIR",
99 "FIR is configured",
100 "Apply IIR",
101 "IIR is configured"
102};
103enum anc_state {
104 ANC_UNCONFIGURED = 0,
105 ANC_APPLY_FIR_IIR = 1,
106 ANC_FIR_IIR_CONFIGURED = 2,
107 ANC_APPLY_FIR = 3,
108 ANC_FIR_CONFIGURED = 4,
109 ANC_APPLY_IIR = 5,
110 ANC_IIR_CONFIGURED = 6
111};
112
113/* Analog microphones */
114enum amic_idx {
115 AMIC_IDX_1A,
116 AMIC_IDX_1B,
117 AMIC_IDX_2
118};
119
120struct ab8500_codec_drvdata_dbg {
121 struct regulator *vaud;
122 struct regulator *vamic1;
123 struct regulator *vamic2;
124 struct regulator *vdmic;
125};
126
127/* Private data for AB8500 device-driver */
128struct ab8500_codec_drvdata {
129 /* Sidetone */
130 long *sid_fir_values;
131 enum sid_state sid_status;
132
133 /* ANC */
134 struct mutex anc_lock;
135 long *anc_fir_values;
136 long *anc_iir_values;
137 enum anc_state anc_status;
138};
139
140static inline const char *amic_micbias_str(enum amic_micbias micbias)
141{
142 switch (micbias) {
143 case AMIC_MICBIAS_VAMIC1:
144 return "VAMIC1";
145 case AMIC_MICBIAS_VAMIC2:
146 return "VAMIC2";
147 default:
148 return "Unknown";
149 }
150}
151
152static inline const char *amic_type_str(enum amic_type type)
153{
154 switch (type) {
155 case AMIC_TYPE_DIFFERENTIAL:
156 return "DIFFERENTIAL";
157 case AMIC_TYPE_SINGLE_ENDED:
158 return "SINGLE ENDED";
159 default:
160 return "Unknown";
161 }
162}
163
164/*
165 * Read'n'write functions
166 */
167
168/* Read a register from the audio-bank of AB8500 */
169static unsigned int ab8500_codec_read_reg(struct snd_soc_codec *codec,
170 unsigned int reg)
171{
172 int status;
173 unsigned int value = 0;
174
175 u8 value8;
176 status = abx500_get_register_interruptible(codec->dev, AB8500_AUDIO,
177 reg, &value8);
178 if (status < 0) {
179 dev_err(codec->dev,
180 "%s: ERROR: Register (0x%02x:0x%02x) read failed (%d).\n",
181 __func__, (u8)AB8500_AUDIO, (u8)reg, status);
182 } else {
183 dev_dbg(codec->dev,
184 "%s: Read 0x%02x from register 0x%02x:0x%02x\n",
185 __func__, value8, (u8)AB8500_AUDIO, (u8)reg);
186 value = (unsigned int)value8;
187 }
188
189 return value;
190}
191
192/* Write to a register in the audio-bank of AB8500 */
193static int ab8500_codec_write_reg(struct snd_soc_codec *codec,
194 unsigned int reg, unsigned int value)
195{
196 int status;
197
198 status = abx500_set_register_interruptible(codec->dev, AB8500_AUDIO,
199 reg, value);
200 if (status < 0)
201 dev_err(codec->dev,
202 "%s: ERROR: Register (%02x:%02x) write failed (%d).\n",
203 __func__, (u8)AB8500_AUDIO, (u8)reg, status);
204 else
205 dev_dbg(codec->dev,
206 "%s: Wrote 0x%02x into register %02x:%02x\n",
207 __func__, (u8)value, (u8)AB8500_AUDIO, (u8)reg);
208
209 return status;
210}
211
212/*
213 * Controls - DAPM
214 */
215
216/* Earpiece */
217
218/* Earpiece source selector */
219static const char * const enum_ear_lineout_source[] = {"Headset Left",
220 "Speaker Left"};
221static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
222 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
223static const struct snd_kcontrol_new dapm_ear_lineout_source =
224 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
225 dapm_enum_ear_lineout_source);
226
227/* LineOut */
228
229/* LineOut source selector */
230static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
231static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
232 AB8500_ANACONF5_HSLDACTOLOL,
233 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
234static const struct snd_kcontrol_new dapm_lineout_source[] = {
235 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
236};
237
238/* Handsfree */
239
240/* Speaker Left - ANC selector */
241static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
242static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
243 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
244static const struct snd_kcontrol_new dapm_HFl_select[] = {
245 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
246};
247
248/* Speaker Right - ANC selector */
249static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
250 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
251static const struct snd_kcontrol_new dapm_HFr_select[] = {
252 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
253};
254
255/* Mic 1 */
256
257/* Mic 1 - Mic 1a or 1b selector */
258static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
259static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
260 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
261static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
262 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
263};
264
265/* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
266static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
267static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
268 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
269static const struct snd_kcontrol_new dapm_ad3_select[] = {
270 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
271};
272
273/* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
274static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
275static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
276 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
277static const struct snd_kcontrol_new dapm_ad6_select[] = {
278 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
279};
280
281/* Mic 2 */
282
283/* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
284static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
285static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
286 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
287static const struct snd_kcontrol_new dapm_ad5_select[] = {
288 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
289};
290
291/* LineIn */
292
293/* LineIn left - AD1 - LineIn Left or DMic 1 selector */
294static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
295static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
296 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
297static const struct snd_kcontrol_new dapm_ad1_select[] = {
298 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
299};
300
301/* LineIn right - Mic 2 or LineIn Right selector */
302static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
303static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
304 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
305static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
306 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
307};
308
309/* LineIn right - AD2 - LineIn Right or DMic2 selector */
310static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
311static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
312 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
313static const struct snd_kcontrol_new dapm_ad2_select[] = {
314 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
315};
316
317
318/* ANC */
319
320static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
321 "Mic 2 / DMic 5"};
322static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
323 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
324static const struct snd_kcontrol_new dapm_anc_in_select[] = {
325 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
326};
327
328/* ANC - Enable/Disable */
329static const struct snd_kcontrol_new dapm_anc_enable[] = {
330 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
331 AB8500_ANCCONF1_ENANC, 0, 0),
332};
333
334/* ANC to Earpiece - Mute */
335static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
336 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
337 AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
338};
339
340
341
342/* Sidetone left */
343
344/* Sidetone left - Input selector */
345static const char * const enum_stfir1_in_sel[] = {
346 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
347};
348static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
349 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
350static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
351 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
352};
353
354/* Sidetone right path */
355
356/* Sidetone right - Input selector */
357static const char * const enum_stfir2_in_sel[] = {
358 "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
359};
360static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
361 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
362static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
363 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
364};
365
366/* Vibra */
367
368static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
369
370static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
371 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
372
373static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
374 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
375};
376
377static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
378 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
379
380static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
381 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
382};
383
384/*
385 * DAPM-widgets
386 */
387
388static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
389
390 /* Clocks */
391 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
392
393 /* Regulators */
822b4b8d
MB		 394 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
395 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
396 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
397 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
679d7abd
OL		 398
399 /* Power */
400 SND_SOC_DAPM_SUPPLY("Audio Power",
401 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
402 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
403 SND_SOC_DAPM_SUPPLY("Audio Analog Power",
404 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
405 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
406
407 /* Main supply node */
408 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
409 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
410
411 /* DA/AD */
412
413 SND_SOC_DAPM_INPUT("ADC Input"),
414 SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
415
416 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
417 SND_SOC_DAPM_OUTPUT("DAC Output"),
418
419 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
420 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
421 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
423 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
424 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
425 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
426 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
427 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
428 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
429 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
430 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
431
432 /* Headset path */
433
434 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
435 AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
436
437 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
438 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
439 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
440 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
441
442 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
443 NULL, 0),
444 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
445 NULL, 0),
446
447 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
448 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
449 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
450 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
451 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
452 AB8500_MUTECONF_MUTDACHSL, 1,
453 NULL, 0),
454 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
455 AB8500_MUTECONF_MUTDACHSR, 1,
456 NULL, 0),
457 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
458 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
459 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
460 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
461
462 SND_SOC_DAPM_MIXER("HSL Mute",
463 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
464 NULL, 0),
465 SND_SOC_DAPM_MIXER("HSR Mute",
466 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
467 NULL, 0),
468 SND_SOC_DAPM_MIXER("HSL Enable",
469 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
470 NULL, 0),
471 SND_SOC_DAPM_MIXER("HSR Enable",
472 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
473 NULL, 0),
474 SND_SOC_DAPM_PGA("HSL Volume",
475 SND_SOC_NOPM, 0, 0,
476 NULL, 0),
477 SND_SOC_DAPM_PGA("HSR Volume",
478 SND_SOC_NOPM, 0, 0,
479 NULL, 0),
480
481 SND_SOC_DAPM_OUTPUT("Headset Left"),
482 SND_SOC_DAPM_OUTPUT("Headset Right"),
483
484 /* LineOut path */
485
486 SND_SOC_DAPM_MUX("LineOut Source",
487 SND_SOC_NOPM, 0, 0, dapm_lineout_source),
488
489 SND_SOC_DAPM_MIXER("LOL Disable HFL",
490 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
491 NULL, 0),
492 SND_SOC_DAPM_MIXER("LOR Disable HFR",
493 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
494 NULL, 0),
495
496 SND_SOC_DAPM_MIXER("LOL Enable",
497 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
498 NULL, 0),
499 SND_SOC_DAPM_MIXER("LOR Enable",
500 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
501 NULL, 0),
502
503 SND_SOC_DAPM_OUTPUT("LineOut Left"),
504 SND_SOC_DAPM_OUTPUT("LineOut Right"),
505
506 /* Earpiece path */
507
508 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
509 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
510 SND_SOC_DAPM_MIXER("EAR DAC",
511 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
512 NULL, 0),
513 SND_SOC_DAPM_MIXER("EAR Mute",
514 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
515 NULL, 0),
516 SND_SOC_DAPM_MIXER("EAR Enable",
517 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
518 NULL, 0),
519
520 SND_SOC_DAPM_OUTPUT("Earpiece"),
521
522 /* Handsfree path */
523
524 SND_SOC_DAPM_MIXER("DA3 Channel Volume",
525 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
526 NULL, 0),
527 SND_SOC_DAPM_MIXER("DA4 Channel Volume",
528 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
529 NULL, 0),
530 SND_SOC_DAPM_MUX("Speaker Left Source",
531 SND_SOC_NOPM, 0, 0, dapm_HFl_select),
532 SND_SOC_DAPM_MUX("Speaker Right Source",
533 SND_SOC_NOPM, 0, 0, dapm_HFr_select),
534 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
535 AB8500_DAPATHCONF_ENDACHFL, 0,
536 NULL, 0),
537 SND_SOC_DAPM_MIXER("HFR DAC",
538 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
539 NULL, 0),
540 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
541 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
542 NULL, 0),
543 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
544 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
545 NULL, 0),
546 SND_SOC_DAPM_MIXER("HFL Enable",
547 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
548 NULL, 0),
549 SND_SOC_DAPM_MIXER("HFR Enable",
550 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
551 NULL, 0),
552
553 SND_SOC_DAPM_OUTPUT("Speaker Left"),
554 SND_SOC_DAPM_OUTPUT("Speaker Right"),
555
556 /* Vibrator path */
557
558 SND_SOC_DAPM_INPUT("PWMGEN1"),
559 SND_SOC_DAPM_INPUT("PWMGEN2"),
560
561 SND_SOC_DAPM_MIXER("DA5 Channel Volume",
562 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
563 NULL, 0),
564 SND_SOC_DAPM_MIXER("DA6 Channel Volume",
565 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
566 NULL, 0),
567 SND_SOC_DAPM_MIXER("VIB1 DAC",
568 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
569 NULL, 0),
570 SND_SOC_DAPM_MIXER("VIB2 DAC",
571 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
572 NULL, 0),
573 SND_SOC_DAPM_MUX("Vibra 1 Controller",
574 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
575 SND_SOC_DAPM_MUX("Vibra 2 Controller",
576 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
577 SND_SOC_DAPM_MIXER("VIB1 Enable",
578 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
579 NULL, 0),
580 SND_SOC_DAPM_MIXER("VIB2 Enable",
581 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
582 NULL, 0),
583
584 SND_SOC_DAPM_OUTPUT("Vibra 1"),
585 SND_SOC_DAPM_OUTPUT("Vibra 2"),
586
587 /* Mic 1 */
588
589 SND_SOC_DAPM_INPUT("Mic 1"),
590
591 SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
592 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
593 SND_SOC_DAPM_MIXER("MIC1 Mute",
594 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
595 NULL, 0),
596 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
597 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
598 NULL, 0),
599 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
600 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
601 NULL, 0),
602 SND_SOC_DAPM_MIXER("MIC1 ADC",
603 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
604 NULL, 0),
605 SND_SOC_DAPM_MUX("AD3 Source Select",
606 SND_SOC_NOPM, 0, 0, dapm_ad3_select),
607 SND_SOC_DAPM_MIXER("AD3 Channel Volume",
608 SND_SOC_NOPM, 0, 0,
609 NULL, 0),
610 SND_SOC_DAPM_MIXER("AD3 Enable",
611 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
612 NULL, 0),
613
614 /* Mic 2 */
615
616 SND_SOC_DAPM_INPUT("Mic 2"),
617
618 SND_SOC_DAPM_MIXER("MIC2 Mute",
619 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
620 NULL, 0),
621 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
622 AB8500_ANACONF2_ENMIC2, 0,
623 NULL, 0),
624
625 /* LineIn */
626
627 SND_SOC_DAPM_INPUT("LineIn Left"),
628 SND_SOC_DAPM_INPUT("LineIn Right"),
629
630 SND_SOC_DAPM_MIXER("LINL Mute",
631 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
632 NULL, 0),
633 SND_SOC_DAPM_MIXER("LINR Mute",
634 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
635 NULL, 0),
636 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
637 AB8500_ANACONF2_ENLINL, 0,
638 NULL, 0),
639 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
640 AB8500_ANACONF2_ENLINR, 0,
641 NULL, 0),
642
643 /* LineIn Bypass path */
644 SND_SOC_DAPM_MIXER("LINL to HSL Volume",
645 SND_SOC_NOPM, 0, 0,
646 NULL, 0),
647 SND_SOC_DAPM_MIXER("LINR to HSR Volume",
648 SND_SOC_NOPM, 0, 0,
649 NULL, 0),
650
651 /* LineIn, Mic 2 */
652 SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
653 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
654 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
655 AB8500_ANACONF3_ENADCLINL, 0,
656 NULL, 0),
657 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
658 AB8500_ANACONF3_ENADCLINR, 0,
659 NULL, 0),
660 SND_SOC_DAPM_MUX("AD1 Source Select",
661 SND_SOC_NOPM, 0, 0, dapm_ad1_select),
662 SND_SOC_DAPM_MUX("AD2 Source Select",
663 SND_SOC_NOPM, 0, 0, dapm_ad2_select),
664 SND_SOC_DAPM_MIXER("AD1 Channel Volume",
665 SND_SOC_NOPM, 0, 0,
666 NULL, 0),
667 SND_SOC_DAPM_MIXER("AD2 Channel Volume",
668 SND_SOC_NOPM, 0, 0,
669 NULL, 0),
670
671 SND_SOC_DAPM_MIXER("AD12 Enable",
672 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
673 NULL, 0),
674
675 /* HD Capture path */
676
677 SND_SOC_DAPM_MUX("AD5 Source Select",
678 SND_SOC_NOPM, 0, 0, dapm_ad5_select),
679 SND_SOC_DAPM_MUX("AD6 Source Select",
680 SND_SOC_NOPM, 0, 0, dapm_ad6_select),
681 SND_SOC_DAPM_MIXER("AD5 Channel Volume",
682 SND_SOC_NOPM, 0, 0,
683 NULL, 0),
684 SND_SOC_DAPM_MIXER("AD6 Channel Volume",
685 SND_SOC_NOPM, 0, 0,
686 NULL, 0),
687 SND_SOC_DAPM_MIXER("AD57 Enable",
688 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
689 NULL, 0),
690 SND_SOC_DAPM_MIXER("AD68 Enable",
691 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
692 NULL, 0),
693
694 /* Digital Microphone path */
695
696 SND_SOC_DAPM_INPUT("DMic 1"),
697 SND_SOC_DAPM_INPUT("DMic 2"),
698 SND_SOC_DAPM_INPUT("DMic 3"),
699 SND_SOC_DAPM_INPUT("DMic 4"),
700 SND_SOC_DAPM_INPUT("DMic 5"),
701 SND_SOC_DAPM_INPUT("DMic 6"),
702
703 SND_SOC_DAPM_MIXER("DMIC1",
704 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
705 NULL, 0),
706 SND_SOC_DAPM_MIXER("DMIC2",
707 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
708 NULL, 0),
709 SND_SOC_DAPM_MIXER("DMIC3",
710 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
711 NULL, 0),
712 SND_SOC_DAPM_MIXER("DMIC4",
713 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
714 NULL, 0),
715 SND_SOC_DAPM_MIXER("DMIC5",
716 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
717 NULL, 0),
718 SND_SOC_DAPM_MIXER("DMIC6",
719 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
720 NULL, 0),
721 SND_SOC_DAPM_MIXER("AD4 Channel Volume",
722 SND_SOC_NOPM, 0, 0,
723 NULL, 0),
724 SND_SOC_DAPM_MIXER("AD4 Enable",
725 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
726 0, NULL, 0),
727
728 /* Acoustical Noise Cancellation path */
729
730 SND_SOC_DAPM_INPUT("ANC Configure Input"),
731 SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
732
733 SND_SOC_DAPM_MUX("ANC Source",
734 SND_SOC_NOPM, 0, 0,
735 dapm_anc_in_select),
736 SND_SOC_DAPM_SWITCH("ANC",
737 SND_SOC_NOPM, 0, 0,
738 dapm_anc_enable),
739 SND_SOC_DAPM_SWITCH("ANC to Earpiece",
740 SND_SOC_NOPM, 0, 0,
741 dapm_anc_ear_mute),
742
743 /* Sidetone Filter path */
744
745 SND_SOC_DAPM_MUX("Sidetone Left Source",
746 SND_SOC_NOPM, 0, 0,
747 dapm_stfir1_in_select),
748 SND_SOC_DAPM_MUX("Sidetone Right Source",
749 SND_SOC_NOPM, 0, 0,
750 dapm_stfir2_in_select),
751 SND_SOC_DAPM_MIXER("STFIR1 Control",
752 SND_SOC_NOPM, 0, 0,
753 NULL, 0),
754 SND_SOC_DAPM_MIXER("STFIR2 Control",
755 SND_SOC_NOPM, 0, 0,
756 NULL, 0),
757 SND_SOC_DAPM_MIXER("STFIR1 Volume",
758 SND_SOC_NOPM, 0, 0,
759 NULL, 0),
760 SND_SOC_DAPM_MIXER("STFIR2 Volume",
761 SND_SOC_NOPM, 0, 0,
762 NULL, 0),
763};
764
765/*
766 * DAPM-routes
767 */
768static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
769 /* Power AB8500 audio-block when AD/DA is active */
770 {"Main Supply", NULL, "V-AUD"},
771 {"Main Supply", NULL, "audioclk"},
772 {"Main Supply", NULL, "Audio Power"},
773 {"Main Supply", NULL, "Audio Analog Power"},
774
775 {"DAC", NULL, "ab8500_0p"},
776 {"DAC", NULL, "Main Supply"},
777 {"ADC", NULL, "ab8500_0c"},
778 {"ADC", NULL, "Main Supply"},
779
780 /* ANC Configure */
781 {"ANC Configure Input", NULL, "Main Supply"},
782 {"ANC Configure Output", NULL, "ANC Configure Input"},
783
784 /* AD/DA */
785 {"ADC", NULL, "ADC Input"},
786 {"DAC Output", NULL, "DAC"},
787
788 /* Powerup charge pump if DA1/2 is in use */
789
790 {"DA_IN1", NULL, "ab8500_0p"},
791 {"DA_IN1", NULL, "Charge Pump"},
792 {"DA_IN2", NULL, "ab8500_0p"},
793 {"DA_IN2", NULL, "Charge Pump"},
794
795 /* Headset path */
796
797 {"DA1 Enable", NULL, "DA_IN1"},
798 {"DA2 Enable", NULL, "DA_IN2"},
799
800 {"HSL Digital Volume", NULL, "DA1 Enable"},
801 {"HSR Digital Volume", NULL, "DA2 Enable"},
802
803 {"HSL DAC", NULL, "HSL Digital Volume"},
804 {"HSR DAC", NULL, "HSR Digital Volume"},
805
806 {"HSL DAC Mute", NULL, "HSL DAC"},
807 {"HSR DAC Mute", NULL, "HSR DAC"},
808
809 {"HSL DAC Driver", NULL, "HSL DAC Mute"},
810 {"HSR DAC Driver", NULL, "HSR DAC Mute"},
811
812 {"HSL Mute", NULL, "HSL DAC Driver"},
813 {"HSR Mute", NULL, "HSR DAC Driver"},
814
815 {"HSL Enable", NULL, "HSL Mute"},
816 {"HSR Enable", NULL, "HSR Mute"},
817
818 {"HSL Volume", NULL, "HSL Enable"},
819 {"HSR Volume", NULL, "HSR Enable"},
820
821 {"Headset Left", NULL, "HSL Volume"},
822 {"Headset Right", NULL, "HSR Volume"},
823
824 /* HF or LineOut path */
825
826 {"DA_IN3", NULL, "ab8500_0p"},
827 {"DA3 Channel Volume", NULL, "DA_IN3"},
828 {"DA_IN4", NULL, "ab8500_0p"},
829 {"DA4 Channel Volume", NULL, "DA_IN4"},
830
831 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
832 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
833
834 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
835 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
836
837 /* HF path */
838
839 {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
840 {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
841
842 {"HFL Enable", NULL, "HFL DAC"},
843 {"HFR Enable", NULL, "HFR DAC"},
844
845 {"Speaker Left", NULL, "HFL Enable"},
846 {"Speaker Right", NULL, "HFR Enable"},
847
848 /* Earpiece path */
849
850 {"Earpiece or LineOut Mono Source", "Headset Left",
851 "HSL Digital Volume"},
852 {"Earpiece or LineOut Mono Source", "Speaker Left",
853 "DA3 or ANC path to HfL"},
854
855 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
856
857 {"EAR Mute", NULL, "EAR DAC"},
858
859 {"EAR Enable", NULL, "EAR Mute"},
860
861 {"Earpiece", NULL, "EAR Enable"},
862
863 /* LineOut path stereo */
864
865 {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
866 {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
867
868 /* LineOut path mono */
869
870 {"LineOut Source", "Mono Path", "EAR DAC"},
871
872 /* LineOut path */
873
874 {"LOL Disable HFL", NULL, "LineOut Source"},
875 {"LOR Disable HFR", NULL, "LineOut Source"},
876
877 {"LOL Enable", NULL, "LOL Disable HFL"},
878 {"LOR Enable", NULL, "LOR Disable HFR"},
879
880 {"LineOut Left", NULL, "LOL Enable"},
881 {"LineOut Right", NULL, "LOR Enable"},
882
883 /* Vibrator path */
884
885 {"DA_IN5", NULL, "ab8500_0p"},
886 {"DA5 Channel Volume", NULL, "DA_IN5"},
887 {"DA_IN6", NULL, "ab8500_0p"},
888 {"DA6 Channel Volume", NULL, "DA_IN6"},
889
890 {"VIB1 DAC", NULL, "DA5 Channel Volume"},
891 {"VIB2 DAC", NULL, "DA6 Channel Volume"},
892
893 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
894 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
895 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
896 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
897
898 {"VIB1 Enable", NULL, "Vibra 1 Controller"},
899 {"VIB2 Enable", NULL, "Vibra 2 Controller"},
900
901 {"Vibra 1", NULL, "VIB1 Enable"},
902 {"Vibra 2", NULL, "VIB2 Enable"},
903
904
905 /* Mic 2 */
906
907 {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
908
909 /* LineIn */
910 {"LINL Mute", NULL, "LineIn Left"},
911 {"LINR Mute", NULL, "LineIn Right"},
912
913 {"LINL Enable", NULL, "LINL Mute"},
914 {"LINR Enable", NULL, "LINR Mute"},
915
916 /* LineIn, Mic 2 */
917 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
918 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
919
920 {"LINL ADC", NULL, "LINL Enable"},
921 {"LINR ADC", NULL, "Mic 2 or LINR Select"},
922
923 {"AD1 Source Select", "LineIn Left", "LINL ADC"},
924 {"AD2 Source Select", "LineIn Right", "LINR ADC"},
925
926 {"AD1 Channel Volume", NULL, "AD1 Source Select"},
927 {"AD2 Channel Volume", NULL, "AD2 Source Select"},
928
929 {"AD12 Enable", NULL, "AD1 Channel Volume"},
930 {"AD12 Enable", NULL, "AD2 Channel Volume"},
931
932 {"AD_OUT1", NULL, "ab8500_0c"},
933 {"AD_OUT1", NULL, "AD12 Enable"},
934 {"AD_OUT2", NULL, "ab8500_0c"},
935 {"AD_OUT2", NULL, "AD12 Enable"},
936
937 /* Mic 1 */
938
939 {"MIC1 Mute", NULL, "Mic 1"},
940
941 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
942 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
943
944 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
945 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
946
947 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
948
949 {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
950
951 {"AD3 Channel Volume", NULL, "AD3 Source Select"},
952
953 {"AD3 Enable", NULL, "AD3 Channel Volume"},
954
955 {"AD_OUT3", NULL, "ab8500_0c"},
956 {"AD_OUT3", NULL, "AD3 Enable"},
957
958 /* HD Capture path */
959
960 {"AD5 Source Select", "Mic 2", "LINR ADC"},
961 {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
962
963 {"AD5 Channel Volume", NULL, "AD5 Source Select"},
964 {"AD6 Channel Volume", NULL, "AD6 Source Select"},
965
966 {"AD57 Enable", NULL, "AD5 Channel Volume"},
967 {"AD68 Enable", NULL, "AD6 Channel Volume"},
968
969 {"AD_OUT57", NULL, "ab8500_0c"},
970 {"AD_OUT57", NULL, "AD57 Enable"},
971 {"AD_OUT68", NULL, "ab8500_0c"},
972 {"AD_OUT68", NULL, "AD68 Enable"},
973
974 /* Digital Microphone path */
975
976 {"DMic 1", NULL, "V-DMIC"},
977 {"DMic 2", NULL, "V-DMIC"},
978 {"DMic 3", NULL, "V-DMIC"},
979 {"DMic 4", NULL, "V-DMIC"},
980 {"DMic 5", NULL, "V-DMIC"},
981 {"DMic 6", NULL, "V-DMIC"},
982
983 {"AD1 Source Select", NULL, "DMic 1"},
984 {"AD2 Source Select", NULL, "DMic 2"},
985 {"AD3 Source Select", NULL, "DMic 3"},
986 {"AD5 Source Select", NULL, "DMic 5"},
987 {"AD6 Source Select", NULL, "DMic 6"},
988
989 {"AD4 Channel Volume", NULL, "DMic 4"},
990 {"AD4 Enable", NULL, "AD4 Channel Volume"},
991
992 {"AD_OUT4", NULL, "ab8500_0c"},
993 {"AD_OUT4", NULL, "AD4 Enable"},
994
995 /* LineIn Bypass path */
996
997 {"LINL to HSL Volume", NULL, "LINL Enable"},
998 {"LINR to HSR Volume", NULL, "LINR Enable"},
999
1000 {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
1001 {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
1002
1003 /* ANC path (Acoustic Noise Cancellation) */
1004
1005 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
1006 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
1007
1008 {"ANC", "Switch", "ANC Source"},
1009
1010 {"Speaker Left Source", "ANC", "ANC"},
1011 {"Speaker Right Source", "ANC", "ANC"},
1012 {"ANC to Earpiece", "Switch", "ANC"},
1013
1014 {"HSL Digital Volume", NULL, "ANC to Earpiece"},
1015
1016 /* Sidetone Filter path */
1017
1018 {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
1019 {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
1020 {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
1021 {"Sidetone Left Source", "Headset Left", "DA_IN1"},
1022 {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
1023 {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
1024 {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1025 {"Sidetone Right Source", "Headset Right", "DA_IN2"},
1026
1027 {"STFIR1 Control", NULL, "Sidetone Left Source"},
1028 {"STFIR2 Control", NULL, "Sidetone Right Source"},
1029
1030 {"STFIR1 Volume", NULL, "STFIR1 Control"},
1031 {"STFIR2 Volume", NULL, "STFIR2 Control"},
1032
1033 {"DA1 Enable", NULL, "STFIR1 Volume"},
1034 {"DA2 Enable", NULL, "STFIR2 Volume"},
1035};
1036
1037static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1038 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1039 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1040};
1041
1042static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1043 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1044 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1045};
1046
1047static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1048 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1049 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1050};
1051
1052/* ANC FIR-coefficients configuration sequence */
1053static void anc_fir(struct snd_soc_codec *codec,
1054 unsigned int bnk, unsigned int par, unsigned int val)
1055{
1056 if (par == 0 && bnk == 0)
1057 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1058 BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1059 BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1060
1061 snd_soc_write(codec, AB8500_ANCCONF5, val >> 8 & 0xff);
1062 snd_soc_write(codec, AB8500_ANCCONF6, val & 0xff);
1063
1064 if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1065 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1066 BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1067}
1068
1069/* ANC IIR-coefficients configuration sequence */
1070static void anc_iir(struct snd_soc_codec *codec, unsigned int bnk,
1071 unsigned int par, unsigned int val)
1072{
1073 if (par == 0) {
1074 if (bnk == 0) {
1075 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1076 BIT(AB8500_ANCCONF1_ANCIIRINIT),
1077 BIT(AB8500_ANCCONF1_ANCIIRINIT));
1078 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1079 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1080 BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1081 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1082 } else {
1083 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1084 BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1085 BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1086 }
1087 } else if (par > 3) {
1088 snd_soc_write(codec, AB8500_ANCCONF7, 0);
1089 snd_soc_write(codec, AB8500_ANCCONF8, val >> 16 & 0xff);
1090 }
1091
1092 snd_soc_write(codec, AB8500_ANCCONF7, val >> 8 & 0xff);
1093 snd_soc_write(codec, AB8500_ANCCONF8, val & 0xff);
1094
1095 if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1096 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1097 BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1098}
1099
1100/* ANC IIR-/FIR-coefficients configuration sequence */
1101static void anc_configure(struct snd_soc_codec *codec,
1102 bool apply_fir, bool apply_iir)
1103{
1104 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1105 unsigned int bnk, par, val;
1106
1107 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1108
1109 if (apply_fir)
1110 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1111 BIT(AB8500_ANCCONF1_ENANC), 0);
1112
1113 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1114 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1115
1116 if (apply_fir)
1117 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1118 for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1119 val = snd_soc_read(codec,
1120 drvdata->anc_fir_values[par]);
1121 anc_fir(codec, bnk, par, val);
1122 }
1123
1124 if (apply_iir)
1125 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1126 for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1127 val = snd_soc_read(codec,
1128 drvdata->anc_iir_values[par]);
1129 anc_iir(codec, bnk, par, val);
1130 }
1131
1132 dev_dbg(codec->dev, "%s: Exit.\n", __func__);
1133}
1134
1135/*
1136 * Control-events
1137 */
1138
1139static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1140 struct snd_ctl_elem_value *ucontrol)
1141{
1142 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1143 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1144
1145 mutex_lock(&codec->mutex);
1146 ucontrol->value.integer.value[0] = drvdata->sid_status;
1147 mutex_unlock(&codec->mutex);
1148
1149 return 0;
1150}
1151
1152/* Write sidetone FIR-coefficients configuration sequence */
1153static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1154 struct snd_ctl_elem_value *ucontrol)
1155{
1156 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1157 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1158 unsigned int param, sidconf, val;
1159 int status = 1;
1160
1161 dev_dbg(codec->dev, "%s: Enter\n", __func__);
1162
1163 if (ucontrol->value.integer.value[0] != SID_APPLY_FIR) {
1164 dev_err(codec->dev,
1165 "%s: ERROR: This control supports '%s' only!\n",
1166 __func__, enum_sid_state[SID_APPLY_FIR]);
1167 return -EIO;
1168 }
1169
1170 mutex_lock(&codec->mutex);
1171
1172 sidconf = snd_soc_read(codec, AB8500_SIDFIRCONF);
1173 if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1174 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1175 dev_err(codec->dev, "%s: Sidetone busy while off!\n",
1176 __func__);
1177 status = -EPERM;
1178 } else {
1179 status = -EBUSY;
1180 }
1181 goto out;
1182 }
1183
1184 snd_soc_write(codec, AB8500_SIDFIRADR, 0);
1185
1186 for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1187 val = snd_soc_read(codec, drvdata->sid_fir_values[param]);
1188 snd_soc_write(codec, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1189 snd_soc_write(codec, AB8500_SIDFIRCOEF2, val & 0xff);
1190 }
1191
1192 snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1193 BIT(AB8500_SIDFIRADR_FIRSIDSET),
1194 BIT(AB8500_SIDFIRADR_FIRSIDSET));
1195 snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1196 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1197
1198 drvdata->sid_status = SID_FIR_CONFIGURED;
1199
1200out:
1201 mutex_unlock(&codec->mutex);
1202
1203 dev_dbg(codec->dev, "%s: Exit\n", __func__);
1204
1205 return status;
1206}
1207
1208static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1209 struct snd_ctl_elem_value *ucontrol)
1210{
1211 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1212 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1213
1214 mutex_lock(&codec->mutex);
1215 ucontrol->value.integer.value[0] = drvdata->anc_status;
1216 mutex_unlock(&codec->mutex);
1217
1218 return 0;
1219}
1220
1221static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1222 struct snd_ctl_elem_value *ucontrol)
1223{
1224 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1225 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1226 struct device *dev = codec->dev;
1227 bool apply_fir, apply_iir;
1228 int req, status;
1229
1230 dev_dbg(dev, "%s: Enter.\n", __func__);
1231
1232 mutex_lock(&drvdata->anc_lock);
1233
1234 req = ucontrol->value.integer.value[0];
1235 if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1236 req != ANC_APPLY_IIR) {
1237 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1238 __func__, enum_anc_state[req]);
9f0ed7a7
DC		 1239 status = -EINVAL;
1240 goto cleanup;
679d7abd
OL		 1241 }
1242 apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1243 apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1244
1245 status = snd_soc_dapm_force_enable_pin(&codec->dapm,
1246 "ANC Configure Input");
1247 if (status < 0) {
1248 dev_err(dev,
1249 "%s: ERROR: Failed to enable power (status = %d)!\n",
1250 __func__, status);
1251 goto cleanup;
1252 }
1253 snd_soc_dapm_sync(&codec->dapm);
1254
1255 mutex_lock(&codec->mutex);
1256 anc_configure(codec, apply_fir, apply_iir);
1257 mutex_unlock(&codec->mutex);
1258
1259 if (apply_fir) {
1260 if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1261 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1262 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1263 drvdata->anc_status = ANC_FIR_CONFIGURED;
1264 }
1265 if (apply_iir) {
1266 if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1267 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1268 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1269 drvdata->anc_status = ANC_IIR_CONFIGURED;
1270 }
1271
1272 status = snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input");
1273 snd_soc_dapm_sync(&codec->dapm);
1274
1275cleanup:
1276 mutex_unlock(&drvdata->anc_lock);
1277
1278 if (status < 0)
1279 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1280 __func__, status);
1281
1282 dev_dbg(dev, "%s: Exit.\n", __func__);
1283
1284 return (status < 0) ? status : 1;
1285}
1286
1287static int filter_control_info(struct snd_kcontrol *kcontrol,
1288 struct snd_ctl_elem_info *uinfo)
1289{
1290 struct filter_control *fc =
1291 (struct filter_control *)kcontrol->private_value;
1292
1293 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1294 uinfo->count = fc->count;
1295 uinfo->value.integer.min = fc->min;
1296 uinfo->value.integer.max = fc->max;
1297
1298 return 0;
1299}
1300
1301static int filter_control_get(struct snd_kcontrol *kcontrol,
1302 struct snd_ctl_elem_value *ucontrol)
1303{
1304 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1305 struct filter_control *fc =
1306 (struct filter_control *)kcontrol->private_value;
1307 unsigned int i;
1308
1309 mutex_lock(&codec->mutex);
1310 for (i = 0; i < fc->count; i++)
1311 ucontrol->value.integer.value[i] = fc->value[i];
1312 mutex_unlock(&codec->mutex);
1313
1314 return 0;
1315}
1316
1317static int filter_control_put(struct snd_kcontrol *kcontrol,
1318 struct snd_ctl_elem_value *ucontrol)
1319{
1320 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1321 struct filter_control *fc =
1322 (struct filter_control *)kcontrol->private_value;
1323 unsigned int i;
1324
1325 mutex_lock(&codec->mutex);
1326 for (i = 0; i < fc->count; i++)
1327 fc->value[i] = ucontrol->value.integer.value[i];
1328 mutex_unlock(&codec->mutex);
1329
1330 return 0;
1331}
1332
1333/*
1334 * Controls - Non-DAPM ASoC
1335 */
1336
1337static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1338/* -32dB = Mute */
1339
1340static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1341/* -63dB = Mute */
1342
1343static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1344/* -1dB = Mute */
1345
1346static const unsigned int hs_gain_tlv[] = {
1347 TLV_DB_RANGE_HEAD(2),
1348 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1349 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0),
1350};
1351
1352static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1353
1354static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1355
1356static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1357/* -38dB = Mute */
1358
1359static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1360 "5ms"};
1361static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1362 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1363
1364static const char * const enum_envdetthre[] = {
1365 "250mV", "300mV", "350mV", "400mV",
1366 "450mV", "500mV", "550mV", "600mV",
1367 "650mV", "700mV", "750mV", "800mV",
1368 "850mV", "900mV", "950mV", "1.00V" };
1369static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1370 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1371static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1372 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1373static const char * const enum_envdettime[] = {
1374 "26.6us", "53.2us", "106us", "213us",
1375 "426us", "851us", "1.70ms", "3.40ms",
1376 "6.81ms", "13.6ms", "27.2ms", "54.5ms",
1377 "109ms", "218ms", "436ms", "872ms" };
1378static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1379 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1380
1381static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1382static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1383 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1384
1385static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1386static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1387 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1388
1389/* Earpiece */
1390
1391static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1392static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1393 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1394static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1395 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1396
1397static const char * const enum_av_mode[] = {"Audio", "Voice"};
1398static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1399 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1400static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1401 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1402
1403/* DA */
1404
1405static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1406 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1407 enum_av_mode);
1408static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1409 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1410 enum_av_mode);
1411static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1412 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1413 enum_av_mode);
1414
1415static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1416static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1417 AB8500_DIGMULTCONF1_DATOHSLEN,
1418 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1419
1420static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1421static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1422 AB8500_DMICFILTCONF_DMIC1SINC3,
1423 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1424static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1425 AB8500_DMICFILTCONF_DMIC3SINC3,
1426 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1427static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1428 AB8500_DMICFILTCONF_DMIC5SINC3,
1429 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1430
1431/* Digital interface - DA from slot mapping */
1432static const char * const enum_da_from_slot_map[] = {"SLOT0",
1433 "SLOT1",
1434 "SLOT2",
1435 "SLOT3",
1436 "SLOT4",
1437 "SLOT5",
1438 "SLOT6",
1439 "SLOT7",
1440 "SLOT8",
1441 "SLOT9",
1442 "SLOT10",
1443 "SLOT11",
1444 "SLOT12",
1445 "SLOT13",
1446 "SLOT14",
1447 "SLOT15",
1448 "SLOT16",
1449 "SLOT17",
1450 "SLOT18",
1451 "SLOT19",
1452 "SLOT20",
1453 "SLOT21",
1454 "SLOT22",
1455 "SLOT23",
1456 "SLOT24",
1457 "SLOT25",
1458 "SLOT26",
1459 "SLOT27",
1460 "SLOT28",
1461 "SLOT29",
1462 "SLOT30",
1463 "SLOT31"};
1464static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1465 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1466 enum_da_from_slot_map);
1467static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1468 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1469 enum_da_from_slot_map);
1470static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1471 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1472 enum_da_from_slot_map);
1473static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1474 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1475 enum_da_from_slot_map);
1476static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1477 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1478 enum_da_from_slot_map);
1479static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1480 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1481 enum_da_from_slot_map);
1482static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1483 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1484 enum_da_from_slot_map);
1485static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1486 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1487 enum_da_from_slot_map);
1488
1489/* Digital interface - AD to slot mapping */
1490static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1491 "AD_OUT2",
1492 "AD_OUT3",
1493 "AD_OUT4",
1494 "AD_OUT5",
1495 "AD_OUT6",
1496 "AD_OUT7",
1497 "AD_OUT8",
1498 "zeroes",
b9600b4b
FB		 1499 "zeroes",
1500 "zeroes",
1501 "zeroes",
1502 "tristate",
1503 "tristate",
1504 "tristate",
679d7abd
OL		 1505 "tristate"};
1506static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1507 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1508 enum_ad_to_slot_map);
1509static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1510 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1511 enum_ad_to_slot_map);
1512static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1513 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1514 enum_ad_to_slot_map);
1515static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1516 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1517 enum_ad_to_slot_map);
1518static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1519 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1520 enum_ad_to_slot_map);
1521static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1522 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1523 enum_ad_to_slot_map);
1524static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1525 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1526 enum_ad_to_slot_map);
1527static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1528 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1529 enum_ad_to_slot_map);
1530static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1531 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1532 enum_ad_to_slot_map);
1533static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1534 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1535 enum_ad_to_slot_map);
1536static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1537 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1538 enum_ad_to_slot_map);
1539static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1540 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1541 enum_ad_to_slot_map);
1542static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1543 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1544 enum_ad_to_slot_map);
1545static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1546 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1547 enum_ad_to_slot_map);
1548static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1549 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1550 enum_ad_to_slot_map);
1551static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1552 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1553 enum_ad_to_slot_map);
1554static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1555 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1556 enum_ad_to_slot_map);
1557static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1558 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1559 enum_ad_to_slot_map);
1560static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1561 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1562 enum_ad_to_slot_map);
1563static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1564 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1565 enum_ad_to_slot_map);
1566static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1567 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1568 enum_ad_to_slot_map);
1569static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1570 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1571 enum_ad_to_slot_map);
1572static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1573 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1574 enum_ad_to_slot_map);
1575static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1576 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1577 enum_ad_to_slot_map);
1578static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1579 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1580 enum_ad_to_slot_map);
1581static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1582 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1583 enum_ad_to_slot_map);
1584static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1585 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1586 enum_ad_to_slot_map);
1587static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1588 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1589 enum_ad_to_slot_map);
1590static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1591 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1592 enum_ad_to_slot_map);
1593static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1594 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1595 enum_ad_to_slot_map);
1596static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1597 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1598 enum_ad_to_slot_map);
1599static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1600 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1601 enum_ad_to_slot_map);
1602
1603/* Digital interface - Burst mode */
1604static const char * const enum_mask[] = {"Unmasked", "Masked"};
1605static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1606 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1607 enum_mask);
1608static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1609static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1610 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1611 enum_bitclk0);
1612static const char * const enum_slavemaster[] = {"Slave", "Master"};
1613static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1614 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1615 enum_slavemaster);
1616
1617/* Sidetone */
1618static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1619
1620/* ANC */
1621static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1622
1623static struct snd_kcontrol_new ab8500_ctrls[] = {
1624 /* Charge pump */
1625 SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1626 soc_enum_envdeththre),
1627 SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1628 soc_enum_envdetlthre),
1629 SOC_SINGLE("Charge Pump Envelope Detection Switch",
1630 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1631 1, 0),
1632 SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1633 soc_enum_envdettime),
1634
1635 /* Headset */
1636 SOC_ENUM("Headset Mode", soc_enum_da12voice),
1637 SOC_SINGLE("Headset High Pass Switch",
1638 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1639 1, 0),
1640 SOC_SINGLE("Headset Low Power Switch",
1641 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1642 1, 0),
1643 SOC_SINGLE("Headset DAC Low Power Switch",
1644 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1645 1, 0),
1646 SOC_SINGLE("Headset DAC Drv Low Power Switch",
1647 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1648 1, 0),
1649 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1650 SOC_ENUM("Headset Source", soc_enum_da2hslr),
1651 SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1652 SOC_DOUBLE_R_TLV("Headset Master Volume",
1653 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1654 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1655 SOC_DOUBLE_R_TLV("Headset Digital Volume",
1656 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1657 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1658 SOC_DOUBLE_TLV("Headset Volume",
1659 AB8500_ANAGAIN3,
1660 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1661 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1662
1663 /* Earpiece */
1664 SOC_ENUM("Earpiece DAC Mode",
1665 soc_enum_eardaclowpow),
1666 SOC_ENUM("Earpiece DAC Drv Mode",
1667 soc_enum_eardrvlowpow),
1668
1669 /* HandsFree */
1670 SOC_ENUM("HF Mode", soc_enum_da34voice),
1671 SOC_SINGLE("HF and Headset Swap Switch",
1672 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1673 1, 0),
1674 SOC_DOUBLE("HF Low EMI Mode Switch",
1675 AB8500_CLASSDCONF1,
1676 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1677 1, 0),
1678 SOC_DOUBLE("HF FIR Bypass Switch",
1679 AB8500_CLASSDCONF2,
1680 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1681 1, 0),
1682 SOC_DOUBLE("HF High Volume Switch",
1683 AB8500_CLASSDCONF2,
1684 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1685 1, 0),
1686 SOC_SINGLE("HF L and R Bridge Switch",
1687 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1688 1, 0),
1689 SOC_DOUBLE_R_TLV("HF Master Volume",
1690 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1691 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1692
1693 /* Vibra */
1694 SOC_DOUBLE("Vibra High Volume Switch",
1695 AB8500_CLASSDCONF2,
1696 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1697 1, 0),
1698 SOC_DOUBLE("Vibra Low EMI Mode Switch",
1699 AB8500_CLASSDCONF1,
1700 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1701 1, 0),
1702 SOC_DOUBLE("Vibra FIR Bypass Switch",
1703 AB8500_CLASSDCONF2,
1704 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1705 1, 0),
1706 SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1707 SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1708 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1709 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1710 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1711 SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1712 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1713 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1714 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1715 SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1716 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1717 1, 0),
1718 SOC_DOUBLE_R_TLV("Vibra Master Volume",
1719 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1720 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1721
1722 /* HandsFree, Vibra */
1723 SOC_SINGLE("ClassD High Pass Volume",
1724 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1725 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1726 SOC_SINGLE("ClassD White Volume",
1727 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1728 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1729
1730 /* Mic 1, Mic 2, LineIn */
1731 SOC_DOUBLE_R_TLV("Mic Master Volume",
1732 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1733 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1734
1735 /* Mic 1 */
1736 SOC_SINGLE_TLV("Mic 1",
1737 AB8500_ANAGAIN1,
1738 AB8500_ANAGAINX_MICXGAIN,
1739 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1740 SOC_SINGLE("Mic 1 Low Power Switch",
1741 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1742 1, 0),
1743
1744 /* Mic 2 */
1745 SOC_DOUBLE("Mic High Pass Switch",
1746 AB8500_ADFILTCONF,
1747 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1748 1, 1),
1749 SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1750 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1751 SOC_SINGLE_TLV("Mic 2",
1752 AB8500_ANAGAIN2,
1753 AB8500_ANAGAINX_MICXGAIN,
1754 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1755 SOC_SINGLE("Mic 2 Low Power Switch",
1756 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1757 1, 0),
1758
1759 /* LineIn */
1760 SOC_DOUBLE("LineIn High Pass Switch",
1761 AB8500_ADFILTCONF,
1762 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1763 1, 1),
1764 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1765 SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1766 SOC_DOUBLE_R_TLV("LineIn Master Volume",
1767 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1768 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1769 SOC_DOUBLE_TLV("LineIn",
1770 AB8500_ANAGAIN4,
1771 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1772 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1773 SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1774 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1775 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1776 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1777 1, lin2hs_gain_tlv),
1778
1779 /* DMic */
1780 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1781 SOC_DOUBLE_R_TLV("DMic Master Volume",
1782 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1783 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1784
1785 /* Digital gains */
1786 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1787
1788 /* Analog loopback */
1789 SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1790 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1791 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1792
1793 /* Digital interface - DA from slot mapping */
1794 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1795 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1796 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1797 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1798 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1799 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1800 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1801 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1802
1803 /* Digital interface - AD to slot mapping */
1804 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1805 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1806 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1807 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1808 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1809 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1810 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1811 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1812 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1813 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1814 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1815 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1816 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1817 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1818 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1819 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1820 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1821 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1822 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1823 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1824 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1825 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1826 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1827 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1828 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1829 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1830 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1831 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1832 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1833 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1834 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1835 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1836
1837 /* Digital interface - Loopback */
1838 SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1839 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1840 1, 0),
1841 SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1842 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1843 1, 0),
1844 SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1845 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1846 1, 0),
1847 SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1848 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1849 1, 0),
1850 SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1851 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1852 1, 0),
1853 SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1854 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1855 1, 0),
1856 SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1857 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1858 1, 0),
1859 SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1860 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1861 1, 0),
1862
1863 /* Digital interface - Burst FIFO */
1864 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1865 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1866 1, 0),
1867 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1868 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1869 SOC_SINGLE("Burst FIFO Threshold",
1870 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1871 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1872 SOC_SINGLE("Burst FIFO Length",
1873 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1874 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1875 SOC_SINGLE("Burst FIFO EOS Extra Slots",
1876 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1877 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1878 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1879 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1880 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1881 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1882
1883 SOC_SINGLE("Burst FIFO Interface Switch",
1884 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1885 1, 0),
1886 SOC_SINGLE("Burst FIFO Switch Frame Number",
1887 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1888 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1889 SOC_SINGLE("Burst FIFO Wake Up Delay",
1890 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1891 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1892 SOC_SINGLE("Burst FIFO Samples In FIFO",
1893 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1894 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1895
1896 /* ANC */
1897 SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1898 anc_status_control_get, anc_status_control_put),
1899 SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1900 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1901 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1902 SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1903 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1904 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1905 SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1906 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1907 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1908 SOC_SINGLE_XR_SX("ANC Warp Delay",
1909 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1910 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1911
1912 /* Sidetone */
1913 SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1914 sid_status_control_get, sid_status_control_put),
1915 SOC_SINGLE_STROBE("Sidetone Reset",
1916 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1917};
1918
1919static struct snd_kcontrol_new ab8500_filter_controls[] = {
1920 AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1921 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1922 AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1923 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1924 AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1925 AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1926 AB8500_SID_FIR_COEFF_MAX)
1927};
1928enum ab8500_filter {
1929 AB8500_FILTER_ANC_FIR = 0,
1930 AB8500_FILTER_ANC_IIR = 1,
1931 AB8500_FILTER_SID_FIR = 2,
1932};
1933
1934/*
1935 * Extended interface for codec-driver
1936 */
1937
1938static int ab8500_audio_init_audioblock(struct snd_soc_codec *codec)
1939{
1940 int status;
1941
1942 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1943
1944 /* Reset audio-registers and disable 32kHz-clock output 2 */
1945 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1946 AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1947 AB8500_STW4500CTRL3_RESETAUDN,
1948 AB8500_STW4500CTRL3_RESETAUDN);
1949 if (status < 0)
1950 return status;
1951
1952 return 0;
1953}
1954
1955static int ab8500_audio_setup_mics(struct snd_soc_codec *codec,
1956 struct amic_settings *amics)
1957{
1958 u8 value8;
1959 unsigned int value;
1960 int status;
1961 const struct snd_soc_dapm_route *route;
1962
1963 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1964
1965 /* Set DMic-clocks to outputs */
1966 status = abx500_get_register_interruptible(codec->dev, (u8)AB8500_MISC,
1967 (u8)AB8500_GPIO_DIR4_REG,
1968 &value8);
1969 if (status < 0)
1970 return status;
1971 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1972 GPIO31_DIR_OUTPUT;
1973 status = abx500_set_register_interruptible(codec->dev,
1974 (u8)AB8500_MISC,
1975 (u8)AB8500_GPIO_DIR4_REG,
1976 value);
1977 if (status < 0)
1978 return status;
1979
1980 /* Attach regulators to AMic DAPM-paths */
1981 dev_dbg(codec->dev, "%s: Mic 1a regulator: %s\n", __func__,
1982 amic_micbias_str(amics->mic1a_micbias));
1983 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1984 status = snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1985 dev_dbg(codec->dev, "%s: Mic 1b regulator: %s\n", __func__,
1986 amic_micbias_str(amics->mic1b_micbias));
1987 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1988 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1989 dev_dbg(codec->dev, "%s: Mic 2 regulator: %s\n", __func__,
1990 amic_micbias_str(amics->mic2_micbias));
1991 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1992 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1993 if (status < 0) {
1994 dev_err(codec->dev,
1995 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1996 __func__, status);
1997 return status;
1998 }
1999
2000 /* Set AMic-configuration */
2001 dev_dbg(codec->dev, "%s: Mic 1 mic-type: %s\n", __func__,
2002 amic_type_str(amics->mic1_type));
2003 snd_soc_update_bits(codec, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
2004 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
2005 0 : AB8500_ANAGAINX_ENSEMICX);
2006 dev_dbg(codec->dev, "%s: Mic 2 mic-type: %s\n", __func__,
2007 amic_type_str(amics->mic2_type));
2008 snd_soc_update_bits(codec, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
2009 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
2010 0 : AB8500_ANAGAINX_ENSEMICX);
2011
2012 return 0;
2013}
2014EXPORT_SYMBOL_GPL(ab8500_audio_setup_mics);
2015
2016static int ab8500_audio_set_ear_cmv(struct snd_soc_codec *codec,
2017 enum ear_cm_voltage ear_cmv)
2018{
2019 char *cmv_str;
2020
2021 switch (ear_cmv) {
2022 case EAR_CMV_0_95V:
2023 cmv_str = "0.95V";
2024 break;
2025 case EAR_CMV_1_10V:
2026 cmv_str = "1.10V";
2027 break;
2028 case EAR_CMV_1_27V:
2029 cmv_str = "1.27V";
2030 break;
2031 case EAR_CMV_1_58V:
2032 cmv_str = "1.58V";
2033 break;
2034 default:
2035 dev_err(codec->dev,
2036 "%s: Unknown earpiece CM-voltage (%d)!\n",
2037 __func__, (int)ear_cmv);
2038 return -EINVAL;
2039 }
2040 dev_dbg(codec->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2041 cmv_str);
2042 snd_soc_update_bits(codec, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2043 ear_cmv);
2044
2045 return 0;
2046}
2047EXPORT_SYMBOL_GPL(ab8500_audio_set_ear_cmv);
2048
2049static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2050 unsigned int delay)
2051{
2052 unsigned int mask, val;
2053 struct snd_soc_codec *codec = dai->codec;
2054
2055 mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2056 val = 0;
2057
2058 switch (delay) {
2059 case 0:
2060 break;
2061 case 1:
2062 val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2063 break;
2064 default:
2065 dev_err(dai->codec->dev,
2066 "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2067 __func__, delay);
2068 return -EINVAL;
2069 }
2070
2071 dev_dbg(dai->codec->dev, "%s: IF0 Bit-delay: %d bits.\n",
2072 __func__, delay);
2073 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2074
2075 return 0;
2076}
2077
2078/* Gates clocking according format mask */
2079static int ab8500_codec_set_dai_clock_gate(struct snd_soc_codec *codec,
2080 unsigned int fmt)
2081{
2082 unsigned int mask;
2083 unsigned int val;
2084
2085 mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2086 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2087
2088 val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2089
2090 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2091 case SND_SOC_DAIFMT_CONT: /* continuous clock */
2092 dev_dbg(codec->dev, "%s: IF0 Clock is continuous.\n",
2093 __func__);
2094 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2095 break;
2096 case SND_SOC_DAIFMT_GATED: /* clock is gated */
2097 dev_dbg(codec->dev, "%s: IF0 Clock is gated.\n",
2098 __func__);
2099 break;
2100 default:
2101 dev_err(codec->dev,
2102 "%s: ERROR: Unsupported clock mask (0x%x)!\n",
2103 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2104 return -EINVAL;
2105 }
2106
2107 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2108
2109 return 0;
2110}
2111
2112static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2113{
2114 unsigned int mask;
2115 unsigned int val;
2116 struct snd_soc_codec *codec = dai->codec;
2117 int status;
2118
2119 dev_dbg(codec->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2120
2121 mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2122 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2123 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2124 BIT(AB8500_DIGIFCONF3_IF0MASTER);
2125 val = 0;
2126
2127 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2128 case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */
2129 dev_dbg(dai->codec->dev,
2130 "%s: IF0 Master-mode: AB8500 master.\n", __func__);
2131 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2132 break;
2133 case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */
2134 dev_dbg(dai->codec->dev,
2135 "%s: IF0 Master-mode: AB8500 slave.\n", __func__);
2136 break;
2137 case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */
2138 case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
2139 dev_err(dai->codec->dev,
2140 "%s: ERROR: The device is either a master or a slave.\n",
2141 __func__);
2142 default:
2143 dev_err(dai->codec->dev,
2144 "%s: ERROR: Unsupporter master mask 0x%x\n",
2145 __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK);
2146 return -EINVAL;
2147 break;
2148 }
2149
2150 snd_soc_update_bits(codec, AB8500_DIGIFCONF3, mask, val);
2151
2152 /* Set clock gating */
2153 status = ab8500_codec_set_dai_clock_gate(codec, fmt);
2154 if (status) {
2155 dev_err(dai->codec->dev,
c46d5c04 2156 "%s: ERROR: Failed to set clock gate (%d).\n",
679d7abd
OL		 2157 __func__, status);
2158 return status;
2159 }
2160
2161 /* Setting data transfer format */
2162
2163 mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2164 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2165 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2166 BIT(AB8500_DIGIFCONF2_BITCLK0P);
2167 val = 0;
2168
2169 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2170 case SND_SOC_DAIFMT_I2S: /* I2S mode */
2171 dev_dbg(dai->codec->dev, "%s: IF0 Protocol: I2S\n", __func__);
2172 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2173 ab8500_audio_set_bit_delay(dai, 0);
2174 break;
2175
2176 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2177 dev_dbg(dai->codec->dev,
2178 "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2179 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2180 ab8500_audio_set_bit_delay(dai, 1);
2181 break;
2182
2183 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2184 dev_dbg(dai->codec->dev,
2185 "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2186 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2187 ab8500_audio_set_bit_delay(dai, 0);
2188 break;
2189
2190 default:
2191 dev_err(dai->codec->dev,
2192 "%s: ERROR: Unsupported format (0x%x)!\n",
2193 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2194 return -EINVAL;
2195 }
2196
2197 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2198 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2199 dev_dbg(dai->codec->dev,
2200 "%s: IF0: Normal bit clock, normal frame\n",
2201 __func__);
2202 break;
2203 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2204 dev_dbg(dai->codec->dev,
2205 "%s: IF0: Normal bit clock, inverted frame\n",
2206 __func__);
2207 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2208 break;
2209 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2210 dev_dbg(dai->codec->dev,
2211 "%s: IF0: Inverted bit clock, normal frame\n",
2212 __func__);
2213 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2214 break;
2215 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2216 dev_dbg(dai->codec->dev,
2217 "%s: IF0: Inverted bit clock, inverted frame\n",
2218 __func__);
2219 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2220 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2221 break;
2222 default:
2223 dev_err(dai->codec->dev,
2224 "%s: ERROR: Unsupported INV mask 0x%x\n",
2225 __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2226 return -EINVAL;
2227 }
2228
2229 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2230
2231 return 0;
2232}
2233
2234static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2235 unsigned int tx_mask, unsigned int rx_mask,
2236 int slots, int slot_width)
2237{
2238 struct snd_soc_codec *codec = dai->codec;
2239 unsigned int val, mask, slots_active;
2240
2241 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2242 BIT(AB8500_DIGIFCONF2_IF0WL1);
2243 val = 0;
2244
2245 switch (slot_width) {
2246 case 16:
2247 break;
2248 case 20:
2249 val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2250 break;
2251 case 24:
2252 val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2253 break;
2254 case 32:
2255 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2256 BIT(AB8500_DIGIFCONF2_IF0WL0);
2257 break;
2258 default:
2259 dev_err(dai->codec->dev, "%s: Unsupported slot-width 0x%x\n",
2260 __func__, slot_width);
2261 return -EINVAL;
2262 }
2263
2264 dev_dbg(dai->codec->dev, "%s: IF0 slot-width: %d bits.\n",
2265 __func__, slot_width);
2266 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2267
2268 /* Setup TDM clocking according to slot count */
2269 dev_dbg(dai->codec->dev, "%s: Slots, total: %d\n", __func__, slots);
2270 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2271 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2272 switch (slots) {
2273 case 2:
2274 val = AB8500_MASK_NONE;
2275 break;
2276 case 4:
2277 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2278 break;
2279 case 8:
2280 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2281 break;
2282 case 16:
2283 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2284 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2285 break;
2286 default:
2287 dev_err(dai->codec->dev,
2288 "%s: ERROR: Unsupported number of slots (%d)!\n",
2289 __func__, slots);
2290 return -EINVAL;
2291 }
2292 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2293
2294 /* Setup TDM DA according to active tx slots */
2295 mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
2296 slots_active = hweight32(tx_mask);
2297 dev_dbg(dai->codec->dev, "%s: Slots, active, TX: %d\n", __func__,
2298 slots_active);
2299 switch (slots_active) {
2300 case 0:
2301 break;
2302 case 1:
2303 /* Slot 9 -> DA_IN1 & DA_IN3 */
2304 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, 11);
2305 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, 11);
2306 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, 11);
2307 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, 11);
2308 break;
2309 case 2:
2310 /* Slot 9 -> DA_IN1 & DA_IN3, Slot 11 -> DA_IN2 & DA_IN4 */
2311 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, 9);
2312 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, 9);
2313 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, 11);
2314 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, 11);
2315
2316 break;
2317 case 8:
2318 dev_dbg(dai->codec->dev,
2319 "%s: In 8-channel mode DA-from-slot mapping is set manually.",
2320 __func__);
2321 break;
2322 default:
2323 dev_err(dai->codec->dev,
2324 "%s: Unsupported number of active TX-slots (%d)!\n",
2325 __func__, slots_active);
2326 return -EINVAL;
2327 }
2328
2329 /* Setup TDM AD according to active RX-slots */
2330 slots_active = hweight32(rx_mask);
2331 dev_dbg(dai->codec->dev, "%s: Slots, active, RX: %d\n", __func__,
2332 slots_active);
2333 switch (slots_active) {
2334 case 0:
2335 break;
2336 case 1:
2337 /* AD_OUT3 -> slot 0 & 1 */
2338 snd_soc_update_bits(codec, AB8500_ADSLOTSEL1, AB8500_MASK_ALL,
2339 AB8500_ADSLOTSELX_AD_OUT3_TO_SLOT_EVEN |
2340 AB8500_ADSLOTSELX_AD_OUT3_TO_SLOT_ODD);
2341 break;
2342 case 2:
2343 /* AD_OUT3 -> slot 0, AD_OUT2 -> slot 1 */
2344 snd_soc_update_bits(codec,
2345 AB8500_ADSLOTSEL1,
2346 AB8500_MASK_ALL,
2347 AB8500_ADSLOTSELX_AD_OUT3_TO_SLOT_EVEN |
2348 AB8500_ADSLOTSELX_AD_OUT2_TO_SLOT_ODD);
2349 break;
2350 case 8:
2351 dev_dbg(dai->codec->dev,
2352 "%s: In 8-channel mode AD-to-slot mapping is set manually.",
2353 __func__);
2354 break;
2355 default:
2356 dev_err(dai->codec->dev,
2357 "%s: Unsupported number of active RX-slots (%d)!\n",
2358 __func__, slots_active);
2359 return -EINVAL;
2360 }
2361
2362 return 0;
2363}
2364
c3f68171 2365static struct snd_soc_dai_driver ab8500_codec_dai[] = {
679d7abd
OL		 2366 {
2367 .name = "ab8500-codec-dai.0",
2368 .id = 0,
2369 .playback = {
2370 .stream_name = "ab8500_0p",
2371 .channels_min = 1,
2372 .channels_max = 8,
2373 .rates = AB8500_SUPPORTED_RATE,
2374 .formats = AB8500_SUPPORTED_FMT,
2375 },
2376 .ops = (struct snd_soc_dai_ops[]) {
2377 {
2378 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2379 .set_fmt = ab8500_codec_set_dai_fmt,
2380 }
2381 },
2382 .symmetric_rates = 1
2383 },
2384 {
2385 .name = "ab8500-codec-dai.1",
2386 .id = 1,
2387 .capture = {
2388 .stream_name = "ab8500_0c",
2389 .channels_min = 1,
2390 .channels_max = 8,
2391 .rates = AB8500_SUPPORTED_RATE,
2392 .formats = AB8500_SUPPORTED_FMT,
2393 },
2394 .ops = (struct snd_soc_dai_ops[]) {
2395 {
2396 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2397 .set_fmt = ab8500_codec_set_dai_fmt,
2398 }
2399 },
2400 .symmetric_rates = 1
2401 }
2402};
2403
db5c811d
LJ		 2404static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2405 struct ab8500_codec_platform_data *codec)
2406{
2407 u32 value;
2408
2409 if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
2410 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2411 else
2412 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2413
2414 if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
2415 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2416 else
2417 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2418
2419 /* Has a non-standard Vamic been requested? */
2420 if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
2421 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2422 else
2423 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2424
2425 if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
2426 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2427 else
2428 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2429
2430 if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
2431 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2432 else
2433 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2434
2435 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2436 switch (value) {
2437 case 950 :
2438 codec->ear_cmv = EAR_CMV_0_95V;
2439 break;
2440 case 1100 :
2441 codec->ear_cmv = EAR_CMV_1_10V;
2442 break;
2443 case 1270 :
2444 codec->ear_cmv = EAR_CMV_1_27V;
2445 break;
2446 case 1580 :
2447 codec->ear_cmv = EAR_CMV_1_58V;
2448 break;
2449 default :
2450 codec->ear_cmv = EAR_CMV_UNKNOWN;
2451 dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2452 }
2453 } else {
2454 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2455 codec->ear_cmv = EAR_CMV_0_95V;
2456 }
2457}
2458
679d7abd
OL		 2459static int ab8500_codec_probe(struct snd_soc_codec *codec)
2460{
2461 struct device *dev = codec->dev;
db5c811d 2462 struct device_node *np = dev->of_node;
679d7abd
OL		 2463 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2464 struct ab8500_platform_data *pdata;
2465 struct filter_control *fc;
2466 int status;
2467
2468 dev_dbg(dev, "%s: Enter.\n", __func__);
2469
d95e9337
MB		 2470 /* Setup AB8500 according to board-settings */
2471 pdata = dev_get_platdata(dev->parent);
2472
db5c811d
LJ		 2473 if (np) {
2474 if (!pdata)
2475 pdata = devm_kzalloc(dev,
2476 sizeof(struct ab8500_platform_data),
2477 GFP_KERNEL);
2478
2479 if (pdata && !pdata->codec)
2480 pdata->codec
2481 = devm_kzalloc(dev,
2482 sizeof(struct ab8500_codec_platform_data),
2483 GFP_KERNEL);
2484
2485 if (!(pdata && pdata->codec))
2486 return -ENOMEM;
2487
2488 ab8500_codec_of_probe(dev, np, pdata->codec);
2489
2490 } else {
2491 if (!(pdata && pdata->codec)) {
2492 dev_err(dev, "No codec platform data or DT found\n");
2493 return -EINVAL;
2494 }
2495 }
2496
679d7abd
OL		 2497 status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
2498 if (status < 0) {
2499 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2500 return status;
2501 }
2502 status = ab8500_audio_set_ear_cmv(codec, pdata->codec->ear_cmv);
2503 if (status < 0) {
2504 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2505 __func__, status);
2506 return status;
2507 }
2508
2509 status = ab8500_audio_init_audioblock(codec);
2510 if (status < 0) {
2511 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2512 __func__, status);
2513 return status;
2514 }
2515
2516 /* Override HW-defaults */
2517 ab8500_codec_write_reg(codec,
2518 AB8500_ANACONF5,
2519 BIT(AB8500_ANACONF5_HSAUTOEN));
2520 ab8500_codec_write_reg(codec,
2521 AB8500_SHORTCIRCONF,
2522 BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2523
2524 /* Add filter controls */
2525 status = snd_soc_add_codec_controls(codec, ab8500_filter_controls,
2526 ARRAY_SIZE(ab8500_filter_controls));
2527 if (status < 0) {
2528 dev_err(dev,
2529 "%s: failed to add ab8500 filter controls (%d).\n",
2530 __func__, status);
2531 return status;
2532 }
2533 fc = (struct filter_control *)
2534 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2535 drvdata->anc_fir_values = (long *)fc->value;
2536 fc = (struct filter_control *)
2537 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2538 drvdata->anc_iir_values = (long *)fc->value;
2539 fc = (struct filter_control *)
2540 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2541 drvdata->sid_fir_values = (long *)fc->value;
2542
2543 (void)snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input");
2544
2545 mutex_init(&drvdata->anc_lock);
2546
2547 return status;
2548}
2549
2550static struct snd_soc_codec_driver ab8500_codec_driver = {
2551 .probe = ab8500_codec_probe,
2552 .read = ab8500_codec_read_reg,
2553 .write = ab8500_codec_write_reg,
2554 .reg_word_size = sizeof(u8),
2555 .controls = ab8500_ctrls,
2556 .num_controls = ARRAY_SIZE(ab8500_ctrls),
2557 .dapm_widgets = ab8500_dapm_widgets,
2558 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets),
2559 .dapm_routes = ab8500_dapm_routes,
2560 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes),
2561};
2562
7a79e94e 2563static int ab8500_codec_driver_probe(struct platform_device *pdev)
679d7abd
OL		 2564{
2565 int status;
2566 struct ab8500_codec_drvdata *drvdata;
2567
2568 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2569
2570 /* Create driver private-data struct */
2571 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2572 GFP_KERNEL);
2573 drvdata->sid_status = SID_UNCONFIGURED;
2574 drvdata->anc_status = ANC_UNCONFIGURED;
2575 dev_set_drvdata(&pdev->dev, drvdata);
2576
2577 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2578 status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver,
2579 ab8500_codec_dai,
2580 ARRAY_SIZE(ab8500_codec_dai));
2581 if (status < 0)
2582 dev_err(&pdev->dev,
2583 "%s: Error: Failed to register codec (%d).\n",
2584 __func__, status);
2585
2586 return status;
2587}
2588
7a79e94e 2589static int ab8500_codec_driver_remove(struct platform_device *pdev)
679d7abd
OL		 2590{
2591 dev_info(&pdev->dev, "%s Enter.\n", __func__);
2592
2593 snd_soc_unregister_codec(&pdev->dev);
2594
2595 return 0;
2596}
2597
2598static struct platform_driver ab8500_codec_platform_driver = {
2599 .driver = {
2600 .name = "ab8500-codec",
2601 .owner = THIS_MODULE,
2602 },
2603 .probe = ab8500_codec_driver_probe,
7a79e94e 2604 .remove = ab8500_codec_driver_remove,
679d7abd
OL		 2605 .suspend = NULL,
2606 .resume = NULL,
2607};
2608module_platform_driver(ab8500_codec_platform_driver);
2609
85f24391 2610MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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