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ddd7a260 LPC |
1 | /* |
2 | * Analog Devices ADAU1373 Audio Codec drive | |
3 | * | |
4 | * Copyright 2011 Analog Devices Inc. | |
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | |
6 | * | |
7 | * Licensed under the GPL-2 or later. | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pm.h> | |
14 | #include <linux/i2c.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/gcd.h> | |
17 | ||
18 | #include <sound/core.h> | |
19 | #include <sound/pcm.h> | |
20 | #include <sound/pcm_params.h> | |
21 | #include <sound/tlv.h> | |
22 | #include <sound/soc.h> | |
23 | #include <sound/adau1373.h> | |
24 | ||
25 | #include "adau1373.h" | |
26 | ||
27 | struct adau1373_dai { | |
28 | unsigned int clk_src; | |
29 | unsigned int sysclk; | |
30 | bool enable_src; | |
31 | bool master; | |
32 | }; | |
33 | ||
34 | struct adau1373 { | |
c3df37c9 | 35 | struct regmap *regmap; |
ddd7a260 LPC |
36 | struct adau1373_dai dais[3]; |
37 | }; | |
38 | ||
39 | #define ADAU1373_INPUT_MODE 0x00 | |
40 | #define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2) | |
41 | #define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2) | |
42 | #define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2) | |
43 | #define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2) | |
44 | #define ADAU1373_LSPK_OUT 0x0d | |
45 | #define ADAU1373_RSPK_OUT 0x0e | |
46 | #define ADAU1373_LHP_OUT 0x0f | |
47 | #define ADAU1373_RHP_OUT 0x10 | |
48 | #define ADAU1373_ADC_GAIN 0x11 | |
49 | #define ADAU1373_LADC_MIXER 0x12 | |
50 | #define ADAU1373_RADC_MIXER 0x13 | |
51 | #define ADAU1373_LLINE1_MIX 0x14 | |
52 | #define ADAU1373_RLINE1_MIX 0x15 | |
53 | #define ADAU1373_LLINE2_MIX 0x16 | |
54 | #define ADAU1373_RLINE2_MIX 0x17 | |
55 | #define ADAU1373_LSPK_MIX 0x18 | |
56 | #define ADAU1373_RSPK_MIX 0x19 | |
57 | #define ADAU1373_LHP_MIX 0x1a | |
58 | #define ADAU1373_RHP_MIX 0x1b | |
59 | #define ADAU1373_EP_MIX 0x1c | |
60 | #define ADAU1373_HP_CTRL 0x1d | |
61 | #define ADAU1373_HP_CTRL2 0x1e | |
62 | #define ADAU1373_LS_CTRL 0x1f | |
63 | #define ADAU1373_EP_CTRL 0x21 | |
64 | #define ADAU1373_MICBIAS_CTRL1 0x22 | |
65 | #define ADAU1373_MICBIAS_CTRL2 0x23 | |
66 | #define ADAU1373_OUTPUT_CTRL 0x24 | |
67 | #define ADAU1373_PWDN_CTRL1 0x25 | |
68 | #define ADAU1373_PWDN_CTRL2 0x26 | |
69 | #define ADAU1373_PWDN_CTRL3 0x27 | |
70 | #define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7) | |
71 | #define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7) | |
72 | #define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7) | |
73 | #define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7) | |
74 | #define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7) | |
75 | #define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7) | |
76 | #define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7) | |
ddd7a260 LPC |
77 | #define ADAU1373_HEADDECT 0x36 |
78 | #define ADAU1373_ADC_DAC_STATUS 0x37 | |
79 | #define ADAU1373_ADC_CTRL 0x3c | |
80 | #define ADAU1373_DAI(x) (0x44 + (x)) | |
81 | #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2) | |
82 | #define ADAU1373_BCLKDIV(x) (0x47 + (x)) | |
83 | #define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2) | |
84 | #define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2) | |
85 | #define ADAU1373_DEEMP_CTRL 0x50 | |
86 | #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x)) | |
87 | #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x)) | |
88 | #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x)) | |
89 | #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2) | |
90 | #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2) | |
91 | #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2) | |
92 | #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2) | |
93 | #define ADAU1373_DAC1_PBL_VOL 0x6e | |
94 | #define ADAU1373_DAC1_PBR_VOL 0x6f | |
95 | #define ADAU1373_DAC2_PBL_VOL 0x70 | |
96 | #define ADAU1373_DAC2_PBR_VOL 0x71 | |
97 | #define ADAU1373_ADC_RECL_VOL 0x72 | |
98 | #define ADAU1373_ADC_RECR_VOL 0x73 | |
99 | #define ADAU1373_DMIC_RECL_VOL 0x74 | |
100 | #define ADAU1373_DMIC_RECR_VOL 0x75 | |
101 | #define ADAU1373_VOL_GAIN1 0x76 | |
102 | #define ADAU1373_VOL_GAIN2 0x77 | |
103 | #define ADAU1373_VOL_GAIN3 0x78 | |
104 | #define ADAU1373_HPF_CTRL 0x7d | |
105 | #define ADAU1373_BASS1 0x7e | |
106 | #define ADAU1373_BASS2 0x7f | |
107 | #define ADAU1373_DRC(x) (0x80 + (x) * 0x10) | |
108 | #define ADAU1373_3D_CTRL1 0xc0 | |
109 | #define ADAU1373_3D_CTRL2 0xc1 | |
110 | #define ADAU1373_FDSP_SEL1 0xdc | |
111 | #define ADAU1373_FDSP_SEL2 0xdd | |
112 | #define ADAU1373_FDSP_SEL3 0xde | |
113 | #define ADAU1373_FDSP_SEL4 0xdf | |
114 | #define ADAU1373_DIGMICCTRL 0xe2 | |
115 | #define ADAU1373_DIGEN 0xeb | |
116 | #define ADAU1373_SOFT_RESET 0xff | |
117 | ||
118 | ||
119 | #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1) | |
120 | #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0) | |
121 | ||
122 | #define ADAU1373_DAI_INVERT_BCLK BIT(7) | |
123 | #define ADAU1373_DAI_MASTER BIT(6) | |
124 | #define ADAU1373_DAI_INVERT_LRCLK BIT(4) | |
125 | #define ADAU1373_DAI_WLEN_16 0x0 | |
126 | #define ADAU1373_DAI_WLEN_20 0x4 | |
127 | #define ADAU1373_DAI_WLEN_24 0x8 | |
128 | #define ADAU1373_DAI_WLEN_32 0xc | |
129 | #define ADAU1373_DAI_WLEN_MASK 0xc | |
130 | #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0 | |
131 | #define ADAU1373_DAI_FORMAT_LEFT_J 0x1 | |
132 | #define ADAU1373_DAI_FORMAT_I2S 0x2 | |
133 | #define ADAU1373_DAI_FORMAT_DSP 0x3 | |
134 | ||
135 | #define ADAU1373_BCLKDIV_SOURCE BIT(5) | |
14a1b8ca TG |
136 | #define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2) |
137 | #define ADAU1373_BCLKDIV_BCLK_MASK 0x03 | |
ddd7a260 LPC |
138 | #define ADAU1373_BCLKDIV_32 0x03 |
139 | #define ADAU1373_BCLKDIV_64 0x02 | |
140 | #define ADAU1373_BCLKDIV_128 0x01 | |
141 | #define ADAU1373_BCLKDIV_256 0x00 | |
142 | ||
143 | #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0) | |
144 | #define ADAU1373_ADC_CTRL_RESET BIT(1) | |
145 | #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2) | |
146 | ||
147 | #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3) | |
148 | #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2) | |
149 | ||
150 | #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0) | |
151 | ||
152 | #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4 | |
153 | #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2 | |
154 | ||
c3df37c9 LPC |
155 | static const struct reg_default adau1373_reg_defaults[] = { |
156 | { ADAU1373_INPUT_MODE, 0x00 }, | |
157 | { ADAU1373_AINL_CTRL(0), 0x00 }, | |
158 | { ADAU1373_AINR_CTRL(0), 0x00 }, | |
159 | { ADAU1373_AINL_CTRL(1), 0x00 }, | |
160 | { ADAU1373_AINR_CTRL(1), 0x00 }, | |
161 | { ADAU1373_AINL_CTRL(2), 0x00 }, | |
162 | { ADAU1373_AINR_CTRL(2), 0x00 }, | |
163 | { ADAU1373_AINL_CTRL(3), 0x00 }, | |
164 | { ADAU1373_AINR_CTRL(3), 0x00 }, | |
165 | { ADAU1373_LLINE_OUT(0), 0x00 }, | |
166 | { ADAU1373_RLINE_OUT(0), 0x00 }, | |
167 | { ADAU1373_LLINE_OUT(1), 0x00 }, | |
168 | { ADAU1373_RLINE_OUT(1), 0x00 }, | |
169 | { ADAU1373_LSPK_OUT, 0x00 }, | |
170 | { ADAU1373_RSPK_OUT, 0x00 }, | |
171 | { ADAU1373_LHP_OUT, 0x00 }, | |
172 | { ADAU1373_RHP_OUT, 0x00 }, | |
173 | { ADAU1373_ADC_GAIN, 0x00 }, | |
174 | { ADAU1373_LADC_MIXER, 0x00 }, | |
175 | { ADAU1373_RADC_MIXER, 0x00 }, | |
176 | { ADAU1373_LLINE1_MIX, 0x00 }, | |
177 | { ADAU1373_RLINE1_MIX, 0x00 }, | |
178 | { ADAU1373_LLINE2_MIX, 0x00 }, | |
179 | { ADAU1373_RLINE2_MIX, 0x00 }, | |
180 | { ADAU1373_LSPK_MIX, 0x00 }, | |
181 | { ADAU1373_RSPK_MIX, 0x00 }, | |
182 | { ADAU1373_LHP_MIX, 0x00 }, | |
183 | { ADAU1373_RHP_MIX, 0x00 }, | |
184 | { ADAU1373_EP_MIX, 0x00 }, | |
185 | { ADAU1373_HP_CTRL, 0x00 }, | |
186 | { ADAU1373_HP_CTRL2, 0x00 }, | |
187 | { ADAU1373_LS_CTRL, 0x00 }, | |
188 | { ADAU1373_EP_CTRL, 0x00 }, | |
189 | { ADAU1373_MICBIAS_CTRL1, 0x00 }, | |
190 | { ADAU1373_MICBIAS_CTRL2, 0x00 }, | |
191 | { ADAU1373_OUTPUT_CTRL, 0x00 }, | |
192 | { ADAU1373_PWDN_CTRL1, 0x00 }, | |
193 | { ADAU1373_PWDN_CTRL2, 0x00 }, | |
194 | { ADAU1373_PWDN_CTRL3, 0x00 }, | |
195 | { ADAU1373_DPLL_CTRL(0), 0x00 }, | |
196 | { ADAU1373_PLL_CTRL1(0), 0x00 }, | |
197 | { ADAU1373_PLL_CTRL2(0), 0x00 }, | |
198 | { ADAU1373_PLL_CTRL3(0), 0x00 }, | |
199 | { ADAU1373_PLL_CTRL4(0), 0x00 }, | |
200 | { ADAU1373_PLL_CTRL5(0), 0x00 }, | |
201 | { ADAU1373_PLL_CTRL6(0), 0x02 }, | |
202 | { ADAU1373_DPLL_CTRL(1), 0x00 }, | |
203 | { ADAU1373_PLL_CTRL1(1), 0x00 }, | |
204 | { ADAU1373_PLL_CTRL2(1), 0x00 }, | |
205 | { ADAU1373_PLL_CTRL3(1), 0x00 }, | |
206 | { ADAU1373_PLL_CTRL4(1), 0x00 }, | |
207 | { ADAU1373_PLL_CTRL5(1), 0x00 }, | |
208 | { ADAU1373_PLL_CTRL6(1), 0x02 }, | |
209 | { ADAU1373_HEADDECT, 0x00 }, | |
210 | { ADAU1373_ADC_CTRL, 0x00 }, | |
211 | { ADAU1373_CLK_SRC_DIV(0), 0x00 }, | |
212 | { ADAU1373_CLK_SRC_DIV(1), 0x00 }, | |
213 | { ADAU1373_DAI(0), 0x0a }, | |
214 | { ADAU1373_DAI(1), 0x0a }, | |
215 | { ADAU1373_DAI(2), 0x0a }, | |
216 | { ADAU1373_BCLKDIV(0), 0x00 }, | |
217 | { ADAU1373_BCLKDIV(1), 0x00 }, | |
218 | { ADAU1373_BCLKDIV(2), 0x00 }, | |
219 | { ADAU1373_SRC_RATIOA(0), 0x00 }, | |
220 | { ADAU1373_SRC_RATIOB(0), 0x00 }, | |
221 | { ADAU1373_SRC_RATIOA(1), 0x00 }, | |
222 | { ADAU1373_SRC_RATIOB(1), 0x00 }, | |
223 | { ADAU1373_SRC_RATIOA(2), 0x00 }, | |
224 | { ADAU1373_SRC_RATIOB(2), 0x00 }, | |
225 | { ADAU1373_DEEMP_CTRL, 0x00 }, | |
226 | { ADAU1373_SRC_DAI_CTRL(0), 0x08 }, | |
227 | { ADAU1373_SRC_DAI_CTRL(1), 0x08 }, | |
228 | { ADAU1373_SRC_DAI_CTRL(2), 0x08 }, | |
229 | { ADAU1373_DIN_MIX_CTRL(0), 0x00 }, | |
230 | { ADAU1373_DIN_MIX_CTRL(1), 0x00 }, | |
231 | { ADAU1373_DIN_MIX_CTRL(2), 0x00 }, | |
232 | { ADAU1373_DIN_MIX_CTRL(3), 0x00 }, | |
233 | { ADAU1373_DIN_MIX_CTRL(4), 0x00 }, | |
234 | { ADAU1373_DOUT_MIX_CTRL(0), 0x00 }, | |
235 | { ADAU1373_DOUT_MIX_CTRL(1), 0x00 }, | |
236 | { ADAU1373_DOUT_MIX_CTRL(2), 0x00 }, | |
237 | { ADAU1373_DOUT_MIX_CTRL(3), 0x00 }, | |
238 | { ADAU1373_DOUT_MIX_CTRL(4), 0x00 }, | |
239 | { ADAU1373_DAI_PBL_VOL(0), 0x00 }, | |
240 | { ADAU1373_DAI_PBR_VOL(0), 0x00 }, | |
241 | { ADAU1373_DAI_PBL_VOL(1), 0x00 }, | |
242 | { ADAU1373_DAI_PBR_VOL(1), 0x00 }, | |
243 | { ADAU1373_DAI_PBL_VOL(2), 0x00 }, | |
244 | { ADAU1373_DAI_PBR_VOL(2), 0x00 }, | |
245 | { ADAU1373_DAI_RECL_VOL(0), 0x00 }, | |
246 | { ADAU1373_DAI_RECR_VOL(0), 0x00 }, | |
247 | { ADAU1373_DAI_RECL_VOL(1), 0x00 }, | |
248 | { ADAU1373_DAI_RECR_VOL(1), 0x00 }, | |
249 | { ADAU1373_DAI_RECL_VOL(2), 0x00 }, | |
250 | { ADAU1373_DAI_RECR_VOL(2), 0x00 }, | |
251 | { ADAU1373_DAC1_PBL_VOL, 0x00 }, | |
252 | { ADAU1373_DAC1_PBR_VOL, 0x00 }, | |
253 | { ADAU1373_DAC2_PBL_VOL, 0x00 }, | |
254 | { ADAU1373_DAC2_PBR_VOL, 0x00 }, | |
255 | { ADAU1373_ADC_RECL_VOL, 0x00 }, | |
256 | { ADAU1373_ADC_RECR_VOL, 0x00 }, | |
257 | { ADAU1373_DMIC_RECL_VOL, 0x00 }, | |
258 | { ADAU1373_DMIC_RECR_VOL, 0x00 }, | |
259 | { ADAU1373_VOL_GAIN1, 0x00 }, | |
260 | { ADAU1373_VOL_GAIN2, 0x00 }, | |
261 | { ADAU1373_VOL_GAIN3, 0x00 }, | |
262 | { ADAU1373_HPF_CTRL, 0x00 }, | |
263 | { ADAU1373_BASS1, 0x00 }, | |
264 | { ADAU1373_BASS2, 0x00 }, | |
265 | { ADAU1373_DRC(0) + 0x0, 0x78 }, | |
266 | { ADAU1373_DRC(0) + 0x1, 0x18 }, | |
267 | { ADAU1373_DRC(0) + 0x2, 0x00 }, | |
268 | { ADAU1373_DRC(0) + 0x3, 0x00 }, | |
269 | { ADAU1373_DRC(0) + 0x4, 0x00 }, | |
270 | { ADAU1373_DRC(0) + 0x5, 0xc0 }, | |
271 | { ADAU1373_DRC(0) + 0x6, 0x00 }, | |
272 | { ADAU1373_DRC(0) + 0x7, 0x00 }, | |
273 | { ADAU1373_DRC(0) + 0x8, 0x00 }, | |
274 | { ADAU1373_DRC(0) + 0x9, 0xc0 }, | |
275 | { ADAU1373_DRC(0) + 0xa, 0x88 }, | |
276 | { ADAU1373_DRC(0) + 0xb, 0x7a }, | |
277 | { ADAU1373_DRC(0) + 0xc, 0xdf }, | |
278 | { ADAU1373_DRC(0) + 0xd, 0x20 }, | |
279 | { ADAU1373_DRC(0) + 0xe, 0x00 }, | |
280 | { ADAU1373_DRC(0) + 0xf, 0x00 }, | |
281 | { ADAU1373_DRC(1) + 0x0, 0x78 }, | |
282 | { ADAU1373_DRC(1) + 0x1, 0x18 }, | |
283 | { ADAU1373_DRC(1) + 0x2, 0x00 }, | |
284 | { ADAU1373_DRC(1) + 0x3, 0x00 }, | |
285 | { ADAU1373_DRC(1) + 0x4, 0x00 }, | |
286 | { ADAU1373_DRC(1) + 0x5, 0xc0 }, | |
287 | { ADAU1373_DRC(1) + 0x6, 0x00 }, | |
288 | { ADAU1373_DRC(1) + 0x7, 0x00 }, | |
289 | { ADAU1373_DRC(1) + 0x8, 0x00 }, | |
290 | { ADAU1373_DRC(1) + 0x9, 0xc0 }, | |
291 | { ADAU1373_DRC(1) + 0xa, 0x88 }, | |
292 | { ADAU1373_DRC(1) + 0xb, 0x7a }, | |
293 | { ADAU1373_DRC(1) + 0xc, 0xdf }, | |
294 | { ADAU1373_DRC(1) + 0xd, 0x20 }, | |
295 | { ADAU1373_DRC(1) + 0xe, 0x00 }, | |
296 | { ADAU1373_DRC(1) + 0xf, 0x00 }, | |
297 | { ADAU1373_DRC(2) + 0x0, 0x78 }, | |
298 | { ADAU1373_DRC(2) + 0x1, 0x18 }, | |
299 | { ADAU1373_DRC(2) + 0x2, 0x00 }, | |
300 | { ADAU1373_DRC(2) + 0x3, 0x00 }, | |
301 | { ADAU1373_DRC(2) + 0x4, 0x00 }, | |
302 | { ADAU1373_DRC(2) + 0x5, 0xc0 }, | |
303 | { ADAU1373_DRC(2) + 0x6, 0x00 }, | |
304 | { ADAU1373_DRC(2) + 0x7, 0x00 }, | |
305 | { ADAU1373_DRC(2) + 0x8, 0x00 }, | |
306 | { ADAU1373_DRC(2) + 0x9, 0xc0 }, | |
307 | { ADAU1373_DRC(2) + 0xa, 0x88 }, | |
308 | { ADAU1373_DRC(2) + 0xb, 0x7a }, | |
309 | { ADAU1373_DRC(2) + 0xc, 0xdf }, | |
310 | { ADAU1373_DRC(2) + 0xd, 0x20 }, | |
311 | { ADAU1373_DRC(2) + 0xe, 0x00 }, | |
312 | { ADAU1373_DRC(2) + 0xf, 0x00 }, | |
313 | { ADAU1373_3D_CTRL1, 0x00 }, | |
314 | { ADAU1373_3D_CTRL2, 0x00 }, | |
315 | { ADAU1373_FDSP_SEL1, 0x00 }, | |
316 | { ADAU1373_FDSP_SEL2, 0x00 }, | |
317 | { ADAU1373_FDSP_SEL2, 0x00 }, | |
318 | { ADAU1373_FDSP_SEL4, 0x00 }, | |
319 | { ADAU1373_DIGMICCTRL, 0x00 }, | |
320 | { ADAU1373_DIGEN, 0x00 }, | |
ddd7a260 LPC |
321 | }; |
322 | ||
31581f3c | 323 | static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv, |
ddd7a260 LPC |
324 | 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1), |
325 | 8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0), | |
326 | 16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0), | |
31581f3c LPC |
327 | 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0) |
328 | ); | |
ddd7a260 LPC |
329 | |
330 | static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0); | |
331 | static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1); | |
332 | static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1); | |
333 | ||
334 | static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0); | |
335 | static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0); | |
336 | static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0); | |
337 | ||
338 | static const char *adau1373_fdsp_sel_text[] = { | |
339 | "None", | |
340 | "Channel 1", | |
341 | "Channel 2", | |
342 | "Channel 3", | |
343 | "Channel 4", | |
344 | "Channel 5", | |
345 | }; | |
346 | ||
4988aff7 | 347 | static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum, |
ddd7a260 | 348 | ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text); |
4988aff7 | 349 | static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum, |
ddd7a260 | 350 | ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text); |
4988aff7 | 351 | static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum, |
ddd7a260 | 352 | ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text); |
4988aff7 | 353 | static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum, |
ddd7a260 | 354 | ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text); |
4988aff7 | 355 | static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum, |
ddd7a260 LPC |
356 | ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text); |
357 | ||
358 | static const char *adau1373_hpf_cutoff_text[] = { | |
359 | "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz", | |
360 | "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz", | |
361 | "800Hz", | |
362 | }; | |
363 | ||
4988aff7 | 364 | static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum, |
ddd7a260 LPC |
365 | ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text); |
366 | ||
367 | static const char *adau1373_bass_lpf_cutoff_text[] = { | |
368 | "801Hz", "1001Hz", | |
369 | }; | |
370 | ||
371 | static const char *adau1373_bass_clip_level_text[] = { | |
372 | "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875", | |
373 | }; | |
374 | ||
375 | static const unsigned int adau1373_bass_clip_level_values[] = { | |
376 | 1, 2, 3, 4, 5, 6, 7, | |
377 | }; | |
378 | ||
379 | static const char *adau1373_bass_hpf_cutoff_text[] = { | |
380 | "158Hz", "232Hz", "347Hz", "520Hz", | |
381 | }; | |
382 | ||
31581f3c | 383 | static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv, |
ddd7a260 LPC |
384 | 0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1), |
385 | 3, 4, TLV_DB_SCALE_ITEM(950, 250, 0), | |
31581f3c LPC |
386 | 5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0) |
387 | ); | |
ddd7a260 | 388 | |
4988aff7 | 389 | static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum, |
ddd7a260 LPC |
390 | ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text); |
391 | ||
4988aff7 | 392 | static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum, |
ddd7a260 LPC |
393 | ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text, |
394 | adau1373_bass_clip_level_values); | |
395 | ||
4988aff7 | 396 | static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum, |
ddd7a260 LPC |
397 | ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text); |
398 | ||
399 | static const char *adau1373_3d_level_text[] = { | |
400 | "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%", | |
401 | "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%", | |
402 | "80%", "86.67", "99.33%", "100%" | |
403 | }; | |
404 | ||
405 | static const char *adau1373_3d_cutoff_text[] = { | |
406 | "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs", | |
407 | "0.16875 fs", "0.27083 fs" | |
408 | }; | |
409 | ||
4988aff7 | 410 | static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum, |
ddd7a260 | 411 | ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text); |
4988aff7 | 412 | static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum, |
ddd7a260 LPC |
413 | ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text); |
414 | ||
31581f3c | 415 | static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv, |
ddd7a260 | 416 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
31581f3c LPC |
417 | 1, 7, TLV_DB_LINEAR_ITEM(-1800, -120) |
418 | ); | |
ddd7a260 LPC |
419 | |
420 | static const char *adau1373_lr_mux_text[] = { | |
421 | "Mute", | |
422 | "Right Channel (L+R)", | |
423 | "Left Channel (L+R)", | |
424 | "Stereo", | |
425 | }; | |
426 | ||
4988aff7 | 427 | static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum, |
ddd7a260 | 428 | ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text); |
4988aff7 | 429 | static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum, |
ddd7a260 | 430 | ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text); |
4988aff7 | 431 | static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum, |
ddd7a260 LPC |
432 | ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text); |
433 | ||
434 | static const struct snd_kcontrol_new adau1373_controls[] = { | |
435 | SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0), | |
436 | ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv), | |
437 | SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1), | |
438 | ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv), | |
439 | SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2), | |
440 | ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv), | |
441 | ||
442 | SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL, | |
443 | ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv), | |
444 | SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL, | |
445 | ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv), | |
446 | ||
447 | SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0), | |
448 | ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv), | |
449 | SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1), | |
450 | ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv), | |
451 | SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2), | |
452 | ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv), | |
453 | ||
454 | SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL, | |
455 | ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv), | |
456 | SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL, | |
457 | ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv), | |
458 | ||
459 | SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0), | |
460 | ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv), | |
461 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT, | |
462 | ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv), | |
463 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT, | |
464 | ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv), | |
465 | ||
466 | SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0), | |
467 | ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv), | |
468 | SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1), | |
469 | ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv), | |
470 | SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2), | |
471 | ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv), | |
472 | SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3), | |
473 | ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv), | |
474 | ||
475 | SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0, | |
476 | adau1373_ep_tlv), | |
477 | ||
478 | SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5, | |
479 | 1, 0, adau1373_gain_boost_tlv), | |
480 | SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3, | |
481 | 1, 0, adau1373_gain_boost_tlv), | |
482 | SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1, | |
483 | 1, 0, adau1373_gain_boost_tlv), | |
484 | SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5, | |
485 | 1, 0, adau1373_gain_boost_tlv), | |
486 | SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3, | |
487 | 1, 0, adau1373_gain_boost_tlv), | |
488 | SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1, | |
489 | 1, 0, adau1373_gain_boost_tlv), | |
490 | SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7, | |
491 | 1, 0, adau1373_gain_boost_tlv), | |
492 | SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5, | |
493 | 1, 0, adau1373_gain_boost_tlv), | |
494 | SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3, | |
495 | 1, 0, adau1373_gain_boost_tlv), | |
496 | SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1, | |
497 | 1, 0, adau1373_gain_boost_tlv), | |
498 | ||
499 | SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4, | |
500 | 1, 0, adau1373_input_boost_tlv), | |
501 | SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5, | |
502 | 1, 0, adau1373_input_boost_tlv), | |
503 | SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6, | |
504 | 1, 0, adau1373_input_boost_tlv), | |
505 | SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7, | |
506 | 1, 0, adau1373_input_boost_tlv), | |
507 | ||
508 | SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3, | |
509 | 1, 0, adau1373_speaker_boost_tlv), | |
510 | ||
511 | SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum), | |
512 | SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum), | |
513 | ||
514 | SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum), | |
515 | SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0), | |
516 | SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum), | |
517 | ||
518 | SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum), | |
84bd1879 | 519 | SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum), |
ddd7a260 LPC |
520 | SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum), |
521 | SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0), | |
522 | SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0, | |
523 | adau1373_bass_tlv), | |
524 | SOC_ENUM("Bass Channel", adau1373_bass_channel_enum), | |
525 | ||
526 | SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum), | |
527 | SOC_ENUM("3D Level", adau1373_3d_level_enum), | |
528 | SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0), | |
529 | SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0, | |
530 | adau1373_3d_tlv), | |
531 | SOC_ENUM("3D Channel", adau1373_bass_channel_enum), | |
532 | ||
533 | SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0), | |
534 | }; | |
535 | ||
536 | static const struct snd_kcontrol_new adau1373_lineout2_controls[] = { | |
537 | SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1), | |
538 | ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv), | |
539 | SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum), | |
540 | }; | |
541 | ||
542 | static const struct snd_kcontrol_new adau1373_drc_controls[] = { | |
543 | SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum), | |
544 | SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum), | |
545 | SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum), | |
546 | }; | |
547 | ||
548 | static int adau1373_pll_event(struct snd_soc_dapm_widget *w, | |
549 | struct snd_kcontrol *kcontrol, int event) | |
550 | { | |
de172051 | 551 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
c3df37c9 | 552 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
ddd7a260 LPC |
553 | unsigned int pll_id = w->name[3] - '1'; |
554 | unsigned int val; | |
555 | ||
556 | if (SND_SOC_DAPM_EVENT_ON(event)) | |
557 | val = ADAU1373_PLL_CTRL6_PLL_EN; | |
558 | else | |
559 | val = 0; | |
560 | ||
c3df37c9 | 561 | regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id), |
ddd7a260 LPC |
562 | ADAU1373_PLL_CTRL6_PLL_EN, val); |
563 | ||
564 | if (SND_SOC_DAPM_EVENT_ON(event)) | |
565 | mdelay(5); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static const char *adau1373_decimator_text[] = { | |
571 | "ADC", | |
572 | "DMIC1", | |
573 | }; | |
574 | ||
28963178 LPC |
575 | static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum, |
576 | adau1373_decimator_text); | |
ddd7a260 LPC |
577 | |
578 | static const struct snd_kcontrol_new adau1373_decimator_mux = | |
84bd1879 | 579 | SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum); |
ddd7a260 LPC |
580 | |
581 | static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = { | |
582 | SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0), | |
583 | SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0), | |
584 | SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0), | |
585 | SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0), | |
586 | SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0), | |
587 | }; | |
588 | ||
589 | static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = { | |
590 | SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0), | |
591 | SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0), | |
592 | SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0), | |
593 | SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0), | |
594 | SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0), | |
595 | }; | |
596 | ||
597 | #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ | |
598 | const struct snd_kcontrol_new _name[] = { \ | |
599 | SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \ | |
600 | SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \ | |
601 | SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \ | |
602 | SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \ | |
603 | SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \ | |
604 | SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \ | |
605 | SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \ | |
606 | SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \ | |
607 | } | |
608 | ||
609 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls, | |
610 | ADAU1373_LLINE1_MIX); | |
611 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls, | |
612 | ADAU1373_RLINE1_MIX); | |
613 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls, | |
614 | ADAU1373_LLINE2_MIX); | |
615 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls, | |
616 | ADAU1373_RLINE2_MIX); | |
617 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls, | |
618 | ADAU1373_LSPK_MIX); | |
619 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls, | |
620 | ADAU1373_RSPK_MIX); | |
621 | static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls, | |
622 | ADAU1373_EP_MIX); | |
623 | ||
624 | static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = { | |
625 | SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0), | |
626 | SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0), | |
627 | SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0), | |
628 | SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0), | |
629 | SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0), | |
630 | SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0), | |
631 | }; | |
632 | ||
633 | static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = { | |
634 | SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0), | |
635 | SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0), | |
636 | SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0), | |
637 | SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0), | |
638 | SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0), | |
639 | SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0), | |
640 | }; | |
641 | ||
642 | #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ | |
643 | const struct snd_kcontrol_new _name[] = { \ | |
644 | SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \ | |
645 | SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \ | |
646 | SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \ | |
647 | SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \ | |
648 | SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \ | |
649 | SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \ | |
650 | SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \ | |
651 | } | |
652 | ||
653 | static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls, | |
654 | ADAU1373_DIN_MIX_CTRL(0)); | |
655 | static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls, | |
656 | ADAU1373_DIN_MIX_CTRL(1)); | |
657 | static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls, | |
658 | ADAU1373_DIN_MIX_CTRL(2)); | |
659 | static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls, | |
660 | ADAU1373_DIN_MIX_CTRL(3)); | |
661 | static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls, | |
662 | ADAU1373_DIN_MIX_CTRL(4)); | |
663 | ||
664 | #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \ | |
665 | const struct snd_kcontrol_new _name[] = { \ | |
666 | SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \ | |
667 | SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \ | |
668 | SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \ | |
669 | SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \ | |
670 | SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \ | |
671 | } | |
672 | ||
673 | static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls, | |
674 | ADAU1373_DOUT_MIX_CTRL(0)); | |
675 | static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls, | |
676 | ADAU1373_DOUT_MIX_CTRL(1)); | |
677 | static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls, | |
678 | ADAU1373_DOUT_MIX_CTRL(2)); | |
679 | static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls, | |
680 | ADAU1373_DOUT_MIX_CTRL(3)); | |
681 | static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls, | |
682 | ADAU1373_DOUT_MIX_CTRL(4)); | |
683 | ||
684 | static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = { | |
685 | /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that | |
686 | * doesn't seem to be the case. */ | |
687 | SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0), | |
688 | SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0), | |
689 | ||
690 | SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0), | |
691 | SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0), | |
692 | ||
84bd1879 | 693 | SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0, |
ddd7a260 LPC |
694 | &adau1373_decimator_mux), |
695 | ||
696 | SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0), | |
697 | SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0), | |
698 | ||
699 | SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0), | |
700 | SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0), | |
701 | SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0), | |
702 | SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0), | |
703 | ||
704 | SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0), | |
705 | SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0), | |
706 | SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0), | |
707 | SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0), | |
708 | ||
709 | SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0, | |
710 | adau1373_left_adc_mixer_controls), | |
711 | SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0, | |
712 | adau1373_right_adc_mixer_controls), | |
713 | ||
714 | SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0, | |
715 | adau1373_left_line2_mixer_controls), | |
716 | SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0, | |
717 | adau1373_right_line2_mixer_controls), | |
718 | SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0, | |
719 | adau1373_left_line1_mixer_controls), | |
720 | SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0, | |
721 | adau1373_right_line1_mixer_controls), | |
722 | ||
723 | SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0, | |
724 | adau1373_ep_mixer_controls), | |
725 | SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0, | |
726 | adau1373_left_spk_mixer_controls), | |
727 | SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0, | |
728 | adau1373_right_spk_mixer_controls), | |
729 | SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
730 | adau1373_left_hp_mixer_controls), | |
731 | SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
732 | adau1373_right_hp_mixer_controls), | |
733 | SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0, | |
734 | NULL, 0), | |
735 | ||
736 | SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0, | |
737 | NULL, 0), | |
738 | SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0, | |
739 | NULL, 0), | |
740 | SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0, | |
741 | NULL, 0), | |
742 | SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0, | |
743 | NULL, 0), | |
744 | SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0, | |
745 | NULL, 0), | |
746 | SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0, | |
747 | NULL, 0), | |
748 | SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0, | |
749 | NULL, 0), | |
750 | SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0, | |
751 | NULL, 0), | |
752 | SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0, | |
753 | NULL, 0), | |
754 | ||
755 | SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
756 | SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
757 | SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
758 | SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
759 | SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), | |
760 | SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), | |
761 | ||
762 | SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0, | |
763 | adau1373_dsp_channel1_mixer_controls), | |
764 | SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0, | |
765 | adau1373_dsp_channel2_mixer_controls), | |
766 | SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0, | |
767 | adau1373_dsp_channel3_mixer_controls), | |
768 | SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0, | |
769 | adau1373_dsp_channel4_mixer_controls), | |
770 | SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0, | |
771 | adau1373_dsp_channel5_mixer_controls), | |
772 | ||
773 | SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0, | |
774 | adau1373_aif1_mixer_controls), | |
775 | SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0, | |
776 | adau1373_aif2_mixer_controls), | |
777 | SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0, | |
778 | adau1373_aif3_mixer_controls), | |
779 | SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0, | |
780 | adau1373_dac1_mixer_controls), | |
781 | SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0, | |
782 | adau1373_dac2_mixer_controls), | |
783 | ||
784 | SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0), | |
785 | SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0), | |
786 | SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0), | |
787 | SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0), | |
788 | SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0), | |
789 | ||
790 | SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event, | |
791 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
792 | SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event, | |
793 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
794 | SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0), | |
795 | SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0), | |
796 | ||
797 | SND_SOC_DAPM_INPUT("AIN1L"), | |
798 | SND_SOC_DAPM_INPUT("AIN1R"), | |
799 | SND_SOC_DAPM_INPUT("AIN2L"), | |
800 | SND_SOC_DAPM_INPUT("AIN2R"), | |
801 | SND_SOC_DAPM_INPUT("AIN3L"), | |
802 | SND_SOC_DAPM_INPUT("AIN3R"), | |
803 | SND_SOC_DAPM_INPUT("AIN4L"), | |
804 | SND_SOC_DAPM_INPUT("AIN4R"), | |
805 | ||
806 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
807 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
808 | ||
809 | SND_SOC_DAPM_OUTPUT("LOUT1L"), | |
810 | SND_SOC_DAPM_OUTPUT("LOUT1R"), | |
811 | SND_SOC_DAPM_OUTPUT("LOUT2L"), | |
812 | SND_SOC_DAPM_OUTPUT("LOUT2R"), | |
813 | SND_SOC_DAPM_OUTPUT("HPL"), | |
814 | SND_SOC_DAPM_OUTPUT("HPR"), | |
815 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
816 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
817 | SND_SOC_DAPM_OUTPUT("EP"), | |
818 | }; | |
819 | ||
820 | static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source, | |
821 | struct snd_soc_dapm_widget *sink) | |
822 | { | |
de172051 | 823 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
ddd7a260 LPC |
824 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
825 | unsigned int dai; | |
826 | const char *clk; | |
827 | ||
828 | dai = sink->name[3] - '1'; | |
829 | ||
830 | if (!adau1373->dais[dai].master) | |
831 | return 0; | |
832 | ||
833 | if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1) | |
834 | clk = "SYSCLK1"; | |
835 | else | |
836 | clk = "SYSCLK2"; | |
837 | ||
838 | return strcmp(source->name, clk) == 0; | |
839 | } | |
840 | ||
841 | static int adau1373_check_src(struct snd_soc_dapm_widget *source, | |
842 | struct snd_soc_dapm_widget *sink) | |
843 | { | |
de172051 | 844 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
ddd7a260 LPC |
845 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
846 | unsigned int dai; | |
847 | ||
848 | dai = sink->name[3] - '1'; | |
849 | ||
850 | return adau1373->dais[dai].enable_src; | |
851 | } | |
852 | ||
853 | #define DSP_CHANNEL_MIXER_ROUTES(_sink) \ | |
854 | { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \ | |
855 | { _sink, "DMIC2 Switch", "DMIC2" }, \ | |
856 | { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \ | |
857 | { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \ | |
858 | { _sink, "AIF1 Switch", "AIF1 IN" }, \ | |
859 | { _sink, "AIF2 Switch", "AIF2 IN" }, \ | |
860 | { _sink, "AIF3 Switch", "AIF3 IN" } | |
861 | ||
862 | #define DSP_OUTPUT_MIXER_ROUTES(_sink) \ | |
863 | { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \ | |
864 | { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \ | |
865 | { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \ | |
866 | { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \ | |
867 | { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" } | |
868 | ||
869 | #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \ | |
870 | { _sink, "Right DAC2 Switch", "Right DAC2" }, \ | |
871 | { _sink, "Left DAC2 Switch", "Left DAC2" }, \ | |
872 | { _sink, "Right DAC1 Switch", "Right DAC1" }, \ | |
873 | { _sink, "Left DAC1 Switch", "Left DAC1" }, \ | |
874 | { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \ | |
875 | { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \ | |
876 | { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \ | |
877 | { _sink, "Input 4 Bypass Switch", "IN4PGA" } | |
878 | ||
879 | #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \ | |
880 | { _sink, "Right DAC2 Switch", "Right DAC2" }, \ | |
881 | { _sink, "Left DAC2 Switch", "Left DAC2" }, \ | |
882 | { _sink, "Right DAC1 Switch", "Right DAC1" }, \ | |
883 | { _sink, "Left DAC1 Switch", "Left DAC1" }, \ | |
884 | { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \ | |
885 | { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \ | |
886 | { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \ | |
887 | { _sink, "Input 4 Bypass Switch", "IN4PGA" } | |
888 | ||
889 | static const struct snd_soc_dapm_route adau1373_dapm_routes[] = { | |
890 | { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" }, | |
891 | { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" }, | |
892 | { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" }, | |
893 | { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" }, | |
894 | { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" }, | |
895 | ||
896 | { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" }, | |
897 | { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" }, | |
898 | { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" }, | |
899 | { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" }, | |
900 | { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" }, | |
901 | ||
902 | { "Left ADC", NULL, "Left ADC Mixer" }, | |
903 | { "Right ADC", NULL, "Right ADC Mixer" }, | |
904 | ||
905 | { "Decimator Mux", "ADC", "Left ADC" }, | |
906 | { "Decimator Mux", "ADC", "Right ADC" }, | |
907 | { "Decimator Mux", "DMIC1", "DMIC1" }, | |
908 | ||
909 | DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"), | |
910 | DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"), | |
911 | DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"), | |
912 | DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"), | |
913 | DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"), | |
914 | ||
915 | DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"), | |
916 | DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"), | |
917 | DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"), | |
918 | DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"), | |
919 | DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"), | |
920 | ||
921 | { "AIF1 OUT", NULL, "AIF1 Mixer" }, | |
922 | { "AIF2 OUT", NULL, "AIF2 Mixer" }, | |
923 | { "AIF3 OUT", NULL, "AIF3 Mixer" }, | |
924 | { "Left DAC1", NULL, "DAC1 Mixer" }, | |
925 | { "Right DAC1", NULL, "DAC1 Mixer" }, | |
926 | { "Left DAC2", NULL, "DAC2 Mixer" }, | |
927 | { "Right DAC2", NULL, "DAC2 Mixer" }, | |
928 | ||
929 | LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"), | |
930 | RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"), | |
931 | LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"), | |
932 | RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"), | |
933 | LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"), | |
934 | RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"), | |
935 | ||
936 | { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" }, | |
937 | { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" }, | |
938 | { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" }, | |
939 | { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" }, | |
940 | { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" }, | |
941 | { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" }, | |
942 | { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" }, | |
943 | { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" }, | |
944 | { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" }, | |
945 | { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" }, | |
946 | { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" }, | |
947 | { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" }, | |
948 | ||
949 | { "Left Headphone Mixer", NULL, "Headphone Enable" }, | |
950 | { "Right Headphone Mixer", NULL, "Headphone Enable" }, | |
951 | ||
952 | { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" }, | |
953 | { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" }, | |
954 | { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" }, | |
955 | { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" }, | |
956 | { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" }, | |
957 | { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" }, | |
958 | { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" }, | |
959 | { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" }, | |
960 | ||
961 | { "LOUT1L", NULL, "Left Lineout1 Mixer" }, | |
962 | { "LOUT1R", NULL, "Right Lineout1 Mixer" }, | |
963 | { "LOUT2L", NULL, "Left Lineout2 Mixer" }, | |
964 | { "LOUT2R", NULL, "Right Lineout2 Mixer" }, | |
965 | { "SPKL", NULL, "Left Speaker Mixer" }, | |
966 | { "SPKR", NULL, "Right Speaker Mixer" }, | |
967 | { "HPL", NULL, "Left Headphone Mixer" }, | |
968 | { "HPR", NULL, "Right Headphone Mixer" }, | |
969 | { "EP", NULL, "Earpiece Mixer" }, | |
970 | ||
971 | { "IN1PGA", NULL, "AIN1L" }, | |
972 | { "IN2PGA", NULL, "AIN2L" }, | |
973 | { "IN3PGA", NULL, "AIN3L" }, | |
974 | { "IN4PGA", NULL, "AIN4L" }, | |
975 | { "IN1PGA", NULL, "AIN1R" }, | |
976 | { "IN2PGA", NULL, "AIN2R" }, | |
977 | { "IN3PGA", NULL, "AIN3R" }, | |
978 | { "IN4PGA", NULL, "AIN4R" }, | |
979 | ||
980 | { "SYSCLK1", NULL, "PLL1" }, | |
981 | { "SYSCLK2", NULL, "PLL2" }, | |
982 | ||
983 | { "Left DAC1", NULL, "SYSCLK1" }, | |
984 | { "Right DAC1", NULL, "SYSCLK1" }, | |
985 | { "Left DAC2", NULL, "SYSCLK1" }, | |
986 | { "Right DAC2", NULL, "SYSCLK1" }, | |
987 | { "Left ADC", NULL, "SYSCLK1" }, | |
988 | { "Right ADC", NULL, "SYSCLK1" }, | |
989 | ||
990 | { "DSP", NULL, "SYSCLK1" }, | |
991 | ||
992 | { "AIF1 Mixer", NULL, "DSP" }, | |
993 | { "AIF2 Mixer", NULL, "DSP" }, | |
994 | { "AIF3 Mixer", NULL, "DSP" }, | |
995 | { "DAC1 Mixer", NULL, "DSP" }, | |
996 | { "DAC2 Mixer", NULL, "DSP" }, | |
997 | { "DAC1 Mixer", NULL, "Playback Engine A" }, | |
998 | { "DAC2 Mixer", NULL, "Playback Engine B" }, | |
999 | { "Left ADC Mixer", NULL, "Recording Engine A" }, | |
1000 | { "Right ADC Mixer", NULL, "Recording Engine A" }, | |
1001 | ||
1002 | { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, | |
1003 | { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, | |
1004 | { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, | |
1005 | { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, | |
1006 | { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, | |
1007 | { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, | |
1008 | ||
1009 | { "AIF1 IN", NULL, "AIF1 CLK" }, | |
1010 | { "AIF1 OUT", NULL, "AIF1 CLK" }, | |
1011 | { "AIF2 IN", NULL, "AIF2 CLK" }, | |
1012 | { "AIF2 OUT", NULL, "AIF2 CLK" }, | |
1013 | { "AIF3 IN", NULL, "AIF3 CLK" }, | |
1014 | { "AIF3 OUT", NULL, "AIF3 CLK" }, | |
1015 | { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src }, | |
1016 | { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src }, | |
1017 | { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src }, | |
1018 | { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src }, | |
1019 | { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src }, | |
1020 | { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src }, | |
1021 | ||
1022 | { "DMIC1", NULL, "DMIC1DAT" }, | |
1023 | { "DMIC1", NULL, "SYSCLK1" }, | |
1024 | { "DMIC1", NULL, "Recording Engine A" }, | |
1025 | { "DMIC2", NULL, "DMIC2DAT" }, | |
1026 | { "DMIC2", NULL, "SYSCLK1" }, | |
1027 | { "DMIC2", NULL, "Recording Engine B" }, | |
1028 | }; | |
1029 | ||
1030 | static int adau1373_hw_params(struct snd_pcm_substream *substream, | |
1031 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
1032 | { | |
1033 | struct snd_soc_codec *codec = dai->codec; | |
1034 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); | |
1035 | struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; | |
1036 | unsigned int div; | |
1037 | unsigned int freq; | |
1038 | unsigned int ctrl; | |
1039 | ||
1040 | freq = adau1373_dai->sysclk; | |
1041 | ||
1042 | if (freq % params_rate(params) != 0) | |
1043 | return -EINVAL; | |
1044 | ||
1045 | switch (freq / params_rate(params)) { | |
1046 | case 1024: /* sysclk / 256 */ | |
1047 | div = 0; | |
1048 | break; | |
1049 | case 1536: /* 2/3 sysclk / 256 */ | |
1050 | div = 1; | |
1051 | break; | |
1052 | case 2048: /* 1/2 sysclk / 256 */ | |
1053 | div = 2; | |
1054 | break; | |
1055 | case 3072: /* 1/3 sysclk / 256 */ | |
1056 | div = 3; | |
1057 | break; | |
1058 | case 4096: /* 1/4 sysclk / 256 */ | |
1059 | div = 4; | |
1060 | break; | |
1061 | case 6144: /* 1/6 sysclk / 256 */ | |
1062 | div = 5; | |
1063 | break; | |
1064 | case 5632: /* 2/11 sysclk / 256 */ | |
1065 | div = 6; | |
1066 | break; | |
1067 | default: | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
1071 | adau1373_dai->enable_src = (div != 0); | |
1072 | ||
c3df37c9 | 1073 | regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id), |
14a1b8ca TG |
1074 | ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK, |
1075 | (div << 2) | ADAU1373_BCLKDIV_64); | |
ddd7a260 | 1076 | |
7c2aff6a MB |
1077 | switch (params_width(params)) { |
1078 | case 16: | |
ddd7a260 LPC |
1079 | ctrl = ADAU1373_DAI_WLEN_16; |
1080 | break; | |
7c2aff6a | 1081 | case 20: |
ddd7a260 LPC |
1082 | ctrl = ADAU1373_DAI_WLEN_20; |
1083 | break; | |
7c2aff6a | 1084 | case 24: |
ddd7a260 LPC |
1085 | ctrl = ADAU1373_DAI_WLEN_24; |
1086 | break; | |
7c2aff6a | 1087 | case 32: |
ddd7a260 LPC |
1088 | ctrl = ADAU1373_DAI_WLEN_32; |
1089 | break; | |
1090 | default: | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | ||
c3df37c9 | 1094 | return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id), |
ddd7a260 LPC |
1095 | ADAU1373_DAI_WLEN_MASK, ctrl); |
1096 | } | |
1097 | ||
1098 | static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1099 | { | |
1100 | struct snd_soc_codec *codec = dai->codec; | |
1101 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); | |
1102 | struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; | |
1103 | unsigned int ctrl; | |
1104 | ||
1105 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1106 | case SND_SOC_DAIFMT_CBM_CFM: | |
1107 | ctrl = ADAU1373_DAI_MASTER; | |
1108 | adau1373_dai->master = true; | |
1109 | break; | |
1110 | case SND_SOC_DAIFMT_CBS_CFS: | |
1111 | ctrl = 0; | |
458f6f69 | 1112 | adau1373_dai->master = false; |
ddd7a260 LPC |
1113 | break; |
1114 | default: | |
1115 | return -EINVAL; | |
1116 | } | |
1117 | ||
1118 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1119 | case SND_SOC_DAIFMT_I2S: | |
1120 | ctrl |= ADAU1373_DAI_FORMAT_I2S; | |
1121 | break; | |
1122 | case SND_SOC_DAIFMT_LEFT_J: | |
1123 | ctrl |= ADAU1373_DAI_FORMAT_LEFT_J; | |
1124 | break; | |
1125 | case SND_SOC_DAIFMT_RIGHT_J: | |
1126 | ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J; | |
1127 | break; | |
1128 | case SND_SOC_DAIFMT_DSP_B: | |
1129 | ctrl |= ADAU1373_DAI_FORMAT_DSP; | |
1130 | break; | |
1131 | default: | |
1132 | return -EINVAL; | |
1133 | } | |
1134 | ||
1135 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1136 | case SND_SOC_DAIFMT_NB_NF: | |
1137 | break; | |
1138 | case SND_SOC_DAIFMT_IB_NF: | |
1139 | ctrl |= ADAU1373_DAI_INVERT_BCLK; | |
1140 | break; | |
1141 | case SND_SOC_DAIFMT_NB_IF: | |
1142 | ctrl |= ADAU1373_DAI_INVERT_LRCLK; | |
1143 | break; | |
1144 | case SND_SOC_DAIFMT_IB_IF: | |
1145 | ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK; | |
1146 | break; | |
1147 | default: | |
1148 | return -EINVAL; | |
1149 | } | |
1150 | ||
c3df37c9 | 1151 | regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id), |
ddd7a260 LPC |
1152 | ~ADAU1373_DAI_WLEN_MASK, ctrl); |
1153 | ||
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai, | |
1158 | int clk_id, unsigned int freq, int dir) | |
1159 | { | |
1160 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(dai->codec); | |
1161 | struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; | |
1162 | ||
1163 | switch (clk_id) { | |
1164 | case ADAU1373_CLK_SRC_PLL1: | |
1165 | case ADAU1373_CLK_SRC_PLL2: | |
1166 | break; | |
1167 | default: | |
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
1171 | adau1373_dai->sysclk = freq; | |
1172 | adau1373_dai->clk_src = clk_id; | |
1173 | ||
c3df37c9 | 1174 | regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id), |
ddd7a260 LPC |
1175 | ADAU1373_BCLKDIV_SOURCE, clk_id << 5); |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
890754a8 | 1180 | static const struct snd_soc_dai_ops adau1373_dai_ops = { |
ddd7a260 LPC |
1181 | .hw_params = adau1373_hw_params, |
1182 | .set_sysclk = adau1373_set_dai_sysclk, | |
1183 | .set_fmt = adau1373_set_dai_fmt, | |
1184 | }; | |
1185 | ||
1186 | #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1187 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1188 | ||
1189 | static struct snd_soc_dai_driver adau1373_dai_driver[] = { | |
1190 | { | |
1191 | .id = 0, | |
1192 | .name = "adau1373-aif1", | |
1193 | .playback = { | |
1194 | .stream_name = "AIF1 Playback", | |
1195 | .channels_min = 2, | |
1196 | .channels_max = 2, | |
1197 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1198 | .formats = ADAU1373_FORMATS, | |
1199 | }, | |
1200 | .capture = { | |
1201 | .stream_name = "AIF1 Capture", | |
1202 | .channels_min = 2, | |
1203 | .channels_max = 2, | |
1204 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1205 | .formats = ADAU1373_FORMATS, | |
1206 | }, | |
1207 | .ops = &adau1373_dai_ops, | |
1208 | .symmetric_rates = 1, | |
1209 | }, | |
1210 | { | |
1211 | .id = 1, | |
1212 | .name = "adau1373-aif2", | |
1213 | .playback = { | |
1214 | .stream_name = "AIF2 Playback", | |
1215 | .channels_min = 2, | |
1216 | .channels_max = 2, | |
1217 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1218 | .formats = ADAU1373_FORMATS, | |
1219 | }, | |
1220 | .capture = { | |
1221 | .stream_name = "AIF2 Capture", | |
1222 | .channels_min = 2, | |
1223 | .channels_max = 2, | |
1224 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1225 | .formats = ADAU1373_FORMATS, | |
1226 | }, | |
1227 | .ops = &adau1373_dai_ops, | |
1228 | .symmetric_rates = 1, | |
1229 | }, | |
1230 | { | |
1231 | .id = 2, | |
1232 | .name = "adau1373-aif3", | |
1233 | .playback = { | |
1234 | .stream_name = "AIF3 Playback", | |
1235 | .channels_min = 2, | |
1236 | .channels_max = 2, | |
1237 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1238 | .formats = ADAU1373_FORMATS, | |
1239 | }, | |
1240 | .capture = { | |
1241 | .stream_name = "AIF3 Capture", | |
1242 | .channels_min = 2, | |
1243 | .channels_max = 2, | |
1244 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1245 | .formats = ADAU1373_FORMATS, | |
1246 | }, | |
1247 | .ops = &adau1373_dai_ops, | |
1248 | .symmetric_rates = 1, | |
1249 | }, | |
1250 | }; | |
1251 | ||
1252 | static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id, | |
1253 | int source, unsigned int freq_in, unsigned int freq_out) | |
1254 | { | |
c3df37c9 | 1255 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
ddd7a260 LPC |
1256 | unsigned int dpll_div = 0; |
1257 | unsigned int x, r, n, m, i, j, mode; | |
1258 | ||
1259 | switch (pll_id) { | |
1260 | case ADAU1373_PLL1: | |
1261 | case ADAU1373_PLL2: | |
1262 | break; | |
1263 | default: | |
1264 | return -EINVAL; | |
1265 | } | |
1266 | ||
1267 | switch (source) { | |
1268 | case ADAU1373_PLL_SRC_BCLK1: | |
1269 | case ADAU1373_PLL_SRC_BCLK2: | |
1270 | case ADAU1373_PLL_SRC_BCLK3: | |
1271 | case ADAU1373_PLL_SRC_LRCLK1: | |
1272 | case ADAU1373_PLL_SRC_LRCLK2: | |
1273 | case ADAU1373_PLL_SRC_LRCLK3: | |
1274 | case ADAU1373_PLL_SRC_MCLK1: | |
1275 | case ADAU1373_PLL_SRC_MCLK2: | |
1276 | case ADAU1373_PLL_SRC_GPIO1: | |
1277 | case ADAU1373_PLL_SRC_GPIO2: | |
1278 | case ADAU1373_PLL_SRC_GPIO3: | |
1279 | case ADAU1373_PLL_SRC_GPIO4: | |
1280 | break; | |
1281 | default: | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
1285 | if (freq_in < 7813 || freq_in > 27000000) | |
1286 | return -EINVAL; | |
1287 | ||
1288 | if (freq_out < 45158000 || freq_out > 49152000) | |
1289 | return -EINVAL; | |
1290 | ||
1291 | /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the | |
1292 | * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */ | |
1293 | while (freq_in < 8000000) { | |
1294 | freq_in *= 2; | |
1295 | dpll_div++; | |
1296 | } | |
1297 | ||
1298 | if (freq_out % freq_in != 0) { | |
1299 | /* fout = fin * (r + (n/m)) / x */ | |
1300 | x = DIV_ROUND_UP(freq_in, 13500000); | |
1301 | freq_in /= x; | |
1302 | r = freq_out / freq_in; | |
1303 | i = freq_out % freq_in; | |
1304 | j = gcd(i, freq_in); | |
1305 | n = i / j; | |
1306 | m = freq_in / j; | |
1307 | x--; | |
1308 | mode = 1; | |
1309 | } else { | |
1310 | /* fout = fin / r */ | |
1311 | r = freq_out / freq_in; | |
1312 | n = 0; | |
1313 | m = 0; | |
1314 | x = 0; | |
1315 | mode = 0; | |
1316 | } | |
1317 | ||
1318 | if (r < 2 || r > 8 || x > 3 || m > 0xffff || n > 0xffff) | |
1319 | return -EINVAL; | |
1320 | ||
1321 | if (dpll_div) { | |
1322 | dpll_div = 11 - dpll_div; | |
c3df37c9 | 1323 | regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id), |
ddd7a260 LPC |
1324 | ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0); |
1325 | } else { | |
c3df37c9 | 1326 | regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id), |
ddd7a260 LPC |
1327 | ADAU1373_PLL_CTRL6_DPLL_BYPASS, |
1328 | ADAU1373_PLL_CTRL6_DPLL_BYPASS); | |
1329 | } | |
1330 | ||
c3df37c9 | 1331 | regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id), |
ddd7a260 | 1332 | (source << 4) | dpll_div); |
c3df37c9 LPC |
1333 | regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff); |
1334 | regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), m & 0xff); | |
1335 | regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff); | |
1336 | regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), n & 0xff); | |
1337 | regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), | |
ddd7a260 LPC |
1338 | (r << 3) | (x << 1) | mode); |
1339 | ||
1340 | /* Set sysclk to pll_rate / 4 */ | |
c3df37c9 | 1341 | regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09); |
ddd7a260 LPC |
1342 | |
1343 | return 0; | |
1344 | } | |
1345 | ||
c3df37c9 | 1346 | static void adau1373_load_drc_settings(struct adau1373 *adau1373, |
ddd7a260 LPC |
1347 | unsigned int nr, uint8_t *drc) |
1348 | { | |
1349 | unsigned int i; | |
1350 | ||
1351 | for (i = 0; i < ADAU1373_DRC_SIZE; ++i) | |
c3df37c9 | 1352 | regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]); |
ddd7a260 LPC |
1353 | } |
1354 | ||
1355 | static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias) | |
1356 | { | |
1357 | switch (micbias) { | |
1358 | case ADAU1373_MICBIAS_2_9V: | |
1359 | case ADAU1373_MICBIAS_2_2V: | |
1360 | case ADAU1373_MICBIAS_2_6V: | |
1361 | case ADAU1373_MICBIAS_1_8V: | |
1362 | return true; | |
1363 | default: | |
1364 | break; | |
1365 | } | |
1366 | return false; | |
1367 | } | |
1368 | ||
1369 | static int adau1373_probe(struct snd_soc_codec *codec) | |
1370 | { | |
c3df37c9 | 1371 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
ddd7a260 LPC |
1372 | struct adau1373_platform_data *pdata = codec->dev->platform_data; |
1373 | bool lineout_differential = false; | |
1374 | unsigned int val; | |
ddd7a260 LPC |
1375 | int i; |
1376 | ||
ddd7a260 LPC |
1377 | if (pdata) { |
1378 | if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting)) | |
1379 | return -EINVAL; | |
1380 | ||
1381 | if (!adau1373_valid_micbias(pdata->micbias1) || | |
1382 | !adau1373_valid_micbias(pdata->micbias2)) | |
1383 | return -EINVAL; | |
1384 | ||
1385 | for (i = 0; i < pdata->num_drc; ++i) { | |
c3df37c9 | 1386 | adau1373_load_drc_settings(adau1373, i, |
ddd7a260 LPC |
1387 | pdata->drc_setting[i]); |
1388 | } | |
1389 | ||
022658be | 1390 | snd_soc_add_codec_controls(codec, adau1373_drc_controls, |
ddd7a260 LPC |
1391 | pdata->num_drc); |
1392 | ||
1393 | val = 0; | |
1394 | for (i = 0; i < 4; ++i) { | |
1395 | if (pdata->input_differential[i]) | |
1396 | val |= BIT(i); | |
1397 | } | |
c3df37c9 | 1398 | regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val); |
ddd7a260 LPC |
1399 | |
1400 | val = 0; | |
1401 | if (pdata->lineout_differential) | |
1402 | val |= ADAU1373_OUTPUT_CTRL_LDIFF; | |
1403 | if (pdata->lineout_ground_sense) | |
1404 | val |= ADAU1373_OUTPUT_CTRL_LNFBEN; | |
c3df37c9 | 1405 | regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val); |
ddd7a260 LPC |
1406 | |
1407 | lineout_differential = pdata->lineout_differential; | |
1408 | ||
c3df37c9 | 1409 | regmap_write(adau1373->regmap, ADAU1373_EP_CTRL, |
ddd7a260 LPC |
1410 | (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) | |
1411 | (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET)); | |
1412 | } | |
1413 | ||
1414 | if (!lineout_differential) { | |
022658be | 1415 | snd_soc_add_codec_controls(codec, adau1373_lineout2_controls, |
ddd7a260 LPC |
1416 | ARRAY_SIZE(adau1373_lineout2_controls)); |
1417 | } | |
1418 | ||
c3df37c9 | 1419 | regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL, |
ddd7a260 LPC |
1420 | ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT); |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | static int adau1373_set_bias_level(struct snd_soc_codec *codec, | |
1426 | enum snd_soc_bias_level level) | |
1427 | { | |
c3df37c9 LPC |
1428 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
1429 | ||
ddd7a260 LPC |
1430 | switch (level) { |
1431 | case SND_SOC_BIAS_ON: | |
1432 | break; | |
1433 | case SND_SOC_BIAS_PREPARE: | |
1434 | break; | |
1435 | case SND_SOC_BIAS_STANDBY: | |
c3df37c9 | 1436 | regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3, |
ddd7a260 LPC |
1437 | ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN); |
1438 | break; | |
1439 | case SND_SOC_BIAS_OFF: | |
c3df37c9 | 1440 | regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3, |
ddd7a260 LPC |
1441 | ADAU1373_PWDN_CTRL3_PWR_EN, 0); |
1442 | break; | |
1443 | } | |
ddd7a260 LPC |
1444 | return 0; |
1445 | } | |
1446 | ||
ddd7a260 LPC |
1447 | static int adau1373_resume(struct snd_soc_codec *codec) |
1448 | { | |
c3df37c9 LPC |
1449 | struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); |
1450 | ||
c3df37c9 | 1451 | regcache_sync(adau1373->regmap); |
ddd7a260 LPC |
1452 | |
1453 | return 0; | |
1454 | } | |
1455 | ||
c3df37c9 LPC |
1456 | static bool adau1373_register_volatile(struct device *dev, unsigned int reg) |
1457 | { | |
1458 | switch (reg) { | |
1459 | case ADAU1373_SOFT_RESET: | |
1460 | case ADAU1373_ADC_DAC_STATUS: | |
1461 | return true; | |
1462 | default: | |
1463 | return false; | |
1464 | } | |
1465 | } | |
1466 | ||
1467 | static const struct regmap_config adau1373_regmap_config = { | |
1468 | .val_bits = 8, | |
1469 | .reg_bits = 8, | |
1470 | ||
1471 | .volatile_reg = adau1373_register_volatile, | |
1472 | .max_register = ADAU1373_SOFT_RESET, | |
1473 | ||
1474 | .cache_type = REGCACHE_RBTREE, | |
1475 | .reg_defaults = adau1373_reg_defaults, | |
1476 | .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults), | |
1477 | }; | |
1478 | ||
ddd7a260 LPC |
1479 | static struct snd_soc_codec_driver adau1373_codec_driver = { |
1480 | .probe = adau1373_probe, | |
ddd7a260 LPC |
1481 | .resume = adau1373_resume, |
1482 | .set_bias_level = adau1373_set_bias_level, | |
eb3032f8 | 1483 | .idle_bias_off = true, |
ddd7a260 LPC |
1484 | |
1485 | .set_pll = adau1373_set_pll, | |
1486 | ||
1487 | .controls = adau1373_controls, | |
1488 | .num_controls = ARRAY_SIZE(adau1373_controls), | |
1489 | .dapm_widgets = adau1373_dapm_widgets, | |
1490 | .num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets), | |
1491 | .dapm_routes = adau1373_dapm_routes, | |
1492 | .num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes), | |
1493 | }; | |
1494 | ||
7a79e94e BP |
1495 | static int adau1373_i2c_probe(struct i2c_client *client, |
1496 | const struct i2c_device_id *id) | |
ddd7a260 LPC |
1497 | { |
1498 | struct adau1373 *adau1373; | |
1499 | int ret; | |
1500 | ||
80c2f9da | 1501 | adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL); |
ddd7a260 LPC |
1502 | if (!adau1373) |
1503 | return -ENOMEM; | |
1504 | ||
c3df37c9 LPC |
1505 | adau1373->regmap = devm_regmap_init_i2c(client, |
1506 | &adau1373_regmap_config); | |
1507 | if (IS_ERR(adau1373->regmap)) | |
1508 | return PTR_ERR(adau1373->regmap); | |
1509 | ||
729485f6 LPC |
1510 | regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00); |
1511 | ||
ddd7a260 LPC |
1512 | dev_set_drvdata(&client->dev, adau1373); |
1513 | ||
1514 | ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver, | |
1515 | adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver)); | |
ddd7a260 LPC |
1516 | return ret; |
1517 | } | |
1518 | ||
7a79e94e | 1519 | static int adau1373_i2c_remove(struct i2c_client *client) |
ddd7a260 LPC |
1520 | { |
1521 | snd_soc_unregister_codec(&client->dev); | |
ddd7a260 LPC |
1522 | return 0; |
1523 | } | |
1524 | ||
1525 | static const struct i2c_device_id adau1373_i2c_id[] = { | |
1526 | { "adau1373", 0 }, | |
1527 | { } | |
1528 | }; | |
1529 | MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id); | |
1530 | ||
1531 | static struct i2c_driver adau1373_i2c_driver = { | |
1532 | .driver = { | |
1533 | .name = "adau1373", | |
ddd7a260 LPC |
1534 | }, |
1535 | .probe = adau1373_i2c_probe, | |
7a79e94e | 1536 | .remove = adau1373_i2c_remove, |
ddd7a260 LPC |
1537 | .id_table = adau1373_i2c_id, |
1538 | }; | |
1539 | ||
d0b2d4fa | 1540 | module_i2c_driver(adau1373_i2c_driver); |
ddd7a260 LPC |
1541 | |
1542 | MODULE_DESCRIPTION("ASoC ADAU1373 driver"); | |
1543 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
1544 | MODULE_LICENSE("GPL"); |