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b0c813ce TT |
1 | /* |
2 | * CS4270 ALSA SoC (ASoC) codec driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
ff7bf02f TT |
6 | * Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed |
7 | * under the terms of the GNU General Public License version 2. This | |
8 | * program is licensed "as is" without any warranty of any kind, whether | |
9 | * express or implied. | |
b0c813ce TT |
10 | * |
11 | * This is an ASoC device driver for the Cirrus Logic CS4270 codec. | |
12 | * | |
13 | * Current features/limitations: | |
14 | * | |
b191f63c DM |
15 | * - Software mode is supported. Stand-alone mode is not supported. |
16 | * - Only I2C is supported, not SPI | |
17 | * - Support for master and slave mode | |
18 | * - The machine driver's 'startup' function must call | |
19 | * cs4270_set_dai_sysclk() with the value of MCLK. | |
20 | * - Only I2S and left-justified modes are supported | |
5e7c0344 | 21 | * - Power management is supported |
b0c813ce TT |
22 | */ |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/platform_device.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
b0c813ce TT |
27 | #include <sound/core.h> |
28 | #include <sound/soc.h> | |
29 | #include <sound/initval.h> | |
30 | #include <linux/i2c.h> | |
5e7c0344 | 31 | #include <linux/delay.h> |
ffbfd336 | 32 | #include <linux/regulator/consumer.h> |
b0c813ce | 33 | |
8432395f TT |
34 | /* |
35 | * The codec isn't really big-endian or little-endian, since the I2S | |
36 | * interface requires data to be sent serially with the MSbit first. | |
37 | * However, to support BE and LE I2S devices, we specify both here. That | |
38 | * way, ALSA will always match the bit patterns. | |
39 | */ | |
40 | #define CS4270_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ | |
41 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ | |
42 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ | |
43 | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
44 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \ | |
45 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE) | |
46 | ||
8432395f TT |
47 | /* CS4270 registers addresses */ |
48 | #define CS4270_CHIPID 0x01 /* Chip ID */ | |
49 | #define CS4270_PWRCTL 0x02 /* Power Control */ | |
50 | #define CS4270_MODE 0x03 /* Mode Control */ | |
51 | #define CS4270_FORMAT 0x04 /* Serial Format, ADC/DAC Control */ | |
52 | #define CS4270_TRANS 0x05 /* Transition Control */ | |
53 | #define CS4270_MUTE 0x06 /* Mute Control */ | |
54 | #define CS4270_VOLA 0x07 /* DAC Channel A Volume Control */ | |
55 | #define CS4270_VOLB 0x08 /* DAC Channel B Volume Control */ | |
56 | ||
57 | #define CS4270_FIRSTREG 0x01 | |
58 | #define CS4270_LASTREG 0x08 | |
59 | #define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1) | |
80ab8817 | 60 | #define CS4270_I2C_INCR 0x80 |
9dbd627b | 61 | |
8432395f TT |
62 | /* Bit masks for the CS4270 registers */ |
63 | #define CS4270_CHIPID_ID 0xF0 | |
64 | #define CS4270_CHIPID_REV 0x0F | |
65 | #define CS4270_PWRCTL_FREEZE 0x80 | |
66 | #define CS4270_PWRCTL_PDN_ADC 0x20 | |
67 | #define CS4270_PWRCTL_PDN_DAC 0x02 | |
68 | #define CS4270_PWRCTL_PDN 0x01 | |
5e7c0344 DM |
69 | #define CS4270_PWRCTL_PDN_ALL \ |
70 | (CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN) | |
8432395f TT |
71 | #define CS4270_MODE_SPEED_MASK 0x30 |
72 | #define CS4270_MODE_1X 0x00 | |
73 | #define CS4270_MODE_2X 0x10 | |
74 | #define CS4270_MODE_4X 0x20 | |
75 | #define CS4270_MODE_SLAVE 0x30 | |
76 | #define CS4270_MODE_DIV_MASK 0x0E | |
77 | #define CS4270_MODE_DIV1 0x00 | |
78 | #define CS4270_MODE_DIV15 0x02 | |
79 | #define CS4270_MODE_DIV2 0x04 | |
80 | #define CS4270_MODE_DIV3 0x06 | |
81 | #define CS4270_MODE_DIV4 0x08 | |
82 | #define CS4270_MODE_POPGUARD 0x01 | |
83 | #define CS4270_FORMAT_FREEZE_A 0x80 | |
84 | #define CS4270_FORMAT_FREEZE_B 0x40 | |
85 | #define CS4270_FORMAT_LOOPBACK 0x20 | |
86 | #define CS4270_FORMAT_DAC_MASK 0x18 | |
87 | #define CS4270_FORMAT_DAC_LJ 0x00 | |
88 | #define CS4270_FORMAT_DAC_I2S 0x08 | |
89 | #define CS4270_FORMAT_DAC_RJ16 0x18 | |
90 | #define CS4270_FORMAT_DAC_RJ24 0x10 | |
91 | #define CS4270_FORMAT_ADC_MASK 0x01 | |
92 | #define CS4270_FORMAT_ADC_LJ 0x00 | |
93 | #define CS4270_FORMAT_ADC_I2S 0x01 | |
94 | #define CS4270_TRANS_ONE_VOL 0x80 | |
95 | #define CS4270_TRANS_SOFT 0x40 | |
96 | #define CS4270_TRANS_ZERO 0x20 | |
97 | #define CS4270_TRANS_INV_ADC_A 0x08 | |
98 | #define CS4270_TRANS_INV_ADC_B 0x10 | |
99 | #define CS4270_TRANS_INV_DAC_A 0x02 | |
100 | #define CS4270_TRANS_INV_DAC_B 0x04 | |
101 | #define CS4270_TRANS_DEEMPH 0x01 | |
102 | #define CS4270_MUTE_AUTO 0x20 | |
103 | #define CS4270_MUTE_ADC_A 0x08 | |
104 | #define CS4270_MUTE_ADC_B 0x10 | |
105 | #define CS4270_MUTE_POLARITY 0x04 | |
106 | #define CS4270_MUTE_DAC_A 0x01 | |
107 | #define CS4270_MUTE_DAC_B 0x02 | |
108 | ||
ffbfd336 DM |
109 | static const char *supply_names[] = { |
110 | "va", "vd", "vlc" | |
111 | }; | |
112 | ||
0db4d070 TT |
113 | /* Private data for the CS4270 */ |
114 | struct cs4270_private { | |
f0fba2ad LG |
115 | enum snd_soc_control_type control_type; |
116 | void *control_data; | |
0db4d070 TT |
117 | u8 reg_cache[CS4270_NUMREGS]; |
118 | unsigned int mclk; /* Input frequency of the MCLK pin */ | |
119 | unsigned int mode; /* The mode (I2S or left-justified) */ | |
4eae080d | 120 | unsigned int slave_mode; |
1a4ba05e | 121 | unsigned int manual_mute; |
ffbfd336 DM |
122 | |
123 | /* power domain regulators */ | |
124 | struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; | |
0db4d070 TT |
125 | }; |
126 | ||
ff7bf02f TT |
127 | /** |
128 | * struct cs4270_mode_ratios - clock ratio tables | |
129 | * @ratio: the ratio of MCLK to the sample rate | |
130 | * @speed_mode: the Speed Mode bits to set in the Mode Control register for | |
131 | * this ratio | |
132 | * @mclk: the Ratio Select bits to set in the Mode Control register for this | |
133 | * ratio | |
8432395f TT |
134 | * |
135 | * The data for this chart is taken from Table 5 of the CS4270 reference | |
136 | * manual. | |
137 | * | |
138 | * This table is used to determine how to program the Mode Control register. | |
139 | * It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling | |
140 | * rates the CS4270 currently supports. | |
141 | * | |
ff7bf02f | 142 | * @speed_mode is the corresponding bit pattern to be written to the |
8432395f TT |
143 | * MODE bits of the Mode Control Register |
144 | * | |
ff7bf02f | 145 | * @mclk is the corresponding bit pattern to be wirten to the MCLK bits of |
8432395f TT |
146 | * the Mode Control Register. |
147 | * | |
148 | * In situations where a single ratio is represented by multiple speed | |
149 | * modes, we favor the slowest speed. E.g, for a ratio of 128, we pick | |
150 | * double-speed instead of quad-speed. However, the CS4270 errata states | |
ff7bf02f | 151 | * that divide-By-1.5 can cause failures, so we avoid that mode where |
8432395f TT |
152 | * possible. |
153 | * | |
ff7bf02f TT |
154 | * Errata: There is an errata for the CS4270 where divide-by-1.5 does not |
155 | * work if Vd is 3.3V. If this effects you, select the | |
8432395f TT |
156 | * CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will |
157 | * never select any sample rates that require divide-by-1.5. | |
158 | */ | |
ff7bf02f | 159 | struct cs4270_mode_ratios { |
8432395f TT |
160 | unsigned int ratio; |
161 | u8 speed_mode; | |
162 | u8 mclk; | |
ff7bf02f TT |
163 | }; |
164 | ||
d9fb7fbd | 165 | static struct cs4270_mode_ratios cs4270_mode_ratios[] = { |
8432395f TT |
166 | {64, CS4270_MODE_4X, CS4270_MODE_DIV1}, |
167 | #ifndef CONFIG_SND_SOC_CS4270_VD33_ERRATA | |
168 | {96, CS4270_MODE_4X, CS4270_MODE_DIV15}, | |
169 | #endif | |
170 | {128, CS4270_MODE_2X, CS4270_MODE_DIV1}, | |
171 | {192, CS4270_MODE_4X, CS4270_MODE_DIV3}, | |
172 | {256, CS4270_MODE_1X, CS4270_MODE_DIV1}, | |
173 | {384, CS4270_MODE_2X, CS4270_MODE_DIV3}, | |
174 | {512, CS4270_MODE_1X, CS4270_MODE_DIV2}, | |
175 | {768, CS4270_MODE_1X, CS4270_MODE_DIV3}, | |
176 | {1024, CS4270_MODE_1X, CS4270_MODE_DIV4} | |
177 | }; | |
178 | ||
179 | /* The number of MCLK/LRCK ratios supported by the CS4270 */ | |
180 | #define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios) | |
9dbd627b | 181 | |
ff7bf02f TT |
182 | /** |
183 | * cs4270_set_dai_sysclk - determine the CS4270 samples rates. | |
184 | * @codec_dai: the codec DAI | |
185 | * @clk_id: the clock ID (ignored) | |
186 | * @freq: the MCLK input frequency | |
187 | * @dir: the clock direction (ignored) | |
9dbd627b | 188 | * |
ff7bf02f TT |
189 | * This function is used to tell the codec driver what the input MCLK |
190 | * frequency is. | |
9dbd627b TT |
191 | * |
192 | * The value of MCLK is used to determine which sample rates are supported | |
193 | * by the CS4270. The ratio of MCLK / Fs must be equal to one of nine | |
ff7bf02f | 194 | * supported values - 64, 96, 128, 192, 256, 384, 512, 768, and 1024. |
9dbd627b TT |
195 | * |
196 | * This function calculates the nine ratios and determines which ones match | |
197 | * a standard sample rate. If there's a match, then it is added to the list | |
ff7bf02f | 198 | * of supported sample rates. |
9dbd627b TT |
199 | * |
200 | * This function must be called by the machine driver's 'startup' function, | |
201 | * otherwise the list of supported sample rates will not be available in | |
202 | * time for ALSA. | |
6aababdf DM |
203 | * |
204 | * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause | |
205 | * theoretically possible sample rates to be enabled. Call it again with a | |
206 | * proper value set one the external clock is set (most probably you would do | |
207 | * that from a machine's driver 'hw_param' hook. | |
9dbd627b | 208 | */ |
e550e17f | 209 | static int cs4270_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
9dbd627b TT |
210 | int clk_id, unsigned int freq, int dir) |
211 | { | |
212 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 213 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
9dbd627b TT |
214 | |
215 | cs4270->mclk = freq; | |
9dbd627b TT |
216 | return 0; |
217 | } | |
218 | ||
ff7bf02f TT |
219 | /** |
220 | * cs4270_set_dai_fmt - configure the codec for the selected audio format | |
221 | * @codec_dai: the codec DAI | |
222 | * @format: a SND_SOC_DAIFMT_x value indicating the data format | |
9dbd627b TT |
223 | * |
224 | * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the | |
225 | * codec accordingly. | |
226 | * | |
227 | * Currently, this function only supports SND_SOC_DAIFMT_I2S and | |
228 | * SND_SOC_DAIFMT_LEFT_J. The CS4270 codec also supports right-justified | |
229 | * data for playback only, but ASoC currently does not support different | |
230 | * formats for playback vs. record. | |
231 | */ | |
e550e17f | 232 | static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai, |
9dbd627b TT |
233 | unsigned int format) |
234 | { | |
235 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 236 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
9dbd627b TT |
237 | int ret = 0; |
238 | ||
4eae080d | 239 | /* set DAI format */ |
9dbd627b TT |
240 | switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { |
241 | case SND_SOC_DAIFMT_I2S: | |
242 | case SND_SOC_DAIFMT_LEFT_J: | |
243 | cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK; | |
244 | break; | |
245 | default: | |
a6c255e0 | 246 | dev_err(codec->dev, "invalid dai format\n"); |
9dbd627b TT |
247 | ret = -EINVAL; |
248 | } | |
249 | ||
4eae080d DM |
250 | /* set master/slave audio interface */ |
251 | switch (format & SND_SOC_DAIFMT_MASTER_MASK) { | |
252 | case SND_SOC_DAIFMT_CBS_CFS: | |
253 | cs4270->slave_mode = 1; | |
254 | break; | |
255 | case SND_SOC_DAIFMT_CBM_CFM: | |
256 | cs4270->slave_mode = 0; | |
257 | break; | |
4eae080d | 258 | default: |
ff09d49a | 259 | /* all other modes are unsupported by the hardware */ |
4eae080d DM |
260 | ret = -EINVAL; |
261 | } | |
262 | ||
9dbd627b TT |
263 | return ret; |
264 | } | |
265 | ||
ff7bf02f TT |
266 | /** |
267 | * cs4270_fill_cache - pre-fill the CS4270 register cache. | |
268 | * @codec: the codec for this CS4270 | |
269 | * | |
270 | * This function fills in the CS4270 register cache by reading the register | |
271 | * values from the hardware. | |
272 | * | |
273 | * This CS4270 registers are cached to avoid excessive I2C I/O operations. | |
274 | * After the initial read to pre-fill the cache, the CS4270 never updates | |
275 | * the register values, so we won't have a cache coherency problem. | |
b0c813ce TT |
276 | * |
277 | * We use the auto-increment feature of the CS4270 to read all registers in | |
278 | * one shot. | |
279 | */ | |
280 | static int cs4270_fill_cache(struct snd_soc_codec *codec) | |
281 | { | |
282 | u8 *cache = codec->reg_cache; | |
283 | struct i2c_client *i2c_client = codec->control_data; | |
284 | s32 length; | |
285 | ||
286 | length = i2c_smbus_read_i2c_block_data(i2c_client, | |
80ab8817 | 287 | CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache); |
b0c813ce TT |
288 | |
289 | if (length != CS4270_NUMREGS) { | |
a6c255e0 | 290 | dev_err(codec->dev, "i2c read failure, addr=0x%x\n", |
b0c813ce TT |
291 | i2c_client->addr); |
292 | return -EIO; | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
ff7bf02f TT |
298 | /** |
299 | * cs4270_read_reg_cache - read from the CS4270 register cache. | |
300 | * @codec: the codec for this CS4270 | |
301 | * @reg: the register to read | |
302 | * | |
303 | * This function returns the value for a given register. It reads only from | |
304 | * the register cache, not the hardware itself. | |
b0c813ce TT |
305 | * |
306 | * This CS4270 registers are cached to avoid excessive I2C I/O operations. | |
307 | * After the initial read to pre-fill the cache, the CS4270 never updates | |
ff7bf02f | 308 | * the register values, so we won't have a cache coherency problem. |
b0c813ce TT |
309 | */ |
310 | static unsigned int cs4270_read_reg_cache(struct snd_soc_codec *codec, | |
311 | unsigned int reg) | |
312 | { | |
313 | u8 *cache = codec->reg_cache; | |
314 | ||
315 | if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) | |
316 | return -EIO; | |
317 | ||
318 | return cache[reg - CS4270_FIRSTREG]; | |
319 | } | |
320 | ||
ff7bf02f TT |
321 | /** |
322 | * cs4270_i2c_write - write to a CS4270 register via the I2C bus. | |
323 | * @codec: the codec for this CS4270 | |
324 | * @reg: the register to write | |
325 | * @value: the value to write to the register | |
b0c813ce TT |
326 | * |
327 | * This function writes the given value to the given CS4270 register, and | |
328 | * also updates the register cache. | |
329 | * | |
330 | * Note that we don't use the hw_write function pointer of snd_soc_codec. | |
331 | * That's because it's too clunky: the hw_write_t prototype does not match | |
332 | * i2c_smbus_write_byte_data(), and it's just another layer of overhead. | |
333 | */ | |
334 | static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg, | |
335 | unsigned int value) | |
336 | { | |
bfc4e861 TT |
337 | u8 *cache = codec->reg_cache; |
338 | ||
b0c813ce TT |
339 | if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) |
340 | return -EIO; | |
341 | ||
bfc4e861 TT |
342 | /* Only perform an I2C operation if the new value is different */ |
343 | if (cache[reg - CS4270_FIRSTREG] != value) { | |
344 | struct i2c_client *client = codec->control_data; | |
345 | if (i2c_smbus_write_byte_data(client, reg, value)) { | |
a6c255e0 | 346 | dev_err(codec->dev, "i2c write failed\n"); |
bfc4e861 TT |
347 | return -EIO; |
348 | } | |
349 | ||
b0c813ce | 350 | /* We've written to the hardware, so update the cache */ |
b0c813ce | 351 | cache[reg - CS4270_FIRSTREG] = value; |
b0c813ce | 352 | } |
bfc4e861 TT |
353 | |
354 | return 0; | |
b0c813ce TT |
355 | } |
356 | ||
ff7bf02f TT |
357 | /** |
358 | * cs4270_hw_params - program the CS4270 with the given hardware parameters. | |
359 | * @substream: the audio stream | |
360 | * @params: the hardware parameters to set | |
361 | * @dai: the SOC DAI (ignored) | |
b0c813ce | 362 | * |
ff7bf02f TT |
363 | * This function programs the hardware with the values provided. |
364 | * Specifically, the sample rate and the data format. | |
365 | * | |
366 | * The .ops functions are used to provide board-specific data, like input | |
367 | * frequencies, to this driver. This function takes that information, | |
b0c813ce TT |
368 | * combines it with the hardware parameters provided, and programs the |
369 | * hardware accordingly. | |
370 | */ | |
371 | static int cs4270_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
372 | struct snd_pcm_hw_params *params, |
373 | struct snd_soc_dai *dai) | |
b0c813ce TT |
374 | { |
375 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 376 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 377 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
e34ba212 | 378 | int ret; |
b0c813ce TT |
379 | unsigned int i; |
380 | unsigned int rate; | |
381 | unsigned int ratio; | |
382 | int reg; | |
383 | ||
384 | /* Figure out which MCLK/LRCK ratio to use */ | |
385 | ||
386 | rate = params_rate(params); /* Sampling rate, in Hz */ | |
387 | ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */ | |
388 | ||
9dbd627b | 389 | for (i = 0; i < NUM_MCLK_RATIOS; i++) { |
8432395f | 390 | if (cs4270_mode_ratios[i].ratio == ratio) |
b0c813ce TT |
391 | break; |
392 | } | |
393 | ||
9dbd627b | 394 | if (i == NUM_MCLK_RATIOS) { |
b0c813ce | 395 | /* We did not find a matching ratio */ |
a6c255e0 | 396 | dev_err(codec->dev, "could not find matching ratio\n"); |
b0c813ce TT |
397 | return -EINVAL; |
398 | } | |
399 | ||
d5e9ba1d | 400 | /* Set the sample rate */ |
b0c813ce TT |
401 | |
402 | reg = snd_soc_read(codec, CS4270_MODE); | |
403 | reg &= ~(CS4270_MODE_SPEED_MASK | CS4270_MODE_DIV_MASK); | |
4eae080d DM |
404 | reg |= cs4270_mode_ratios[i].mclk; |
405 | ||
406 | if (cs4270->slave_mode) | |
407 | reg |= CS4270_MODE_SLAVE; | |
408 | else | |
409 | reg |= cs4270_mode_ratios[i].speed_mode; | |
b0c813ce TT |
410 | |
411 | ret = snd_soc_write(codec, CS4270_MODE, reg); | |
412 | if (ret < 0) { | |
a6c255e0 | 413 | dev_err(codec->dev, "i2c write failed\n"); |
b0c813ce TT |
414 | return ret; |
415 | } | |
416 | ||
d5e9ba1d | 417 | /* Set the DAI format */ |
b0c813ce TT |
418 | |
419 | reg = snd_soc_read(codec, CS4270_FORMAT); | |
420 | reg &= ~(CS4270_FORMAT_DAC_MASK | CS4270_FORMAT_ADC_MASK); | |
421 | ||
422 | switch (cs4270->mode) { | |
423 | case SND_SOC_DAIFMT_I2S: | |
424 | reg |= CS4270_FORMAT_DAC_I2S | CS4270_FORMAT_ADC_I2S; | |
425 | break; | |
426 | case SND_SOC_DAIFMT_LEFT_J: | |
427 | reg |= CS4270_FORMAT_DAC_LJ | CS4270_FORMAT_ADC_LJ; | |
428 | break; | |
429 | default: | |
a6c255e0 | 430 | dev_err(codec->dev, "unknown dai format\n"); |
b0c813ce TT |
431 | return -EINVAL; |
432 | } | |
433 | ||
434 | ret = snd_soc_write(codec, CS4270_FORMAT, reg); | |
435 | if (ret < 0) { | |
a6c255e0 | 436 | dev_err(codec->dev, "i2c write failed\n"); |
b0c813ce TT |
437 | return ret; |
438 | } | |
439 | ||
b0c813ce TT |
440 | return ret; |
441 | } | |
442 | ||
ff7bf02f | 443 | /** |
1a4ba05e | 444 | * cs4270_dai_mute - enable/disable the CS4270 external mute |
ff7bf02f TT |
445 | * @dai: the SOC DAI |
446 | * @mute: 0 = disable mute, 1 = enable mute | |
b0c813ce TT |
447 | * |
448 | * This function toggles the mute bits in the MUTE register. The CS4270's | |
449 | * mute capability is intended for external muting circuitry, so if the | |
450 | * board does not have the MUTEA or MUTEB pins connected to such circuitry, | |
451 | * then this function will do nothing. | |
452 | */ | |
1a4ba05e | 453 | static int cs4270_dai_mute(struct snd_soc_dai *dai, int mute) |
b0c813ce TT |
454 | { |
455 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 456 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
b0c813ce TT |
457 | int reg6; |
458 | ||
459 | reg6 = snd_soc_read(codec, CS4270_MUTE); | |
460 | ||
461 | if (mute) | |
d5e9ba1d | 462 | reg6 |= CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B; |
1a4ba05e | 463 | else { |
d5e9ba1d | 464 | reg6 &= ~(CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B); |
1a4ba05e DM |
465 | reg6 |= cs4270->manual_mute; |
466 | } | |
b0c813ce TT |
467 | |
468 | return snd_soc_write(codec, CS4270_MUTE, reg6); | |
469 | } | |
b0c813ce | 470 | |
1a4ba05e DM |
471 | /** |
472 | * cs4270_soc_put_mute - put callback for the 'Master Playback switch' | |
473 | * alsa control. | |
474 | * @kcontrol: mixer control | |
475 | * @ucontrol: control element information | |
476 | * | |
477 | * This function basically passes the arguments on to the generic | |
478 | * snd_soc_put_volsw() function and saves the mute information in | |
479 | * our private data structure. This is because we want to prevent | |
480 | * cs4270_dai_mute() neglecting the user's decision to manually | |
481 | * mute the codec's output. | |
482 | * | |
483 | * Returns 0 for success. | |
484 | */ | |
485 | static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol, | |
486 | struct snd_ctl_elem_value *ucontrol) | |
487 | { | |
488 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 489 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
1a4ba05e DM |
490 | int left = !ucontrol->value.integer.value[0]; |
491 | int right = !ucontrol->value.integer.value[1]; | |
492 | ||
493 | cs4270->manual_mute = (left ? CS4270_MUTE_DAC_A : 0) | | |
494 | (right ? CS4270_MUTE_DAC_B : 0); | |
495 | ||
496 | return snd_soc_put_volsw(kcontrol, ucontrol); | |
497 | } | |
498 | ||
b0c813ce TT |
499 | /* A list of non-DAPM controls that the CS4270 supports */ |
500 | static const struct snd_kcontrol_new cs4270_snd_controls[] = { | |
501 | SOC_DOUBLE_R("Master Playback Volume", | |
d5e9ba1d TT |
502 | CS4270_VOLA, CS4270_VOLB, 0, 0xFF, 1), |
503 | SOC_SINGLE("Digital Sidetone Switch", CS4270_FORMAT, 5, 1, 0), | |
504 | SOC_SINGLE("Soft Ramp Switch", CS4270_TRANS, 6, 1, 0), | |
505 | SOC_SINGLE("Zero Cross Switch", CS4270_TRANS, 5, 1, 0), | |
7e1aa1dc | 506 | SOC_SINGLE("De-emphasis filter", CS4270_TRANS, 0, 1, 0), |
d5e9ba1d TT |
507 | SOC_SINGLE("Popguard Switch", CS4270_MODE, 0, 1, 1), |
508 | SOC_SINGLE("Auto-Mute Switch", CS4270_MUTE, 5, 1, 0), | |
1a4ba05e DM |
509 | SOC_DOUBLE("Master Capture Switch", CS4270_MUTE, 3, 4, 1, 1), |
510 | SOC_DOUBLE_EXT("Master Playback Switch", CS4270_MUTE, 0, 1, 1, 1, | |
511 | snd_soc_get_volsw, cs4270_soc_put_mute), | |
b0c813ce TT |
512 | }; |
513 | ||
6335d055 EM |
514 | static struct snd_soc_dai_ops cs4270_dai_ops = { |
515 | .hw_params = cs4270_hw_params, | |
516 | .set_sysclk = cs4270_set_dai_sysclk, | |
517 | .set_fmt = cs4270_set_dai_fmt, | |
1a4ba05e | 518 | .digital_mute = cs4270_dai_mute, |
6335d055 EM |
519 | }; |
520 | ||
5c75848a | 521 | static struct snd_soc_dai_driver cs4270_dai = { |
f0fba2ad | 522 | .name = "cs4270-hifi", |
0db4d070 TT |
523 | .playback = { |
524 | .stream_name = "Playback", | |
525 | .channels_min = 1, | |
526 | .channels_max = 2, | |
f0fba2ad LG |
527 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
528 | .rate_min = 4000, | |
529 | .rate_max = 216000, | |
0db4d070 TT |
530 | .formats = CS4270_FORMATS, |
531 | }, | |
532 | .capture = { | |
533 | .stream_name = "Capture", | |
534 | .channels_min = 1, | |
535 | .channels_max = 2, | |
f0fba2ad LG |
536 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
537 | .rate_min = 4000, | |
538 | .rate_max = 216000, | |
0db4d070 TT |
539 | .formats = CS4270_FORMATS, |
540 | }, | |
6335d055 | 541 | .ops = &cs4270_dai_ops, |
0db4d070 | 542 | }; |
0db4d070 | 543 | |
ff7bf02f TT |
544 | /** |
545 | * cs4270_probe - ASoC probe function | |
546 | * @pdev: platform device | |
547 | * | |
548 | * This function is called when ASoC has all the pieces it needs to | |
549 | * instantiate a sound driver. | |
04eb093c | 550 | */ |
f0fba2ad | 551 | static int cs4270_probe(struct snd_soc_codec *codec) |
04eb093c | 552 | { |
b2c812e2 | 553 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
f0fba2ad | 554 | int i, ret, reg; |
04eb093c | 555 | |
f0fba2ad | 556 | codec->control_data = cs4270->control_data; |
b0c813ce TT |
557 | |
558 | /* The I2C interface is set up, so pre-fill our register cache */ | |
559 | ||
560 | ret = cs4270_fill_cache(codec); | |
561 | if (ret < 0) { | |
f0fba2ad LG |
562 | dev_err(codec->dev, "failed to fill register cache\n"); |
563 | return ret; | |
0db4d070 TT |
564 | } |
565 | ||
d5e9ba1d TT |
566 | /* Disable auto-mute. This feature appears to be buggy. In some |
567 | * situations, auto-mute will not deactivate when it should, so we want | |
568 | * this feature disabled by default. An application (e.g. alsactl) can | |
569 | * re-enabled it by using the controls. | |
570 | */ | |
571 | ||
572 | reg = cs4270_read_reg_cache(codec, CS4270_MUTE); | |
573 | reg &= ~CS4270_MUTE_AUTO; | |
574 | ret = cs4270_i2c_write(codec, CS4270_MUTE, reg); | |
575 | if (ret < 0) { | |
f0fba2ad | 576 | dev_err(codec->dev, "i2c write failed\n"); |
d5e9ba1d TT |
577 | return ret; |
578 | } | |
579 | ||
580 | /* Disable automatic volume control. The hardware enables, and it | |
581 | * causes volume change commands to be delayed, sometimes until after | |
582 | * playback has started. An application (e.g. alsactl) can | |
583 | * re-enabled it by using the controls. | |
584 | */ | |
585 | ||
586 | reg = cs4270_read_reg_cache(codec, CS4270_TRANS); | |
587 | reg &= ~(CS4270_TRANS_SOFT | CS4270_TRANS_ZERO); | |
588 | ret = cs4270_i2c_write(codec, CS4270_TRANS, reg); | |
589 | if (ret < 0) { | |
f0fba2ad | 590 | dev_err(codec->dev, "i2c write failed\n"); |
d5e9ba1d TT |
591 | return ret; |
592 | } | |
593 | ||
f0fba2ad LG |
594 | /* Add the non-DAPM controls */ |
595 | ret = snd_soc_add_controls(codec, cs4270_snd_controls, | |
596 | ARRAY_SIZE(cs4270_snd_controls)); | |
0db4d070 | 597 | if (ret < 0) { |
f0fba2ad LG |
598 | dev_err(codec->dev, "failed to add controls\n"); |
599 | return ret; | |
b0c813ce TT |
600 | } |
601 | ||
f0fba2ad LG |
602 | /* get the power supply regulators */ |
603 | for (i = 0; i < ARRAY_SIZE(supply_names); i++) | |
604 | cs4270->supplies[i].supply = supply_names[i]; | |
605 | ||
606 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(cs4270->supplies), | |
607 | cs4270->supplies); | |
608 | if (ret < 0) | |
609 | return ret; | |
610 | ||
611 | ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies), | |
612 | cs4270->supplies); | |
613 | if (ret < 0) | |
614 | goto error_free_regulators; | |
ec2cd95f | 615 | |
b0c813ce TT |
616 | return 0; |
617 | ||
f0fba2ad LG |
618 | error_free_regulators: |
619 | regulator_bulk_free(ARRAY_SIZE(cs4270->supplies), | |
620 | cs4270->supplies); | |
b0c813ce | 621 | |
b0c813ce TT |
622 | return ret; |
623 | } | |
624 | ||
ff7bf02f | 625 | /** |
f0fba2ad LG |
626 | * cs4270_remove - ASoC remove function |
627 | * @pdev: platform device | |
ff7bf02f | 628 | * |
f0fba2ad | 629 | * This function is the counterpart to cs4270_probe(). |
ff7bf02f | 630 | */ |
f0fba2ad | 631 | static int cs4270_remove(struct snd_soc_codec *codec) |
0db4d070 | 632 | { |
f0fba2ad | 633 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
0db4d070 | 634 | |
f0fba2ad LG |
635 | regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies), cs4270->supplies); |
636 | regulator_bulk_free(ARRAY_SIZE(cs4270->supplies), cs4270->supplies); | |
0db4d070 TT |
637 | |
638 | return 0; | |
ff637d38 | 639 | }; |
ff637d38 | 640 | |
5e7c0344 DM |
641 | #ifdef CONFIG_PM |
642 | ||
643 | /* This suspend/resume implementation can handle both - a simple standby | |
644 | * where the codec remains powered, and a full suspend, where the voltage | |
645 | * domain the codec is connected to is teared down and/or any other hardware | |
646 | * reset condition is asserted. | |
647 | * | |
648 | * The codec's own power saving features are enabled in the suspend callback, | |
649 | * and all registers are written back to the hardware when resuming. | |
650 | */ | |
651 | ||
f0fba2ad | 652 | static int cs4270_soc_suspend(struct snd_soc_codec *codec, pm_message_t mesg) |
15b5bdae | 653 | { |
b2c812e2 | 654 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
ffbfd336 | 655 | int reg, ret; |
15b5bdae | 656 | |
ffbfd336 DM |
657 | reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL; |
658 | if (reg < 0) | |
659 | return reg; | |
660 | ||
661 | ret = snd_soc_write(codec, CS4270_PWRCTL, reg); | |
662 | if (ret < 0) | |
663 | return ret; | |
664 | ||
665 | regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies), | |
666 | cs4270->supplies); | |
667 | ||
668 | return 0; | |
15b5bdae DM |
669 | } |
670 | ||
f0fba2ad | 671 | static int cs4270_soc_resume(struct snd_soc_codec *codec) |
15b5bdae | 672 | { |
b2c812e2 | 673 | struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); |
15b5bdae | 674 | struct i2c_client *i2c_client = codec->control_data; |
5e7c0344 DM |
675 | int reg; |
676 | ||
ffbfd336 DM |
677 | regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies), |
678 | cs4270->supplies); | |
679 | ||
5e7c0344 DM |
680 | /* In case the device was put to hard reset during sleep, we need to |
681 | * wait 500ns here before any I2C communication. */ | |
682 | ndelay(500); | |
683 | ||
684 | /* first restore the entire register cache ... */ | |
685 | for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) { | |
686 | u8 val = snd_soc_read(codec, reg); | |
687 | ||
15b5bdae | 688 | if (i2c_smbus_write_byte_data(i2c_client, reg, val)) { |
5e7c0344 DM |
689 | dev_err(codec->dev, "i2c write failed\n"); |
690 | return -EIO; | |
691 | } | |
692 | } | |
693 | ||
694 | /* ... then disable the power-down bits */ | |
695 | reg = snd_soc_read(codec, CS4270_PWRCTL); | |
696 | reg &= ~CS4270_PWRCTL_PDN_ALL; | |
697 | ||
698 | return snd_soc_write(codec, CS4270_PWRCTL, reg); | |
699 | } | |
700 | #else | |
15b5bdae DM |
701 | #define cs4270_soc_suspend NULL |
702 | #define cs4270_soc_resume NULL | |
5e7c0344 DM |
703 | #endif /* CONFIG_PM */ |
704 | ||
f0fba2ad LG |
705 | /* |
706 | * ASoC codec device structure | |
707 | * | |
708 | * Assign this variable to the codec_dev field of the machine driver's | |
709 | * snd_soc_device structure. | |
710 | */ | |
711 | static struct snd_soc_codec_driver soc_codec_device_cs4270 = { | |
712 | .probe = cs4270_probe, | |
713 | .remove = cs4270_remove, | |
714 | .suspend = cs4270_soc_suspend, | |
715 | .resume = cs4270_soc_resume, | |
716 | .read = cs4270_read_reg_cache, | |
717 | .write = cs4270_i2c_write, | |
718 | .reg_cache_size = CS4270_NUMREGS, | |
719 | .reg_word_size = sizeof(u8), | |
720 | }; | |
721 | ||
722 | /** | |
723 | * cs4270_i2c_probe - initialize the I2C interface of the CS4270 | |
724 | * @i2c_client: the I2C client object | |
725 | * @id: the I2C device ID (ignored) | |
726 | * | |
727 | * This function is called whenever the I2C subsystem finds a device that | |
728 | * matches the device ID given via a prior call to i2c_add_driver(). | |
729 | */ | |
730 | static int cs4270_i2c_probe(struct i2c_client *i2c_client, | |
731 | const struct i2c_device_id *id) | |
732 | { | |
733 | struct cs4270_private *cs4270; | |
734 | int ret; | |
735 | ||
736 | /* Verify that we have a CS4270 */ | |
737 | ||
738 | ret = i2c_smbus_read_byte_data(i2c_client, CS4270_CHIPID); | |
739 | if (ret < 0) { | |
740 | dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n", | |
741 | i2c_client->addr); | |
742 | return ret; | |
743 | } | |
744 | /* The top four bits of the chip ID should be 1100. */ | |
745 | if ((ret & 0xF0) != 0xC0) { | |
746 | dev_err(&i2c_client->dev, "device at addr %X is not a CS4270\n", | |
747 | i2c_client->addr); | |
748 | return -ENODEV; | |
749 | } | |
750 | ||
751 | dev_info(&i2c_client->dev, "found device at i2c address %X\n", | |
752 | i2c_client->addr); | |
753 | dev_info(&i2c_client->dev, "hardware revision %X\n", ret & 0xF); | |
754 | ||
755 | cs4270 = kzalloc(sizeof(struct cs4270_private), GFP_KERNEL); | |
756 | if (!cs4270) { | |
757 | dev_err(&i2c_client->dev, "could not allocate codec\n"); | |
758 | return -ENOMEM; | |
759 | } | |
760 | ||
761 | i2c_set_clientdata(i2c_client, cs4270); | |
762 | cs4270->control_data = i2c_client; | |
763 | cs4270->control_type = SND_SOC_I2C; | |
764 | ||
765 | ret = snd_soc_register_codec(&i2c_client->dev, | |
766 | &soc_codec_device_cs4270, &cs4270_dai, 1); | |
767 | if (ret < 0) | |
768 | kfree(cs4270); | |
769 | return ret; | |
770 | } | |
771 | ||
772 | /** | |
773 | * cs4270_i2c_remove - remove an I2C device | |
774 | * @i2c_client: the I2C client object | |
775 | * | |
776 | * This function is the counterpart to cs4270_i2c_probe(). | |
777 | */ | |
778 | static int cs4270_i2c_remove(struct i2c_client *i2c_client) | |
779 | { | |
780 | snd_soc_unregister_codec(&i2c_client->dev); | |
781 | kfree(i2c_get_clientdata(i2c_client)); | |
782 | return 0; | |
783 | } | |
784 | ||
785 | /* | |
786 | * cs4270_id - I2C device IDs supported by this driver | |
787 | */ | |
788 | static struct i2c_device_id cs4270_id[] = { | |
789 | {"cs4270", 0}, | |
790 | {} | |
791 | }; | |
792 | MODULE_DEVICE_TABLE(i2c, cs4270_id); | |
793 | ||
ff7bf02f TT |
794 | /* |
795 | * cs4270_i2c_driver - I2C device identification | |
796 | * | |
797 | * This structure tells the I2C subsystem how to identify and support a | |
798 | * given I2C device type. | |
799 | */ | |
ff637d38 TT |
800 | static struct i2c_driver cs4270_i2c_driver = { |
801 | .driver = { | |
f0fba2ad | 802 | .name = "cs4270-codec", |
ff637d38 TT |
803 | .owner = THIS_MODULE, |
804 | }, | |
805 | .id_table = cs4270_id, | |
806 | .probe = cs4270_i2c_probe, | |
0db4d070 | 807 | .remove = cs4270_i2c_remove, |
ff637d38 | 808 | }; |
b0c813ce | 809 | |
c9b3a40f | 810 | static int __init cs4270_init(void) |
64089b84 | 811 | { |
a6c255e0 | 812 | pr_info("Cirrus Logic CS4270 ALSA SoC Codec Driver\n"); |
0db4d070 | 813 | |
04eb093c | 814 | return i2c_add_driver(&cs4270_i2c_driver); |
64089b84 MB |
815 | } |
816 | module_init(cs4270_init); | |
817 | ||
818 | static void __exit cs4270_exit(void) | |
819 | { | |
04eb093c | 820 | i2c_del_driver(&cs4270_i2c_driver); |
64089b84 MB |
821 | } |
822 | module_exit(cs4270_exit); | |
823 | ||
b0c813ce TT |
824 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
825 | MODULE_DESCRIPTION("Cirrus Logic CS4270 ALSA SoC Codec Driver"); | |
826 | MODULE_LICENSE("GPL"); |