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ASoC: rt5677: Revise the filter powers
[deliverable/linux.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
f9f6a592 18#include <linux/of_gpio.h>
0e826e86
OC		 19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
af48f1d0 23#include <linux/firmware.h>
44caf764 24#include <linux/gpio.h>
0e826e86
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
30f14b43 33#include "rl6231.h"
0e826e86 34#include "rt5677.h"
af48f1d0 35#include "rt5677-spi.h"
0e826e86
OC		 36
37#define RT5677_DEVICE_ID 0x6327
38
39#define RT5677_PR_RANGE_BASE (0xff + 1)
40#define RT5677_PR_SPACING 0x100
41
42#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
2dfe2b08
OC		 58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
0e826e86
OC		 65};
66#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
67
68static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
86ae04b1 177 {RT5677_ASRC_12 , 0x0018},
0e826e86
OC		 178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
272};
273
274static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
275{
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
281 return true;
282 }
283 }
284
285 switch (reg) {
286 case RT5677_RESET:
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320}
321
322static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323{
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541}
542
af48f1d0
OC		 543/**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
19ba484d 545 * @rt5677: Private Data.
af48f1d0
OC		 546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
19ba484d 552static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
af48f1d0
OC		 553 unsigned int addr, unsigned int value, unsigned int opcode)
554{
19ba484d 555 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
19ba484d
OC		 560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
af48f1d0
OC		 562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
19ba484d 567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
19ba484d 574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
af48f1d0
OC		 575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
19ba484d 581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
af48f1d0
OC		 582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
19ba484d
OC		 588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
af48f1d0
OC		 590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599}
600
601/**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
19ba484d 603 * rt5677: Private Data.
af48f1d0
OC		 604 * @addr: Address index.
605 * @value: Address data.
606 *
19ba484d 607 *
af48f1d0
OC		 608 * Returns 0 for success or negative error code.
609 */
610static int rt5677_dsp_mode_i2c_read_addr(
19ba484d 611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
af48f1d0 612{
19ba484d 613 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
19ba484d
OC		 619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
af48f1d0
OC		 621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
19ba484d 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
19ba484d
OC		 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
af48f1d0
OC		 635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
19ba484d
OC		 640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
af48f1d0
OC		 642 *value = (msb << 16) | lsb;
643
644err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648}
649
650/**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
19ba484d 652 * rt5677: Private Data.
af48f1d0
OC		 653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
19ba484d 659static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
af48f1d0
OC		 660 unsigned int reg, unsigned int value)
661{
19ba484d 662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
af48f1d0
OC		 663 value, 0x0001);
664}
665
666/**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
19ba484d 670 * @value: Register data.
af48f1d0
OC		 671 *
672 *
19ba484d 673 * Returns 0 for success or negative error code.
af48f1d0 674 */
19ba484d
OC		 675static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
af48f1d0 677{
19ba484d
OC		 678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
af48f1d0 680
19ba484d 681 *value &= 0xffff;
af48f1d0 682
19ba484d 683 return ret;
af48f1d0
OC		 684}
685
19ba484d 686static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
af48f1d0 687{
19ba484d 688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
af48f1d0 689
19ba484d
OC		 690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
af48f1d0 696 }
af48f1d0
OC		 697}
698
699static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700{
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
705 if (on && !activity) {
706 activity = true;
707
708 regcache_cache_only(rt5677->regmap, false);
709 regcache_cache_bypass(rt5677->regmap, true);
710
711 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
712 regmap_update_bits(rt5677->regmap,
713 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
714 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
715 RT5677_LDO1_SEL_MASK, 0x0);
716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
717 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
19ba484d
OC		 718 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
719 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
720 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
721 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
722 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
af48f1d0 723 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
19ba484d
OC		 724 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
725 rt5677_set_dsp_mode(codec, true);
af48f1d0
OC		 726
727 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
728 codec->dev);
729 if (ret == 0) {
730 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
731 release_firmware(rt5677->fw1);
732 }
733
734 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
735 codec->dev);
736 if (ret == 0) {
737 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
738 release_firmware(rt5677->fw2);
739 }
740
19ba484d 741 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
af48f1d0
OC		 742
743 regcache_cache_bypass(rt5677->regmap, false);
744 regcache_cache_only(rt5677->regmap, true);
745 } else if (!on && activity) {
746 activity = false;
747
748 regcache_cache_only(rt5677->regmap, false);
749 regcache_cache_bypass(rt5677->regmap, true);
750
19ba484d
OC		 751 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
752 rt5677_set_dsp_mode(codec, false);
753 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
af48f1d0
OC		 754
755 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
756
757 regcache_cache_bypass(rt5677->regmap, false);
758 regcache_mark_dirty(rt5677->regmap);
759 regcache_sync(rt5677->regmap);
760 }
761
762 return 0;
763}
764
0e826e86 765static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
40e3262e 766static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0e826e86 767static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
40e3262e 768static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0e826e86 769static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 770static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 771
772/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
773static unsigned int bst_tlv[] = {
774 TLV_DB_RANGE_HEAD(7),
775 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
776 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
777 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
778 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
779 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
780 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
781 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
782};
783
af48f1d0
OC		 784static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
785 struct snd_ctl_elem_value *ucontrol)
786{
787 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
788 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
789
790 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
791
792 return 0;
793}
794
795static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
796 struct snd_ctl_elem_value *ucontrol)
797{
798 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
799 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
800
801 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
802
803 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
804 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
805
806 return 0;
807}
808
0e826e86
OC		 809static const struct snd_kcontrol_new rt5677_snd_controls[] = {
810 /* OUTPUT Control */
811 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
812 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
813 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
814 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
815 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
816 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
817
818 /* DAC Digital Volume */
819 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
40e3262e 820 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 821 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
40e3262e 822 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 823 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
40e3262e 824 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 825 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
40e3262e 826 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86
OC		 827
828 /* IN1/IN2 Control */
829 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
830 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
831
832 /* ADC Digital Volume Control */
833 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
834 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
835 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
836 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
837 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
838 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
839 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
840 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
841 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
842 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
843
844 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
40e3262e 845 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 846 adc_vol_tlv),
847 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
40e3262e 848 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 849 adc_vol_tlv),
850 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
40e3262e 851 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 852 adc_vol_tlv),
853 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
40e3262e 854 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 855 adc_vol_tlv),
856 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
40e3262e 857 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 858 adc_vol_tlv),
859
90bdbb46
OC		 860 /* Sidetone Control */
861 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
862 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
863
0e826e86 864 /* ADC Boost Volume Control */
80220f29 865 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 866 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
867 adc_bst_tlv),
80220f29 868 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 869 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
870 adc_bst_tlv),
80220f29 871 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 872 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
873 adc_bst_tlv),
80220f29 874 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 875 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
876 adc_bst_tlv),
80220f29 877 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 878 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
879 adc_bst_tlv),
af48f1d0
OC		 880
881 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
882 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 883};
884
885/**
886 * set_dmic_clk - Set parameter of dmic.
887 *
888 * @w: DAPM widget.
889 * @kcontrol: The kcontrol of this widget.
890 * @event: Event id.
891 *
892 * Choose dmic clock between 1MHz and 3MHz.
893 * It is better for clock to approximate 3MHz.
894 */
895static int set_dmic_clk(struct snd_soc_dapm_widget *w,
896 struct snd_kcontrol *kcontrol, int event)
897{
898 struct snd_soc_codec *codec = w->codec;
899 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9a53581e 900 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
0e826e86
OC		 901
902 if (idx < 0)
903 dev_err(codec->dev, "Failed to set DMIC clock\n");
904 else
905 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
906 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
907 return idx;
908}
909
910static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
911 struct snd_soc_dapm_widget *sink)
912{
913 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
914 unsigned int val;
915
916 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
917 val &= RT5677_SCLK_SRC_MASK;
918 if (val == RT5677_SCLK_SRC_PLL1)
919 return 1;
920 else
921 return 0;
922}
923
924/* Digital Mixer */
925static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
926 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
927 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
928 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
929 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
930};
931
932static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
933 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
934 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
935 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
936 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
937};
938
939static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
940 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
941 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
942 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
943 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
944};
945
946static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
947 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
948 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
949 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
950 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
951};
952
953static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
954 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
955 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
956 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
957 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
958};
959
960static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
961 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
962 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
963 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
964 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
965};
966
967static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
968 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
969 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
970 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
971 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
972};
973
974static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
975 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
976 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
977 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
978 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
979};
980
981static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
982 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
983 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
984 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
985 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
986};
987
988static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
989 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
990 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
991 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
992 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
993};
994
995static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
996 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
997 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
998 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
999 RT5677_M_DAC1_L_SFT, 1, 1),
1000};
1001
1002static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1003 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1004 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1005 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1006 RT5677_M_DAC1_R_SFT, 1, 1),
1007};
1008
1009static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1010 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1011 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1012 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1013 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1014 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1015 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1016 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1017 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1018};
1019
1020static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1021 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1022 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1023 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1024 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1025 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1026 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1027 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1028 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1029};
1030
1031static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1032 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1033 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1034 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1035 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1036 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1037 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1038 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1039 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1040};
1041
1042static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1043 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1044 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1045 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1046 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1047 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1048 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1049 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1050 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1051};
1052
1053static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1054 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1055 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1056 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1057 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1058 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1059 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1060 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1061 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1062};
1063
1064static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1065 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1066 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1067 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1068 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1069 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1070 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1071 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1072 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1073};
1074
1075static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1076 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1077 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1078 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1079 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1080 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1081 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1082 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1083 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1084};
1085
1086static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1087 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1088 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1089 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1090 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1091 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1092 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1093 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1094 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1095};
1096
1097static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1098 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1099 RT5677_DSP_IB_01_H_SFT, 1, 1),
1100 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1101 RT5677_DSP_IB_23_H_SFT, 1, 1),
1102 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1103 RT5677_DSP_IB_45_H_SFT, 1, 1),
1104 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1105 RT5677_DSP_IB_6_H_SFT, 1, 1),
1106 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1107 RT5677_DSP_IB_7_H_SFT, 1, 1),
1108 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1109 RT5677_DSP_IB_8_H_SFT, 1, 1),
1110 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1111 RT5677_DSP_IB_9_H_SFT, 1, 1),
1112};
1113
1114static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1115 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1116 RT5677_DSP_IB_01_L_SFT, 1, 1),
1117 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1118 RT5677_DSP_IB_23_L_SFT, 1, 1),
1119 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1120 RT5677_DSP_IB_45_L_SFT, 1, 1),
1121 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1122 RT5677_DSP_IB_6_L_SFT, 1, 1),
1123 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1124 RT5677_DSP_IB_7_L_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1126 RT5677_DSP_IB_8_L_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1128 RT5677_DSP_IB_9_L_SFT, 1, 1),
1129};
1130
1131static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1132 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1133 RT5677_DSP_IB_01_H_SFT, 1, 1),
1134 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1135 RT5677_DSP_IB_23_H_SFT, 1, 1),
1136 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1137 RT5677_DSP_IB_45_H_SFT, 1, 1),
1138 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1139 RT5677_DSP_IB_6_H_SFT, 1, 1),
1140 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1141 RT5677_DSP_IB_7_H_SFT, 1, 1),
1142 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1143 RT5677_DSP_IB_8_H_SFT, 1, 1),
1144 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1145 RT5677_DSP_IB_9_H_SFT, 1, 1),
1146};
1147
1148static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1149 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1150 RT5677_DSP_IB_01_L_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1152 RT5677_DSP_IB_23_L_SFT, 1, 1),
1153 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1154 RT5677_DSP_IB_45_L_SFT, 1, 1),
1155 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1156 RT5677_DSP_IB_6_L_SFT, 1, 1),
1157 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1158 RT5677_DSP_IB_7_L_SFT, 1, 1),
1159 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1160 RT5677_DSP_IB_8_L_SFT, 1, 1),
1161 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1162 RT5677_DSP_IB_9_L_SFT, 1, 1),
1163};
1164
1165static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1166 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1167 RT5677_DSP_IB_01_H_SFT, 1, 1),
1168 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1169 RT5677_DSP_IB_23_H_SFT, 1, 1),
1170 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1171 RT5677_DSP_IB_45_H_SFT, 1, 1),
1172 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1173 RT5677_DSP_IB_6_H_SFT, 1, 1),
1174 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1175 RT5677_DSP_IB_7_H_SFT, 1, 1),
1176 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1177 RT5677_DSP_IB_8_H_SFT, 1, 1),
1178 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1179 RT5677_DSP_IB_9_H_SFT, 1, 1),
1180};
1181
1182static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1183 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1184 RT5677_DSP_IB_01_L_SFT, 1, 1),
1185 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1186 RT5677_DSP_IB_23_L_SFT, 1, 1),
1187 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1188 RT5677_DSP_IB_45_L_SFT, 1, 1),
1189 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1190 RT5677_DSP_IB_6_L_SFT, 1, 1),
1191 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1192 RT5677_DSP_IB_7_L_SFT, 1, 1),
1193 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1194 RT5677_DSP_IB_8_L_SFT, 1, 1),
1195 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1196 RT5677_DSP_IB_9_L_SFT, 1, 1),
1197};
1198
1199
1200/* Mux */
1b7fd76a 1201/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1202static const char * const rt5677_dac1_src[] = {
1203 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1204 "OB 01"
1205};
1206
1207static SOC_ENUM_SINGLE_DECL(
1208 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1209 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1210
1211static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1212 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1213
1b7fd76a 1214/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1215static const char * const rt5677_adda1_src[] = {
1216 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1217};
1218
1219static SOC_ENUM_SINGLE_DECL(
1220 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1221 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1222
1223static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1224 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1225
1226
1b7fd76a 1227/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1228static const char * const rt5677_dac2l_src[] = {
1229 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1230 "OB 2",
1231};
1232
1233static SOC_ENUM_SINGLE_DECL(
1234 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1235 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1236
1237static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1238 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1239
1240static const char * const rt5677_dac2r_src[] = {
1241 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1242 "OB 3", "Haptic Generator", "VAD ADC"
1243};
1244
1245static SOC_ENUM_SINGLE_DECL(
1246 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1247 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1248
1249static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1250 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1251
1b7fd76a 1252/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1253static const char * const rt5677_dac3l_src[] = {
1254 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1255 "SLB DAC 4", "OB 4"
1256};
1257
1258static SOC_ENUM_SINGLE_DECL(
1259 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1260 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1261
1262static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1263 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1264
1265static const char * const rt5677_dac3r_src[] = {
1266 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1267 "SLB DAC 5", "OB 5"
1268};
1269
1270static SOC_ENUM_SINGLE_DECL(
1271 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1272 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1273
1274static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1275 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1276
1b7fd76a 1277/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1278static const char * const rt5677_dac4l_src[] = {
1279 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1280 "SLB DAC 6", "OB 6"
1281};
1282
1283static SOC_ENUM_SINGLE_DECL(
1284 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1285 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1286
1287static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1288 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1289
1290static const char * const rt5677_dac4r_src[] = {
1291 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1292 "SLB DAC 7", "OB 7"
1293};
1294
1295static SOC_ENUM_SINGLE_DECL(
1296 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1297 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1298
1299static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1300 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1301
1302/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1303static const char * const rt5677_iob_bypass_src[] = {
1304 "Bypass", "Pass SRC"
1305};
1306
1307static SOC_ENUM_SINGLE_DECL(
1308 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1309 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1310
1311static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1312 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1313
1314static SOC_ENUM_SINGLE_DECL(
1315 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1316 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1317
1318static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1319 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1320
1321static SOC_ENUM_SINGLE_DECL(
1322 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1323 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1324
1325static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1326 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1327
1328static SOC_ENUM_SINGLE_DECL(
1329 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1330 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1331
1332static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1333 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1334
1335static SOC_ENUM_SINGLE_DECL(
1336 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1337 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1338
1339static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1340 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86 1341
d65fd3a4 1342/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
0e826e86
OC		 1343static const char * const rt5677_stereo_adc2_src[] = {
1344 "DD MIX1", "DMIC", "Stereo DAC MIX"
1345};
1346
1347static SOC_ENUM_SINGLE_DECL(
1348 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1349 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1350
1351static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1352 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1353
1354static SOC_ENUM_SINGLE_DECL(
1355 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1356 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1357
1358static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1359 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1360
1361static SOC_ENUM_SINGLE_DECL(
1362 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1363 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1364
1365static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1366 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1367
1368/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1369static const char * const rt5677_dmic_src[] = {
1370 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1371};
1372
1373static SOC_ENUM_SINGLE_DECL(
1374 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1375 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1376
1377static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1378 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1379
1380static SOC_ENUM_SINGLE_DECL(
1381 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1382 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1383
1384static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1385 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1386
1387static SOC_ENUM_SINGLE_DECL(
1388 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1389 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1390
1391static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1392 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1393
1394static SOC_ENUM_SINGLE_DECL(
1395 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1396 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1397
1398static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1399 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1400
1401static SOC_ENUM_SINGLE_DECL(
1402 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1403 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1404
1405static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1406 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1407
1408static SOC_ENUM_SINGLE_DECL(
1409 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1410 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1411
1412static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1413 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1414
1b7fd76a 1415/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1416static const char * const rt5677_stereo2_adc_lr_src[] = {
1417 "L", "LR"
1418};
1419
1420static SOC_ENUM_SINGLE_DECL(
1421 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1422 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1423
1424static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1425 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86 1426
d65fd3a4 1427/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
0e826e86
OC		 1428static const char * const rt5677_stereo_adc1_src[] = {
1429 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1430};
1431
1432static SOC_ENUM_SINGLE_DECL(
1433 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1434 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1435
1436static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1437 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1438
1439static SOC_ENUM_SINGLE_DECL(
1440 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1441 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1442
1443static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1444 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1445
1446static SOC_ENUM_SINGLE_DECL(
1447 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1448 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1449
1450static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1451 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1452
1b7fd76a 1453/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1454static const char * const rt5677_mono_adc2_l_src[] = {
1455 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1456};
1457
1458static SOC_ENUM_SINGLE_DECL(
1459 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1460 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1461
1462static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1463 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1464
1b7fd76a 1465/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1466static const char * const rt5677_mono_adc1_l_src[] = {
1467 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1468};
1469
1470static SOC_ENUM_SINGLE_DECL(
1471 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1472 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1473
1474static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1475 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1476
1b7fd76a 1477/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1478static const char * const rt5677_mono_adc2_r_src[] = {
1479 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1480};
1481
1482static SOC_ENUM_SINGLE_DECL(
1483 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1484 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1485
1486static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1487 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1488
1b7fd76a 1489/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1490static const char * const rt5677_mono_adc1_r_src[] = {
1491 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1492};
1493
1494static SOC_ENUM_SINGLE_DECL(
1495 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1496 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1497
1498static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1499 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1500
1501/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1502static const char * const rt5677_stereo4_adc2_src[] = {
1503 "DD MIX1", "DMIC", "DD MIX2"
1504};
1505
1506static SOC_ENUM_SINGLE_DECL(
1507 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1508 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1509
1510static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1511 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1512
1513
1514/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1515static const char * const rt5677_stereo4_adc1_src[] = {
1516 "DD MIX1", "ADC1/2", "DD MIX2"
1517};
1518
1519static SOC_ENUM_SINGLE_DECL(
1520 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1521 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1522
1523static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1524 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1525
1526/* InBound0/1 Source */ /* MX-A3 [14:12] */
1527static const char * const rt5677_inbound01_src[] = {
1528 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1529 "VAD ADC/DAC1 FS"
1530};
1531
1532static SOC_ENUM_SINGLE_DECL(
1533 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1534 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1535
1536static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1537 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1538
1539/* InBound2/3 Source */ /* MX-A3 [10:8] */
1540static const char * const rt5677_inbound23_src[] = {
1541 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1542 "DAC1 FS", "IF4 DAC"
1543};
1544
1545static SOC_ENUM_SINGLE_DECL(
1546 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1547 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1548
1549static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1550 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1551
1552/* InBound4/5 Source */ /* MX-A3 [6:4] */
1553static const char * const rt5677_inbound45_src[] = {
1554 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1555 "IF3 DAC"
1556};
1557
1558static SOC_ENUM_SINGLE_DECL(
1559 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1560 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1561
1562static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1563 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1564
1565/* InBound6 Source */ /* MX-A3 [2:0] */
1566static const char * const rt5677_inbound6_src[] = {
1567 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1568 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1569};
1570
1571static SOC_ENUM_SINGLE_DECL(
1572 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1573 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1574
1575static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1576 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1577
1578/* InBound7 Source */ /* MX-A4 [14:12] */
1579static const char * const rt5677_inbound7_src[] = {
1580 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1581 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1582};
1583
1584static SOC_ENUM_SINGLE_DECL(
1585 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1586 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1587
1588static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1589 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1590
1591/* InBound8 Source */ /* MX-A4 [10:8] */
1592static const char * const rt5677_inbound8_src[] = {
1593 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1594 "MONO ADC MIX L", "DACL1 FS"
1595};
1596
1597static SOC_ENUM_SINGLE_DECL(
1598 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1599 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1600
1601static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1602 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1603
1604/* InBound9 Source */ /* MX-A4 [6:4] */
1605static const char * const rt5677_inbound9_src[] = {
1606 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1607 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1608};
1609
1610static SOC_ENUM_SINGLE_DECL(
1611 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1612 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1613
1614static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1615 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1616
1617/* VAD Source */ /* MX-9F [6:4] */
1618static const char * const rt5677_vad_src[] = {
1619 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1620 "STO3 ADC MIX L"
1621};
1622
1623static SOC_ENUM_SINGLE_DECL(
1624 rt5677_vad_enum, RT5677_VAD_CTRL4,
1625 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1626
1627static const struct snd_kcontrol_new rt5677_vad_src_mux =
1628 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1629
1630/* Sidetone Source */ /* MX-13 [11:9] */
1631static const char * const rt5677_sidetone_src[] = {
1632 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1633};
1634
1635static SOC_ENUM_SINGLE_DECL(
1636 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1637 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1638
1639static const struct snd_kcontrol_new rt5677_sidetone_mux =
1640 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1641
1642/* DAC1/2 Source */ /* MX-15 [1:0] */
1643static const char * const rt5677_dac12_src[] = {
1644 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1645};
1646
1647static SOC_ENUM_SINGLE_DECL(
1648 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1649 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1650
1651static const struct snd_kcontrol_new rt5677_dac12_mux =
1652 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1653
1654/* DAC3 Source */ /* MX-15 [5:4] */
1655static const char * const rt5677_dac3_src[] = {
1656 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1657};
1658
1659static SOC_ENUM_SINGLE_DECL(
1660 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1661 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1662
1663static const struct snd_kcontrol_new rt5677_dac3_mux =
1664 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1665
1b7fd76a 1666/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 1667static const char * const rt5677_pdm_src[] = {
1668 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1669};
1670
1671static SOC_ENUM_SINGLE_DECL(
1672 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1673 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1674
1675static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 1676 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 1677
1678static SOC_ENUM_SINGLE_DECL(
1679 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1680 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1681
1682static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 1683 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 1684
1685static SOC_ENUM_SINGLE_DECL(
1686 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1687 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1688
1689static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 1690 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 1691
1692static SOC_ENUM_SINGLE_DECL(
1693 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1694 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1695
1696static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 1697 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86 1698
d65fd3a4 1699/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
0e826e86
OC		 1700static const char * const rt5677_if12_adc1_src[] = {
1701 "STO1 ADC MIX", "OB01", "VAD ADC"
1702};
1703
1704static SOC_ENUM_SINGLE_DECL(
1705 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1706 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1707
1708static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 1709 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 1710
1711static SOC_ENUM_SINGLE_DECL(
1712 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1713 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1714
1715static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 1716 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 1717
1718static SOC_ENUM_SINGLE_DECL(
1719 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1720 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1721
1722static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 1723 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 1724
1725/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1726static const char * const rt5677_if12_adc2_src[] = {
1727 "STO2 ADC MIX", "OB23"
1728};
1729
1730static SOC_ENUM_SINGLE_DECL(
1731 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1732 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1733
1734static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 1735 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 1736
1737static SOC_ENUM_SINGLE_DECL(
1738 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1739 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1740
1741static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 1742 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 1743
1744static SOC_ENUM_SINGLE_DECL(
1745 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1746 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1747
1748static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 1749 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 1750
1751/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1752static const char * const rt5677_if12_adc3_src[] = {
1753 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1754};
1755
1756static SOC_ENUM_SINGLE_DECL(
1757 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1758 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1759
1760static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 1761 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 1762
1763static SOC_ENUM_SINGLE_DECL(
1764 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1765 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1766
1767static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 1768 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 1769
1770static SOC_ENUM_SINGLE_DECL(
1771 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1772 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1773
1774static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 1775 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86 1776
d65fd3a4 1777/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
0e826e86
OC		 1778static const char * const rt5677_if12_adc4_src[] = {
1779 "STO4 ADC MIX", "OB67", "OB01"
1780};
1781
1782static SOC_ENUM_SINGLE_DECL(
1783 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1784 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1785
1786static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 1787 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 1788
1789static SOC_ENUM_SINGLE_DECL(
1790 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1791 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1792
1793static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 1794 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 1795
1796static SOC_ENUM_SINGLE_DECL(
1797 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1798 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1799
1800static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 1801 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86 1802
d65fd3a4 1803/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
0e826e86
OC		 1804static const char * const rt5677_if34_adc_src[] = {
1805 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1806 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1807};
1808
1809static SOC_ENUM_SINGLE_DECL(
1810 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1811 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1812
1813static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 1814 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 1815
1816static SOC_ENUM_SINGLE_DECL(
1817 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1818 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1819
1820static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 1821 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86 1822
e6f6ebc1
OC		 1823/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1824static const char * const rt5677_if12_adc_swap_src[] = {
1825 "L/R", "R/L", "L/L", "R/R"
1826};
1827
1828static SOC_ENUM_SINGLE_DECL(
1829 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1830 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1831
1832static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1833 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1834
1835static SOC_ENUM_SINGLE_DECL(
1836 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1837 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1838
1839static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1840 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1841
1842static SOC_ENUM_SINGLE_DECL(
1843 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1844 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1845
1846static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1847 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1848
1849static SOC_ENUM_SINGLE_DECL(
1850 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1851 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1852
1853static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1854 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1855
1856static SOC_ENUM_SINGLE_DECL(
1857 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1858 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1859
1860static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1861 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1862
1863static SOC_ENUM_SINGLE_DECL(
1864 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1865 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1866
1867static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1868 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1869
1870static SOC_ENUM_SINGLE_DECL(
1871 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1872 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1873
1874static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1875 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1876
1877static SOC_ENUM_SINGLE_DECL(
1878 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1879 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1880
1881static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1882 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1883
d65fd3a4 1884/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
e6f6ebc1
OC		 1885static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1886 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1887 "3/1/2/4", "3/4/1/2"
1888};
1889
1890static SOC_ENUM_SINGLE_DECL(
1891 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1892 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1893
1894static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1895 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1896
1897/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1898static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1899 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1900 "2/3/1/4", "3/4/1/2"
1901};
1902
1903static SOC_ENUM_SINGLE_DECL(
1904 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
1905 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
1906
1907static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
1908 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
1909
91159eca
OC		 1910/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
1911 MX-3F[14:12][10:8][6:4][2:0]
1912 MX-43[14:12][10:8][6:4][2:0]
1913 MX-44[14:12][10:8][6:4][2:0] */
1914static const char * const rt5677_if12_dac_tdm_sel_src[] = {
1915 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
1916};
1917
1918static SOC_ENUM_SINGLE_DECL(
1919 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
1920 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
1921
1922static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
1923 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
1924
1925static SOC_ENUM_SINGLE_DECL(
1926 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
1927 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
1928
1929static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
1930 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
1931
1932static SOC_ENUM_SINGLE_DECL(
1933 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
1934 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
1935
1936static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
1937 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
1938
1939static SOC_ENUM_SINGLE_DECL(
1940 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
1941 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
1942
1943static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
1944 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
1945
1946static SOC_ENUM_SINGLE_DECL(
1947 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
1948 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
1949
1950static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
1951 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
1952
1953static SOC_ENUM_SINGLE_DECL(
1954 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
1955 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
1956
1957static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
1958 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
1959
1960static SOC_ENUM_SINGLE_DECL(
1961 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
1962 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
1963
1964static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
1965 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
1966
1967static SOC_ENUM_SINGLE_DECL(
1968 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
1969 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
1970
1971static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
1972 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
1973
1974static SOC_ENUM_SINGLE_DECL(
1975 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
1976 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
1977
1978static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
1979 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
1980
1981static SOC_ENUM_SINGLE_DECL(
1982 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
1983 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
1984
1985static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
1986 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
1987
1988static SOC_ENUM_SINGLE_DECL(
1989 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
1990 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
1991
1992static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
1993 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
1994
1995static SOC_ENUM_SINGLE_DECL(
1996 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
1997 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
1998
1999static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2000 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2001
2002static SOC_ENUM_SINGLE_DECL(
2003 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2004 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2005
2006static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2007 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2008
2009static SOC_ENUM_SINGLE_DECL(
2010 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2011 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2012
2013static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2014 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2015
2016static SOC_ENUM_SINGLE_DECL(
2017 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2018 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2019
2020static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2021 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2022
2023static SOC_ENUM_SINGLE_DECL(
2024 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2025 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2026
2027static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2028 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2029
0e826e86
OC		 2030static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2031 struct snd_kcontrol *kcontrol, int event)
2032{
2033 struct snd_soc_codec *codec = w->codec;
2034 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2035
2036 switch (event) {
2037 case SND_SOC_DAPM_POST_PMU:
2038 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2039 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2040 break;
2041
2042 case SND_SOC_DAPM_PRE_PMD:
2043 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2044 RT5677_PWR_BST1_P, 0);
2045 break;
2046
2047 default:
2048 return 0;
2049 }
2050
2051 return 0;
2052}
2053
2054static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2055 struct snd_kcontrol *kcontrol, int event)
2056{
2057 struct snd_soc_codec *codec = w->codec;
2058 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2059
2060 switch (event) {
2061 case SND_SOC_DAPM_POST_PMU:
2062 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2063 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2064 break;
2065
2066 case SND_SOC_DAPM_PRE_PMD:
2067 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2068 RT5677_PWR_BST2_P, 0);
2069 break;
2070
2071 default:
2072 return 0;
2073 }
2074
2075 return 0;
2076}
2077
2078static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2079 struct snd_kcontrol *kcontrol, int event)
2080{
2081 struct snd_soc_codec *codec = w->codec;
2082 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2083
2084 switch (event) {
2085 case SND_SOC_DAPM_POST_PMU:
2086 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2087 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2088 break;
2089 default:
2090 return 0;
2091 }
2092
2093 return 0;
2094}
2095
2096static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2097 struct snd_kcontrol *kcontrol, int event)
2098{
2099 struct snd_soc_codec *codec = w->codec;
2100 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2101
2102 switch (event) {
2103 case SND_SOC_DAPM_POST_PMU:
2104 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2105 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2106 break;
2107 default:
2108 return 0;
2109 }
2110
2111 return 0;
2112}
2113
2114static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2115 struct snd_kcontrol *kcontrol, int event)
2116{
2117 struct snd_soc_codec *codec = w->codec;
2118 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2119
2120 switch (event) {
2121 case SND_SOC_DAPM_POST_PMU:
2122 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2123 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2124 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2125 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2126 break;
f58c3b91
OC		 2127
2128 case SND_SOC_DAPM_PRE_PMD:
2129 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2130 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2131 RT5677_PWR_CLK_MB, 0);
2132 break;
2133
0e826e86
OC		 2134 default:
2135 return 0;
2136 }
2137
2138 return 0;
2139}
2140
e6f6ebc1
OC		 2141static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2142 struct snd_kcontrol *kcontrol, int event)
2143{
2144 struct snd_soc_codec *codec = w->codec;
2145 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2146 unsigned int value;
2147
2148 switch (event) {
2149 case SND_SOC_DAPM_PRE_PMU:
2150 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2151 if (value & RT5677_IF1_ADC_CTRL_MASK)
2152 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2153 RT5677_IF1_ADC_MODE_MASK,
2154 RT5677_IF1_ADC_MODE_TDM);
2155 break;
2156
2157 default:
2158 return 0;
2159 }
2160
2161 return 0;
2162}
2163
2164static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2165 struct snd_kcontrol *kcontrol, int event)
2166{
2167 struct snd_soc_codec *codec = w->codec;
2168 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2169 unsigned int value;
2170
2171 switch (event) {
2172 case SND_SOC_DAPM_PRE_PMU:
2173 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2174 if (value & RT5677_IF2_ADC_CTRL_MASK)
2175 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2176 RT5677_IF2_ADC_MODE_MASK,
2177 RT5677_IF2_ADC_MODE_TDM);
2178 break;
2179
2180 default:
2181 return 0;
2182 }
2183
2184 return 0;
2185}
2186
683996cb
OC		 2187static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2188 struct snd_kcontrol *kcontrol, int event)
2189{
2190 struct snd_soc_codec *codec = w->codec;
2191 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2192
2193 switch (event) {
2194 case SND_SOC_DAPM_POST_PMU:
2195 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2196 !rt5677->is_vref_slow) {
2197 mdelay(20);
2198 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2199 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2200 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2201 rt5677->is_vref_slow = true;
2202 }
2203 break;
2204
2205 default:
2206 return 0;
2207 }
2208
2209 return 0;
2210}
2211
0e826e86
OC		 2212static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2213 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2214 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
2215 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2216 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
2217
2218 /* Input Side */
2219 /* micbias */
3d0c03d9 2220 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 2221 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2222 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 2223
2224 /* Input Lines */
2225 SND_SOC_DAPM_INPUT("DMIC L1"),
2226 SND_SOC_DAPM_INPUT("DMIC R1"),
2227 SND_SOC_DAPM_INPUT("DMIC L2"),
2228 SND_SOC_DAPM_INPUT("DMIC R2"),
2229 SND_SOC_DAPM_INPUT("DMIC L3"),
2230 SND_SOC_DAPM_INPUT("DMIC R3"),
2231 SND_SOC_DAPM_INPUT("DMIC L4"),
2232 SND_SOC_DAPM_INPUT("DMIC R4"),
2233
2234 SND_SOC_DAPM_INPUT("IN1P"),
2235 SND_SOC_DAPM_INPUT("IN1N"),
2236 SND_SOC_DAPM_INPUT("IN2P"),
2237 SND_SOC_DAPM_INPUT("IN2N"),
2238
2239 SND_SOC_DAPM_INPUT("Haptic Generator"),
2240
2d15d974
BL		 2241 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2242 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2243 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2244 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2245
2246 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2247 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2248 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2249 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2250 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2251 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2252 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2253 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 2254
2255 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2256 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2257
2258 /* Boost */
2259 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2260 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2261 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2262 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2263 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2264 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2265
2266 /* ADCs */
2267 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2268 0, 0),
2269 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2270 0, 0),
2271 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2272
2273 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2274 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2275 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2276 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2277 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2278 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2279 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2280 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2281
2282 /* ADC Mux */
2283 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2284 &rt5677_sto1_dmic_mux),
2285 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2286 &rt5677_sto1_adc1_mux),
2287 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2288 &rt5677_sto1_adc2_mux),
2289 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2290 &rt5677_sto2_dmic_mux),
2291 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2292 &rt5677_sto2_adc1_mux),
2293 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2294 &rt5677_sto2_adc2_mux),
2295 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2296 &rt5677_sto2_adc_lr_mux),
2297 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2298 &rt5677_sto3_dmic_mux),
2299 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2300 &rt5677_sto3_adc1_mux),
2301 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2302 &rt5677_sto3_adc2_mux),
2303 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2304 &rt5677_sto4_dmic_mux),
2305 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2306 &rt5677_sto4_adc1_mux),
2307 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2308 &rt5677_sto4_adc2_mux),
2309 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2310 &rt5677_mono_dmic_l_mux),
2311 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2312 &rt5677_mono_dmic_r_mux),
2313 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2314 &rt5677_mono_adc2_l_mux),
2315 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2316 &rt5677_mono_adc1_l_mux),
2317 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2318 &rt5677_mono_adc1_r_mux),
2319 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2320 &rt5677_mono_adc2_r_mux),
2321
2322 /* ADC Mixer */
2323 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2324 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2325 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2326 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2327 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2328 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2329 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2330 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2331 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2332 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2333 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2334 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2335 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2336 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2337 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2338 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2339 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2340 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2341 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2342 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2343 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2344 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2345 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2346 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2347 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2348 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2349 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2350 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2351 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2352 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2353 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2354 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2355
2356 /* ADC PGA */
2357 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2358 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2359 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2360 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2361 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2362 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2363 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2364 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2365 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2366 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2367 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2368 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2369 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2370 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
e6f6ebc1
OC		 2371 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2372 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
0e826e86
OC		 2373
2374 /* DSP */
2375 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2376 &rt5677_ib9_src_mux),
2377 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2378 &rt5677_ib8_src_mux),
2379 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2380 &rt5677_ib7_src_mux),
2381 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2382 &rt5677_ib6_src_mux),
2383 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2384 &rt5677_ib45_src_mux),
2385 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2386 &rt5677_ib23_src_mux),
2387 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2388 &rt5677_ib01_src_mux),
2389 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2390 &rt5677_ib45_bypass_src_mux),
2391 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2392 &rt5677_ib23_bypass_src_mux),
2393 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2394 &rt5677_ib01_bypass_src_mux),
2395 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2396 &rt5677_ob23_bypass_src_mux),
2397 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2398 &rt5677_ob01_bypass_src_mux),
2399
2400 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2401 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2402
2403 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2404 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2405 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2406 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2407 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2408 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2409
2410 /* Digital Interface */
2411 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2412 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2413 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2414 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2415 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2416 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2417 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2418 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2419 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2420 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2421 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2422 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2423 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2424 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2425 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2426 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2427 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2428 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2429
2430 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2431 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2432 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2433 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2434 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2435 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2436 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2437 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2438 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2439 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2440 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2441 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2442 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2443 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2444 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2445 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2446 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2447 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2448
2449 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2450 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2451 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2452 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2453 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2454 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2455 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2456 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2457
2458 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2459 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2460 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2461 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2462 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2463 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2464 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2465 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2466
2467 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2468 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2469 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2470 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2471 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2472 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2473 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2474 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2475 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2476 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2477 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2478 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2479 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2480 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2481 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2482 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2483 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2484 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2485
2486 /* Digital Interface Select */
2487 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2488 &rt5677_if1_adc1_mux),
2489 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2490 &rt5677_if1_adc2_mux),
2491 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2492 &rt5677_if1_adc3_mux),
2493 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2494 &rt5677_if1_adc4_mux),
e6f6ebc1
OC		 2495 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2496 &rt5677_if1_adc1_swap_mux),
2497 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2498 &rt5677_if1_adc2_swap_mux),
2499 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2500 &rt5677_if1_adc3_swap_mux),
2501 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2502 &rt5677_if1_adc4_swap_mux),
2503 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2504 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2505 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2506 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2507 &rt5677_if2_adc1_mux),
2508 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2509 &rt5677_if2_adc2_mux),
2510 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2511 &rt5677_if2_adc3_mux),
2512 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2513 &rt5677_if2_adc4_mux),
e6f6ebc1
OC		 2514 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2515 &rt5677_if2_adc1_swap_mux),
2516 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2517 &rt5677_if2_adc2_swap_mux),
2518 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2519 &rt5677_if2_adc3_swap_mux),
2520 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2521 &rt5677_if2_adc4_swap_mux),
2522 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2523 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2524 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2525 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2526 &rt5677_if3_adc_mux),
2527 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2528 &rt5677_if4_adc_mux),
2529 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2530 &rt5677_slb_adc1_mux),
2531 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2532 &rt5677_slb_adc2_mux),
2533 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2534 &rt5677_slb_adc3_mux),
2535 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2536 &rt5677_slb_adc4_mux),
2537
91159eca
OC		 2538 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2539 &rt5677_if1_dac0_tdm_sel_mux),
2540 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2541 &rt5677_if1_dac1_tdm_sel_mux),
2542 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2543 &rt5677_if1_dac2_tdm_sel_mux),
2544 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2545 &rt5677_if1_dac3_tdm_sel_mux),
2546 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2547 &rt5677_if1_dac4_tdm_sel_mux),
2548 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2549 &rt5677_if1_dac5_tdm_sel_mux),
2550 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2551 &rt5677_if1_dac6_tdm_sel_mux),
2552 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2553 &rt5677_if1_dac7_tdm_sel_mux),
2554
2555 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2556 &rt5677_if2_dac0_tdm_sel_mux),
2557 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2558 &rt5677_if2_dac1_tdm_sel_mux),
2559 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2560 &rt5677_if2_dac2_tdm_sel_mux),
2561 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2562 &rt5677_if2_dac3_tdm_sel_mux),
2563 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2564 &rt5677_if2_dac4_tdm_sel_mux),
2565 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2566 &rt5677_if2_dac5_tdm_sel_mux),
2567 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2568 &rt5677_if2_dac6_tdm_sel_mux),
2569 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2570 &rt5677_if2_dac7_tdm_sel_mux),
2571
0e826e86
OC		 2572 /* Audio Interface */
2573 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2574 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2575 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2576 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2577 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2578 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2579 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2580 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2581 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2582 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2583
2584 /* Sidetone Mux */
2585 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2586 &rt5677_sidetone_mux),
90bdbb46
OC		 2587 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2588 RT5677_ST_EN_SFT, 0, NULL, 0),
2589
0e826e86
OC		 2590 /* VAD Mux*/
2591 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2592 &rt5677_vad_src_mux),
2593
2594 /* Tensilica DSP */
2595 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2596 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2597 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2598 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2599 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2600 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2601 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2602 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2603 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2604 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2605 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2606 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2607 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2608
2609 /* Output Side */
d65fd3a4 2610 /* DAC mixer before sound effect */
0e826e86
OC		 2611 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2612 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2613 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2614 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2615 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2616
2617 /* DAC Mux */
2618 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2619 &rt5677_dac1_mux),
2620 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2621 &rt5677_adda1_mux),
2622 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2623 &rt5677_dac12_mux),
2624 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2625 &rt5677_dac3_mux),
2626
2627 /* DAC2 channel Mux */
2628 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2629 &rt5677_dac2_l_mux),
2630 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2631 &rt5677_dac2_r_mux),
2632
2633 /* DAC3 channel Mux */
2634 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2635 &rt5677_dac3_l_mux),
2636 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2637 &rt5677_dac3_r_mux),
2638
2639 /* DAC4 channel Mux */
2640 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2641 &rt5677_dac4_l_mux),
2642 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2643 &rt5677_dac4_r_mux),
2644
2645 /* DAC Mixer */
2646 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2647 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
6800b5ba 2648 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
0e826e86 2649 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
6800b5ba 2650 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
0e826e86 2651 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
6800b5ba
OC		 2652 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2653 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2654 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2655 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2656 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2657 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2658 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2659 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
0e826e86
OC		 2660
2661 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2662 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2663 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2664 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2665 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2666 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2667 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2668 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2669 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2670 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2671 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2672 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2673 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2674 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2675 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2676 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2677 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2678 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2679 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2680 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2681
2682 /* DACs */
2683 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2684 RT5677_PWR_DAC1_BIT, 0),
2685 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2686 RT5677_PWR_DAC2_BIT, 0),
2687 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2688 RT5677_PWR_DAC3_BIT, 0),
2689
2690 /* PDM */
2691 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2692 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2694 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2695
2696 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2697 1, &rt5677_pdm1_l_mux),
2698 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2699 1, &rt5677_pdm1_r_mux),
2700 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2701 1, &rt5677_pdm2_l_mux),
2702 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2703 1, &rt5677_pdm2_r_mux),
2704
683996cb 2705 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0e826e86 2706 0, NULL, 0),
683996cb 2707 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0e826e86 2708 0, NULL, 0),
683996cb 2709 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0e826e86
OC		 2710 0, NULL, 0),
2711
683996cb
OC		 2712 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2713 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2714 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2715 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2716 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2717 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2718
0e826e86
OC		 2719 /* Output Lines */
2720 SND_SOC_DAPM_OUTPUT("LOUT1"),
2721 SND_SOC_DAPM_OUTPUT("LOUT2"),
2722 SND_SOC_DAPM_OUTPUT("LOUT3"),
2723 SND_SOC_DAPM_OUTPUT("PDM1L"),
2724 SND_SOC_DAPM_OUTPUT("PDM1R"),
2725 SND_SOC_DAPM_OUTPUT("PDM2L"),
2726 SND_SOC_DAPM_OUTPUT("PDM2R"),
683996cb
OC		 2727
2728 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
0e826e86
OC		 2729};
2730
2731static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2732 { "DMIC1", NULL, "DMIC L1" },
2733 { "DMIC1", NULL, "DMIC R1" },
2734 { "DMIC2", NULL, "DMIC L2" },
2735 { "DMIC2", NULL, "DMIC R2" },
2736 { "DMIC3", NULL, "DMIC L3" },
2737 { "DMIC3", NULL, "DMIC R3" },
2738 { "DMIC4", NULL, "DMIC L4" },
2739 { "DMIC4", NULL, "DMIC R4" },
2740
2741 { "DMIC L1", NULL, "DMIC CLK" },
2742 { "DMIC R1", NULL, "DMIC CLK" },
2743 { "DMIC L2", NULL, "DMIC CLK" },
2744 { "DMIC R2", NULL, "DMIC CLK" },
2745 { "DMIC L3", NULL, "DMIC CLK" },
2746 { "DMIC R3", NULL, "DMIC CLK" },
2747 { "DMIC L4", NULL, "DMIC CLK" },
2748 { "DMIC R4", NULL, "DMIC CLK" },
2749
2d15d974
BL		 2750 { "DMIC L1", NULL, "DMIC1 power" },
2751 { "DMIC R1", NULL, "DMIC1 power" },
2752 { "DMIC L3", NULL, "DMIC3 power" },
2753 { "DMIC R3", NULL, "DMIC3 power" },
2754 { "DMIC L4", NULL, "DMIC4 power" },
2755 { "DMIC R4", NULL, "DMIC4 power" },
2756
0e826e86
OC		 2757 { "BST1", NULL, "IN1P" },
2758 { "BST1", NULL, "IN1N" },
2759 { "BST2", NULL, "IN2P" },
2760 { "BST2", NULL, "IN2N" },
2761
22e51345
BL		 2762 { "IN1P", NULL, "MICBIAS1" },
2763 { "IN1N", NULL, "MICBIAS1" },
2764 { "IN2P", NULL, "MICBIAS1" },
2765 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 2766
2767 { "ADC 1", NULL, "BST1" },
2768 { "ADC 1", NULL, "ADC 1 power" },
2769 { "ADC 1", NULL, "ADC1 clock" },
2770 { "ADC 2", NULL, "BST2" },
2771 { "ADC 2", NULL, "ADC 2 power" },
2772 { "ADC 2", NULL, "ADC2 clock" },
2773
2774 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2775 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2776 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2777 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2778
2779 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2780 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2781 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2782 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2783
2784 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2785 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2786 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2787 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2788
2789 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2790 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2791 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2792 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2793
2794 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2795 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2796 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2797 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2798
2799 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2800 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2801 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2802 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2803
2804 { "ADC 1_2", NULL, "ADC 1" },
2805 { "ADC 1_2", NULL, "ADC 2" },
2806
2807 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2808 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2809 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2810
2811 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2812 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2813 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2814
2815 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2816 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2817 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2818
2819 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2820 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2821 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2822
2823 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2824 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2825 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2826
2827 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2828 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2829 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2830
2831 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2832 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2833 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2834
2835 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2836 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2837 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2838
2839 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2840 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2841 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2842
2843 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2844 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2845 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2846
2847 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2848 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2849 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2850
2851 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2852 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2853 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2854
2855 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2856 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2857 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2858 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2859
2860 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2861 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2862 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2863
2864 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2865 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2866 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2867
2868 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2869 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2870
2871 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2872 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2873 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2874 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2875
2876 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2877 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2878
2879 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2880 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2881
2882 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2883 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2884 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2885
2886 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2887 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2888 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2889
2890 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2891 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2892
2893 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2894 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2895 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2896 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2897
2898 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2899 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2900 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2901
2902 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2903 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2904 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2905
2906 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2907 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2908
2909 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2910 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2911 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2912 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2913
2914 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2915 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2916 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2917
2918 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2919 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2920 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2921
2922 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2923 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2924
2925 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2926 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2927 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2928 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2929
2930 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2931 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2932 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2933 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2934
2935 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2936 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2937
2938 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2939 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2940 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2941 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2942 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2943
2944 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2945 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2946 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2947
2948 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2949 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2950
2951 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2952 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2953 { "IF1 ADC3 Mux", "OB45", "OB45" },
2954
2955 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2956 { "IF1 ADC4 Mux", "OB67", "OB67" },
2957 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2958
e6f6ebc1
OC		 2959 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
2960 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
2961 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
2962 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
2963
2964 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
2965 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
2966 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
2967 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
2968
2969 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
2970 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
2971 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
2972 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
2973
2974 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
2975 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
2976 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
2977 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
2978
2979 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
2980 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
2981 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
2982 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
2983
2984 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
2985 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
2986 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
2987 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
2988 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
2989 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
2990 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
2991 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
2992
0e826e86 2993 { "AIF1TX", NULL, "I2S1" },
e6f6ebc1 2994 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
0e826e86
OC		 2995
2996 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2997 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2998 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2999
3000 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3001 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3002
3003 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3004 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3005 { "IF2 ADC3 Mux", "OB45", "OB45" },
3006
3007 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3008 { "IF2 ADC4 Mux", "OB67", "OB67" },
3009 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3010
e6f6ebc1
OC		 3011 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3012 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3013 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3014 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3015
3016 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3017 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3018 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3019 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3020
3021 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3022 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3023 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3024 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3025
3026 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3027 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3028 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3029 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3030
3031 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3032 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3033 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3034 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3035
3036 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3037 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3038 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3039 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3040 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3041 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3042 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3043 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3044
0e826e86 3045 { "AIF2TX", NULL, "I2S2" },
e6f6ebc1 3046 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
0e826e86
OC		 3047
3048 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3049 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3050 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3051 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3052 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3053 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3054 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3055 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3056
3057 { "AIF3TX", NULL, "I2S3" },
3058 { "AIF3TX", NULL, "IF3 ADC Mux" },
3059
3060 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3061 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3062 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3063 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3064 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3065 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3066 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3067 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3068
3069 { "AIF4TX", NULL, "I2S4" },
3070 { "AIF4TX", NULL, "IF4 ADC Mux" },
3071
3072 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3073 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3074 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3075
3076 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3077 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3078
3079 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3080 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3081 { "SLB ADC3 Mux", "OB45", "OB45" },
3082
3083 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3084 { "SLB ADC4 Mux", "OB67", "OB67" },
3085 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3086
3087 { "SLBTX", NULL, "SLB" },
3088 { "SLBTX", NULL, "SLB ADC1 Mux" },
3089 { "SLBTX", NULL, "SLB ADC2 Mux" },
3090 { "SLBTX", NULL, "SLB ADC3 Mux" },
3091 { "SLBTX", NULL, "SLB ADC4 Mux" },
3092
3093 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3094 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3095 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3096 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3097 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3098
3099 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3100 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3101
3102 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3103 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3104 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3105 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3106 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3107 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3108
3109 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3110 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3111
3112 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3113 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3114 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3115 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3116 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3117
3118 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3119 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3120
3121 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
3122 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
3123 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3124 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3125 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3126 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3127 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3128 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3129
3130 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
3131 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
3132 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3133 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3134 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3135 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3136 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3137 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3138
3139 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3140 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3141 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3142 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3143 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3144 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3145
3146 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3147 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3148 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3149 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3150 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3151 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3152 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3153
3154 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3155 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3156 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3157 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3158 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3159 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3160 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3161
3162 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3163 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3164 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3165 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3166 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3167 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3168 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3169
3170 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3171 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3172 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3173 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3174 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3175 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3176 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3177
3178 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3179 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3180 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3181 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3182 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3183 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3184 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3185
3186 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3187 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3188 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3189 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3190 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3191 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3192 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3193
3194 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3195 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3196 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3197 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3198 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3199 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3200 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3201
3202 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3203 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3204 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3205 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3206
3207 { "OutBound2", NULL, "OB23 Bypass Mux" },
3208 { "OutBound3", NULL, "OB23 Bypass Mux" },
3209 { "OutBound4", NULL, "OB4 MIX" },
3210 { "OutBound5", NULL, "OB5 MIX" },
3211 { "OutBound6", NULL, "OB6 MIX" },
3212 { "OutBound7", NULL, "OB7 MIX" },
3213
3214 { "OB45", NULL, "OutBound4" },
3215 { "OB45", NULL, "OutBound5" },
3216 { "OB67", NULL, "OutBound6" },
3217 { "OB67", NULL, "OutBound7" },
3218
3219 { "IF1 DAC0", NULL, "AIF1RX" },
3220 { "IF1 DAC1", NULL, "AIF1RX" },
3221 { "IF1 DAC2", NULL, "AIF1RX" },
3222 { "IF1 DAC3", NULL, "AIF1RX" },
3223 { "IF1 DAC4", NULL, "AIF1RX" },
3224 { "IF1 DAC5", NULL, "AIF1RX" },
3225 { "IF1 DAC6", NULL, "AIF1RX" },
3226 { "IF1 DAC7", NULL, "AIF1RX" },
3227 { "IF1 DAC0", NULL, "I2S1" },
3228 { "IF1 DAC1", NULL, "I2S1" },
3229 { "IF1 DAC2", NULL, "I2S1" },
3230 { "IF1 DAC3", NULL, "I2S1" },
3231 { "IF1 DAC4", NULL, "I2S1" },
3232 { "IF1 DAC5", NULL, "I2S1" },
3233 { "IF1 DAC6", NULL, "I2S1" },
3234 { "IF1 DAC7", NULL, "I2S1" },
3235
91159eca
OC		 3236 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3237 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3238 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3239 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3240 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3241 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3242 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3243 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3244
3245 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3246 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3247 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3248 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3249 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3250 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3251 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3252 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3253
3254 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3255 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3256 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3257 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3258 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3259 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3260 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3261 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3262
3263 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3264 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3265 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3266 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3267 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3268 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3269 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3270 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3271
3272 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3273 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3274 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3275 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3276 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3277 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3278 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3279 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3280
3281 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3282 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3283 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3284 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3285 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3286 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3287 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3288 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3289
3290 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3291 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3292 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3293 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3294 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3295 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3296 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3297 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3298
3299 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3300 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3301 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3302 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3303 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3304 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3305 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3306 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3307
3308 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3309 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3310 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3311 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3312 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3313 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3314 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3315 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
0e826e86
OC		 3316
3317 { "IF2 DAC0", NULL, "AIF2RX" },
3318 { "IF2 DAC1", NULL, "AIF2RX" },
3319 { "IF2 DAC2", NULL, "AIF2RX" },
3320 { "IF2 DAC3", NULL, "AIF2RX" },
3321 { "IF2 DAC4", NULL, "AIF2RX" },
3322 { "IF2 DAC5", NULL, "AIF2RX" },
3323 { "IF2 DAC6", NULL, "AIF2RX" },
3324 { "IF2 DAC7", NULL, "AIF2RX" },
3325 { "IF2 DAC0", NULL, "I2S2" },
3326 { "IF2 DAC1", NULL, "I2S2" },
3327 { "IF2 DAC2", NULL, "I2S2" },
3328 { "IF2 DAC3", NULL, "I2S2" },
3329 { "IF2 DAC4", NULL, "I2S2" },
3330 { "IF2 DAC5", NULL, "I2S2" },
3331 { "IF2 DAC6", NULL, "I2S2" },
3332 { "IF2 DAC7", NULL, "I2S2" },
3333
91159eca
OC		 3334 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3335 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3336 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3337 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3338 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3339 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3340 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3341 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3342
3343 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3344 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3345 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3346 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3347 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3348 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3349 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3350 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3351
3352 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3353 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3354 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3355 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3356 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3357 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3358 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3359 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3360
3361 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3362 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3363 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3364 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3365 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3366 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3367 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3368 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3369
3370 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3371 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3372 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3373 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3374 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3375 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3376 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3377 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3378
3379 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3380 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3381 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3382 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3383 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3384 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3385 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3386 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3387
3388 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3389 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3390 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3391 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3392 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3393 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3394 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3395 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3396
3397 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3398 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3399 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3400 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3401 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3402 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3403 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3404 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3405
3406 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3407 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3408 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3409 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3410 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3411 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3412 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3413 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
0e826e86
OC		 3414
3415 { "IF3 DAC", NULL, "AIF3RX" },
3416 { "IF3 DAC", NULL, "I2S3" },
3417
3418 { "IF4 DAC", NULL, "AIF4RX" },
3419 { "IF4 DAC", NULL, "I2S4" },
3420
3421 { "IF3 DAC L", NULL, "IF3 DAC" },
3422 { "IF3 DAC R", NULL, "IF3 DAC" },
3423
3424 { "IF4 DAC L", NULL, "IF4 DAC" },
3425 { "IF4 DAC R", NULL, "IF4 DAC" },
3426
3427 { "SLB DAC0", NULL, "SLBRX" },
3428 { "SLB DAC1", NULL, "SLBRX" },
3429 { "SLB DAC2", NULL, "SLBRX" },
3430 { "SLB DAC3", NULL, "SLBRX" },
3431 { "SLB DAC4", NULL, "SLBRX" },
3432 { "SLB DAC5", NULL, "SLBRX" },
3433 { "SLB DAC6", NULL, "SLBRX" },
3434 { "SLB DAC7", NULL, "SLBRX" },
3435 { "SLB DAC0", NULL, "SLB" },
3436 { "SLB DAC1", NULL, "SLB" },
3437 { "SLB DAC2", NULL, "SLB" },
3438 { "SLB DAC3", NULL, "SLB" },
3439 { "SLB DAC4", NULL, "SLB" },
3440 { "SLB DAC5", NULL, "SLB" },
3441 { "SLB DAC6", NULL, "SLB" },
3442 { "SLB DAC7", NULL, "SLB" },
3443
3444 { "SLB DAC01", NULL, "SLB DAC0" },
3445 { "SLB DAC01", NULL, "SLB DAC1" },
3446 { "SLB DAC23", NULL, "SLB DAC2" },
3447 { "SLB DAC23", NULL, "SLB DAC3" },
3448 { "SLB DAC45", NULL, "SLB DAC4" },
3449 { "SLB DAC45", NULL, "SLB DAC5" },
3450 { "SLB DAC67", NULL, "SLB DAC6" },
3451 { "SLB DAC67", NULL, "SLB DAC7" },
3452
3453 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3454 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3455 { "ADDA1 Mux", "OB 67", "OB67" },
3456
3457 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3458 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3459 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3460 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3461 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3462 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3463
3464 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3465 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3466 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3467 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3468
3469 { "DAC1 FS", NULL, "DAC1 MIXL" },
3470 { "DAC1 FS", NULL, "DAC1 MIXR" },
3471
3472 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3473 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3474 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3475 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3476 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3477 { "DAC2 L Mux", "OB 2", "OutBound2" },
3478
3479 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3480 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3481 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3482 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3483 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3484 { "DAC2 R Mux", "OB 3", "OutBound3" },
3485 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3486 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3487
3488 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3489 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3490 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3491 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3492 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3493 { "DAC3 L Mux", "OB 4", "OutBound4" },
3494
3495 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3496 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3497 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3498 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3499 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3500 { "DAC3 R Mux", "OB 5", "OutBound5" },
3501
3502 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3503 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3504 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3505 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3506 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3507 { "DAC4 L Mux", "OB 6", "OutBound6" },
3508
3509 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3510 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3511 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3512 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3513 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3514 { "DAC4 R Mux", "OB 7", "OutBound7" },
3515
3516 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3517 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3518 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3519 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3520 { "Sidetone Mux", "ADC1", "ADC 1" },
3521 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 3522 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 3523
3524 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3525 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3526 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3527 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3528 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3529 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3530 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3531 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3532 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3533 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3534
3535 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3536 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3537 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3538 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
6800b5ba 3539 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
0e826e86
OC		 3540 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3541 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3542 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3543 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
6800b5ba 3544 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
0e826e86
OC		 3545
3546 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3547 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3548 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3549 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3550 { "DD1 MIXL", NULL, "dac mono3 left filter" },
0e826e86
OC		 3551 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3552 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3553 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3554 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3555 { "DD1 MIXR", NULL, "dac mono3 right filter" },
0e826e86
OC		 3556
3557 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3558 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3559 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3560 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 3561 { "DD2 MIXL", NULL, "dac mono4 left filter" },
0e826e86
OC		 3562 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3563 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3564 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3565 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 3566 { "DD2 MIXR", NULL, "dac mono4 right filter" },
0e826e86
OC		 3567
3568 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3569 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3570 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3571 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3572 { "DD1 MIX", NULL, "DD1 MIXL" },
3573 { "DD1 MIX", NULL, "DD1 MIXR" },
3574 { "DD2 MIX", NULL, "DD2 MIXL" },
3575 { "DD2 MIX", NULL, "DD2 MIXR" },
3576
3577 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3578 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3579 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3580 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3581
3582 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3583 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3584 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3585 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3586
3587 { "DAC 1", NULL, "DAC12 SRC Mux" },
3588 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
3589 { "DAC 2", NULL, "DAC12 SRC Mux" },
3590 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
3591 { "DAC 3", NULL, "DAC3 SRC Mux" },
3592 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
3593
3594 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3595 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3596 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3597 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3598 { "PDM1 L Mux", NULL, "PDM1 Power" },
3599 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3600 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3601 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3602 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3603 { "PDM1 R Mux", NULL, "PDM1 Power" },
3604 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3605 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3606 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3607 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3608 { "PDM2 L Mux", NULL, "PDM2 Power" },
3609 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3610 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3611 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3612 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3613 { "PDM2 R Mux", NULL, "PDM2 Power" },
3614
3615 { "LOUT1 amp", NULL, "DAC 1" },
3616 { "LOUT2 amp", NULL, "DAC 2" },
3617 { "LOUT3 amp", NULL, "DAC 3" },
3618
683996cb
OC		 3619 { "LOUT1 vref", NULL, "LOUT1 amp" },
3620 { "LOUT2 vref", NULL, "LOUT2 amp" },
3621 { "LOUT3 vref", NULL, "LOUT3 amp" },
3622
3623 { "LOUT1", NULL, "LOUT1 vref" },
3624 { "LOUT2", NULL, "LOUT2 vref" },
3625 { "LOUT3", NULL, "LOUT3 vref" },
0e826e86
OC		 3626
3627 { "PDM1L", NULL, "PDM1 L Mux" },
3628 { "PDM1R", NULL, "PDM1 R Mux" },
3629 { "PDM2L", NULL, "PDM2 L Mux" },
3630 { "PDM2R", NULL, "PDM2 R Mux" },
3631};
3632
2d15d974
BL		 3633static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3634 { "DMIC L2", NULL, "DMIC1 power" },
3635 { "DMIC R2", NULL, "DMIC1 power" },
3636};
3637
3638static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3639 { "DMIC L2", NULL, "DMIC2 power" },
3640 { "DMIC R2", NULL, "DMIC2 power" },
3641};
3642
0e826e86
OC		 3643static int rt5677_hw_params(struct snd_pcm_substream *substream,
3644 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3645{
3646 struct snd_soc_codec *codec = dai->codec;
3647 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3648 unsigned int val_len = 0, val_clk, mask_clk;
3649 int pre_div, bclk_ms, frame_size;
3650
3651 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 3652 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 3653 if (pre_div < 0) {
8a4bd60a
AP		 3654 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3655 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 3656 return -EINVAL;
3657 }
3658 frame_size = snd_soc_params_to_frame_size(params);
3659 if (frame_size < 0) {
3660 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3661 return -EINVAL;
3662 }
3663 bclk_ms = frame_size > 32;
3664 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3665
3666 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3667 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3668 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3669 bclk_ms, pre_div, dai->id);
3670
3671 switch (params_width(params)) {
3672 case 16:
3673 break;
3674 case 20:
3675 val_len |= RT5677_I2S_DL_20;
3676 break;
3677 case 24:
3678 val_len |= RT5677_I2S_DL_24;
3679 break;
3680 case 8:
3681 val_len |= RT5677_I2S_DL_8;
3682 break;
3683 default:
3684 return -EINVAL;
3685 }
3686
3687 switch (dai->id) {
3688 case RT5677_AIF1:
3689 mask_clk = RT5677_I2S_PD1_MASK;
3690 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3691 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3692 RT5677_I2S_DL_MASK, val_len);
3693 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3694 mask_clk, val_clk);
3695 break;
3696 case RT5677_AIF2:
3697 mask_clk = RT5677_I2S_PD2_MASK;
3698 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3699 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3700 RT5677_I2S_DL_MASK, val_len);
3701 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3702 mask_clk, val_clk);
3703 break;
3704 case RT5677_AIF3:
3705 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3706 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3707 pre_div << RT5677_I2S_PD3_SFT;
3708 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3709 RT5677_I2S_DL_MASK, val_len);
3710 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3711 mask_clk, val_clk);
3712 break;
3713 case RT5677_AIF4:
3714 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3715 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3716 pre_div << RT5677_I2S_PD4_SFT;
3717 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3718 RT5677_I2S_DL_MASK, val_len);
3719 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3720 mask_clk, val_clk);
3721 break;
3722 default:
3723 break;
3724 }
3725
3726 return 0;
3727}
3728
3729static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3730{
3731 struct snd_soc_codec *codec = dai->codec;
3732 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3733 unsigned int reg_val = 0;
3734
3735 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3736 case SND_SOC_DAIFMT_CBM_CFM:
3737 rt5677->master[dai->id] = 1;
3738 break;
3739 case SND_SOC_DAIFMT_CBS_CFS:
3740 reg_val |= RT5677_I2S_MS_S;
3741 rt5677->master[dai->id] = 0;
3742 break;
3743 default:
3744 return -EINVAL;
3745 }
3746
3747 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3748 case SND_SOC_DAIFMT_NB_NF:
3749 break;
3750 case SND_SOC_DAIFMT_IB_NF:
3751 reg_val |= RT5677_I2S_BP_INV;
3752 break;
3753 default:
3754 return -EINVAL;
3755 }
3756
3757 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3758 case SND_SOC_DAIFMT_I2S:
3759 break;
3760 case SND_SOC_DAIFMT_LEFT_J:
3761 reg_val |= RT5677_I2S_DF_LEFT;
3762 break;
3763 case SND_SOC_DAIFMT_DSP_A:
3764 reg_val |= RT5677_I2S_DF_PCM_A;
3765 break;
3766 case SND_SOC_DAIFMT_DSP_B:
3767 reg_val |= RT5677_I2S_DF_PCM_B;
3768 break;
3769 default:
3770 return -EINVAL;
3771 }
3772
3773 switch (dai->id) {
3774 case RT5677_AIF1:
3775 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3776 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3777 RT5677_I2S_DF_MASK, reg_val);
3778 break;
3779 case RT5677_AIF2:
3780 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3781 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3782 RT5677_I2S_DF_MASK, reg_val);
3783 break;
3784 case RT5677_AIF3:
3785 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3786 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3787 RT5677_I2S_DF_MASK, reg_val);
3788 break;
3789 case RT5677_AIF4:
3790 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3791 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3792 RT5677_I2S_DF_MASK, reg_val);
3793 break;
3794 default:
3795 break;
3796 }
3797
3798
3799 return 0;
3800}
3801
3802static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3803 int clk_id, unsigned int freq, int dir)
3804{
3805 struct snd_soc_codec *codec = dai->codec;
3806 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3807 unsigned int reg_val = 0;
3808
3809 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3810 return 0;
3811
3812 switch (clk_id) {
3813 case RT5677_SCLK_S_MCLK:
3814 reg_val |= RT5677_SCLK_SRC_MCLK;
3815 break;
3816 case RT5677_SCLK_S_PLL1:
3817 reg_val |= RT5677_SCLK_SRC_PLL1;
3818 break;
3819 case RT5677_SCLK_S_RCCLK:
3820 reg_val |= RT5677_SCLK_SRC_RCCLK;
3821 break;
3822 default:
3823 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3824 return -EINVAL;
3825 }
3826 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3827 RT5677_SCLK_SRC_MASK, reg_val);
3828 rt5677->sysclk = freq;
3829 rt5677->sysclk_src = clk_id;
3830
3831 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3832
3833 return 0;
3834}
3835
3836/**
3837 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3838 * @freq_in: external clock provided to codec.
3839 * @freq_out: target clock which codec works on.
3840 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3841 *
3842 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3843 *
3844 * Returns 0 for success or negative error code.
3845 */
3846static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 3847 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 3848{
099d334e 3849 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 3850 return -EINVAL;
3851
099d334e 3852 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 3853}
3854
3855static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3856 unsigned int freq_in, unsigned int freq_out)
3857{
3858 struct snd_soc_codec *codec = dai->codec;
3859 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 3860 struct rl6231_pll_code pll_code;
0e826e86
OC		 3861 int ret;
3862
3863 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3864 freq_out == rt5677->pll_out)
3865 return 0;
3866
3867 if (!freq_in || !freq_out) {
3868 dev_dbg(codec->dev, "PLL disabled\n");
3869
3870 rt5677->pll_in = 0;
3871 rt5677->pll_out = 0;
3872 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3873 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3874 return 0;
3875 }
3876
3877 switch (source) {
3878 case RT5677_PLL1_S_MCLK:
3879 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3880 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3881 break;
3882 case RT5677_PLL1_S_BCLK1:
3883 case RT5677_PLL1_S_BCLK2:
3884 case RT5677_PLL1_S_BCLK3:
3885 case RT5677_PLL1_S_BCLK4:
3886 switch (dai->id) {
3887 case RT5677_AIF1:
3888 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3889 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3890 break;
3891 case RT5677_AIF2:
3892 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3893 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3894 break;
3895 case RT5677_AIF3:
3896 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3897 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3898 break;
3899 case RT5677_AIF4:
3900 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3901 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3902 break;
3903 default:
3904 break;
3905 }
3906 break;
3907 default:
3908 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3909 return -EINVAL;
3910 }
3911
3912 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3913 if (ret < 0) {
3914 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3915 return ret;
3916 }
3917
099d334e
AL		 3918 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3919 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3920 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 3921
3922 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 3923 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 3924 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3925 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3926 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3927
3928 rt5677->pll_in = freq_in;
3929 rt5677->pll_out = freq_out;
3930 rt5677->pll_src = source;
3931
3932 return 0;
3933}
3934
48561afe
OC		 3935static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3936 unsigned int rx_mask, int slots, int slot_width)
3937{
3938 struct snd_soc_codec *codec = dai->codec;
3939 unsigned int val = 0;
3940
3941 if (rx_mask || tx_mask)
3942 val |= (1 << 12);
3943
3944 switch (slots) {
3945 case 4:
3946 val |= (1 << 10);
3947 break;
3948 case 6:
3949 val |= (2 << 10);
3950 break;
3951 case 8:
3952 val |= (3 << 10);
3953 break;
3954 case 2:
3955 default:
3956 break;
3957 }
3958
3959 switch (slot_width) {
3960 case 20:
3961 val |= (1 << 8);
3962 break;
3963 case 24:
3964 val |= (2 << 8);
3965 break;
3966 case 32:
3967 val |= (3 << 8);
3968 break;
3969 case 16:
3970 default:
3971 break;
3972 }
3973
3974 switch (dai->id) {
3975 case RT5677_AIF1:
3976 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
3977 break;
3978 case RT5677_AIF2:
3979 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
3980 break;
3981 default:
3982 break;
3983 }
3984
3985 return 0;
3986}
3987
0e826e86
OC		 3988static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3989 enum snd_soc_bias_level level)
3990{
3991 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3992
3993 switch (level) {
3994 case SND_SOC_BIAS_ON:
3995 break;
3996
3997 case SND_SOC_BIAS_PREPARE:
3998 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
af48f1d0
OC		 3999 rt5677_set_dsp_vad(codec, false);
4000
0e826e86
OC		 4001 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4002 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4003 0x0055);
4004 regmap_update_bits(rt5677->regmap,
4005 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4006 0x0f00, 0x0f00);
4007 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
683996cb 4008 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
0e826e86
OC		 4009 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4010 RT5677_PWR_BG | RT5677_PWR_VREF2,
4011 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4012 RT5677_PWR_BG | RT5677_PWR_VREF2);
683996cb 4013 rt5677->is_vref_slow = false;
0e826e86
OC		 4014 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4015 RT5677_PWR_CORE, RT5677_PWR_CORE);
4016 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4017 0x1, 0x1);
4018 }
4019 break;
4020
4021 case SND_SOC_BIAS_STANDBY:
4022 break;
4023
4024 case SND_SOC_BIAS_OFF:
4025 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4026 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4027 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 4028 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 4029 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4030 regmap_update_bits(rt5677->regmap,
4031 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 4032
4033 if (rt5677->dsp_vad_en)
4034 rt5677_set_dsp_vad(codec, true);
0e826e86
OC		 4035 break;
4036
4037 default:
4038 break;
4039 }
4040 codec->dapm.bias_level = level;
4041
4042 return 0;
4043}
4044
44caf764
OC		 4045#ifdef CONFIG_GPIOLIB
4046static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4047{
4048 return container_of(chip, struct rt5677_priv, gpio_chip);
4049}
4050
4051static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4052{
4053 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4054
4055 switch (offset) {
4056 case RT5677_GPIO1 ... RT5677_GPIO5:
4057 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4058 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4059 break;
4060
4061 case RT5677_GPIO6:
4062 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4063 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4064 break;
4065
4066 default:
4067 break;
4068 }
4069}
4070
4071static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4072 unsigned offset, int value)
4073{
4074 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4075
4076 switch (offset) {
4077 case RT5677_GPIO1 ... RT5677_GPIO5:
4078 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4079 0x3 << (offset * 3 + 1),
4080 (0x2 | !!value) << (offset * 3 + 1));
4081 break;
4082
4083 case RT5677_GPIO6:
4084 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4085 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4086 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4087 break;
4088
4089 default:
4090 break;
4091 }
4092
4093 return 0;
4094}
4095
4096static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4097{
4098 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4099 int value, ret;
4100
4101 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4102 if (ret < 0)
4103 return ret;
4104
4105 return (value & (0x1 << offset)) >> offset;
4106}
4107
4108static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4109{
4110 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4111
4112 switch (offset) {
4113 case RT5677_GPIO1 ... RT5677_GPIO5:
4114 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4115 0x1 << (offset * 3 + 2), 0x0);
4116 break;
4117
4118 case RT5677_GPIO6:
4119 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4120 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4121 break;
4122
4123 default:
4124 break;
4125 }
4126
4127 return 0;
4128}
4129
40eb90a1
AP		 4130/** Configures the gpio as
4131 * 0 - floating
4132 * 1 - pull down
4133 * 2 - pull up
4134 */
4135static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4136 int value)
4137{
4138 int shift;
4139
4140 switch (offset) {
4141 case RT5677_GPIO1 ... RT5677_GPIO2:
4142 shift = 2 * (1 - offset);
4143 regmap_update_bits(rt5677->regmap,
4144 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4145 0x3 << shift,
4146 (value & 0x3) << shift);
4147 break;
4148
4149 case RT5677_GPIO3 ... RT5677_GPIO6:
4150 shift = 2 * (9 - offset);
4151 regmap_update_bits(rt5677->regmap,
4152 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4153 0x3 << shift,
4154 (value & 0x3) << shift);
4155 break;
4156
4157 default:
4158 break;
4159 }
4160}
4161
5e3363ad
OC		 4162static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4163{
4164 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4165 struct regmap_irq_chip_data *data = rt5677->irq_data;
4166 int irq;
4167
4168 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4169 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4170 (rt5677->pdata.jd1_gpio == 2 &&
4171 offset == RT5677_GPIO2) ||
4172 (rt5677->pdata.jd1_gpio == 3 &&
4173 offset == RT5677_GPIO3)) {
4174 irq = RT5677_IRQ_JD1;
4175 } else {
4176 return -ENXIO;
4177 }
4178 }
4179
4180 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4181 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4182 (rt5677->pdata.jd2_gpio == 2 &&
4183 offset == RT5677_GPIO5) ||
4184 (rt5677->pdata.jd2_gpio == 3 &&
4185 offset == RT5677_GPIO6)) {
4186 irq = RT5677_IRQ_JD2;
4187 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4188 offset == RT5677_GPIO4) ||
4189 (rt5677->pdata.jd3_gpio == 2 &&
4190 offset == RT5677_GPIO5) ||
4191 (rt5677->pdata.jd3_gpio == 3 &&
4192 offset == RT5677_GPIO6)) {
4193 irq = RT5677_IRQ_JD3;
4194 } else {
4195 return -ENXIO;
4196 }
4197 }
4198
4199 return regmap_irq_get_virq(data, irq);
4200}
4201
44caf764
OC		 4202static struct gpio_chip rt5677_template_chip = {
4203 .label = "rt5677",
4204 .owner = THIS_MODULE,
4205 .direction_output = rt5677_gpio_direction_out,
4206 .set = rt5677_gpio_set,
4207 .direction_input = rt5677_gpio_direction_in,
4208 .get = rt5677_gpio_get,
5e3363ad 4209 .to_irq = rt5677_to_irq,
44caf764
OC		 4210 .can_sleep = 1,
4211};
4212
4213static void rt5677_init_gpio(struct i2c_client *i2c)
4214{
4215 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4216 int ret;
4217
4218 rt5677->gpio_chip = rt5677_template_chip;
4219 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4220 rt5677->gpio_chip.dev = &i2c->dev;
4221 rt5677->gpio_chip.base = -1;
4222
4223 ret = gpiochip_add(&rt5677->gpio_chip);
4224 if (ret != 0)
4225 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4226}
4227
4228static void rt5677_free_gpio(struct i2c_client *i2c)
4229{
4230 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 4231
5d5e63af 4232 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 4233}
4234#else
45b6e1d3
AP		 4235static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4236 int value)
4237{
4238}
4239
44caf764
OC		 4240static void rt5677_init_gpio(struct i2c_client *i2c)
4241{
4242}
4243
4244static void rt5677_free_gpio(struct i2c_client *i2c)
4245{
4246}
4247#endif
4248
0e826e86
OC		 4249static int rt5677_probe(struct snd_soc_codec *codec)
4250{
4251 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 4252 int i;
0e826e86
OC		 4253
4254 rt5677->codec = codec;
4255
2d15d974
BL		 4256 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4257 snd_soc_dapm_add_routes(&codec->dapm,
4258 rt5677_dmic2_clk_2,
4259 ARRAY_SIZE(rt5677_dmic2_clk_2));
4260 } else { /*use dmic1 clock by default*/
4261 snd_soc_dapm_add_routes(&codec->dapm,
4262 rt5677_dmic2_clk_1,
4263 ARRAY_SIZE(rt5677_dmic2_clk_1));
4264 }
4265
0e826e86
OC		 4266 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4267
4268 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4269 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4270
40eb90a1
AP		 4271 for (i = 0; i < RT5677_GPIO_NUM; i++)
4272 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4273
5e3363ad
OC		 4274 if (rt5677->irq_data) {
4275 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4276 0x8000);
4277 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4278 0x0008);
4279
4280 if (rt5677->pdata.jd1_gpio)
4281 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4282 RT5677_SEL_GPIO_JD1_MASK,
4283 rt5677->pdata.jd1_gpio <<
4284 RT5677_SEL_GPIO_JD1_SFT);
4285
4286 if (rt5677->pdata.jd2_gpio)
4287 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4288 RT5677_SEL_GPIO_JD2_MASK,
4289 rt5677->pdata.jd2_gpio <<
4290 RT5677_SEL_GPIO_JD2_SFT);
4291
4292 if (rt5677->pdata.jd3_gpio)
4293 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4294 RT5677_SEL_GPIO_JD3_MASK,
4295 rt5677->pdata.jd3_gpio <<
4296 RT5677_SEL_GPIO_JD3_SFT);
4297 }
4298
af48f1d0 4299 mutex_init(&rt5677->dsp_cmd_lock);
6fe17da0 4300 mutex_init(&rt5677->dsp_pri_lock);
af48f1d0 4301
0e826e86
OC		 4302 return 0;
4303}
4304
4305static int rt5677_remove(struct snd_soc_codec *codec)
4306{
4307 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4308
4309 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f9f6a592
AP		 4310 if (gpio_is_valid(rt5677->pow_ldo2))
4311 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 4312
4313 return 0;
4314}
4315
4316#ifdef CONFIG_PM
4317static int rt5677_suspend(struct snd_soc_codec *codec)
4318{
4319 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4320
af48f1d0
OC		 4321 if (!rt5677->dsp_vad_en) {
4322 regcache_cache_only(rt5677->regmap, true);
4323 regcache_mark_dirty(rt5677->regmap);
4324 }
4325
f9f6a592
AP		 4326 if (gpio_is_valid(rt5677->pow_ldo2))
4327 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 4328
4329 return 0;
4330}
4331
4332static int rt5677_resume(struct snd_soc_codec *codec)
4333{
4334 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4335
f9f6a592
AP		 4336 if (gpio_is_valid(rt5677->pow_ldo2)) {
4337 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4338 msleep(10);
4339 }
af48f1d0
OC		 4340
4341 if (!rt5677->dsp_vad_en) {
4342 regcache_cache_only(rt5677->regmap, false);
4343 regcache_sync(rt5677->regmap);
4344 }
0e826e86
OC		 4345
4346 return 0;
4347}
4348#else
4349#define rt5677_suspend NULL
4350#define rt5677_resume NULL
4351#endif
4352
19ba484d
OC		 4353static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4354{
4355 struct i2c_client *client = context;
4356 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4357
6fe17da0
OC		 4358 if (rt5677->is_dsp_mode) {
4359 if (reg > 0xff) {
4360 mutex_lock(&rt5677->dsp_pri_lock);
4361 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4362 reg & 0xff);
4363 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4364 mutex_unlock(&rt5677->dsp_pri_lock);
4365 } else {
4366 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4367 }
4368 } else {
19ba484d 4369 regmap_read(rt5677->regmap_physical, reg, val);
6fe17da0 4370 }
19ba484d
OC		 4371
4372 return 0;
4373}
4374
4375static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4376{
4377 struct i2c_client *client = context;
4378 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4379
6fe17da0
OC		 4380 if (rt5677->is_dsp_mode) {
4381 if (reg > 0xff) {
4382 mutex_lock(&rt5677->dsp_pri_lock);
4383 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4384 reg & 0xff);
4385 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4386 val);
4387 mutex_unlock(&rt5677->dsp_pri_lock);
4388 } else {
4389 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4390 }
4391 } else {
19ba484d 4392 regmap_write(rt5677->regmap_physical, reg, val);
6fe17da0 4393 }
19ba484d
OC		 4394
4395 return 0;
4396}
4397
0e826e86
OC		 4398#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4399#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4400 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4401
4402static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4403 .hw_params = rt5677_hw_params,
4404 .set_fmt = rt5677_set_dai_fmt,
4405 .set_sysclk = rt5677_set_dai_sysclk,
4406 .set_pll = rt5677_set_dai_pll,
48561afe 4407 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 4408};
4409
4410static struct snd_soc_dai_driver rt5677_dai[] = {
4411 {
4412 .name = "rt5677-aif1",
4413 .id = RT5677_AIF1,
4414 .playback = {
4415 .stream_name = "AIF1 Playback",
4416 .channels_min = 1,
4417 .channels_max = 2,
4418 .rates = RT5677_STEREO_RATES,
4419 .formats = RT5677_FORMATS,
4420 },
4421 .capture = {
4422 .stream_name = "AIF1 Capture",
4423 .channels_min = 1,
4424 .channels_max = 2,
4425 .rates = RT5677_STEREO_RATES,
4426 .formats = RT5677_FORMATS,
4427 },
4428 .ops = &rt5677_aif_dai_ops,
4429 },
4430 {
4431 .name = "rt5677-aif2",
4432 .id = RT5677_AIF2,
4433 .playback = {
4434 .stream_name = "AIF2 Playback",
4435 .channels_min = 1,
4436 .channels_max = 2,
4437 .rates = RT5677_STEREO_RATES,
4438 .formats = RT5677_FORMATS,
4439 },
4440 .capture = {
4441 .stream_name = "AIF2 Capture",
4442 .channels_min = 1,
4443 .channels_max = 2,
4444 .rates = RT5677_STEREO_RATES,
4445 .formats = RT5677_FORMATS,
4446 },
4447 .ops = &rt5677_aif_dai_ops,
4448 },
4449 {
4450 .name = "rt5677-aif3",
4451 .id = RT5677_AIF3,
4452 .playback = {
4453 .stream_name = "AIF3 Playback",
4454 .channels_min = 1,
4455 .channels_max = 2,
4456 .rates = RT5677_STEREO_RATES,
4457 .formats = RT5677_FORMATS,
4458 },
4459 .capture = {
4460 .stream_name = "AIF3 Capture",
4461 .channels_min = 1,
4462 .channels_max = 2,
4463 .rates = RT5677_STEREO_RATES,
4464 .formats = RT5677_FORMATS,
4465 },
4466 .ops = &rt5677_aif_dai_ops,
4467 },
4468 {
4469 .name = "rt5677-aif4",
4470 .id = RT5677_AIF4,
4471 .playback = {
4472 .stream_name = "AIF4 Playback",
4473 .channels_min = 1,
4474 .channels_max = 2,
4475 .rates = RT5677_STEREO_RATES,
4476 .formats = RT5677_FORMATS,
4477 },
4478 .capture = {
4479 .stream_name = "AIF4 Capture",
4480 .channels_min = 1,
4481 .channels_max = 2,
4482 .rates = RT5677_STEREO_RATES,
4483 .formats = RT5677_FORMATS,
4484 },
4485 .ops = &rt5677_aif_dai_ops,
4486 },
4487 {
4488 .name = "rt5677-slimbus",
4489 .id = RT5677_AIF5,
4490 .playback = {
4491 .stream_name = "SLIMBus Playback",
4492 .channels_min = 1,
4493 .channels_max = 2,
4494 .rates = RT5677_STEREO_RATES,
4495 .formats = RT5677_FORMATS,
4496 },
4497 .capture = {
4498 .stream_name = "SLIMBus Capture",
4499 .channels_min = 1,
4500 .channels_max = 2,
4501 .rates = RT5677_STEREO_RATES,
4502 .formats = RT5677_FORMATS,
4503 },
4504 .ops = &rt5677_aif_dai_ops,
4505 },
4506};
4507
4508static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4509 .probe = rt5677_probe,
4510 .remove = rt5677_remove,
4511 .suspend = rt5677_suspend,
4512 .resume = rt5677_resume,
4513 .set_bias_level = rt5677_set_bias_level,
4514 .idle_bias_off = true,
4515 .controls = rt5677_snd_controls,
4516 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4517 .dapm_widgets = rt5677_dapm_widgets,
4518 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4519 .dapm_routes = rt5677_dapm_routes,
4520 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4521};
4522
19ba484d
OC		 4523static const struct regmap_config rt5677_regmap_physical = {
4524 .name = "physical",
4525 .reg_bits = 8,
4526 .val_bits = 16,
4527
6fe17da0
OC		 4528 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4529 RT5677_PR_SPACING),
19ba484d
OC		 4530 .readable_reg = rt5677_readable_register,
4531
4532 .cache_type = REGCACHE_NONE,
6fe17da0
OC		 4533 .ranges = rt5677_ranges,
4534 .num_ranges = ARRAY_SIZE(rt5677_ranges),
19ba484d
OC		 4535};
4536
0e826e86
OC		 4537static const struct regmap_config rt5677_regmap = {
4538 .reg_bits = 8,
4539 .val_bits = 16,
4540
4541 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4542 RT5677_PR_SPACING),
4543
4544 .volatile_reg = rt5677_volatile_register,
4545 .readable_reg = rt5677_readable_register,
19ba484d
OC		 4546 .reg_read = rt5677_read,
4547 .reg_write = rt5677_write,
0e826e86
OC		 4548
4549 .cache_type = REGCACHE_RBTREE,
4550 .reg_defaults = rt5677_reg,
4551 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4552 .ranges = rt5677_ranges,
4553 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4554};
4555
4556static const struct i2c_device_id rt5677_i2c_id[] = {
4557 { "rt5677", 0 },
4558 { }
4559};
4560MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4561
f9f6a592
AP		 4562static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4563{
6f67c380
AP		 4564 rt5677->pdata.in1_diff = of_property_read_bool(np,
4565 "realtek,in1-differential");
4566 rt5677->pdata.in2_diff = of_property_read_bool(np,
4567 "realtek,in2-differential");
4568 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4569 "realtek,lout1-differential");
4570 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4571 "realtek,lout2-differential");
4572 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4573 "realtek,lout3-differential");
4574
f9f6a592
AP		 4575 rt5677->pow_ldo2 = of_get_named_gpio(np,
4576 "realtek,pow-ldo2-gpio", 0);
4577
4578 /*
4579 * POW_LDO2 is optional (it may be statically tied on the board).
4580 * -ENOENT means that the property doesn't exist, i.e. there is no
4581 * GPIO, so is not an error. Any other error code means the property
4582 * exists, but could not be parsed.
4583 */
4584 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4585 (rt5677->pow_ldo2 != -ENOENT))
4586 return rt5677->pow_ldo2;
4587
40eb90a1
AP		 4588 of_property_read_u8_array(np, "realtek,gpio-config",
4589 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4590
5e3363ad
OC		 4591 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4592 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4593 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4594
f9f6a592
AP		 4595 return 0;
4596}
4597
5e3363ad
OC		 4598static struct regmap_irq rt5677_irqs[] = {
4599 [RT5677_IRQ_JD1] = {
4600 .reg_offset = 0,
4601 .mask = RT5677_EN_IRQ_GPIO_JD1,
4602 },
4603 [RT5677_IRQ_JD2] = {
4604 .reg_offset = 0,
4605 .mask = RT5677_EN_IRQ_GPIO_JD2,
4606 },
4607 [RT5677_IRQ_JD3] = {
4608 .reg_offset = 0,
4609 .mask = RT5677_EN_IRQ_GPIO_JD3,
4610 },
4611};
4612
4613static struct regmap_irq_chip rt5677_irq_chip = {
4614 .name = "rt5677",
4615 .irqs = rt5677_irqs,
4616 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4617
4618 .num_regs = 1,
4619 .status_base = RT5677_IRQ_CTRL1,
4620 .mask_base = RT5677_IRQ_CTRL1,
4621 .mask_invert = 1,
4622};
4623
35d40d10 4624static int rt5677_init_irq(struct i2c_client *i2c)
5e3363ad
OC		 4625{
4626 int ret;
4627 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4628
4629 if (!rt5677->pdata.jd1_gpio &&
4630 !rt5677->pdata.jd2_gpio &&
4631 !rt5677->pdata.jd3_gpio)
4632 return 0;
4633
4634 if (!i2c->irq) {
4635 dev_err(&i2c->dev, "No interrupt specified\n");
4636 return -EINVAL;
4637 }
4638
4639 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4640 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4641 &rt5677_irq_chip, &rt5677->irq_data);
4642
4643 if (ret != 0) {
4644 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4645 return ret;
4646 }
4647
4648 return 0;
4649}
4650
35d40d10 4651static void rt5677_free_irq(struct i2c_client *i2c)
5e3363ad
OC		 4652{
4653 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4654
4655 if (rt5677->irq_data)
4656 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4657}
4658
0e826e86
OC		 4659static int rt5677_i2c_probe(struct i2c_client *i2c,
4660 const struct i2c_device_id *id)
4661{
4662 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4663 struct rt5677_priv *rt5677;
4664 int ret;
4665 unsigned int val;
4666
4667 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4668 GFP_KERNEL);
4669 if (rt5677 == NULL)
4670 return -ENOMEM;
4671
4672 i2c_set_clientdata(i2c, rt5677);
4673
4674 if (pdata)
4675 rt5677->pdata = *pdata;
4676
f9f6a592
AP		 4677 if (i2c->dev.of_node) {
4678 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4679 if (ret) {
4680 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4681 ret);
4682 return ret;
4683 }
4684 } else {
4685 rt5677->pow_ldo2 = -EINVAL;
4686 }
4687
4688 if (gpio_is_valid(rt5677->pow_ldo2)) {
4689 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4690 GPIOF_OUT_INIT_HIGH,
4691 "RT5677 POW_LDO2");
4692 if (ret < 0) {
4693 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4694 rt5677->pow_ldo2, ret);
4695 return ret;
4696 }
4697 /* Wait a while until I2C bus becomes available. The datasheet
4698 * does not specify the exact we should wait but startup
4699 * sequence mentiones at least a few milliseconds.
4700 */
4701 msleep(10);
4702 }
4703
19ba484d
OC		 4704 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4705 &rt5677_regmap_physical);
4706 if (IS_ERR(rt5677->regmap_physical)) {
4707 ret = PTR_ERR(rt5677->regmap_physical);
4708 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4709 ret);
4710 return ret;
4711 }
4712
4713 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
0e826e86
OC		 4714 if (IS_ERR(rt5677->regmap)) {
4715 ret = PTR_ERR(rt5677->regmap);
4716 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4717 ret);
4718 return ret;
4719 }
4720
4721 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4722 if (val != RT5677_DEVICE_ID) {
4723 dev_err(&i2c->dev,
4724 "Device with ID register %x is not rt5677\n", val);
4725 return -ENODEV;
4726 }
4727
4728 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4729
4730 ret = regmap_register_patch(rt5677->regmap, init_list,
4731 ARRAY_SIZE(init_list));
4732 if (ret != 0)
4733 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4734
4735 if (rt5677->pdata.in1_diff)
4736 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4737 RT5677_IN_DF1, RT5677_IN_DF1);
4738
4739 if (rt5677->pdata.in2_diff)
4740 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4741 RT5677_IN_DF2, RT5677_IN_DF2);
4742
6f67c380
AP		 4743 if (rt5677->pdata.lout1_diff)
4744 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4745 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4746
4747 if (rt5677->pdata.lout2_diff)
4748 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4749 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4750
4751 if (rt5677->pdata.lout3_diff)
4752 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4753 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4754
2d15d974
BL		 4755 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4756 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4757 RT5677_GPIO5_FUNC_MASK,
4758 RT5677_GPIO5_FUNC_DMIC);
4759 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4760 RT5677_GPIO5_DIR_MASK,
4761 RT5677_GPIO5_DIR_OUT);
4762 }
4763
44caf764 4764 rt5677_init_gpio(i2c);
35d40d10 4765 rt5677_init_irq(i2c);
44caf764 4766
d0bdcb91
AL		 4767 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4768 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 4769}
4770
4771static int rt5677_i2c_remove(struct i2c_client *i2c)
4772{
4773 snd_soc_unregister_codec(&i2c->dev);
35d40d10 4774 rt5677_free_irq(i2c);
44caf764 4775 rt5677_free_gpio(i2c);
0e826e86
OC		 4776
4777 return 0;
4778}
4779
4780static struct i2c_driver rt5677_i2c_driver = {
4781 .driver = {
4782 .name = "rt5677",
4783 .owner = THIS_MODULE,
4784 },
4785 .probe = rt5677_i2c_probe,
4786 .remove = rt5677_i2c_remove,
4787 .id_table = rt5677_i2c_id,
4788};
c8cfbec8 4789module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 4790
4791MODULE_DESCRIPTION("ASoC RT5677 driver");
4792MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4793MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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