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Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
bd0593f5 19#include <linux/log2.h>
e5d80e82 20#include <linux/regmap.h>
9b34e6cc
ZZ		 21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
58e49424 24#include <linux/of_device.h>
9b34e6cc
ZZ		 25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
9b34e6cc
ZZ		 32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
151798f8 38/* default value of sgtl5000 registers */
e5d80e82 39static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82
FE		 41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 50 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
51 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
52 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
53 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82
FE		 54 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
55 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
61 { SGTL5000_DAP_CTRL, 0x0000 },
62 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 66 { SGTL5000_DAP_SURROUND, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 73 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 74 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 78};
79
80/* regulator supplies for sgtl5000, VDDD is an optional external supply */
81enum sgtl5000_regulator_supplies {
82 VDDA,
83 VDDIO,
84 VDDD,
85 SGTL5000_SUPPLY_NUM
86};
87
88/* vddd is optional supply */
89static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
90 "VDDA",
91 "VDDIO",
92 "VDDD"
93};
94
95#define LDO_CONSUMER_NAME "VDDD_LDO"
96#define LDO_VOLTAGE 1200000
97
98static struct regulator_consumer_supply ldo_consumer[] = {
99 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
100};
101
61a142b7 102static struct regulator_init_data ldo_init_data = {
9b34e6cc 103 .constraints = {
cd041f64
FE		 104 .min_uV = 1200000,
105 .max_uV = 1200000,
9b34e6cc
ZZ		 106 .valid_modes_mask = REGULATOR_MODE_NORMAL,
107 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
108 },
109 .num_consumer_supplies = 1,
110 .consumer_supplies = &ldo_consumer[0],
111};
112
113/*
114 * sgtl5000 internal ldo regulator,
115 * enabled when VDDD not provided
116 */
117struct ldo_regulator {
118 struct regulator_desc desc;
119 struct regulator_dev *dev;
120 int voltage;
121 void *codec_data;
122 bool enabled;
123};
124
bd0593f5
JMH		 125enum sgtl5000_micbias_resistor {
126 SGTL5000_MICBIAS_OFF = 0,
127 SGTL5000_MICBIAS_2K = 2,
128 SGTL5000_MICBIAS_4K = 4,
129 SGTL5000_MICBIAS_8K = 8,
130};
131
9b34e6cc
ZZ		 132/* sgtl5000 private structure in codec */
133struct sgtl5000_priv {
134 int sysclk; /* sysclk rate */
135 int master; /* i2s master or not */
136 int fmt; /* i2s data format */
137 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
138 struct ldo_regulator *ldo;
e5d80e82 139 struct regmap *regmap;
9e13f345 140 struct clk *mclk;
252e91ff 141 int revision;
bd0593f5 142 u8 micbias_resistor;
87357797 143 u8 micbias_voltage;
9b34e6cc
ZZ		 144};
145
146/*
147 * mic_bias power on/off share the same register bits with
148 * output impedance of mic bias, when power on mic bias, we
149 * need reclaim it to impedance value.
150 * 0x0 = Powered off
151 * 0x1 = 2Kohm
152 * 0x2 = 4Kohm
153 * 0x3 = 8Kohm
154 */
155static int mic_bias_event(struct snd_soc_dapm_widget *w,
156 struct snd_kcontrol *kcontrol, int event)
157{
73bffd17
LPC		 158 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
159 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
bd0593f5 160
9b34e6cc
ZZ		 161 switch (event) {
162 case SND_SOC_DAPM_POST_PMU:
bd0593f5 163 /* change mic bias resistor */
73bffd17 164 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
bd0593f5
JMH		 165 SGTL5000_BIAS_R_MASK,
166 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 167 break;
168
169 case SND_SOC_DAPM_PRE_PMD:
73bffd17 170 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 171 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 172 break;
173 }
174 return 0;
175}
176
177/*
f0cdcf3a
ZZ		 178 * As manual described, ADC/DAC only works when VAG powerup,
179 * So enabled VAG before ADC/DAC up.
180 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 181 */
f0cdcf3a 182static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 183 struct snd_kcontrol *kcontrol, int event)
184{
73bffd17 185 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
f091f3f0
LW		 186 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
187
9b34e6cc 188 switch (event) {
dd4d2d6d 189 case SND_SOC_DAPM_POST_PMU:
73bffd17 190 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
9b34e6cc
ZZ		 191 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
192 break;
193
dd4d2d6d 194 case SND_SOC_DAPM_PRE_PMD:
f091f3f0
LW		 195 /*
196 * Don't clear VAG_POWERUP, when both DAC and ADC are
197 * operational to prevent inadvertently starving the
198 * other one of them.
199 */
73bffd17 200 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
f091f3f0 201 mask) != mask) {
73bffd17 202 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
f091f3f0
LW		 203 SGTL5000_VAG_POWERUP, 0);
204 msleep(400);
205 }
9b34e6cc
ZZ		 206 break;
207 default:
208 break;
209 }
210
211 return 0;
212}
213
214/* input sources for ADC */
215static const char *adc_mux_text[] = {
216 "MIC_IN", "LINE_IN"
217};
218
c8ed6504
TI		 219static SOC_ENUM_SINGLE_DECL(adc_enum,
220 SGTL5000_CHIP_ANA_CTRL, 2,
221 adc_mux_text);
9b34e6cc
ZZ		 222
223static const struct snd_kcontrol_new adc_mux =
224SOC_DAPM_ENUM("Capture Mux", adc_enum);
225
226/* input sources for DAC */
227static const char *dac_mux_text[] = {
228 "DAC", "LINE_IN"
229};
230
c8ed6504
TI		 231static SOC_ENUM_SINGLE_DECL(dac_enum,
232 SGTL5000_CHIP_ANA_CTRL, 6,
233 dac_mux_text);
9b34e6cc
ZZ		 234
235static const struct snd_kcontrol_new dac_mux =
236SOC_DAPM_ENUM("Headphone Mux", dac_enum);
237
238static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
239 SND_SOC_DAPM_INPUT("LINE_IN"),
240 SND_SOC_DAPM_INPUT("MIC_IN"),
241
242 SND_SOC_DAPM_OUTPUT("HP_OUT"),
243 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
244
8fc8ec92
MB		 245 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
246 mic_bias_event,
247 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 248
f0cdcf3a
ZZ		 249 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
250 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 251
252 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
253 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
254
255 /* aif for i2s input */
256 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
257 0, SGTL5000_CHIP_DIG_POWER,
258 0, 0),
259
260 /* aif for i2s output */
261 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
262 0, SGTL5000_CHIP_DIG_POWER,
263 1, 0),
264
f0cdcf3a 265 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 266 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 267
268 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
269 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 270};
271
272/* routes for sgtl5000 */
89989637 273static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 274 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
275 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
276
277 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
278 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
279
280 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
281 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
282 {"LO", NULL, "DAC"}, /* dac --> line_out */
283
284 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
285 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
286
287 {"LINE_OUT", NULL, "LO"},
288 {"HP_OUT", NULL, "HP"},
289};
290
291/* custom function to fetch info of PCM playback volume */
292static int dac_info_volsw(struct snd_kcontrol *kcontrol,
293 struct snd_ctl_elem_info *uinfo)
294{
295 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
296 uinfo->count = 2;
297 uinfo->value.integer.min = 0;
298 uinfo->value.integer.max = 0xfc - 0x3c;
299 return 0;
300}
301
302/*
303 * custom function to get of PCM playback volume
304 *
305 * dac volume register
306 * 15-------------8-7--------------0
307 * | R channel vol | L channel vol |
308 * -------------------------------
309 *
310 * PCM volume with 0.5017 dB steps from 0 to -90 dB
311 *
312 * register values map to dB
313 * 0x3B and less = Reserved
314 * 0x3C = 0 dB
315 * 0x3D = -0.5 dB
316 * 0xF0 = -90 dB
317 * 0xFC and greater = Muted
318 *
319 * register value map to userspace value
320 *
321 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
322 * ------------------------------
323 * userspace value 0xc0 0
324 */
325static int dac_get_volsw(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_value *ucontrol)
327{
ea53bf77 328 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 329 int reg;
330 int l;
331 int r;
332
333 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
334
335 /* get left channel volume */
336 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
337
338 /* get right channel volume */
339 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
340
341 /* make sure value fall in (0x3c,0xfc) */
342 l = clamp(l, 0x3c, 0xfc);
343 r = clamp(r, 0x3c, 0xfc);
344
345 /* invert it and map to userspace value */
346 l = 0xfc - l;
347 r = 0xfc - r;
348
349 ucontrol->value.integer.value[0] = l;
350 ucontrol->value.integer.value[1] = r;
351
352 return 0;
353}
354
355/*
356 * custom function to put of PCM playback volume
357 *
358 * dac volume register
359 * 15-------------8-7--------------0
360 * | R channel vol | L channel vol |
361 * -------------------------------
362 *
363 * PCM volume with 0.5017 dB steps from 0 to -90 dB
364 *
365 * register values map to dB
366 * 0x3B and less = Reserved
367 * 0x3C = 0 dB
368 * 0x3D = -0.5 dB
369 * 0xF0 = -90 dB
370 * 0xFC and greater = Muted
371 *
372 * userspace value map to register value
373 *
374 * userspace value 0xc0 0
375 * ------------------------------
376 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
377 */
378static int dac_put_volsw(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380{
ea53bf77 381 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 382 int reg;
383 int l;
384 int r;
385
386 l = ucontrol->value.integer.value[0];
387 r = ucontrol->value.integer.value[1];
388
389 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
390 l = clamp(l, 0, 0xfc - 0x3c);
391 r = clamp(r, 0, 0xfc - 0x3c);
392
393 /* invert it, get the value can be set to register */
394 l = 0xfc - l;
395 r = 0xfc - r;
396
397 /* shift to get the register value */
398 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
399 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
400
401 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
402
403 return 0;
404}
405
406static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
407
408/* tlv for mic gain, 0db 20db 30db 40db */
53eb1ca3 409static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
9b34e6cc 410 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
53eb1ca3
LPC		 411 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
412);
9b34e6cc
ZZ		 413
414/* tlv for hp volume, -51.5db to 12.0db, step .5db */
415static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
416
417static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
418 /* SOC_DOUBLE_S8_TLV with invert */
419 {
420 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
421 .name = "PCM Playback Volume",
422 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
423 SNDRV_CTL_ELEM_ACCESS_READWRITE,
424 .info = dac_info_volsw,
425 .get = dac_get_volsw,
426 .put = dac_put_volsw,
427 },
428
429 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
430 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
431 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 432 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 433 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
434
435 SOC_DOUBLE_TLV("Headphone Playback Volume",
436 SGTL5000_CHIP_ANA_HP_CTRL,
437 0, 8,
438 0x7f, 1,
439 headphone_volume),
440 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
441 5, 1, 0),
442
443 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 444 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 445};
446
447/* mute the codec used by alsa core */
448static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
449{
450 struct snd_soc_codec *codec = codec_dai->codec;
451 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
452
453 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
454 adcdac_ctrl, mute ? adcdac_ctrl : 0);
455
456 return 0;
457}
458
459/* set codec format */
460static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
461{
462 struct snd_soc_codec *codec = codec_dai->codec;
463 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
464 u16 i2sctl = 0;
465
466 sgtl5000->master = 0;
467 /*
468 * i2s clock and frame master setting.
469 * ONLY support:
470 * - clock and frame slave,
471 * - clock and frame master
472 */
473 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
474 case SND_SOC_DAIFMT_CBS_CFS:
475 break;
476 case SND_SOC_DAIFMT_CBM_CFM:
477 i2sctl |= SGTL5000_I2S_MASTER;
478 sgtl5000->master = 1;
479 break;
480 default:
481 return -EINVAL;
482 }
483
484 /* setting i2s data format */
485 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
486 case SND_SOC_DAIFMT_DSP_A:
9ee802ec 487 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 488 break;
489 case SND_SOC_DAIFMT_DSP_B:
9ee802ec 490 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 491 i2sctl |= SGTL5000_I2S_LRALIGN;
492 break;
493 case SND_SOC_DAIFMT_I2S:
9ee802ec 494 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 495 break;
496 case SND_SOC_DAIFMT_RIGHT_J:
9ee802ec 497 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 498 i2sctl |= SGTL5000_I2S_LRPOL;
499 break;
500 case SND_SOC_DAIFMT_LEFT_J:
9ee802ec 501 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 502 i2sctl |= SGTL5000_I2S_LRALIGN;
503 break;
504 default:
505 return -EINVAL;
506 }
507
508 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
509
510 /* Clock inversion */
511 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
512 case SND_SOC_DAIFMT_NB_NF:
513 break;
514 case SND_SOC_DAIFMT_IB_NF:
515 i2sctl |= SGTL5000_I2S_SCLK_INV;
516 break;
517 default:
518 return -EINVAL;
519 }
520
521 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
522
523 return 0;
524}
525
526/* set codec sysclk */
527static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
528 int clk_id, unsigned int freq, int dir)
529{
530 struct snd_soc_codec *codec = codec_dai->codec;
531 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
532
533 switch (clk_id) {
534 case SGTL5000_SYSCLK:
535 sgtl5000->sysclk = freq;
536 break;
537 default:
538 return -EINVAL;
539 }
540
541 return 0;
542}
543
544/*
545 * set clock according to i2s frame clock,
7f6d75d7
FE		 546 * sgtl5000 provides 2 clock sources:
547 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 548 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 549 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 550 *
551 * clock setting rules:
7f6d75d7
FE		 552 * 1. in slave mode, only sys_mclk can be used
553 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
554 * and above.
555 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 556 */
557static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
558{
559 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
560 int clk_ctl = 0;
561 int sys_fs; /* sample freq */
562
563 /*
564 * sample freq should be divided by frame clock,
7f6d75d7
FE		 565 * if frame clock is lower than 44.1 kHz, sample freq should be set to
566 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 567 */
568 switch (frame_rate) {
569 case 8000:
570 case 16000:
571 sys_fs = 32000;
572 break;
573 case 11025:
574 case 22050:
575 sys_fs = 44100;
576 break;
577 default:
578 sys_fs = frame_rate;
579 break;
580 }
581
582 /* set divided factor of frame clock */
583 switch (sys_fs / frame_rate) {
584 case 4:
585 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
586 break;
587 case 2:
588 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
589 break;
590 case 1:
591 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
592 break;
593 default:
594 return -EINVAL;
595 }
596
597 /* set the sys_fs according to frame rate */
598 switch (sys_fs) {
599 case 32000:
600 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
601 break;
602 case 44100:
603 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
604 break;
605 case 48000:
606 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
607 break;
608 case 96000:
609 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
610 break;
611 default:
612 dev_err(codec->dev, "frame rate %d not supported\n",
613 frame_rate);
614 return -EINVAL;
615 }
616
617 /*
618 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 619 * factor of freq = 96 kHz can only be 256, since mclk is in the range
620 * of 8 MHz - 27 MHz
9b34e6cc 621 */
2a4cfd10 622 switch (sgtl5000->sysclk / frame_rate) {
9b34e6cc
ZZ		 623 case 256:
624 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
625 SGTL5000_MCLK_FREQ_SHIFT;
626 break;
627 case 384:
628 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
629 SGTL5000_MCLK_FREQ_SHIFT;
630 break;
631 case 512:
632 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
633 SGTL5000_MCLK_FREQ_SHIFT;
634 break;
635 default:
7f6d75d7 636 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 637 if (sgtl5000->master) {
638 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
639 SGTL5000_MCLK_FREQ_SHIFT;
640 } else {
641 dev_err(codec->dev,
642 "PLL not supported in slave mode\n");
fa558d01
FE		 643 dev_err(codec->dev, "%d ratio is not supported. "
644 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
2a4cfd10 645 sgtl5000->sysclk / frame_rate);
9b34e6cc
ZZ		 646 return -EINVAL;
647 }
648 }
649
650 /* if using pll, please check manual 6.4.2 for detail */
651 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
652 u64 out, t;
653 int div2;
654 int pll_ctl;
655 unsigned int in, int_div, frac_div;
656
657 if (sgtl5000->sysclk > 17000000) {
658 div2 = 1;
659 in = sgtl5000->sysclk / 2;
660 } else {
661 div2 = 0;
662 in = sgtl5000->sysclk;
663 }
664 if (sys_fs == 44100)
665 out = 180633600;
666 else
667 out = 196608000;
668 t = do_div(out, in);
669 int_div = out;
670 t *= 2048;
671 do_div(t, in);
672 frac_div = t;
673 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
674 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
675
676 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
677 if (div2)
678 snd_soc_update_bits(codec,
679 SGTL5000_CHIP_CLK_TOP_CTRL,
680 SGTL5000_INPUT_FREQ_DIV2,
681 SGTL5000_INPUT_FREQ_DIV2);
682 else
683 snd_soc_update_bits(codec,
684 SGTL5000_CHIP_CLK_TOP_CTRL,
685 SGTL5000_INPUT_FREQ_DIV2,
686 0);
687
688 /* power up pll */
689 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
690 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
691 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 692
693 /* if using pll, clk_ctrl must be set after pll power up */
694 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 695 } else {
e06e4c2d
OS		 696 /* otherwise, clk_ctrl must be set before pll power down */
697 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
698
9b34e6cc
ZZ		 699 /* power down pll */
700 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
701 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
702 0);
703 }
704
9b34e6cc
ZZ		 705 return 0;
706}
707
708/*
709 * Set PCM DAI bit size and sample rate.
710 * input: params_rate, params_fmt
711 */
712static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
713 struct snd_pcm_hw_params *params,
714 struct snd_soc_dai *dai)
715{
e6968a17 716 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 717 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
718 int channels = params_channels(params);
719 int i2s_ctl = 0;
720 int stereo;
721 int ret;
722
723 /* sysclk should already set */
724 if (!sgtl5000->sysclk) {
725 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
726 return -EFAULT;
727 }
728
729 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
730 stereo = SGTL5000_DAC_STEREO;
731 else
732 stereo = SGTL5000_ADC_STEREO;
733
734 /* set mono to save power */
735 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
736 channels == 1 ? 0 : stereo);
737
738 /* set codec clock base on lrclk */
739 ret = sgtl5000_set_clock(codec, params_rate(params));
740 if (ret)
741 return ret;
742
743 /* set i2s data format */
dacc2aef
MB		 744 switch (params_width(params)) {
745 case 16:
9b34e6cc
ZZ		 746 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
747 return -EINVAL;
748 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
749 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
750 SGTL5000_I2S_SCLKFREQ_SHIFT;
751 break;
dacc2aef 752 case 20:
9b34e6cc
ZZ		 753 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
754 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
755 SGTL5000_I2S_SCLKFREQ_SHIFT;
756 break;
dacc2aef 757 case 24:
9b34e6cc
ZZ		 758 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
759 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
760 SGTL5000_I2S_SCLKFREQ_SHIFT;
761 break;
dacc2aef 762 case 32:
9b34e6cc
ZZ		 763 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
764 return -EINVAL;
765 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
766 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
767 SGTL5000_I2S_SCLKFREQ_SHIFT;
768 break;
769 default:
770 return -EINVAL;
771 }
772
33cb92cf
AL		 773 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
774 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
775 i2s_ctl);
9b34e6cc
ZZ		 776
777 return 0;
778}
779
333802e9 780#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 781static int ldo_regulator_is_enabled(struct regulator_dev *dev)
782{
783 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
784
785 return ldo->enabled;
786}
787
788static int ldo_regulator_enable(struct regulator_dev *dev)
789{
790 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
791 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
792 int reg;
793
794 if (ldo_regulator_is_enabled(dev))
795 return 0;
796
797 /* set regulator value firstly */
798 reg = (1600 - ldo->voltage / 1000) / 50;
799 reg = clamp(reg, 0x0, 0xf);
800
801 /* amend the voltage value, unit: uV */
802 ldo->voltage = (1600 - reg * 50) * 1000;
803
804 /* set voltage to register */
805 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 806 SGTL5000_LINREG_VDDD_MASK, reg);
9b34e6cc
ZZ		 807
808 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
809 SGTL5000_LINEREG_D_POWERUP,
810 SGTL5000_LINEREG_D_POWERUP);
811
7f6d75d7 812 /* when internal ldo is enabled, simple digital power can be disabled */
9b34e6cc
ZZ		 813 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
814 SGTL5000_LINREG_SIMPLE_POWERUP,
815 0);
816
817 ldo->enabled = 1;
818 return 0;
819}
820
821static int ldo_regulator_disable(struct regulator_dev *dev)
822{
823 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
824 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
825
826 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
827 SGTL5000_LINEREG_D_POWERUP,
828 0);
829
830 /* clear voltage info */
831 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 832 SGTL5000_LINREG_VDDD_MASK, 0);
9b34e6cc
ZZ		 833
834 ldo->enabled = 0;
835
836 return 0;
837}
838
839static int ldo_regulator_get_voltage(struct regulator_dev *dev)
840{
841 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
842
843 return ldo->voltage;
844}
845
846static struct regulator_ops ldo_regulator_ops = {
847 .is_enabled = ldo_regulator_is_enabled,
848 .enable = ldo_regulator_enable,
849 .disable = ldo_regulator_disable,
850 .get_voltage = ldo_regulator_get_voltage,
851};
852
853static int ldo_regulator_register(struct snd_soc_codec *codec,
854 struct regulator_init_data *init_data,
855 int voltage)
856{
857 struct ldo_regulator *ldo;
5b13de7a 858 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
c172708d 859 struct regulator_config config = { };
9b34e6cc
ZZ		 860
861 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
862
be813334 863 if (!ldo)
9b34e6cc 864 return -ENOMEM;
9b34e6cc
ZZ		 865
866 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
867 if (!ldo->desc.name) {
868 kfree(ldo);
869 dev_err(codec->dev, "failed to allocate decs name memory\n");
870 return -ENOMEM;
871 }
872
873 ldo->desc.type = REGULATOR_VOLTAGE;
874 ldo->desc.owner = THIS_MODULE;
875 ldo->desc.ops = &ldo_regulator_ops;
876 ldo->desc.n_voltages = 1;
877
878 ldo->codec_data = codec;
879 ldo->voltage = voltage;
880
c172708d
MB		 881 config.dev = codec->dev;
882 config.driver_data = ldo;
883 config.init_data = init_data;
884
885 ldo->dev = regulator_register(&ldo->desc, &config);
9b34e6cc 886 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 887 int ret = PTR_ERR(ldo->dev);
888
9b34e6cc
ZZ		 889 dev_err(codec->dev, "failed to register regulator\n");
890 kfree(ldo->desc.name);
891 kfree(ldo);
892
62f75aaf 893 return ret;
9b34e6cc 894 }
5b13de7a 895 sgtl5000->ldo = ldo;
9b34e6cc
ZZ		 896
897 return 0;
898}
899
900static int ldo_regulator_remove(struct snd_soc_codec *codec)
901{
902 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
903 struct ldo_regulator *ldo = sgtl5000->ldo;
904
905 if (!ldo)
906 return 0;
907
908 regulator_unregister(ldo->dev);
909 kfree(ldo->desc.name);
910 kfree(ldo);
911
912 return 0;
913}
333802e9
MB		 914#else
915static int ldo_regulator_register(struct snd_soc_codec *codec,
916 struct regulator_init_data *init_data,
917 int voltage)
918{
09bddc8e 919 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 920 return -EINVAL;
921}
922
923static int ldo_regulator_remove(struct snd_soc_codec *codec)
924{
925 return 0;
926}
927#endif
9b34e6cc
ZZ		 928
929/*
930 * set dac bias
931 * common state changes:
932 * startup:
933 * off --> standby --> prepare --> on
934 * standby --> prepare --> on
935 *
936 * stop:
937 * on --> prepare --> standby
938 */
939static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
940 enum snd_soc_bias_level level)
941{
942 int ret;
943 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
944
945 switch (level) {
946 case SND_SOC_BIAS_ON:
947 case SND_SOC_BIAS_PREPARE:
948 break;
949 case SND_SOC_BIAS_STANDBY:
8533eb24 950 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
9b34e6cc
ZZ		 951 ret = regulator_bulk_enable(
952 ARRAY_SIZE(sgtl5000->supplies),
953 sgtl5000->supplies);
954 if (ret)
955 return ret;
956 udelay(10);
2bdc1bb2
MB		 957
958 regcache_cache_only(sgtl5000->regmap, false);
959
960 ret = regcache_sync(sgtl5000->regmap);
961 if (ret != 0) {
962 dev_err(codec->dev,
963 "Failed to restore cache: %d\n", ret);
964
965 regcache_cache_only(sgtl5000->regmap, true);
966 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
967 sgtl5000->supplies);
968
969 return ret;
970 }
9b34e6cc
ZZ		 971 }
972
973 break;
974 case SND_SOC_BIAS_OFF:
2bdc1bb2 975 regcache_cache_only(sgtl5000->regmap, true);
9b34e6cc
ZZ		 976 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
977 sgtl5000->supplies);
978 break;
979 }
980
9b34e6cc
ZZ		 981 return 0;
982}
983
984#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
985 SNDRV_PCM_FMTBIT_S20_3LE |\
986 SNDRV_PCM_FMTBIT_S24_LE |\
987 SNDRV_PCM_FMTBIT_S32_LE)
988
85e7652d 989static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 990 .hw_params = sgtl5000_pcm_hw_params,
991 .digital_mute = sgtl5000_digital_mute,
992 .set_fmt = sgtl5000_set_dai_fmt,
993 .set_sysclk = sgtl5000_set_dai_sysclk,
994};
995
996static struct snd_soc_dai_driver sgtl5000_dai = {
997 .name = "sgtl5000",
998 .playback = {
999 .stream_name = "Playback",
1000 .channels_min = 1,
1001 .channels_max = 2,
1002 /*
1003 * only support 8~48K + 96K,
1004 * TODO modify hw_param to support more
1005 */
1006 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1007 .formats = SGTL5000_FORMATS,
1008 },
1009 .capture = {
1010 .stream_name = "Capture",
1011 .channels_min = 1,
1012 .channels_max = 2,
1013 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1014 .formats = SGTL5000_FORMATS,
1015 },
1016 .ops = &sgtl5000_ops,
1017 .symmetric_rates = 1,
1018};
1019
e5d80e82 1020static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 1021{
1022 switch (reg) {
1023 case SGTL5000_CHIP_ID:
1024 case SGTL5000_CHIP_ADCDAC_CTRL:
1025 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 1026 return true;
9b34e6cc
ZZ		 1027 }
1028
e5d80e82
FE		 1029 return false;
1030}
1031
1032static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1033{
1034 switch (reg) {
1035 case SGTL5000_CHIP_ID:
1036 case SGTL5000_CHIP_DIG_POWER:
1037 case SGTL5000_CHIP_CLK_CTRL:
1038 case SGTL5000_CHIP_I2S_CTRL:
1039 case SGTL5000_CHIP_SSS_CTRL:
1040 case SGTL5000_CHIP_ADCDAC_CTRL:
1041 case SGTL5000_CHIP_DAC_VOL:
1042 case SGTL5000_CHIP_PAD_STRENGTH:
1043 case SGTL5000_CHIP_ANA_ADC_CTRL:
1044 case SGTL5000_CHIP_ANA_HP_CTRL:
1045 case SGTL5000_CHIP_ANA_CTRL:
1046 case SGTL5000_CHIP_LINREG_CTRL:
1047 case SGTL5000_CHIP_REF_CTRL:
1048 case SGTL5000_CHIP_MIC_CTRL:
1049 case SGTL5000_CHIP_LINE_OUT_CTRL:
1050 case SGTL5000_CHIP_LINE_OUT_VOL:
1051 case SGTL5000_CHIP_ANA_POWER:
1052 case SGTL5000_CHIP_PLL_CTRL:
1053 case SGTL5000_CHIP_CLK_TOP_CTRL:
1054 case SGTL5000_CHIP_ANA_STATUS:
1055 case SGTL5000_CHIP_SHORT_CTRL:
1056 case SGTL5000_CHIP_ANA_TEST2:
1057 case SGTL5000_DAP_CTRL:
1058 case SGTL5000_DAP_PEQ:
1059 case SGTL5000_DAP_BASS_ENHANCE:
1060 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1061 case SGTL5000_DAP_AUDIO_EQ:
1062 case SGTL5000_DAP_SURROUND:
1063 case SGTL5000_DAP_FLT_COEF_ACCESS:
1064 case SGTL5000_DAP_COEF_WR_B0_MSB:
1065 case SGTL5000_DAP_COEF_WR_B0_LSB:
1066 case SGTL5000_DAP_EQ_BASS_BAND0:
1067 case SGTL5000_DAP_EQ_BASS_BAND1:
1068 case SGTL5000_DAP_EQ_BASS_BAND2:
1069 case SGTL5000_DAP_EQ_BASS_BAND3:
1070 case SGTL5000_DAP_EQ_BASS_BAND4:
1071 case SGTL5000_DAP_MAIN_CHAN:
1072 case SGTL5000_DAP_MIX_CHAN:
1073 case SGTL5000_DAP_AVC_CTRL:
1074 case SGTL5000_DAP_AVC_THRESHOLD:
1075 case SGTL5000_DAP_AVC_ATTACK:
1076 case SGTL5000_DAP_AVC_DECAY:
1077 case SGTL5000_DAP_COEF_WR_B1_MSB:
1078 case SGTL5000_DAP_COEF_WR_B1_LSB:
1079 case SGTL5000_DAP_COEF_WR_B2_MSB:
1080 case SGTL5000_DAP_COEF_WR_B2_LSB:
1081 case SGTL5000_DAP_COEF_WR_A1_MSB:
1082 case SGTL5000_DAP_COEF_WR_A1_LSB:
1083 case SGTL5000_DAP_COEF_WR_A2_MSB:
1084 case SGTL5000_DAP_COEF_WR_A2_LSB:
1085 return true;
1086
1087 default:
1088 return false;
1089 }
9b34e6cc
ZZ		 1090}
1091
1f39d939
AS		 1092/*
1093 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1094 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1095 * The calculatation was done for all possible register values which
1096 * is the array index and the following formula: 10^((idx−15)/40) * 100
1097 */
1098static const u8 vol_quot_table[] = {
1099 42, 45, 47, 50, 53, 56, 60, 63,
1100 67, 71, 75, 79, 84, 89, 94, 100,
1101 106, 112, 119, 126, 133, 141, 150, 158,
1102 168, 178, 188, 200, 211, 224, 237, 251
1103};
1104
9b34e6cc
ZZ		 1105/*
1106 * sgtl5000 has 3 internal power supplies:
1107 * 1. VAG, normally set to vdda/2
7f6d75d7 1108 * 2. charge pump, set to different value
9b34e6cc
ZZ		 1109 * according to voltage of vdda and vddio
1110 * 3. line out VAG, normally set to vddio/2
1111 *
1112 * and should be set according to:
1113 * 1. vddd provided by external or not
1114 * 2. vdda and vddio voltage value. > 3.1v or not
1115 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1116 */
1117static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1118{
1119 int vddd;
1120 int vdda;
1121 int vddio;
1122 u16 ana_pwr;
1123 u16 lreg_ctrl;
1124 int vag;
d2b7c2aa 1125 int lo_vag;
1f39d939
AS		 1126 int vol_quot;
1127 int lo_vol;
1128 size_t i;
9b34e6cc
ZZ		 1129 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1130
1131 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1132 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1133 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1134
1135 vdda = vdda / 1000;
1136 vddio = vddio / 1000;
1137 vddd = vddd / 1000;
1138
1139 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1140 dev_err(codec->dev, "regulator voltage not set correctly\n");
1141
1142 return -EINVAL;
1143 }
1144
1145 /* according to datasheet, maximum voltage of supplies */
1146 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1147 dev_err(codec->dev,
cf1ee98d 1148 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 1149 vdda, vddio, vddd);
1150
1151 return -EINVAL;
1152 }
1153
1154 /* reset value */
1155 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1156 ana_pwr |= SGTL5000_DAC_STEREO |
1157 SGTL5000_ADC_STEREO |
1158 SGTL5000_REFTOP_POWERUP;
1159 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1160
1161 if (vddio < 3100 && vdda < 3100) {
1162 /* enable internal oscillator used for charge pump */
1163 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1164 SGTL5000_INT_OSC_EN,
1165 SGTL5000_INT_OSC_EN);
1166 /* Enable VDDC charge pump */
1167 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1168 } else if (vddio >= 3100 && vdda >= 3100) {
c7d910b8 1169 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
9b34e6cc
ZZ		 1170 /* VDDC use VDDIO rail */
1171 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1172 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1173 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1174 }
1175
1176 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1177
1178 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1179
1180 /* set voltage to register */
1181 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1182 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1183
1184 /*
1185 * if vddd linear reg has been enabled,
1186 * simple digital supply should be clear to get
1187 * proper VDDD voltage.
1188 */
1189 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1190 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1191 SGTL5000_LINREG_SIMPLE_POWERUP,
1192 0);
1193 else
1194 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1195 SGTL5000_LINREG_SIMPLE_POWERUP |
1196 SGTL5000_STARTUP_POWERUP,
1197 0);
1198
1199 /*
1200 * set ADC/DAC VAG to vdda / 2,
1201 * should stay in range (0.8v, 1.575v)
1202 */
1203 vag = vdda / 2;
1204 if (vag <= SGTL5000_ANA_GND_BASE)
1205 vag = 0;
1206 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1207 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1208 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1209 else
1210 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1211
1212 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1213 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1214
1215 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
d2b7c2aa
AS		 1216 lo_vag = vddio / 2;
1217 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1218 lo_vag = 0;
1219 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
9b34e6cc 1220 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
d2b7c2aa 1221 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
9b34e6cc 1222 else
d2b7c2aa 1223 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
9b34e6cc
ZZ		 1224 SGTL5000_LINE_OUT_GND_STP;
1225
1226 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1227 SGTL5000_LINE_OUT_CURRENT_MASK |
1228 SGTL5000_LINE_OUT_GND_MASK,
d2b7c2aa 1229 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
9b34e6cc
ZZ		 1230 SGTL5000_LINE_OUT_CURRENT_360u <<
1231 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1232
1f39d939
AS		 1233 /*
1234 * Set lineout output level in range (0..31)
1235 * the same value is used for right and left channel
1236 *
1237 * Searching for a suitable index solving this formula:
1238 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1239 */
1240 vol_quot = (vag * 100) / lo_vag;
1241 lo_vol = 0;
1242 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1243 if (vol_quot >= vol_quot_table[i])
1244 lo_vol = i;
1245 else
1246 break;
1247 }
1248
1249 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1250 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1251 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1252 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1253 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1254
9b34e6cc
ZZ		 1255 return 0;
1256}
1257
e94a4062
WS		 1258static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1259{
1260 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1261 int ret;
1262
1263 /* set internal ldo to 1.2v */
1264 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1265 if (ret) {
1266 dev_err(codec->dev,
1267 "Failed to register vddd internal supplies: %d\n", ret);
1268 return ret;
1269 }
1270
1271 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1272
e94a4062
WS		 1273 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1274 return 0;
1275}
1276
9b34e6cc
ZZ		 1277static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1278{
9b34e6cc 1279 int ret;
9b34e6cc
ZZ		 1280 int i;
1281 int external_vddd = 0;
1282 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
11db0da8 1283 struct regulator *vddd;
9b34e6cc
ZZ		 1284
1285 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1286 sgtl5000->supplies[i].supply = supply_names[i];
1287
11db0da8
SG		 1288 /* External VDDD only works before revision 0x11 */
1289 if (sgtl5000->revision < 0x11) {
1290 vddd = regulator_get_optional(codec->dev, "VDDD");
1291 if (IS_ERR(vddd)) {
1292 /* See if it's just not registered yet */
1293 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1294 return -EPROBE_DEFER;
1295 } else {
1296 external_vddd = 1;
1297 regulator_put(vddd);
1298 }
1299 }
1300
1301 if (!external_vddd) {
e94a4062
WS		 1302 ret = sgtl5000_replace_vddd_with_ldo(codec);
1303 if (ret)
9b34e6cc 1304 return ret;
9b34e6cc
ZZ		 1305 }
1306
e42be7e1 1307 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
11db0da8
SG		 1308 sgtl5000->supplies);
1309 if (ret)
1310 goto err_ldo_remove;
1311
9b34e6cc
ZZ		 1312 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1313 sgtl5000->supplies);
1314 if (ret)
e42be7e1 1315 goto err_regulator_free;
9b34e6cc
ZZ		 1316
1317 /* wait for all power rails bring up */
1318 udelay(10);
1319
9b34e6cc
ZZ		 1320 return 0;
1321
e42be7e1
FE		 1322err_regulator_free:
1323 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1324 sgtl5000->supplies);
11db0da8
SG		 1325err_ldo_remove:
1326 if (!external_vddd)
9b34e6cc
ZZ		 1327 ldo_regulator_remove(codec);
1328 return ret;
1329
1330}
1331
1332static int sgtl5000_probe(struct snd_soc_codec *codec)
1333{
1334 int ret;
1335 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1336
9b34e6cc
ZZ		 1337 ret = sgtl5000_enable_regulators(codec);
1338 if (ret)
1339 return ret;
1340
1341 /* power up sgtl5000 */
1342 ret = sgtl5000_set_power_regs(codec);
1343 if (ret)
1344 goto err;
1345
1346 /* enable small pop, introduce 400ms delay in turning off */
1347 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
c251ea7b 1348 SGTL5000_SMALL_POP, 1);
9b34e6cc
ZZ		 1349
1350 /* disable short cut detector */
1351 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1352
1353 /*
1354 * set i2s as default input of sound switch
1355 * TODO: add sound switch to control and dapm widge.
1356 */
1357 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1358 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1359 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1360 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1361
1362 /* enable dac volume ramp by default */
1363 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1364 SGTL5000_DAC_VOL_RAMP_EN |
1365 SGTL5000_DAC_MUTE_RIGHT |
1366 SGTL5000_DAC_MUTE_LEFT);
1367
1368 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1369
1370 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1371 SGTL5000_HP_ZCD_EN |
1372 SGTL5000_ADC_ZCD_EN);
1373
bd0593f5
JMH		 1374 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1375 SGTL5000_BIAS_R_MASK,
1376 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc 1377
87357797
JMH		 1378 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1379 SGTL5000_BIAS_R_MASK,
1380 sgtl5000->micbias_voltage << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 1381 /*
1382 * disable DAP
1383 * TODO:
1384 * Enable DAP in kcontrol and dapm.
1385 */
1386 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1387
9b34e6cc
ZZ		 1388 return 0;
1389
1390err:
1391 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1392 sgtl5000->supplies);
e42be7e1
FE		 1393 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1394 sgtl5000->supplies);
9b34e6cc
ZZ		 1395 ldo_regulator_remove(codec);
1396
1397 return ret;
1398}
1399
1400static int sgtl5000_remove(struct snd_soc_codec *codec)
1401{
1402 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1403
9b34e6cc
ZZ		 1404 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1405 sgtl5000->supplies);
e42be7e1
FE		 1406 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1407 sgtl5000->supplies);
9b34e6cc
ZZ		 1408 ldo_regulator_remove(codec);
1409
1410 return 0;
1411}
1412
61a142b7 1413static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1414 .probe = sgtl5000_probe,
1415 .remove = sgtl5000_remove,
9b34e6cc 1416 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1417 .suspend_bias_off = true,
89989637
FE		 1418 .controls = sgtl5000_snd_controls,
1419 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1420 .dapm_widgets = sgtl5000_dapm_widgets,
1421 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1422 .dapm_routes = sgtl5000_dapm_routes,
1423 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1424};
1425
e5d80e82
FE		 1426static const struct regmap_config sgtl5000_regmap = {
1427 .reg_bits = 16,
1428 .val_bits = 16,
cb23e852 1429 .reg_stride = 2,
e5d80e82
FE		 1430
1431 .max_register = SGTL5000_MAX_REG_OFFSET,
1432 .volatile_reg = sgtl5000_volatile,
1433 .readable_reg = sgtl5000_readable,
1434
1435 .cache_type = REGCACHE_RBTREE,
1436 .reg_defaults = sgtl5000_reg_defaults,
1437 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1438};
1439
af8ee112
FE		 1440/*
1441 * Write all the default values from sgtl5000_reg_defaults[] array into the
1442 * sgtl5000 registers, to make sure we always start with the sane registers
1443 * values as stated in the datasheet.
1444 *
1445 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1446 * we follow this approach to guarantee we always start from the default values
1447 * and avoid problems like, not being able to probe after an audio playback
1448 * followed by a system reset or a 'reboot' command in Linux
1449 */
1450static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1451{
1452 int i, ret, val, index;
1453
1454 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1455 val = sgtl5000_reg_defaults[i].def;
1456 index = sgtl5000_reg_defaults[i].reg;
1457 ret = regmap_write(sgtl5000->regmap, index, val);
1458 if (ret)
1459 return ret;
1460 }
1461
1462 return 0;
1463}
1464
7a79e94e
BP		 1465static int sgtl5000_i2c_probe(struct i2c_client *client,
1466 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1467{
1468 struct sgtl5000_priv *sgtl5000;
b871f1ad 1469 int ret, reg, rev;
bd0593f5
JMH		 1470 struct device_node *np = client->dev.of_node;
1471 u32 value;
9b34e6cc 1472
3f7256fe 1473 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
9b34e6cc
ZZ		 1474 if (!sgtl5000)
1475 return -ENOMEM;
1476
e5d80e82
FE		 1477 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1478 if (IS_ERR(sgtl5000->regmap)) {
1479 ret = PTR_ERR(sgtl5000->regmap);
1480 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1481 return ret;
1482 }
1483
9e13f345
FE		 1484 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1485 if (IS_ERR(sgtl5000->mclk)) {
1486 ret = PTR_ERR(sgtl5000->mclk);
1487 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1488 /* Defer the probe to see if the clk will be provided later */
1489 if (ret == -ENOENT)
1490 return -EPROBE_DEFER;
9e13f345
FE		 1491 return ret;
1492 }
1493
1494 ret = clk_prepare_enable(sgtl5000->mclk);
1495 if (ret)
1496 return ret;
1497
58cc9c9a
EN		 1498 /* Need 8 clocks before I2C accesses */
1499 udelay(1);
1500
b871f1ad
FE		 1501 /* read chip information */
1502 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1503 if (ret)
9e13f345 1504 goto disable_clk;
b871f1ad
FE		 1505
1506 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1507 SGTL5000_PARTID_PART_ID) {
1508 dev_err(&client->dev,
1509 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1510 ret = -ENODEV;
1511 goto disable_clk;
b871f1ad
FE		 1512 }
1513
1514 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1515 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1516 sgtl5000->revision = rev;
b871f1ad 1517
bd0593f5
JMH		 1518 if (np) {
1519 if (!of_property_read_u32(np,
1520 "micbias-resistor-k-ohms", &value)) {
1521 switch (value) {
1522 case SGTL5000_MICBIAS_OFF:
1523 sgtl5000->micbias_resistor = 0;
1524 break;
1525 case SGTL5000_MICBIAS_2K:
1526 sgtl5000->micbias_resistor = 1;
1527 break;
1528 case SGTL5000_MICBIAS_4K:
1529 sgtl5000->micbias_resistor = 2;
1530 break;
1531 case SGTL5000_MICBIAS_8K:
1532 sgtl5000->micbias_resistor = 3;
1533 break;
1534 default:
1535 sgtl5000->micbias_resistor = 2;
1536 dev_err(&client->dev,
1537 "Unsuitable MicBias resistor\n");
1538 }
1539 } else {
1540 /* default is 4Kohms */
1541 sgtl5000->micbias_resistor = 2;
1542 }
87357797
JMH		 1543 if (!of_property_read_u32(np,
1544 "micbias-voltage-m-volts", &value)) {
1545 /* 1250mV => 0 */
1546 /* steps of 250mV */
1547 if ((value >= 1250) && (value <= 3000))
1548 sgtl5000->micbias_voltage = (value / 250) - 5;
1549 else {
1550 sgtl5000->micbias_voltage = 0;
bd0593f5
JMH		 1551 dev_err(&client->dev,
1552 "Unsuitable MicBias resistor\n");
1553 }
1554 } else {
87357797 1555 sgtl5000->micbias_voltage = 0;
bd0593f5
JMH		 1556 }
1557 }
1558
9b34e6cc
ZZ		 1559 i2c_set_clientdata(client, sgtl5000);
1560
af8ee112
FE		 1561 /* Ensure sgtl5000 will start with sane register values */
1562 ret = sgtl5000_fill_defaults(sgtl5000);
1563 if (ret)
9e13f345 1564 goto disable_clk;
af8ee112 1565
9b34e6cc
ZZ		 1566 ret = snd_soc_register_codec(&client->dev,
1567 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1568 if (ret)
1569 goto disable_clk;
1570
1571 return 0;
1572
1573disable_clk:
1574 clk_disable_unprepare(sgtl5000->mclk);
512fa7c4 1575 return ret;
9b34e6cc
ZZ		 1576}
1577
7a79e94e 1578static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1579{
7c647af4 1580 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1581
9e13f345
FE		 1582 snd_soc_unregister_codec(&client->dev);
1583 clk_disable_unprepare(sgtl5000->mclk);
9b34e6cc
ZZ		 1584 return 0;
1585}
1586
1587static const struct i2c_device_id sgtl5000_id[] = {
1588 {"sgtl5000", 0},
1589 {},
1590};
1591
1592MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1593
58e49424
SG		 1594static const struct of_device_id sgtl5000_dt_ids[] = {
1595 { .compatible = "fsl,sgtl5000", },
1596 { /* sentinel */ }
1597};
4c54c6de 1598MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1599
9b34e6cc
ZZ		 1600static struct i2c_driver sgtl5000_i2c_driver = {
1601 .driver = {
1602 .name = "sgtl5000",
58e49424 1603 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1604 },
1605 .probe = sgtl5000_i2c_probe,
7a79e94e 1606 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1607 .id_table = sgtl5000_id,
1608};
1609
67d45090 1610module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1611
1612MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1613MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1614MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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