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5df7f71d DM |
1 | /* |
2 | * tas2552.h - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Author: Dan Murphy <dmurphy@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | */ | |
17 | ||
18 | #ifndef __TAS2552_H__ | |
19 | #define __TAS2552_H__ | |
20 | ||
21 | /* Register Address Map */ | |
4afdd89d | 22 | #define TAS2552_DEVICE_STATUS 0x00 |
5df7f71d DM |
23 | #define TAS2552_CFG_1 0x01 |
24 | #define TAS2552_CFG_2 0x02 | |
25 | #define TAS2552_CFG_3 0x03 | |
26 | #define TAS2552_DOUT 0x04 | |
27 | #define TAS2552_SER_CTRL_1 0x05 | |
28 | #define TAS2552_SER_CTRL_2 0x06 | |
29 | #define TAS2552_OUTPUT_DATA 0x07 | |
30 | #define TAS2552_PLL_CTRL_1 0x08 | |
31 | #define TAS2552_PLL_CTRL_2 0x09 | |
32 | #define TAS2552_PLL_CTRL_3 0x0a | |
33 | #define TAS2552_BTIP 0x0b | |
34 | #define TAS2552_BTS_CTRL 0x0c | |
35 | #define TAS2552_RESERVED_0D 0x0d | |
4afdd89d PU |
36 | #define TAS2552_LIMIT_RATE_HYS 0x0e |
37 | #define TAS2552_LIMIT_RELEASE 0x0f | |
38 | #define TAS2552_LIMIT_INT_COUNT 0x10 | |
5df7f71d DM |
39 | #define TAS2552_PDM_CFG 0x11 |
40 | #define TAS2552_PGA_GAIN 0x12 | |
4afdd89d | 41 | #define TAS2552_EDGE_RATE_CTRL 0x13 |
2a9dd1db | 42 | #define TAS2552_BOOST_APT_CTRL 0x14 |
5df7f71d DM |
43 | #define TAS2552_VER_NUM 0x16 |
44 | #define TAS2552_VBAT_DATA 0x19 | |
45 | #define TAS2552_MAX_REG 0x20 | |
46 | ||
47 | /* CFG1 Register Masks */ | |
7de544fd PU |
48 | #define TAS2552_DEV_RESET (1 << 0) |
49 | #define TAS2552_SWS (1 << 1) | |
50 | #define TAS2552_MUTE (1 << 2) | |
51 | #define TAS2552_PLL_SRC_MCLK (0x0 << 4) | |
52 | #define TAS2552_PLL_SRC_BCLK (0x1 << 4) | |
53 | #define TAS2552_PLL_SRC_IVCLKIN (0x2 << 4) | |
54 | #define TAS2552_PLL_SRC_1_8_FIXED (0x3 << 4) | |
55 | #define TAS2552_PLL_SRC_MASK TAS2552_PLL_SRC_1_8_FIXED | |
5df7f71d DM |
56 | |
57 | /* CFG2 Register Masks */ | |
58 | #define TAS2552_CLASSD_EN (1 << 7) | |
59 | #define TAS2552_BOOST_EN (1 << 6) | |
60 | #define TAS2552_APT_EN (1 << 5) | |
61 | #define TAS2552_PLL_ENABLE (1 << 3) | |
62 | #define TAS2552_LIM_EN (1 << 2) | |
63 | #define TAS2552_IVSENSE_EN (1 << 1) | |
64 | ||
a571cb17 PU |
65 | /* CFG3 Register Masks */ |
66 | #define TAS2552_WCLK_FREQ_8KHZ (0x0 << 0) | |
67 | #define TAS2552_WCLK_FREQ_11_12KHZ (0x1 << 0) | |
68 | #define TAS2552_WCLK_FREQ_16KHZ (0x2 << 0) | |
69 | #define TAS2552_WCLK_FREQ_22_24KHZ (0x3 << 0) | |
70 | #define TAS2552_WCLK_FREQ_32KHZ (0x4 << 0) | |
71 | #define TAS2552_WCLK_FREQ_44_48KHZ (0x5 << 0) | |
72 | #define TAS2552_WCLK_FREQ_88_96KHZ (0x6 << 0) | |
73 | #define TAS2552_WCLK_FREQ_176_192KHZ (0x7 << 0) | |
74 | #define TAS2552_WCLK_FREQ_MASK TAS2552_WCLK_FREQ_176_192KHZ | |
75 | #define TAS2552_DIN_SRC_SEL_MUTED (0x0 << 3) | |
76 | #define TAS2552_DIN_SRC_SEL_LEFT (0x1 << 3) | |
77 | #define TAS2552_DIN_SRC_SEL_RIGHT (0x2 << 3) | |
78 | #define TAS2552_DIN_SRC_SEL_AVG_L_R (0x3 << 3) | |
79 | #define TAS2552_PDM_IN_SEL (1 << 5) | |
80 | #define TAS2552_I2S_OUT_SEL (1 << 6) | |
81 | #define TAS2552_ANALOG_IN_SEL (1 << 7) | |
82 | ||
3f747a81 PU |
83 | /* DOUT Register Masks */ |
84 | #define TAS2552_SDOUT_TRISTATE (1 << 2) | |
85 | ||
1b68c7dc | 86 | /* Serial Interface Control Register Masks */ |
d20b098d PU |
87 | #define TAS2552_WORDLENGTH_16BIT (0x0 << 0) |
88 | #define TAS2552_WORDLENGTH_20BIT (0x1 << 0) | |
89 | #define TAS2552_WORDLENGTH_24BIT (0x2 << 0) | |
90 | #define TAS2552_WORDLENGTH_32BIT (0x3 << 0) | |
91 | #define TAS2552_WORDLENGTH_MASK TAS2552_WORDLENGTH_32BIT | |
1b68c7dc PU |
92 | #define TAS2552_DATAFORMAT_I2S (0x0 << 2) |
93 | #define TAS2552_DATAFORMAT_DSP (0x1 << 2) | |
94 | #define TAS2552_DATAFORMAT_RIGHT_J (0x2 << 2) | |
95 | #define TAS2552_DATAFORMAT_LEFT_J (0x3 << 2) | |
96 | #define TAS2552_DATAFORMAT_MASK TAS2552_DATAFORMAT_LEFT_J | |
d20b098d PU |
97 | #define TAS2552_CLKSPERFRAME_32 (0x0 << 4) |
98 | #define TAS2552_CLKSPERFRAME_64 (0x1 << 4) | |
99 | #define TAS2552_CLKSPERFRAME_128 (0x2 << 4) | |
100 | #define TAS2552_CLKSPERFRAME_256 (0x3 << 4) | |
101 | #define TAS2552_CLKSPERFRAME_MASK TAS2552_CLKSPERFRAME_256 | |
1b68c7dc PU |
102 | #define TAS2552_BCLKDIR (1 << 6) |
103 | #define TAS2552_WCLKDIR (1 << 7) | |
5df7f71d | 104 | |
5df7f71d | 105 | /* OUTPUT_DATA register */ |
b2822f19 PU |
106 | #define TAS2552_DATA_OUT_I_DATA (0x0) |
107 | #define TAS2552_DATA_OUT_V_DATA (0x1) | |
108 | #define TAS2552_DATA_OUT_VBAT_DATA (0x2) | |
109 | #define TAS2552_DATA_OUT_VBOOST_DATA (0x3) | |
110 | #define TAS2552_DATA_OUT_PGA_GAIN (0x4) | |
111 | #define TAS2552_DATA_OUT_IV_DATA (0x5) | |
112 | #define TAS2552_DATA_OUT_VBAT_VBOOST_GAIN (0x6) | |
113 | #define TAS2552_DATA_OUT_DISABLED (0x7) | |
114 | #define TAS2552_L_DATA_OUT(x) ((x) << 0) | |
115 | #define TAS2552_R_DATA_OUT(x) ((x) << 3) | |
116 | #define TAS2552_PDM_DATA_SEL_I (0x0 << 6) | |
117 | #define TAS2552_PDM_DATA_SEL_V (0x1 << 6) | |
118 | #define TAS2552_PDM_DATA_SEL_I_V (0x2 << 6) | |
119 | #define TAS2552_PDM_DATA_SEL_V_I (0x3 << 6) | |
120 | #define TAS2552_PDM_DATA_SEL_MASK TAS2552_PDM_DATA_SEL_V_I | |
5df7f71d DM |
121 | |
122 | /* PDM CFG Register */ | |
89683fde PU |
123 | #define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0) |
124 | #define TAS2552_PDM_CLK_SEL_IVCLKIN (0x1 << 0) | |
125 | #define TAS2552_PDM_CLK_SEL_BCLK (0x2 << 0) | |
126 | #define TAS2552_PDM_CLK_SEL_MCLK (0x3 << 0) | |
127 | #define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK | |
128 | #define TAS2552_PDM_DATA_ES (1 << 2) | |
5df7f71d | 129 | |
2a9dd1db PU |
130 | /* Boost Auto-pass through register */ |
131 | #define TAS2552_APT_DELAY_50 (0x0 << 0) | |
132 | #define TAS2552_APT_DELAY_75 (0x1 << 0) | |
133 | #define TAS2552_APT_DELAY_125 (0x2 << 0) | |
134 | #define TAS2552_APT_DELAY_200 (0x3 << 0) | |
135 | #define TAS2552_APT_THRESH_05_02 (0x0 << 2) | |
136 | #define TAS2552_APT_THRESH_10_07 (0x1 << 2) | |
137 | #define TAS2552_APT_THRESH_14_11 (0x2 << 2) | |
138 | #define TAS2552_APT_THRESH_20_17 (0x3 << 2) | |
5df7f71d DM |
139 | |
140 | /* PLL Control Register */ | |
1014f7ef PU |
141 | #define TAS2552_PLL_J_MASK 0x7f |
142 | #define TAS2552_PLL_D_UPPER(x) (((x) >> 8) & 0x3f) | |
143 | #define TAS2552_PLL_D_LOWER(x) ((x) & 0xff) | |
144 | #define TAS2552_PLL_BYPASS (1 << 7) | |
5df7f71d DM |
145 | |
146 | #endif |