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ASoC: tas5086: add DAPM mux controls
[deliverable/linux.git] / sound / soc / codecs / tas5086.c
CommitLineData
4fa89346
DM		 1/*
2 * TAS5086 ASoC codec driver
3 *
4 * Copyright (c) 2013 Daniel Mack <zonque@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * TODO:
17 * - implement DAPM and input muxing
18 * - implement modulation limit
19 * - implement non-default PWM start
20 *
21 * Note that this chip has a very unusual register layout, specifically
22 * because the registers are of unequal size, and multi-byte registers
23 * require bulk writes to take effect. Regmap does not support that kind
24 * of devices.
25 *
26 * Currently, the driver does not touch any of the registers >= 0x20, so
27 * it doesn't matter because the entire map can be accessed as 8-bit
28 * array. In case more features will be added in the future
29 * that require access to higher registers, the entire regmap H/W I/O
30 * routines have to be open-coded.
31 */
32
33#include <linux/module.h>
34#include <linux/slab.h>
35#include <linux/delay.h>
36#include <linux/gpio.h>
37#include <linux/i2c.h>
38#include <linux/regmap.h>
39#include <linux/spi/spi.h>
40#include <linux/of_device.h>
41#include <linux/of_gpio.h>
42#include <sound/pcm.h>
43#include <sound/pcm_params.h>
44#include <sound/soc.h>
45#include <sound/tlv.h>
46#include <sound/tas5086.h>
47
48#define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
49 SNDRV_PCM_FMTBIT_S20_3LE | \
50 SNDRV_PCM_FMTBIT_S24_3LE)
51
52#define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
53 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
54 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
55 SNDRV_PCM_RATE_192000)
56
57/*
58 * TAS5086 registers
59 */
60#define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */
61#define TAS5086_CLOCK_RATE(val) (val << 5)
62#define TAS5086_CLOCK_RATE_MASK (0x7 << 5)
63#define TAS5086_CLOCK_RATIO(val) (val << 2)
64#define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
65#define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
66#define TAS5086_CLOCK_VALID (1 << 0)
67
68#define TAS5086_DEEMPH_MASK 0x03
69#define TAS5086_SOFT_MUTE_ALL 0x3f
70
71#define TAS5086_DEV_ID 0x01 /* Device ID register */
72#define TAS5086_ERROR_STATUS 0x02 /* Error status register */
73#define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */
74#define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */
75#define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
76#define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */
77#define TAS5086_MASTER_VOL 0x07 /* Master volume */
78#define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
79#define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */
80#define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */
81#define TAS5086_PWM_START 0x18 /* PWM start register */
82#define TAS5086_SURROUND 0x19 /* Surround register */
83#define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */
84#define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */
85#define TAS5086_BKNDERR 0x1c
8892d479
DM		 86#define TAS5086_INPUT_MUX 0x20
87#define TAS5086_PWM_OUTPUT_MUX 0x25
88
89#define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX
4fa89346
DM		 90
91/*
92 * Default TAS5086 power-up configuration
93 */
94static const struct reg_default tas5086_reg_defaults[] = {
95 { 0x00, 0x6c },
96 { 0x01, 0x03 },
97 { 0x02, 0x00 },
98 { 0x03, 0xa0 },
99 { 0x04, 0x05 },
100 { 0x05, 0x60 },
101 { 0x06, 0x00 },
102 { 0x07, 0xff },
103 { 0x08, 0x30 },
104 { 0x09, 0x30 },
105 { 0x0a, 0x30 },
106 { 0x0b, 0x30 },
107 { 0x0c, 0x30 },
108 { 0x0d, 0x30 },
109 { 0x0e, 0xb1 },
110 { 0x0f, 0x00 },
111 { 0x10, 0x02 },
112 { 0x11, 0x00 },
113 { 0x12, 0x00 },
114 { 0x13, 0x00 },
115 { 0x14, 0x00 },
116 { 0x15, 0x00 },
117 { 0x16, 0x00 },
118 { 0x17, 0x00 },
119 { 0x18, 0x3f },
120 { 0x19, 0x00 },
121 { 0x1a, 0x18 },
122 { 0x1b, 0x82 },
123 { 0x1c, 0x05 },
124};
125
6b36d370
DM		 126static int tas5086_register_size(struct device *dev, unsigned int reg)
127{
128 switch (reg) {
129 case TAS5086_DEV_ID ... TAS5086_BKNDERR:
130 return 1;
8892d479
DM		 131 case TAS5086_INPUT_MUX:
132 case TAS5086_PWM_OUTPUT_MUX:
133 return 4;
6b36d370
DM		 134 }
135
136 dev_err(dev, "Unsupported register address: %d\n", reg);
137 return 0;
138}
139
4fa89346
DM		 140static bool tas5086_accessible_reg(struct device *dev, unsigned int reg)
141{
8892d479
DM		 142 switch (reg) {
143 case 0x0f:
144 case 0x11 ... 0x17:
145 case 0x1d ... 0x1f:
146 return false;
147 default:
148 return true;
149 }
4fa89346
DM		 150}
151
152static bool tas5086_volatile_reg(struct device *dev, unsigned int reg)
153{
154 switch (reg) {
155 case TAS5086_DEV_ID:
156 case TAS5086_ERROR_STATUS:
157 return true;
158 }
159
160 return false;
161}
162
163static bool tas5086_writeable_reg(struct device *dev, unsigned int reg)
164{
165 return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID);
166}
167
6b36d370
DM		 168static int tas5086_reg_write(void *context, unsigned int reg,
169 unsigned int value)
170{
171 struct i2c_client *client = context;
172 unsigned int i, size;
173 uint8_t buf[5];
174 int ret;
175
176 size = tas5086_register_size(&client->dev, reg);
177 if (size == 0)
178 return -EINVAL;
179
180 buf[0] = reg;
181
182 for (i = size; i >= 1; --i) {
183 buf[i] = value;
184 value >>= 8;
185 }
186
187 ret = i2c_master_send(client, buf, size + 1);
188 if (ret == size + 1)
189 return 0;
190 else if (ret < 0)
191 return ret;
192 else
193 return -EIO;
194}
195
196static int tas5086_reg_read(void *context, unsigned int reg,
197 unsigned int *value)
198{
199 struct i2c_client *client = context;
200 uint8_t send_buf, recv_buf[4];
201 struct i2c_msg msgs[2];
202 unsigned int size;
203 unsigned int i;
204 int ret;
205
206 size = tas5086_register_size(&client->dev, reg);
207 if (size == 0)
208 return -EINVAL;
209
210 send_buf = reg;
211
212 msgs[0].addr = client->addr;
213 msgs[0].len = sizeof(send_buf);
214 msgs[0].buf = &send_buf;
215 msgs[0].flags = 0;
216
217 msgs[1].addr = client->addr;
218 msgs[1].len = size;
219 msgs[1].buf = recv_buf;
220 msgs[1].flags = I2C_M_RD;
221
222 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
223 if (ret < 0)
224 return ret;
225 else if (ret != ARRAY_SIZE(msgs))
226 return -EIO;
227
228 *value = 0;
229
230 for (i = 0; i < size; i++) {
231 *value <<= 8;
232 *value |= recv_buf[i];
233 }
234
235 return 0;
236}
237
4fa89346
DM		 238struct tas5086_private {
239 struct regmap *regmap;
240 unsigned int mclk, sclk;
241 unsigned int format;
242 bool deemph;
243 /* Current sample rate for de-emphasis control */
244 int rate;
245 /* GPIO driving Reset pin, if any */
246 int gpio_nreset;
247};
248
249static int tas5086_deemph[] = { 0, 32000, 44100, 48000 };
250
251static int tas5086_set_deemph(struct snd_soc_codec *codec)
252{
253 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
254 int i, val = 0;
255
256 if (priv->deemph)
257 for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++)
258 if (tas5086_deemph[i] == priv->rate)
259 val = i;
260
261 return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1,
262 TAS5086_DEEMPH_MASK, val);
263}
264
265static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
266 struct snd_ctl_elem_value *ucontrol)
267{
268 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
269 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
270
271 ucontrol->value.enumerated.item[0] = priv->deemph;
272
273 return 0;
274}
275
276static int tas5086_put_deemph(struct snd_kcontrol *kcontrol,
277 struct snd_ctl_elem_value *ucontrol)
278{
279 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
280 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
281
282 priv->deemph = ucontrol->value.enumerated.item[0];
283
284 return tas5086_set_deemph(codec);
285}
286
287
288static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai,
289 int clk_id, unsigned int freq, int dir)
290{
291 struct snd_soc_codec *codec = codec_dai->codec;
292 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
293
294 switch (clk_id) {
295 case TAS5086_CLK_IDX_MCLK:
296 priv->mclk = freq;
297 break;
298 case TAS5086_CLK_IDX_SCLK:
299 priv->sclk = freq;
300 break;
301 }
302
303 return 0;
304}
305
306static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai,
307 unsigned int format)
308{
309 struct snd_soc_codec *codec = codec_dai->codec;
310 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
311
312 /* The TAS5086 can only be slave to all clocks */
313 if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
314 dev_err(codec->dev, "Invalid clocking mode\n");
315 return -EINVAL;
316 }
317
318 /* we need to refer to the data format from hw_params() */
319 priv->format = format;
320
321 return 0;
322}
323
324static const int tas5086_sample_rates[] = {
325 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000
326};
327
328static const int tas5086_ratios[] = {
329 64, 128, 192, 256, 384, 512
330};
331
332static int index_in_array(const int *array, int len, int needle)
333{
334 int i;
335
336 for (i = 0; i < len; i++)
337 if (array[i] == needle)
338 return i;
339
340 return -ENOENT;
341}
342
343static int tas5086_hw_params(struct snd_pcm_substream *substream,
344 struct snd_pcm_hw_params *params,
345 struct snd_soc_dai *dai)
346{
347 struct snd_soc_codec *codec = dai->codec;
348 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
28dbd161 349 int val;
4fa89346
DM		 350 int ret;
351
352 priv->rate = params_rate(params);
353
354 /* Look up the sample rate and refer to the offset in the list */
355 val = index_in_array(tas5086_sample_rates,
356 ARRAY_SIZE(tas5086_sample_rates), priv->rate);
357
358 if (val < 0) {
359 dev_err(codec->dev, "Invalid sample rate\n");
360 return -EINVAL;
361 }
362
363 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
364 TAS5086_CLOCK_RATE_MASK,
365 TAS5086_CLOCK_RATE(val));
366 if (ret < 0)
367 return ret;
368
369 /* MCLK / Fs ratio */
370 val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios),
371 priv->mclk / priv->rate);
372 if (val < 0) {
373 dev_err(codec->dev, "Inavlid MCLK / Fs ratio\n");
374 return -EINVAL;
375 }
376
377 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
378 TAS5086_CLOCK_RATIO_MASK,
379 TAS5086_CLOCK_RATIO(val));
380 if (ret < 0)
381 return ret;
382
383
384 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
385 TAS5086_CLOCK_SCLK_RATIO_48,
386 (priv->sclk == 48 * priv->rate) ?
387 TAS5086_CLOCK_SCLK_RATIO_48 : 0);
388 if (ret < 0)
389 return ret;
390
391 /*
392 * The chip has a very unituitive register mapping and muxes information
393 * about data format and sample depth into the same register, but not on
394 * a logical bit-boundary. Hence, we have to refer to the format passed
395 * in the set_dai_fmt() callback and set up everything from here.
396 *
397 * First, determine the 'base' value, using the format ...
398 */
399 switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
400 case SND_SOC_DAIFMT_RIGHT_J:
401 val = 0x00;
402 break;
403 case SND_SOC_DAIFMT_I2S:
404 val = 0x03;
405 break;
406 case SND_SOC_DAIFMT_LEFT_J:
407 val = 0x06;
408 break;
409 default:
410 dev_err(codec->dev, "Invalid DAI format\n");
411 return -EINVAL;
412 }
413
414 /* ... then add the offset for the sample bit depth. */
415 switch (params_format(params)) {
416 case SNDRV_PCM_FORMAT_S16_LE:
417 val += 0;
418 break;
419 case SNDRV_PCM_FORMAT_S20_3LE:
420 val += 1;
421 break;
422 case SNDRV_PCM_FORMAT_S24_3LE:
423 val += 2;
424 break;
425 default:
426 dev_err(codec->dev, "Invalid bit width\n");
427 return -EINVAL;
428 };
429
430 ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val);
431 if (ret < 0)
432 return ret;
433
434 /* clock is considered valid now */
435 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
436 TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID);
437 if (ret < 0)
438 return ret;
439
440 return tas5086_set_deemph(codec);
441}
442
443static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
444{
445 struct snd_soc_codec *codec = dai->codec;
446 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
447 unsigned int val = 0;
448
449 if (mute)
450 val = TAS5086_SOFT_MUTE_ALL;
451
452 return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val);
453}
454
455/* TAS5086 controls */
456static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
457
458static const struct snd_kcontrol_new tas5086_controls[] = {
459 SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL,
460 0, 0xff, 1, tas5086_dac_tlv),
461 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
462 TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1),
463 0, 0xff, 1, tas5086_dac_tlv),
464 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
465 TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3),
466 0, 0xff, 1, tas5086_dac_tlv),
467 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
468 TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5),
469 0, 0xff, 1, tas5086_dac_tlv),
470 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
471 tas5086_get_deemph, tas5086_put_deemph),
472};
473
18710acd
DM		 474/* Input mux controls */
475static const char *tas5086_dapm_sdin_texts[] =
476{
477 "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
478 "SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
479};
480
481static const struct soc_enum tas5086_dapm_input_mux_enum[] = {
482 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts),
483 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts),
484 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts),
485 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts),
486 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts),
487 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts),
488};
489
490static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = {
491 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
492 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
493 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
494 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
495 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
496 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
497};
498
499/* Output mux controls */
500static const char *tas5086_dapm_channel_texts[] =
501 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
502 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
503
504static const struct soc_enum tas5086_dapm_output_mux_enum[] = {
505 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts),
506 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts),
507 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts),
508 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts),
509 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts),
510 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts),
511};
512
513static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = {
514 SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]),
515 SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]),
516 SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]),
517 SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]),
518 SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]),
519 SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]),
520};
521
522static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = {
523 SND_SOC_DAPM_INPUT("SDIN1-L"),
524 SND_SOC_DAPM_INPUT("SDIN1-R"),
525 SND_SOC_DAPM_INPUT("SDIN2-L"),
526 SND_SOC_DAPM_INPUT("SDIN2-R"),
527 SND_SOC_DAPM_INPUT("SDIN3-L"),
528 SND_SOC_DAPM_INPUT("SDIN3-R"),
529 SND_SOC_DAPM_INPUT("SDIN4-L"),
530 SND_SOC_DAPM_INPUT("SDIN4-R"),
531
532 SND_SOC_DAPM_OUTPUT("PWM1"),
533 SND_SOC_DAPM_OUTPUT("PWM2"),
534 SND_SOC_DAPM_OUTPUT("PWM3"),
535 SND_SOC_DAPM_OUTPUT("PWM4"),
536 SND_SOC_DAPM_OUTPUT("PWM5"),
537 SND_SOC_DAPM_OUTPUT("PWM6"),
538
539 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
540 &tas5086_dapm_input_mux_controls[0]),
541 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
542 &tas5086_dapm_input_mux_controls[1]),
543 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
544 &tas5086_dapm_input_mux_controls[2]),
545 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
546 &tas5086_dapm_input_mux_controls[3]),
547 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
548 &tas5086_dapm_input_mux_controls[4]),
549 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
550 &tas5086_dapm_input_mux_controls[5]),
551
552 SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0,
553 &tas5086_dapm_output_mux_controls[0]),
554 SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0,
555 &tas5086_dapm_output_mux_controls[1]),
556 SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0,
557 &tas5086_dapm_output_mux_controls[2]),
558 SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0,
559 &tas5086_dapm_output_mux_controls[3]),
560 SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0,
561 &tas5086_dapm_output_mux_controls[4]),
562 SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0,
563 &tas5086_dapm_output_mux_controls[5]),
564};
565
566static const struct snd_soc_dapm_route tas5086_dapm_routes[] = {
567 /* SDIN inputs -> channel muxes */
568 { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
569 { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
570 { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
571 { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
572 { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
573 { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
574
575 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
576 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
577 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
578 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
579 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
580 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
581
582 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
583 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
584 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
585 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
586 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
587 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
588
589 { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
590 { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
591 { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
592 { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
593 { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
594 { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
595
596 { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
597 { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
598 { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
599 { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
600 { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
601 { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
602
603 { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
604 { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
605 { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
606 { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
607 { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
608 { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
609
610 { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
611 { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
612 { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
613 { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
614 { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
615 { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
616
617 /* Channel muxes -> PWM muxes */
618 { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
619 { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
620 { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
621 { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
622 { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
623 { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
624
625 { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
626 { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
627 { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
628 { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
629 { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
630 { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
631
632 { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
633 { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
634 { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
635 { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
636 { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
637 { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
638
639 { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
640 { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
641 { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
642 { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
643 { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
644 { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
645
646 { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
647 { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
648 { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
649 { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
650 { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
651 { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
652
653 { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
654 { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
655 { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
656 { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
657 { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
658 { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
659
660 /* The PWM muxes are directly connected to the PWM outputs */
661 { "PWM1", NULL, "PWM1 Mux" },
662 { "PWM2", NULL, "PWM2 Mux" },
663 { "PWM3", NULL, "PWM3 Mux" },
664 { "PWM4", NULL, "PWM4 Mux" },
665 { "PWM5", NULL, "PWM5 Mux" },
666 { "PWM6", NULL, "PWM6 Mux" },
667
668};
669
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DM		 670static const struct snd_soc_dai_ops tas5086_dai_ops = {
671 .hw_params = tas5086_hw_params,
672 .set_sysclk = tas5086_set_dai_sysclk,
673 .set_fmt = tas5086_set_dai_fmt,
674 .mute_stream = tas5086_mute_stream,
675};
676
677static struct snd_soc_dai_driver tas5086_dai = {
678 .name = "tas5086-hifi",
679 .playback = {
680 .stream_name = "Playback",
681 .channels_min = 2,
682 .channels_max = 6,
683 .rates = TAS5086_PCM_RATES,
684 .formats = TAS5086_PCM_FORMATS,
685 },
686 .ops = &tas5086_dai_ops,
687};
688
689#ifdef CONFIG_PM
690static int tas5086_soc_resume(struct snd_soc_codec *codec)
691{
692 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
693
694 /* Restore codec state */
695 return regcache_sync(priv->regmap);
696}
697#else
698#define tas5086_soc_resume NULL
699#endif /* CONFIG_PM */
700
701#ifdef CONFIG_OF
702static const struct of_device_id tas5086_dt_ids[] = {
703 { .compatible = "ti,tas5086", },
704 { }
705};
706MODULE_DEVICE_TABLE(of, tas5086_dt_ids);
707#endif
708
709/* charge period values in microseconds */
710static const int tas5086_charge_period[] = {
711 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200,
712 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000,
713 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000,
714};
715
716static int tas5086_probe(struct snd_soc_codec *codec)
717{
718 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
719 int charge_period = 1300000; /* hardware default is 1300 ms */
720 int i, ret;
721
722 if (of_match_device(of_match_ptr(tas5086_dt_ids), codec->dev)) {
723 struct device_node *of_node = codec->dev->of_node;
724 of_property_read_u32(of_node, "ti,charge-period", &charge_period);
725 }
726
727 /* lookup and set split-capacitor charge period */
728 if (charge_period == 0) {
729 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0);
730 } else {
731 i = index_in_array(tas5086_charge_period,
732 ARRAY_SIZE(tas5086_charge_period),
733 charge_period);
734 if (i >= 0)
735 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE,
736 i + 0x08);
737 else
738 dev_warn(codec->dev,
739 "Invalid split-cap charge period of %d ns.\n",
740 charge_period);
741 }
742
743 /* enable factory trim */
744 ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00);
745 if (ret < 0)
746 return ret;
747
748 /* start all channels */
749 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20);
750 if (ret < 0)
751 return ret;
752
753 /* set master volume to 0 dB */
754 ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30);
755 if (ret < 0)
756 return ret;
757
758 /* mute all channels for now */
759 ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE,
760 TAS5086_SOFT_MUTE_ALL);
761 if (ret < 0)
762 return ret;
763
764 return 0;
765}
766
767static int tas5086_remove(struct snd_soc_codec *codec)
768{
769 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
770
771 if (gpio_is_valid(priv->gpio_nreset))
772 /* Set codec to the reset state */
773 gpio_set_value(priv->gpio_nreset, 0);
774
775 return 0;
776};
777
778static struct snd_soc_codec_driver soc_codec_dev_tas5086 = {
779 .probe = tas5086_probe,
780 .remove = tas5086_remove,
781 .resume = tas5086_soc_resume,
782 .controls = tas5086_controls,
783 .num_controls = ARRAY_SIZE(tas5086_controls),
18710acd
DM		 784 .dapm_widgets = tas5086_dapm_widgets,
785 .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets),
786 .dapm_routes = tas5086_dapm_routes,
787 .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes),
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DM		 788};
789
790static const struct i2c_device_id tas5086_i2c_id[] = {
791 { "tas5086", 0 },
792 { }
793};
794MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id);
795
796static const struct regmap_config tas5086_regmap = {
797 .reg_bits = 8,
8892d479
DM		 798 .val_bits = 32,
799 .max_register = TAS5086_MAX_REGISTER,
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DM		 800 .reg_defaults = tas5086_reg_defaults,
801 .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults),
802 .cache_type = REGCACHE_RBTREE,
803 .volatile_reg = tas5086_volatile_reg,
804 .writeable_reg = tas5086_writeable_reg,
805 .readable_reg = tas5086_accessible_reg,
6b36d370
DM		 806 .reg_read = tas5086_reg_read,
807 .reg_write = tas5086_reg_write,
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DM		 808};
809
810static int tas5086_i2c_probe(struct i2c_client *i2c,
811 const struct i2c_device_id *id)
812{
813 struct tas5086_private *priv;
814 struct device *dev = &i2c->dev;
815 int gpio_nreset = -EINVAL;
816 int i, ret;
817
818 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
819 if (!priv)
820 return -ENOMEM;
821
6b36d370 822 priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap);
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DM		 823 if (IS_ERR(priv->regmap)) {
824 ret = PTR_ERR(priv->regmap);
825 dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
826 return ret;
827 }
828
829 i2c_set_clientdata(i2c, priv);
830
831 if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) {
832 struct device_node *of_node = dev->of_node;
833 gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0);
834 }
835
836 if (gpio_is_valid(gpio_nreset))
837 if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset"))
838 gpio_nreset = -EINVAL;
839
840 if (gpio_is_valid(gpio_nreset)) {
841 /* Reset codec - minimum assertion time is 400ns */
842 gpio_direction_output(gpio_nreset, 0);
843 udelay(1);
844 gpio_set_value(gpio_nreset, 1);
845
846 /* Codec needs ~15ms to wake up */
847 msleep(15);
848 }
849
850 priv->gpio_nreset = gpio_nreset;
851
852 /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */
853 ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i);
854 if (ret < 0)
855 return ret;
856
857 if (i != 0x3) {
858 dev_err(dev,
859 "Failed to identify TAS5086 codec (got %02x)\n", i);
860 return -ENODEV;
861 }
862
863 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086,
864 &tas5086_dai, 1);
865}
866
867static int tas5086_i2c_remove(struct i2c_client *i2c)
868{
869 snd_soc_unregister_codec(&i2c->dev);
870 return 0;
871}
872
873static struct i2c_driver tas5086_i2c_driver = {
874 .driver = {
875 .name = "tas5086",
876 .owner = THIS_MODULE,
877 .of_match_table = of_match_ptr(tas5086_dt_ids),
878 },
879 .id_table = tas5086_i2c_id,
880 .probe = tas5086_i2c_probe,
881 .remove = tas5086_i2c_remove,
882};
883
c300d6de 884module_i2c_driver(tas5086_i2c_driver);
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DM		 885
886MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>");
887MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver");
888MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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