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Merge remote branch 'asoc/for-2.6.37' into for-2.6.37
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49#include <sound/soc-dapm.h>
50#include <sound/initval.h>
7565fc38 51#include <sound/tlv.h>
5193d62f 52#include <sound/tlv320aic3x.h>
44d0a879
VB		 53
54#include "tlv320aic3x.h"
55
07779fdd
JN		 56#define AIC3X_NUM_SUPPLIES 4
57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62};
44d0a879
VB		 63
64/* codec private data */
65struct aic3x_priv {
07779fdd 66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
69 void *control_data;
44d0a879
VB		 70 unsigned int sysclk;
71 int master;
5193d62f 72 int gpio_reset;
6184f105
RC		 73#define AIC3X_MODEL_3X 0
74#define AIC3X_MODEL_33 1
75#define AIC3X_MODEL_3007 2
76 u16 model;
44d0a879
VB		 77};
78
79/*
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
84 */
85static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
112};
113
114/*
9900daa8
JN		 115 * read from the aic3x register space. Only use for this function is if
116 * wanting to read volatile bits from those registers that has both read-only
117 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 118 */
54e7e616
DM		 119static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
120 u8 *value)
44d0a879
VB		 121{
122 u8 *cache = codec->reg_cache;
44d0a879 123
44d0a879 124 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 125 return -1;
5f345346 126
9900daa8
JN		 127 *value = codec->hw_read(codec, reg);
128 cache[reg] = *value;
54e7e616 129
54e7e616
DM		 130 return 0;
131}
132
44d0a879
VB		 133#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
134{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
135 .info = snd_soc_info_volsw, \
136 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
137 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
138
139/*
140 * All input lines are connected when !0xf and disconnected with 0xf bit field,
141 * so we have to use specific dapm_put call for input mixer
142 */
143static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
144 struct snd_ctl_elem_value *ucontrol)
145{
146 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 147 struct soc_mixer_control *mc =
148 (struct soc_mixer_control *)kcontrol->private_value;
149 unsigned int reg = mc->reg;
150 unsigned int shift = mc->shift;
151 int max = mc->max;
152 unsigned int mask = (1 << fls(max)) - 1;
153 unsigned int invert = mc->invert;
44d0a879
VB		 154 unsigned short val, val_mask;
155 int ret;
156 struct snd_soc_dapm_path *path;
157 int found = 0;
158
159 val = (ucontrol->value.integer.value[0] & mask);
160
161 mask = 0xf;
162 if (val)
163 val = mask;
164
165 if (invert)
166 val = mask - val;
167 val_mask = mask << shift;
168 val = val << shift;
169
170 mutex_lock(&widget->codec->mutex);
171
172 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
173 /* find dapm widget path assoc with kcontrol */
174 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
175 if (path->kcontrol != kcontrol)
176 continue;
177
178 /* found, now check type */
179 found = 1;
180 if (val)
181 /* new connection */
182 path->connect = invert ? 0 : 1;
183 else
184 /* old connection must be powered down */
185 path->connect = invert ? 1 : 0;
186 break;
187 }
188
189 if (found)
a5302181 190 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 191 }
192
193 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
194
195 mutex_unlock(&widget->codec->mutex);
196 return ret;
197}
198
199static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
200static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
201static const char *aic3x_left_hpcom_mux[] =
202 { "differential of HPLOUT", "constant VCM", "single-ended" };
203static const char *aic3x_right_hpcom_mux[] =
204 { "differential of HPROUT", "constant VCM", "single-ended",
205 "differential of HPLCOM", "external feedback" };
206static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 207static const char *aic3x_adc_hpf[] =
208 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 209
210#define LDAC_ENUM 0
211#define RDAC_ENUM 1
212#define LHPCOM_ENUM 2
213#define RHPCOM_ENUM 3
214#define LINE1L_ENUM 4
215#define LINE1R_ENUM 5
216#define LINE2L_ENUM 6
217#define LINE2R_ENUM 7
4d20f70a 218#define ADC_HPF_ENUM 8
44d0a879
VB		 219
220static const struct soc_enum aic3x_enum[] = {
221 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
222 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
223 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
224 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
225 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
226 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
227 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
228 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 229 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 230};
231
7565fc38
JN		 232/*
233 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
234 */
235static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
236/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
237static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
238/*
239 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
240 * Step size is approximately 0.5 dB over most of the scale but increasing
241 * near the very low levels.
242 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
243 * but having increasing dB difference below that (and where it doesn't count
244 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
245 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
246 */
247static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
248
44d0a879
VB		 249static const struct snd_kcontrol_new aic3x_snd_controls[] = {
250 /* Output */
7565fc38
JN		 251 SOC_DOUBLE_R_TLV("PCM Playback Volume",
252 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 253
098b1718
JN		 254 /*
255 * Output controls that map to output mixer switches. Note these are
256 * only for swapped L-to-R and R-to-L routes. See below stereo controls
257 * for direct L-to-L and R-to-R routes.
258 */
259 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
260 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
261 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
262 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
263 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
264 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
265
266 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
267 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
268 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
269 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
270 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
271 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
272
273 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
274 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
275 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
276 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
277 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
278 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
279
280 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
281 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
283 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
285 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
286
287 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
288 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
290 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
292 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
293
294 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
295 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
297 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
299 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
300
301 /* Stereo output controls for direct L-to-L and R-to-R routes */
302 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
303 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
304 0, 118, 1, output_stage_tlv),
305 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
306 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
307 0, 118, 1, output_stage_tlv),
7565fc38
JN		 308 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
309 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
310 0, 118, 1, output_stage_tlv),
098b1718
JN		 311
312 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
313 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 314 0, 118, 1, output_stage_tlv),
098b1718
JN		 315 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
316 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 317 0, 118, 1, output_stage_tlv),
7565fc38
JN		 318 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
319 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
320 0, 118, 1, output_stage_tlv),
098b1718
JN		 321
322 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
323 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 324 0, 118, 1, output_stage_tlv),
098b1718
JN		 325 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
326 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 327 0, 118, 1, output_stage_tlv),
7565fc38
JN		 328 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
329 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
330 0, 118, 1, output_stage_tlv),
098b1718
JN		 331
332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
333 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 334 0, 118, 1, output_stage_tlv),
098b1718
JN		 335 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
336 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 337 0, 118, 1, output_stage_tlv),
7565fc38
JN		 338 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
339 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
340 0, 118, 1, output_stage_tlv),
098b1718
JN		 341
342 /* Output pin mute controls */
343 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
344 0x01, 0),
345 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
346 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
347 0x01, 0),
f9bc0297 348 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 349 0x01, 0),
44d0a879
VB		 350
351 /*
352 * Note: enable Automatic input Gain Controller with care. It can
353 * adjust PGA to max value when ADC is on and will never go back.
354 */
355 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
356
357 /* Input */
7565fc38
JN		 358 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
359 0, 119, 0, adc_tlv),
44d0a879 360 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 361
362 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 363};
364
6184f105
RC		 365/*
366 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
367 */
368static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
369
370static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
371 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
372
44d0a879
VB		 373/* Left DAC Mux */
374static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
375SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
376
377/* Right DAC Mux */
378static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
379SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
380
381/* Left HPCOM Mux */
382static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
383SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
384
385/* Right HPCOM Mux */
386static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
387SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
388
c3b79e05
JN		 389/* Left Line Mixer */
390static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
391 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
392 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
393 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 397};
398
c3b79e05
JN		 399/* Right Line Mixer */
400static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
401 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
407};
408
409/* Mono Mixer */
410static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
411 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
417};
418
419/* Left HP Mixer */
420static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
421 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
427};
428
429/* Right HP Mixer */
430static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
431 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
437};
438
439/* Left HPCOM Mixer */
440static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
447};
448
449/* Right HPCOM Mixer */
450static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 457};
458
459/* Left PGA Mixer */
460static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
461 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 462 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 463 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
464 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 465 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 466};
467
468/* Right PGA Mixer */
469static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
470 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 471 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 472 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 473 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 474 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
475};
476
477/* Left Line1 Mux */
478static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
479SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
480
481/* Right Line1 Mux */
482static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
483SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
484
485/* Left Line2 Mux */
486static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
487SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
488
489/* Right Line2 Mux */
490static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
491SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
492
44d0a879
VB		 493static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
494 /* Left DAC to Left Outputs */
495 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
496 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
497 &aic3x_left_dac_mux_controls),
44d0a879
VB		 498 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
499 &aic3x_left_hpcom_mux_controls),
500 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
501 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
502 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
503
504 /* Right DAC to Right Outputs */
505 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
506 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
507 &aic3x_right_dac_mux_controls),
44d0a879
VB		 508 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
509 &aic3x_right_hpcom_mux_controls),
510 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
511 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
512 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
513
514 /* Mono Output */
515 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
516
54f01916 517 /* Inputs to Left ADC */
44d0a879
VB		 518 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
519 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
520 &aic3x_left_pga_mixer_controls[0],
521 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
522 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
523 &aic3x_left_line1_mux_controls),
54f01916
DM		 524 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
525 &aic3x_left_line1_mux_controls),
44d0a879
VB		 526 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
527 &aic3x_left_line2_mux_controls),
528
54f01916 529 /* Inputs to Right ADC */
44d0a879
VB		 530 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
531 LINE1R_2_RADC_CTRL, 2, 0),
532 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
533 &aic3x_right_pga_mixer_controls[0],
534 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 535 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
536 &aic3x_right_line1_mux_controls),
44d0a879
VB		 537 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_right_line1_mux_controls),
539 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
540 &aic3x_right_line2_mux_controls),
541
ee15ffdb
JN		 542 /*
543 * Not a real mic bias widget but similar function. This is for dynamic
544 * control of GPIO1 digital mic modulator clock output function when
545 * using digital mic.
546 */
547 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
548 AIC3X_GPIO1_REG, 4, 0xf,
549 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
550 AIC3X_GPIO1_FUNC_DISABLED),
551
552 /*
553 * Also similar function like mic bias. Selects digital mic with
554 * configurable oversampling rate instead of ADC converter.
555 */
556 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
557 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
558 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
559 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
560 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
561 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
562
44d0a879 563 /* Mic Bias */
0bd72a3d
JN		 564 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
565 MICBIAS_CTRL, 6, 3, 1, 0),
566 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
567 MICBIAS_CTRL, 6, 3, 2, 0),
568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
569 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 570
c3b79e05
JN		 571 /* Output mixers */
572 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
573 &aic3x_left_line_mixer_controls[0],
574 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
575 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
576 &aic3x_right_line_mixer_controls[0],
577 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
578 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
579 &aic3x_mono_mixer_controls[0],
580 ARRAY_SIZE(aic3x_mono_mixer_controls)),
581 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
582 &aic3x_left_hp_mixer_controls[0],
583 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
584 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
585 &aic3x_right_hp_mixer_controls[0],
586 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
587 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
588 &aic3x_left_hpcom_mixer_controls[0],
589 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
590 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
591 &aic3x_right_hpcom_mixer_controls[0],
592 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 593
594 SND_SOC_DAPM_OUTPUT("LLOUT"),
595 SND_SOC_DAPM_OUTPUT("RLOUT"),
596 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
597 SND_SOC_DAPM_OUTPUT("HPLOUT"),
598 SND_SOC_DAPM_OUTPUT("HPROUT"),
599 SND_SOC_DAPM_OUTPUT("HPLCOM"),
600 SND_SOC_DAPM_OUTPUT("HPRCOM"),
601
602 SND_SOC_DAPM_INPUT("MIC3L"),
603 SND_SOC_DAPM_INPUT("MIC3R"),
604 SND_SOC_DAPM_INPUT("LINE1L"),
605 SND_SOC_DAPM_INPUT("LINE1R"),
606 SND_SOC_DAPM_INPUT("LINE2L"),
607 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 608
609 /*
610 * Virtual output pin to detection block inside codec. This can be
611 * used to keep codec bias on if gpio or detection features are needed.
612 * Force pin on or construct a path with an input jack and mic bias
613 * widgets.
614 */
615 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 616};
617
6184f105
RC		 618static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
619 /* Class-D outputs */
620 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
621 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
622
623 SND_SOC_DAPM_OUTPUT("SPOP"),
624 SND_SOC_DAPM_OUTPUT("SPOM"),
625};
626
d0cc0d3a 627static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 628 /* Left Input */
629 {"Left Line1L Mux", "single-ended", "LINE1L"},
630 {"Left Line1L Mux", "differential", "LINE1L"},
631
632 {"Left Line2L Mux", "single-ended", "LINE2L"},
633 {"Left Line2L Mux", "differential", "LINE2L"},
634
635 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 636 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 637 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
638 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 639 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 640
641 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 642 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 643
644 /* Right Input */
645 {"Right Line1R Mux", "single-ended", "LINE1R"},
646 {"Right Line1R Mux", "differential", "LINE1R"},
647
648 {"Right Line2R Mux", "single-ended", "LINE2R"},
649 {"Right Line2R Mux", "differential", "LINE2R"},
650
54f01916 651 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 652 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
653 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 654 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 655 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
656
657 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 658 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 659
ee15ffdb
JN		 660 /*
661 * Logical path between digital mic enable and GPIO1 modulator clock
662 * output function
663 */
664 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
665 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
666 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 667
668 /* Left DAC Output */
669 {"Left DAC Mux", "DAC_L1", "Left DAC"},
670 {"Left DAC Mux", "DAC_L2", "Left DAC"},
671 {"Left DAC Mux", "DAC_L3", "Left DAC"},
672
673 /* Right DAC Output */
674 {"Right DAC Mux", "DAC_R1", "Right DAC"},
675 {"Right DAC Mux", "DAC_R2", "Right DAC"},
676 {"Right DAC Mux", "DAC_R3", "Right DAC"},
677
678 /* Left Line Output */
679 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
680 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
681 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
682 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
683 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
684 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
685
686 {"Left Line Out", NULL, "Left Line Mixer"},
687 {"Left Line Out", NULL, "Left DAC Mux"},
688 {"LLOUT", NULL, "Left Line Out"},
689
690 /* Right Line Output */
691 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
692 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
693 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
694 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
695 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
696 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
697
698 {"Right Line Out", NULL, "Right Line Mixer"},
699 {"Right Line Out", NULL, "Right DAC Mux"},
700 {"RLOUT", NULL, "Right Line Out"},
701
702 /* Mono Output */
703 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
704 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
705 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
706 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
707 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
708 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
709
710 {"Mono Out", NULL, "Mono Mixer"},
711 {"MONO_LOUT", NULL, "Mono Out"},
712
713 /* Left HP Output */
714 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
715 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
716 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
717 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
718 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
719 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
720
721 {"Left HP Out", NULL, "Left HP Mixer"},
722 {"Left HP Out", NULL, "Left DAC Mux"},
723 {"HPLOUT", NULL, "Left HP Out"},
724
725 /* Right HP Output */
726 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
727 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
728 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
729 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
730 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
731 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
732
733 {"Right HP Out", NULL, "Right HP Mixer"},
734 {"Right HP Out", NULL, "Right DAC Mux"},
735 {"HPROUT", NULL, "Right HP Out"},
736
737 /* Left HPCOM Output */
738 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
739 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
740 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
741 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
742 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
743 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
744
745 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
746 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
747 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
748 {"Left HP Com", NULL, "Left HPCOM Mux"},
749 {"HPLCOM", NULL, "Left HP Com"},
750
751 /* Right HPCOM Output */
752 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
753 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
754 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
755 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
756 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
757 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
758
759 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
760 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
761 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
762 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
763 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
764 {"Right HP Com", NULL, "Right HPCOM Mux"},
765 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 766};
767
6184f105
RC		 768static const struct snd_soc_dapm_route intercon_3007[] = {
769 /* Class-D outputs */
770 {"Left Class-D Out", NULL, "Left Line Out"},
771 {"Right Class-D Out", NULL, "Left Line Out"},
772 {"SPOP", NULL, "Left Class-D Out"},
773 {"SPOM", NULL, "Right Class-D Out"},
774};
775
44d0a879
VB		 776static int aic3x_add_widgets(struct snd_soc_codec *codec)
777{
6184f105
RC		 778 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
779
d0cc0d3a
MB		 780 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
781 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 782
783 /* set up audio path interconnects */
d0cc0d3a 784 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879 785
6184f105
RC		 786 if (aic3x->model == AIC3X_MODEL_3007) {
787 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets,
788 ARRAY_SIZE(aic3007_dapm_widgets));
789 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007));
790 }
791
44d0a879
VB		 792 return 0;
793}
794
44d0a879 795static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 796 struct snd_pcm_hw_params *params,
797 struct snd_soc_dai *dai)
44d0a879
VB		 798{
799 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 800 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 801 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 802 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 803 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
804 u16 d, pll_d = 1;
06c71282 805 u8 reg;
255173b4 806 int clk;
44d0a879 807
4f9c16cc 808 /* select data word length */
e18eca43 809 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 810 switch (params_format(params)) {
811 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 812 break;
4f9c16cc
DM		 813 case SNDRV_PCM_FORMAT_S20_3LE:
814 data |= (0x01 << 4);
44d0a879 815 break;
4f9c16cc
DM		 816 case SNDRV_PCM_FORMAT_S24_LE:
817 data |= (0x02 << 4);
44d0a879 818 break;
4f9c16cc
DM		 819 case SNDRV_PCM_FORMAT_S32_LE:
820 data |= (0x03 << 4);
44d0a879
VB		 821 break;
822 }
e18eca43 823 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 824
825 /* Fsref can be 44100 or 48000 */
826 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
827
828 /* Try to find a value for Q which allows us to bypass the PLL and
829 * generate CODEC_CLK directly. */
830 for (pll_q = 2; pll_q < 18; pll_q++)
831 if (aic3x->sysclk / (128 * pll_q) == fsref) {
832 bypass_pll = 1;
833 break;
834 }
835
836 if (bypass_pll) {
837 pll_q &= 0xf;
e18eca43
JN		 838 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
839 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 840 /* disable PLL if it is bypassed */
e18eca43
JN		 841 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
842 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 843
844 } else {
e18eca43 845 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 846 /* enable PLL when it is used */
e18eca43
JN		 847 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
848 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 849 }
4f9c16cc
DM		 850
851 /* Route Left DAC to left channel input and
852 * right DAC to right channel input */
853 data = (LDAC2LCH | RDAC2RCH);
854 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
855 if (params_rate(params) >= 64000)
856 data |= DUAL_RATE_MODE;
e18eca43 857 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 858
859 /* codec sample rate select */
4f9c16cc
DM		 860 data = (fsref * 20) / params_rate(params);
861 if (params_rate(params) < 64000)
862 data /= 2;
863 data /= 5;
864 data -= 2;
44d0a879 865 data |= (data << 4);
e18eca43 866 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 867
4f9c16cc
DM		 868 if (bypass_pll)
869 return 0;
870
255173b4
PM		 871 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
872 * one wins the game. Try with d==0 first, next with d!=0.
873 * Constraints for j are according to the datasheet.
4f9c16cc 874 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 875 */
255173b4 876
4f9c16cc
DM		 877 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
878
879 for (r = 1; r <= 16; r++)
880 for (p = 1; p <= 8; p++) {
255173b4
PM		 881 for (j = 4; j <= 55; j++) {
882 /* This is actually 1000*((j+(d/10000))*r)/p
883 * The term had to be converted to get
884 * rid of the division by 10000; d = 0 here
885 */
5baf8315 886 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 887
888 /* Check whether this values get closer than
889 * the best ones we had before
890 */
5baf8315 891 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 892 abs(codec_clk - last_clk)) {
893 pll_j = j; pll_d = 0;
894 pll_r = r; pll_p = p;
5baf8315 895 last_clk = tmp_clk;
255173b4
PM		 896 }
897
898 /* Early exit for exact matches */
5baf8315 899 if (tmp_clk == codec_clk)
255173b4
PM		 900 goto found;
901 }
902 }
4f9c16cc 903
255173b4
PM		 904 /* try with d != 0 */
905 for (p = 1; p <= 8; p++) {
906 j = codec_clk * p / 1000;
4f9c16cc 907
255173b4
PM		 908 if (j < 4 || j > 11)
909 continue;
4f9c16cc 910
255173b4
PM		 911 /* do not use codec_clk here since we'd loose precision */
912 d = ((2048 * p * fsref) - j * aic3x->sysclk)
913 * 100 / (aic3x->sysclk/100);
4f9c16cc 914
255173b4 915 clk = (10000 * j + d) / (10 * p);
4f9c16cc 916
255173b4
PM		 917 /* check whether this values get closer than the best
918 * ones we had before */
919 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
920 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
921 last_clk = clk;
4f9c16cc
DM		 922 }
923
255173b4
PM		 924 /* Early exit for exact matches */
925 if (clk == codec_clk)
926 goto found;
927 }
928
4f9c16cc
DM		 929 if (last_clk == 0) {
930 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
931 return -EINVAL;
932 }
44d0a879 933
255173b4 934found:
e18eca43
JN		 935 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
936 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
937 data | (pll_p << PLLP_SHIFT));
938 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
939 pll_r << PLLR_SHIFT);
940 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
941 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
942 (pll_d >> 6) << PLLD_MSB_SHIFT);
943 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
944 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 945
44d0a879
VB		 946 return 0;
947}
948
e550e17f 949static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 950{
951 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 952 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
953 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 954
955 if (mute) {
e18eca43
JN		 956 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
957 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 958 } else {
e18eca43
JN		 959 snd_soc_write(codec, LDAC_VOL, ldac_reg);
960 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 961 }
962
963 return 0;
964}
965
e550e17f 966static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 967 int clk_id, unsigned int freq, int dir)
968{
969 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 970 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 971
4f9c16cc
DM		 972 aic3x->sysclk = freq;
973 return 0;
44d0a879
VB		 974}
975
e550e17f 976static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 977 unsigned int fmt)
978{
979 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 980 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 981 u8 iface_areg, iface_breg;
a24f4f68 982 int delay = 0;
81971a14 983
e18eca43
JN		 984 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
985 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 986
987 /* set master/slave audio interface */
988 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
989 case SND_SOC_DAIFMT_CBM_CFM:
990 aic3x->master = 1;
991 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
992 break;
993 case SND_SOC_DAIFMT_CBS_CFS:
994 aic3x->master = 0;
995 break;
996 default:
997 return -EINVAL;
998 }
999
4b7d2831
JN		 1000 /*
1001 * match both interface format and signal polarities since they
1002 * are fixed
1003 */
1004 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1005 SND_SOC_DAIFMT_INV_MASK)) {
1006 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1007 break;
a24f4f68
TK		 1008 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1009 delay = 1;
4b7d2831 1010 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1011 iface_breg |= (0x01 << 6);
1012 break;
4b7d2831 1013 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1014 iface_breg |= (0x02 << 6);
1015 break;
4b7d2831 1016 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1017 iface_breg |= (0x03 << 6);
1018 break;
1019 default:
1020 return -EINVAL;
1021 }
1022
1023 /* set iface */
e18eca43
JN		 1024 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1025 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1026 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1027
1028 return 0;
1029}
1030
0be9898a
MB		 1031static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1032 enum snd_soc_bias_level level)
44d0a879 1033{
b2c812e2 1034 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1035 u8 reg;
1036
0be9898a
MB		 1037 switch (level) {
1038 case SND_SOC_BIAS_ON:
db13802e
JN		 1039 break;
1040 case SND_SOC_BIAS_PREPARE:
c23fd751
JN		 1041 if (codec->bias_level == SND_SOC_BIAS_STANDBY &&
1042 aic3x->master) {
44d0a879 1043 /* enable pll */
e18eca43
JN		 1044 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1045 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1046 reg | PLL_ENABLE);
44d0a879
VB		 1047 }
1048 break;
0be9898a 1049 case SND_SOC_BIAS_STANDBY:
c23fd751
JN		 1050 if (codec->bias_level == SND_SOC_BIAS_PREPARE &&
1051 aic3x->master) {
44d0a879 1052 /* disable pll */
e18eca43
JN		 1053 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1054 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1055 reg & ~PLL_ENABLE);
44d0a879
VB		 1056 }
1057 break;
c23fd751
JN		 1058 case SND_SOC_BIAS_OFF:
1059 break;
44d0a879 1060 }
0be9898a 1061 codec->bias_level = level;
44d0a879
VB		 1062
1063 return 0;
1064}
1065
54e7e616
DM		 1066void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1067{
1068 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1069 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1070 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1071 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1072}
1073EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1074
1075int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1076{
1077 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1078 u8 val, bit = gpio ? 2: 1;
1079
1080 aic3x_read(codec, reg, &val);
1081 return (val >> bit) & 1;
1082}
1083EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1084
6f2a974b
DM		 1085void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1086 int headset_debounce, int button_debounce)
1087{
1088 u8 val;
1089
1090 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1091 << AIC3X_HEADSET_DETECT_SHIFT) |
1092 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1093 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1094 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1095 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1096
1097 if (detect & AIC3X_HEADSET_DETECT_MASK)
1098 val |= AIC3X_HEADSET_DETECT_ENABLED;
1099
e18eca43 1100 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1101}
1102EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1103
54e7e616
DM		 1104int aic3x_headset_detected(struct snd_soc_codec *codec)
1105{
1106 u8 val;
6f2a974b
DM		 1107 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1108 return (val >> 4) & 1;
54e7e616
DM		 1109}
1110EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1111
6f2a974b
DM		 1112int aic3x_button_pressed(struct snd_soc_codec *codec)
1113{
1114 u8 val;
1115 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1116 return (val >> 5) & 1;
1117}
1118EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1119
44d0a879
VB		 1120#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1121#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1122 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1123
6335d055
EM		 1124static struct snd_soc_dai_ops aic3x_dai_ops = {
1125 .hw_params = aic3x_hw_params,
1126 .digital_mute = aic3x_mute,
1127 .set_sysclk = aic3x_set_dai_sysclk,
1128 .set_fmt = aic3x_set_dai_fmt,
1129};
1130
f0fba2ad
LG		 1131static struct snd_soc_dai_driver aic3x_dai = {
1132 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1133 .playback = {
1134 .stream_name = "Playback",
1135 .channels_min = 1,
1136 .channels_max = 2,
1137 .rates = AIC3X_RATES,
1138 .formats = AIC3X_FORMATS,},
1139 .capture = {
1140 .stream_name = "Capture",
1141 .channels_min = 1,
1142 .channels_max = 2,
1143 .rates = AIC3X_RATES,
1144 .formats = AIC3X_FORMATS,},
6335d055 1145 .ops = &aic3x_dai_ops,
14017615 1146 .symmetric_rates = 1,
44d0a879 1147};
44d0a879 1148
f0fba2ad 1149static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1150{
0be9898a 1151 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1152
1153 return 0;
1154}
1155
f0fba2ad 1156static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1157{
44d0a879
VB		 1158 int i;
1159 u8 data[2];
1160 u8 *cache = codec->reg_cache;
1161
1162 /* Sync reg_cache with the hardware */
1163 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1164 data[0] = i;
1165 data[1] = cache[i];
1166 codec->hw_write(codec->control_data, data, 2);
1167 }
1168
29e189c2 1169 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1170
1171 return 0;
1172}
1173
1174/*
1175 * initialise the AIC3X driver
1176 * register the mixer and dsp interfaces with the kernel
1177 */
cb3826f5 1178static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1179{
6184f105 1180 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1181 int reg;
1182
e18eca43
JN		 1183 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1184 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1185
44d0a879 1186 /* DAC default volume and mute */
e18eca43
JN		 1187 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1188 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1189
1190 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1191 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1192 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1193 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1194 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1195 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1196 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1197 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1198 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1199 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1200 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1201
1202 /* unmute all outputs */
e18eca43
JN		 1203 reg = snd_soc_read(codec, LLOPM_CTRL);
1204 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1205 reg = snd_soc_read(codec, RLOPM_CTRL);
1206 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1207 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1208 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1209 reg = snd_soc_read(codec, HPLOUT_CTRL);
1210 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1211 reg = snd_soc_read(codec, HPROUT_CTRL);
1212 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1213 reg = snd_soc_read(codec, HPLCOM_CTRL);
1214 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1215 reg = snd_soc_read(codec, HPRCOM_CTRL);
1216 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1217
1218 /* ADC default volume and unmute */
e18eca43
JN		 1219 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1220 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1221 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1222 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1223 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1224
1225 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1226 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1227 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1228 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1229 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1230 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1231 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1232 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1233 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1234 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1235 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1236
1237 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1238 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1239 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1240 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1241 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1242 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1243 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1244 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1245 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1246 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1247 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1248
6184f105
RC		 1249 if (aic3x->model == AIC3X_MODEL_3007) {
1250 /* Class-D speaker driver init; datasheet p. 46 */
e18eca43
JN		 1251 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1252 snd_soc_write(codec, 0xD, 0x0D);
1253 snd_soc_write(codec, 0x8, 0x5C);
1254 snd_soc_write(codec, 0x8, 0x5D);
1255 snd_soc_write(codec, 0x8, 0x5C);
1256 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1257 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1258 }
1259
44d0a879 1260 /* off, with power on */
0be9898a 1261 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1262
cb3826f5
BD		 1263 return 0;
1264}
54e7e616 1265
f0fba2ad 1266static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1267{
f0fba2ad 1268 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
a84a441b 1269 int ret;
f0fba2ad 1270
f0fba2ad 1271 codec->control_data = aic3x->control_data;
cb3826f5 1272
a84a441b
JN		 1273 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1274 if (ret != 0) {
1275 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1276 return ret;
1277 }
1278
37b47656
JN		 1279 aic3x_init(codec);
1280
f0fba2ad
LG		 1281 if (aic3x->setup) {
1282 /* setup GPIO functions */
e18eca43
JN		 1283 snd_soc_write(codec, AIC3X_GPIO1_REG,
1284 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1285 snd_soc_write(codec, AIC3X_GPIO2_REG,
1286 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1287 }
1288
f0fba2ad
LG		 1289 snd_soc_add_controls(codec, aic3x_snd_controls,
1290 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1291 if (aic3x->model == AIC3X_MODEL_3007)
1292 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1293
f0fba2ad 1294 aic3x_add_widgets(codec);
cb3826f5
BD		 1295
1296 return 0;
44d0a879
VB		 1297}
1298
f0fba2ad 1299static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1300{
f0fba2ad 1301 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
cb3826f5
BD		 1302 return 0;
1303}
44d0a879 1304
f0fba2ad 1305static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1306 .set_bias_level = aic3x_set_bias_level,
1307 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1308 .reg_word_size = sizeof(u8),
1309 .reg_cache_default = aic3x_reg,
1310 .probe = aic3x_probe,
1311 .remove = aic3x_remove,
1312 .suspend = aic3x_suspend,
1313 .resume = aic3x_resume,
1314};
1315
44d0a879
VB		 1316#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1317/*
1318 * AIC3X 2 wire address can be up to 4 devices with device addresses
1319 * 0x18, 0x19, 0x1A, 0x1B
1320 */
44d0a879 1321
6184f105
RC		 1322static const struct i2c_device_id aic3x_i2c_id[] = {
1323 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1324 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1325 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1326 { }
1327};
1328MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1329
44d0a879
VB		 1330/*
1331 * If the i2c layer weren't so broken, we could pass this kind of data
1332 * around
1333 */
ba8ed121
JD		 1334static int aic3x_i2c_probe(struct i2c_client *i2c,
1335 const struct i2c_device_id *id)
44d0a879 1336{
5193d62f 1337 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1338 struct aic3x_priv *aic3x;
07779fdd 1339 int ret, i;
6184f105 1340 const struct i2c_device_id *tbl;
44d0a879 1341
cb3826f5
BD		 1342 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1343 if (aic3x == NULL) {
1344 dev_err(&i2c->dev, "failed to create private data\n");
1345 return -ENOMEM;
1346 }
1347
f0fba2ad 1348 aic3x->control_data = i2c;
a84a441b
JN		 1349 aic3x->control_type = SND_SOC_I2C;
1350
cb3826f5 1351 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1352 if (pdata) {
1353 aic3x->gpio_reset = pdata->gpio_reset;
1354 aic3x->setup = pdata->setup;
1355 } else {
1356 aic3x->gpio_reset = -1;
1357 }
cb3826f5 1358
c776357e
JN		 1359 if (aic3x->gpio_reset >= 0) {
1360 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
5193d62f
JN		 1361 if (ret != 0)
1362 goto err_gpio;
5193d62f
JN		 1363 gpio_direction_output(aic3x->gpio_reset, 0);
1364 }
1365
6184f105
RC		 1366 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1367 if (!strcmp(tbl->name, id->name))
1368 break;
1369 }
1370 aic3x->model = tbl - aic3x_i2c_id;
1371
07779fdd
JN		 1372 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1373 aic3x->supplies[i].supply = aic3x_supply_names[i];
1374
f0fba2ad 1375 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
07779fdd
JN		 1376 aic3x->supplies);
1377 if (ret != 0) {
f0fba2ad 1378 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
07779fdd
JN		 1379 goto err_get;
1380 }
1381
1382 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1383 aic3x->supplies);
1384 if (ret != 0) {
f0fba2ad 1385 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
07779fdd
JN		 1386 goto err_enable;
1387 }
1388
5193d62f
JN		 1389 if (aic3x->gpio_reset >= 0) {
1390 udelay(1);
1391 gpio_set_value(aic3x->gpio_reset, 1);
1392 }
1393
f0fba2ad
LG		 1394 ret = snd_soc_register_codec(&i2c->dev,
1395 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1396 if (ret < 0)
1397 goto err_enable;
1398 return ret;
07779fdd
JN		 1399
1400err_enable:
1401 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1402err_get:
5193d62f
JN		 1403 if (aic3x->gpio_reset >= 0)
1404 gpio_free(aic3x->gpio_reset);
1405err_gpio:
07779fdd
JN		 1406 kfree(aic3x);
1407 return ret;
44d0a879
VB		 1408}
1409
ba8ed121 1410static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1411{
cb3826f5
BD		 1412 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1413
f0fba2ad
LG		 1414 if (aic3x->gpio_reset >= 0) {
1415 gpio_set_value(aic3x->gpio_reset, 0);
1416 gpio_free(aic3x->gpio_reset);
1417 }
1418 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1419 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1420
1421 snd_soc_unregister_codec(&client->dev);
1422 kfree(i2c_get_clientdata(client));
1423 return 0;
44d0a879
VB		 1424}
1425
44d0a879
VB		 1426/* machine i2c codec control layer */
1427static struct i2c_driver aic3x_i2c_driver = {
1428 .driver = {
f0fba2ad 1429 .name = "tlv320aic3x-codec",
44d0a879
VB		 1430 .owner = THIS_MODULE,
1431 },
cb3826f5 1432 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1433 .remove = aic3x_i2c_remove,
1434 .id_table = aic3x_i2c_id,
44d0a879 1435};
54e7e616 1436
cb3826f5 1437static inline void aic3x_i2c_init(void)
ba8ed121 1438{
ba8ed121
JD		 1439 int ret;
1440
1441 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1442 if (ret)
1443 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1444 __func__, ret);
1445}
ba8ed121 1446
cb3826f5
BD		 1447static inline void aic3x_i2c_exit(void)
1448{
ba8ed121 1449 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1450}
44d0a879
VB		 1451#endif
1452
f0fba2ad 1453static int __init aic3x_modinit(void)
44d0a879 1454{
44d0a879 1455 int ret = 0;
f0fba2ad
LG		 1456#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1457 ret = i2c_add_driver(&aic3x_i2c_driver);
1458 if (ret != 0) {
1459 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1460 ret);
44d0a879 1461 }
f0fba2ad 1462#endif
44d0a879
VB		 1463 return ret;
1464}
64089b84
MB		 1465module_init(aic3x_modinit);
1466
1467static void __exit aic3x_exit(void)
1468{
f0fba2ad
LG		 1469#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1470 i2c_del_driver(&aic3x_i2c_driver);
1471#endif
64089b84
MB		 1472}
1473module_exit(aic3x_exit);
1474
44d0a879
VB		 1475MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1476MODULE_AUTHOR("Vladimir Barinov");
1477MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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