[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.h

/*
 * ALSA SoC TLV320AIC3X codec driver
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _AIC3X_H
#define _AIC3X_H

/* AIC3X register space */
#define AIC3X_CACHEREGNUM		103

/* Page select register */
#define AIC3X_PAGE_SELECT		0
/* Software reset register */
#define AIC3X_RESET			1
/* Codec Sample rate select register */
#define AIC3X_SAMPLE_RATE_SEL_REG	2
/* PLL progrramming register A */
#define AIC3X_PLL_PROGA_REG		3
/* PLL progrramming register B */
#define AIC3X_PLL_PROGB_REG		4
/* PLL progrramming register C */
#define AIC3X_PLL_PROGC_REG		5
/* PLL progrramming register D */
#define AIC3X_PLL_PROGD_REG		6
/* Codec datapath setup register */
#define AIC3X_CODEC_DATAPATH_REG	7
/* Audio serial data interface control register A */
#define AIC3X_ASD_INTF_CTRLA		8
/* Audio serial data interface control register B */
#define AIC3X_ASD_INTF_CTRLB		9
/* Audio serial data interface control register C */
#define AIC3X_ASD_INTF_CTRLC		10
/* Audio overflow status and PLL R value programming register */
#define AIC3X_OVRF_STATUS_AND_PLLR_REG	11
/* Audio codec digital filter control register */
#define AIC3X_CODEC_DFILT_CTRL		12
/* Headset/button press detection register */
#define AIC3X_HEADSET_DETECT_CTRL_A	13
#define AIC3X_HEADSET_DETECT_CTRL_B	14
/* ADC PGA Gain control registers */
#define LADC_VOL			15
#define RADC_VOL			16
/* MIC3 control registers */
#define MIC3LR_2_LADC_CTRL		17
#define MIC3LR_2_RADC_CTRL		18
/* Line1 Input control registers */
#define LINE1L_2_LADC_CTRL		19
#define LINE1R_2_LADC_CTRL		21
#define LINE1R_2_RADC_CTRL		22
#define LINE1L_2_RADC_CTRL		24
/* Line2 Input control registers */
#define LINE2L_2_LADC_CTRL		20
#define LINE2R_2_RADC_CTRL		23
/* MICBIAS Control Register */
#define MICBIAS_CTRL			25

/* AGC Control Registers A, B, C */
#define LAGC_CTRL_A			26
#define LAGC_CTRL_B			27
#define LAGC_CTRL_C			28
#define RAGC_CTRL_A			29
#define RAGC_CTRL_B			30
#define RAGC_CTRL_C			31

/* DAC Power and Left High Power Output control registers */
#define DAC_PWR				37
#define HPLCOM_CFG			37
/* Right High Power Output control registers */
#define HPRCOM_CFG			38
/* DAC Output Switching control registers */
#define DAC_LINE_MUX			41
/* High Power Output Driver Pop Reduction registers */
#define HPOUT_POP_REDUCTION		42
/* DAC Digital control registers */
#define LDAC_VOL			43
#define RDAC_VOL			44
/* Left High Power Output control registers */
#define LINE2L_2_HPLOUT_VOL		45
#define PGAL_2_HPLOUT_VOL		46
#define DACL1_2_HPLOUT_VOL		47
#define LINE2R_2_HPLOUT_VOL		48
#define PGAR_2_HPLOUT_VOL		49
#define DACR1_2_HPLOUT_VOL		50
#define HPLOUT_CTRL			51
/* Left High Power COM control registers */
#define LINE2L_2_HPLCOM_VOL		52
#define PGAL_2_HPLCOM_VOL		53
#define DACL1_2_HPLCOM_VOL		54
#define LINE2R_2_HPLCOM_VOL		55
#define PGAR_2_HPLCOM_VOL		56
#define DACR1_2_HPLCOM_VOL		57
#define HPLCOM_CTRL			58
/* Right High Power Output control registers */
#define LINE2L_2_HPROUT_VOL		59
#define PGAL_2_HPROUT_VOL		60
#define DACL1_2_HPROUT_VOL		61
#define LINE2R_2_HPROUT_VOL		62
#define PGAR_2_HPROUT_VOL		63
#define DACR1_2_HPROUT_VOL		64
#define HPROUT_CTRL			65
/* Right High Power COM control registers */
#define LINE2L_2_HPRCOM_VOL		66
#define PGAL_2_HPRCOM_VOL		67
#define DACL1_2_HPRCOM_VOL		68
#define LINE2R_2_HPRCOM_VOL		69
#define PGAR_2_HPRCOM_VOL		70
#define DACR1_2_HPRCOM_VOL		71
#define HPRCOM_CTRL			72
/* Mono Line Output Plus/Minus control registers */
#define LINE2L_2_MONOLOPM_VOL		73
#define PGAL_2_MONOLOPM_VOL		74
#define DACL1_2_MONOLOPM_VOL		75
#define LINE2R_2_MONOLOPM_VOL		76
#define PGAR_2_MONOLOPM_VOL		77
#define DACR1_2_MONOLOPM_VOL		78
#define MONOLOPM_CTRL			79
/* Class-D speaker driver on tlv320aic3007 */
#define CLASSD_CTRL			73
/* Left Line Output Plus/Minus control registers */
#define LINE2L_2_LLOPM_VOL		80
#define PGAL_2_LLOPM_VOL		81
#define DACL1_2_LLOPM_VOL		82
#define LINE2R_2_LLOPM_VOL		83
#define PGAR_2_LLOPM_VOL		84
#define DACR1_2_LLOPM_VOL		85
#define LLOPM_CTRL			86
/* Right Line Output Plus/Minus control registers */
#define LINE2L_2_RLOPM_VOL		87
#define PGAL_2_RLOPM_VOL		88
#define DACL1_2_RLOPM_VOL		89
#define LINE2R_2_RLOPM_VOL		90
#define PGAR_2_RLOPM_VOL		91
#define DACR1_2_RLOPM_VOL		92
#define RLOPM_CTRL			93
/* GPIO/IRQ registers */
#define AIC3X_STICKY_IRQ_FLAGS_REG	96
#define AIC3X_RT_IRQ_FLAGS_REG		97
#define AIC3X_GPIO1_REG			98
#define AIC3X_GPIO2_REG			99
#define AIC3X_GPIOA_REG			100
#define AIC3X_GPIOB_REG			101
/* Clock generation control register */
#define AIC3X_CLKGEN_CTRL_REG		102

/* Page select register bits */
#define PAGE0_SELECT		0
#define PAGE1_SELECT		1

/* Audio serial data interface control register A bits */
#define BIT_CLK_MASTER          0x80
#define WORD_CLK_MASTER         0x40

/* Codec Datapath setup register 7 */
#define FSREF_44100		(1 << 7)
#define FSREF_48000		(0 << 7)
#define DUAL_RATE_MODE		((1 << 5) | (1 << 6))
#define LDAC2LCH		(0x1 << 3)
#define RDAC2RCH		(0x1 << 1)

/* PLL registers bitfields */
#define PLLP_SHIFT		0
#define PLLQ_SHIFT		3
#define PLLR_SHIFT		0
#define PLLJ_SHIFT		2
#define PLLD_MSB_SHIFT		0
#define PLLD_LSB_SHIFT		2

/* Clock generation register bits */
#define CODEC_CLKIN_PLLDIV	0
#define CODEC_CLKIN_CLKDIV	1
#define PLL_CLKIN_SHIFT		4
#define MCLK_SOURCE		0x0
#define PLL_CLKDIV_SHIFT	0

/* Software reset register bits */
#define SOFT_RESET		0x80

/* PLL progrramming register A bits */
#define PLL_ENABLE		0x80

/* Route bits */
#define ROUTE_ON		0x80

/* Mute bits */
#define UNMUTE			0x08
#define MUTE_ON			0x80

/* Power bits */
#define LADC_PWR_ON		0x04
#define RADC_PWR_ON		0x04
#define LDAC_PWR_ON		0x80
#define RDAC_PWR_ON		0x40
#define HPLOUT_PWR_ON		0x01
#define HPROUT_PWR_ON		0x01
#define HPLCOM_PWR_ON		0x01
#define HPRCOM_PWR_ON		0x01
#define MONOLOPM_PWR_ON		0x01
#define LLOPM_PWR_ON		0x01
#define RLOPM_PWR_ON	0x01

#define INVERT_VOL(val)   (0x7f - val)

/* Default output volume (inverted) */
#define DEFAULT_VOL     INVERT_VOL(0x50)
/* Default input volume */
#define DEFAULT_GAIN    0x20

void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);

/* headset detection / button API */

/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
 * and cellular headsets (GND + speaker output + microphone input).
 * It is recommended to enable MIC bias for this function to work properly.
 * For more information, please refer to the datasheet. */
enum {
	AIC3X_HEADSET_DETECT_OFF	= 0,
	AIC3X_HEADSET_DETECT_STEREO	= 1,
	AIC3X_HEADSET_DETECT_CELLULAR   = 2,
	AIC3X_HEADSET_DETECT_BOTH	= 3
};

enum {
	AIC3X_HEADSET_DEBOUNCE_16MS	= 0,
	AIC3X_HEADSET_DEBOUNCE_32MS	= 1,
	AIC3X_HEADSET_DEBOUNCE_64MS	= 2,
	AIC3X_HEADSET_DEBOUNCE_128MS	= 3,
	AIC3X_HEADSET_DEBOUNCE_256MS	= 4,
	AIC3X_HEADSET_DEBOUNCE_512MS	= 5
};

enum {
	AIC3X_BUTTON_DEBOUNCE_0MS	= 0,
	AIC3X_BUTTON_DEBOUNCE_8MS	= 1,
	AIC3X_BUTTON_DEBOUNCE_16MS	= 2,
	AIC3X_BUTTON_DEBOUNCE_32MS	= 3
};

#define AIC3X_HEADSET_DETECT_ENABLED	0x80
#define AIC3X_HEADSET_DETECT_SHIFT	5
#define AIC3X_HEADSET_DETECT_MASK	3
#define AIC3X_HEADSET_DEBOUNCE_SHIFT	2
#define AIC3X_HEADSET_DEBOUNCE_MASK	7
#define AIC3X_BUTTON_DEBOUNCE_SHIFT 	0
#define AIC3X_BUTTON_DEBOUNCE_MASK	3

/* see the enums above for valid parameters to this function */
void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
				 int headset_debounce, int button_debounce);
int aic3x_headset_detected(struct snd_soc_codec *codec);
int aic3x_button_pressed(struct snd_soc_codec *codec);

#endif /* _AIC3X_H */
Commit	Line	Data
44d0a879 VB	1	/*
	2	* ALSA SoC TLV320AIC3X codec driver
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef _AIC3X_H
	13	#define _AIC3X_H
	14
	15	/* AIC3X register space */
	16	#define AIC3X_CACHEREGNUM 103
	17
	18	/* Page select register */
	19	#define AIC3X_PAGE_SELECT 0
	20	/* Software reset register */
	21	#define AIC3X_RESET 1
	22	/* Codec Sample rate select register */
	23	#define AIC3X_SAMPLE_RATE_SEL_REG 2
	24	/* PLL progrramming register A */
	25	#define AIC3X_PLL_PROGA_REG 3
	26	/* PLL progrramming register B */
	27	#define AIC3X_PLL_PROGB_REG 4
	28	/* PLL progrramming register C */
	29	#define AIC3X_PLL_PROGC_REG 5
	30	/* PLL progrramming register D */
	31	#define AIC3X_PLL_PROGD_REG 6
	32	/* Codec datapath setup register */
	33	#define AIC3X_CODEC_DATAPATH_REG 7
	34	/* Audio serial data interface control register A */
	35	#define AIC3X_ASD_INTF_CTRLA 8
	36	/* Audio serial data interface control register B */
	37	#define AIC3X_ASD_INTF_CTRLB 9
a24f4f68 TK	38	/* Audio serial data interface control register C */
a24f4f68 TK	39	#define AIC3X_ASD_INTF_CTRLC 10
44d0a879 VB	40	/* Audio overflow status and PLL R value programming register */
44d0a879 VB	41	#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
4d20f70a JN	42	/* Audio codec digital filter control register */
4d20f70a JN	43	#define AIC3X_CODEC_DFILT_CTRL 12
6f2a974b DM	44	/* Headset/button press detection register */
	45	#define AIC3X_HEADSET_DETECT_CTRL_A 13
	46	#define AIC3X_HEADSET_DETECT_CTRL_B 14
44d0a879 VB	47	/* ADC PGA Gain control registers */
	48	#define LADC_VOL 15
	49	#define RADC_VOL 16
	50	/* MIC3 control registers */
	51	#define MIC3LR_2_LADC_CTRL 17
	52	#define MIC3LR_2_RADC_CTRL 18
	53	/* Line1 Input control registers */
	54	#define LINE1L_2_LADC_CTRL 19
54f01916	55	#define LINE1R_2_LADC_CTRL 21
44d0a879	56	#define LINE1R_2_RADC_CTRL 22
54f01916	57	#define LINE1L_2_RADC_CTRL 24
44d0a879 VB	58	/* Line2 Input control registers */
	59	#define LINE2L_2_LADC_CTRL 20
	60	#define LINE2R_2_RADC_CTRL 23
	61	/* MICBIAS Control Register */
	62	#define MICBIAS_CTRL 25
	63
	64	/* AGC Control Registers A, B, C */
	65	#define LAGC_CTRL_A 26
	66	#define LAGC_CTRL_B 27
	67	#define LAGC_CTRL_C 28
	68	#define RAGC_CTRL_A 29
	69	#define RAGC_CTRL_B 30
	70	#define RAGC_CTRL_C 31
	71
	72	/* DAC Power and Left High Power Output control registers */
	73	#define DAC_PWR 37
	74	#define HPLCOM_CFG 37
	75	/* Right High Power Output control registers */
	76	#define HPRCOM_CFG 38
	77	/* DAC Output Switching control registers */
	78	#define DAC_LINE_MUX 41
	79	/* High Power Output Driver Pop Reduction registers */
	80	#define HPOUT_POP_REDUCTION 42
	81	/* DAC Digital control registers */
	82	#define LDAC_VOL 43
	83	#define RDAC_VOL 44
b2eaac20	84	/* Left High Power Output control registers */
44d0a879	85	#define LINE2L_2_HPLOUT_VOL 45
44d0a879	86	#define PGAL_2_HPLOUT_VOL 46
44d0a879	87	#define DACL1_2_HPLOUT_VOL 47
c3b79e05	88	#define LINE2R_2_HPLOUT_VOL 48
b2eaac20	89	#define PGAR_2_HPLOUT_VOL 49
c3b79e05	90	#define DACR1_2_HPLOUT_VOL 50
44d0a879	91	#define HPLOUT_CTRL 51
b2eaac20	92	/* Left High Power COM control registers */
44d0a879	93	#define LINE2L_2_HPLCOM_VOL 52
44d0a879	94	#define PGAL_2_HPLCOM_VOL 53
b2eaac20	95	#define DACL1_2_HPLCOM_VOL 54
c3b79e05	96	#define LINE2R_2_HPLCOM_VOL 55
54f01916	97	#define PGAR_2_HPLCOM_VOL 56
c3b79e05	98	#define DACR1_2_HPLCOM_VOL 57
b2eaac20 JN	99	#define HPLCOM_CTRL 58
b2eaac20 JN	100	/* Right High Power Output control registers */
c3b79e05	101	#define LINE2L_2_HPROUT_VOL 59
b2eaac20	102	#define PGAL_2_HPROUT_VOL 60
c3b79e05	103	#define DACL1_2_HPROUT_VOL 61
b2eaac20 JN	104	#define LINE2R_2_HPROUT_VOL 62
	105	#define PGAR_2_HPROUT_VOL 63
	106	#define DACR1_2_HPROUT_VOL 64
	107	#define HPROUT_CTRL 65
	108	/* Right High Power COM control registers */
c3b79e05	109	#define LINE2L_2_HPRCOM_VOL 66
54f01916	110	#define PGAL_2_HPRCOM_VOL 67
c3b79e05	111	#define DACL1_2_HPRCOM_VOL 68
b2eaac20	112	#define LINE2R_2_HPRCOM_VOL 69
44d0a879	113	#define PGAR_2_HPRCOM_VOL 70
44d0a879	114	#define DACR1_2_HPRCOM_VOL 71
44d0a879 VB	115	#define HPRCOM_CTRL 72
	116	/* Mono Line Output Plus/Minus control registers */
	117	#define LINE2L_2_MONOLOPM_VOL 73
44d0a879	118	#define PGAL_2_MONOLOPM_VOL 74
44d0a879	119	#define DACL1_2_MONOLOPM_VOL 75
b2eaac20 JN	120	#define LINE2R_2_MONOLOPM_VOL 76
b2eaac20 JN	121	#define PGAR_2_MONOLOPM_VOL 77
44d0a879 VB	122	#define DACR1_2_MONOLOPM_VOL 78
44d0a879 VB	123	#define MONOLOPM_CTRL 79
6184f105 RC	124	/* Class-D speaker driver on tlv320aic3007 */
6184f105 RC	125	#define CLASSD_CTRL 73
b2eaac20	126	/* Left Line Output Plus/Minus control registers */
44d0a879	127	#define LINE2L_2_LLOPM_VOL 80
44d0a879	128	#define PGAL_2_LLOPM_VOL 81
44d0a879	129	#define DACL1_2_LLOPM_VOL 82
b2eaac20 JN	130	#define LINE2R_2_LLOPM_VOL 83
b2eaac20 JN	131	#define PGAR_2_LLOPM_VOL 84
54f01916	132	#define DACR1_2_LLOPM_VOL 85
44d0a879	133	#define LLOPM_CTRL 86
b2eaac20 JN	134	/* Right Line Output Plus/Minus control registers */
	135	#define LINE2L_2_RLOPM_VOL 87
	136	#define PGAL_2_RLOPM_VOL 88
	137	#define DACL1_2_RLOPM_VOL 89
	138	#define LINE2R_2_RLOPM_VOL 90
	139	#define PGAR_2_RLOPM_VOL 91
	140	#define DACR1_2_RLOPM_VOL 92
44d0a879	141	#define RLOPM_CTRL 93
54e7e616 DM	142	/* GPIO/IRQ registers */
	143	#define AIC3X_STICKY_IRQ_FLAGS_REG 96
	144	#define AIC3X_RT_IRQ_FLAGS_REG 97
	145	#define AIC3X_GPIO1_REG 98
	146	#define AIC3X_GPIO2_REG 99
	147	#define AIC3X_GPIOA_REG 100
4f9c16cc	148	#define AIC3X_GPIOB_REG 101
54e7e616	149	/* Clock generation control register */
44d0a879 VB	150	#define AIC3X_CLKGEN_CTRL_REG 102
	151
	152	/* Page select register bits */
	153	#define PAGE0_SELECT 0
	154	#define PAGE1_SELECT 1
	155
	156	/* Audio serial data interface control register A bits */
	157	#define BIT_CLK_MASTER 0x80
	158	#define WORD_CLK_MASTER 0x40
	159
	160	/* Codec Datapath setup register 7 */
	161	#define FSREF_44100 (1 << 7)
	162	#define FSREF_48000 (0 << 7)
	163	#define DUAL_RATE_MODE ((1 << 5) \| (1 << 6))
	164	#define LDAC2LCH (0x1 << 3)
	165	#define RDAC2RCH (0x1 << 1)
	166
	167	/* PLL registers bitfields */
	168	#define PLLP_SHIFT 0
4f9c16cc	169	#define PLLQ_SHIFT 3
44d0a879 VB	170	#define PLLR_SHIFT 0
	171	#define PLLJ_SHIFT 2
	172	#define PLLD_MSB_SHIFT 0
	173	#define PLLD_LSB_SHIFT 2
	174
	175	/* Clock generation register bits */
4f9c16cc DM	176	#define CODEC_CLKIN_PLLDIV 0
4f9c16cc DM	177	#define CODEC_CLKIN_CLKDIV 1
44d0a879 VB	178	#define PLL_CLKIN_SHIFT 4
	179	#define MCLK_SOURCE 0x0
	180	#define PLL_CLKDIV_SHIFT 0
	181
	182	/* Software reset register bits */
	183	#define SOFT_RESET 0x80
	184
	185	/* PLL progrramming register A bits */
	186	#define PLL_ENABLE 0x80
	187
	188	/* Route bits */
	189	#define ROUTE_ON 0x80
	190
	191	/* Mute bits */
	192	#define UNMUTE 0x08
	193	#define MUTE_ON 0x80
	194
	195	/* Power bits */
	196	#define LADC_PWR_ON 0x04
	197	#define RADC_PWR_ON 0x04
	198	#define LDAC_PWR_ON 0x80
	199	#define RDAC_PWR_ON 0x40
	200	#define HPLOUT_PWR_ON 0x01
	201	#define HPROUT_PWR_ON 0x01
	202	#define HPLCOM_PWR_ON 0x01
	203	#define HPRCOM_PWR_ON 0x01
	204	#define MONOLOPM_PWR_ON 0x01
	205	#define LLOPM_PWR_ON 0x01
	206	#define RLOPM_PWR_ON 0x01
	207
	208	#define INVERT_VOL(val) (0x7f - val)
	209
	210	/* Default output volume (inverted) */
	211	#define DEFAULT_VOL INVERT_VOL(0x50)
	212	/* Default input volume */
	213	#define DEFAULT_GAIN 0x20
	214
54e7e616 DM	215	void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
54e7e616 DM	216	int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
6f2a974b DM	217
	218	/* headset detection / button API */
	219
	220	/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
	221	* and cellular headsets (GND + speaker output + microphone input).
	222	* It is recommended to enable MIC bias for this function to work properly.
	223	* For more information, please refer to the datasheet. */
	224	enum {
	225	AIC3X_HEADSET_DETECT_OFF = 0,
	226	AIC3X_HEADSET_DETECT_STEREO = 1,
	227	AIC3X_HEADSET_DETECT_CELLULAR = 2,
	228	AIC3X_HEADSET_DETECT_BOTH = 3
	229	};
	230
	231	enum {
	232	AIC3X_HEADSET_DEBOUNCE_16MS = 0,
	233	AIC3X_HEADSET_DEBOUNCE_32MS = 1,
	234	AIC3X_HEADSET_DEBOUNCE_64MS = 2,
	235	AIC3X_HEADSET_DEBOUNCE_128MS = 3,
	236	AIC3X_HEADSET_DEBOUNCE_256MS = 4,
	237	AIC3X_HEADSET_DEBOUNCE_512MS = 5
	238	};
	239
	240	enum {
	241	AIC3X_BUTTON_DEBOUNCE_0MS = 0,
	242	AIC3X_BUTTON_DEBOUNCE_8MS = 1,
	243	AIC3X_BUTTON_DEBOUNCE_16MS = 2,
	244	AIC3X_BUTTON_DEBOUNCE_32MS = 3
	245	};
	246
	247	#define AIC3X_HEADSET_DETECT_ENABLED 0x80
	248	#define AIC3X_HEADSET_DETECT_SHIFT 5
	249	#define AIC3X_HEADSET_DETECT_MASK 3
	250	#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
	251	#define AIC3X_HEADSET_DEBOUNCE_MASK 7
	252	#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
	253	#define AIC3X_BUTTON_DEBOUNCE_MASK 3
	254
	255	/* see the enums above for valid parameters to this function */
	256	void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
	257	int headset_debounce, int button_debounce);
54e7e616	258	int aic3x_headset_detected(struct snd_soc_codec *codec);
6f2a974b	259	int aic3x_button_pressed(struct snd_soc_codec *codec);
54e7e616	260
44d0a879	261	#endif /* _AIC3X_H */