[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.h

/*
 * ALSA SoC TLV320AIC3X codec driver
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _AIC3X_H
#define _AIC3X_H

/* AIC3X register space */
#define AIC3X_CACHEREGNUM		103

/* Page select register */
#define AIC3X_PAGE_SELECT		0
/* Software reset register */
#define AIC3X_RESET			1
/* Codec Sample rate select register */
#define AIC3X_SAMPLE_RATE_SEL_REG	2
/* PLL progrramming register A */
#define AIC3X_PLL_PROGA_REG		3
/* PLL progrramming register B */
#define AIC3X_PLL_PROGB_REG		4
/* PLL progrramming register C */
#define AIC3X_PLL_PROGC_REG		5
/* PLL progrramming register D */
#define AIC3X_PLL_PROGD_REG		6
/* Codec datapath setup register */
#define AIC3X_CODEC_DATAPATH_REG	7
/* Audio serial data interface control register A */
#define AIC3X_ASD_INTF_CTRLA		8
/* Audio serial data interface control register B */
#define AIC3X_ASD_INTF_CTRLB		9
/* Audio overflow status and PLL R value programming register */
#define AIC3X_OVRF_STATUS_AND_PLLR_REG	11
/* Audio codec digital filter control register */
#define AIC3X_CODEC_DFILT_CTRL		12

/* ADC PGA Gain control registers */
#define LADC_VOL			15
#define RADC_VOL			16
/* MIC3 control registers */
#define MIC3LR_2_LADC_CTRL		17
#define MIC3LR_2_RADC_CTRL		18
/* Line1 Input control registers */
#define LINE1L_2_LADC_CTRL		19
#define LINE1R_2_LADC_CTRL		21
#define LINE1R_2_RADC_CTRL		22
#define LINE1L_2_RADC_CTRL		24
/* Line2 Input control registers */
#define LINE2L_2_LADC_CTRL		20
#define LINE2R_2_RADC_CTRL		23
/* MICBIAS Control Register */
#define MICBIAS_CTRL			25

/* AGC Control Registers A, B, C */
#define LAGC_CTRL_A			26
#define LAGC_CTRL_B			27
#define LAGC_CTRL_C			28
#define RAGC_CTRL_A			29
#define RAGC_CTRL_B			30
#define RAGC_CTRL_C			31

/* DAC Power and Left High Power Output control registers */
#define DAC_PWR				37
#define HPLCOM_CFG			37
/* Right High Power Output control registers */
#define HPRCOM_CFG			38
/* DAC Output Switching control registers */
#define DAC_LINE_MUX			41
/* High Power Output Driver Pop Reduction registers */
#define HPOUT_POP_REDUCTION		42
/* DAC Digital control registers */
#define LDAC_VOL			43
#define RDAC_VOL			44
/* High Power Output control registers */
#define LINE2L_2_HPLOUT_VOL		45
#define LINE2R_2_HPROUT_VOL		62
#define PGAL_2_HPLOUT_VOL		46
#define PGAL_2_HPROUT_VOL		60
#define PGAR_2_HPLOUT_VOL		49
#define PGAR_2_HPROUT_VOL		63
#define DACL1_2_HPLOUT_VOL		47
#define DACR1_2_HPROUT_VOL		64
#define HPLOUT_CTRL			51
#define HPROUT_CTRL			65
/* High Power COM control registers */
#define LINE2L_2_HPLCOM_VOL		52
#define LINE2R_2_HPRCOM_VOL		69
#define PGAL_2_HPLCOM_VOL		53
#define PGAR_2_HPLCOM_VOL		56
#define PGAL_2_HPRCOM_VOL		67
#define PGAR_2_HPRCOM_VOL		70
#define DACL1_2_HPLCOM_VOL		54
#define DACR1_2_HPRCOM_VOL		71
#define HPLCOM_CTRL			58
#define HPRCOM_CTRL			72
/* Mono Line Output Plus/Minus control registers */
#define LINE2L_2_MONOLOPM_VOL		73
#define LINE2R_2_MONOLOPM_VOL		76
#define PGAL_2_MONOLOPM_VOL		74
#define PGAR_2_MONOLOPM_VOL		77
#define DACL1_2_MONOLOPM_VOL		75
#define DACR1_2_MONOLOPM_VOL		78
#define MONOLOPM_CTRL			79
/* Line Output Plus/Minus control registers */
#define LINE2L_2_LLOPM_VOL		80
#define LINE2L_2_RLOPM_VOL		87
#define LINE2R_2_LLOPM_VOL		83
#define LINE2R_2_RLOPM_VOL		90
#define PGAL_2_LLOPM_VOL		81
#define PGAL_2_RLOPM_VOL		88
#define PGAR_2_LLOPM_VOL		84
#define PGAR_2_RLOPM_VOL		91
#define DACL1_2_LLOPM_VOL		82
#define DACL1_2_RLOPM_VOL		89
#define DACR1_2_RLOPM_VOL		92
#define DACR1_2_LLOPM_VOL		85
#define LLOPM_CTRL			86
#define RLOPM_CTRL			93
/* GPIO/IRQ registers */
#define AIC3X_STICKY_IRQ_FLAGS_REG	96
#define AIC3X_RT_IRQ_FLAGS_REG		97
#define AIC3X_GPIO1_REG			98
#define AIC3X_GPIO2_REG			99
#define AIC3X_GPIOA_REG			100
#define AIC3X_GPIOB_REG			101
/* Clock generation control register */
#define AIC3X_CLKGEN_CTRL_REG		102

/* Page select register bits */
#define PAGE0_SELECT		0
#define PAGE1_SELECT		1

/* Audio serial data interface control register A bits */
#define BIT_CLK_MASTER          0x80
#define WORD_CLK_MASTER         0x40

/* Codec Datapath setup register 7 */
#define FSREF_44100		(1 << 7)
#define FSREF_48000		(0 << 7)
#define DUAL_RATE_MODE		((1 << 5) | (1 << 6))
#define LDAC2LCH		(0x1 << 3)
#define RDAC2RCH		(0x1 << 1)

/* PLL registers bitfields */
#define PLLP_SHIFT		0
#define PLLQ_SHIFT		3
#define PLLR_SHIFT		0
#define PLLJ_SHIFT		2
#define PLLD_MSB_SHIFT		0
#define PLLD_LSB_SHIFT		2

/* Clock generation register bits */
#define CODEC_CLKIN_PLLDIV	0
#define CODEC_CLKIN_CLKDIV	1
#define PLL_CLKIN_SHIFT		4
#define MCLK_SOURCE		0x0
#define PLL_CLKDIV_SHIFT	0

/* Software reset register bits */
#define SOFT_RESET		0x80

/* PLL progrramming register A bits */
#define PLL_ENABLE		0x80

/* Route bits */
#define ROUTE_ON		0x80

/* Mute bits */
#define UNMUTE			0x08
#define MUTE_ON			0x80

/* Power bits */
#define LADC_PWR_ON		0x04
#define RADC_PWR_ON		0x04
#define LDAC_PWR_ON		0x80
#define RDAC_PWR_ON		0x40
#define HPLOUT_PWR_ON		0x01
#define HPROUT_PWR_ON		0x01
#define HPLCOM_PWR_ON		0x01
#define HPRCOM_PWR_ON		0x01
#define MONOLOPM_PWR_ON		0x01
#define LLOPM_PWR_ON		0x01
#define RLOPM_PWR_ON	0x01

#define INVERT_VOL(val)   (0x7f - val)

/* Default output volume (inverted) */
#define DEFAULT_VOL     INVERT_VOL(0x50)
/* Default input volume */
#define DEFAULT_GAIN    0x20

/* GPIO API */
enum {
	AIC3X_GPIO1_FUNC_DISABLED		= 0,
	AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC	= 1,
	AIC3X_GPIO1_FUNC_CLOCK_MUX		= 2,
	AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2		= 3,
	AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4		= 4,
	AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8		= 5,
	AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ	= 6,
	AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ		= 7,
	AIC3X_GPIO1_FUNC_INPUT			= 8,
	AIC3X_GPIO1_FUNC_OUTPUT			= 9,
	AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK	= 10,
	AIC3X_GPIO1_FUNC_AUDIO_WORDCLK		= 11,
	AIC3X_GPIO1_FUNC_BUTTON_IRQ		= 12,
	AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ	= 13,
	AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ	= 14,
	AIC3X_GPIO1_FUNC_ALL_IRQ		= 16
};

enum {
	AIC3X_GPIO2_FUNC_DISABLED		= 0,
	AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ	= 2,
	AIC3X_GPIO2_FUNC_INPUT			= 3,
	AIC3X_GPIO2_FUNC_OUTPUT			= 4,
	AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT	= 5,
	AIC3X_GPIO2_FUNC_AUDIO_BITCLK		= 8,
	AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
	AIC3X_GPIO2_FUNC_ALL_IRQ		= 10,
	AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
	AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
	AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ	= 13,
	AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ		= 14,
	AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ	= 15
};

void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
int aic3x_headset_detected(struct snd_soc_codec *codec);

struct aic3x_setup_data {
	int i2c_bus;
	unsigned short i2c_address;
	unsigned int gpio_func[2];
};

extern struct snd_soc_dai aic3x_dai;
extern struct snd_soc_codec_device soc_codec_dev_aic3x;

#endif /* _AIC3X_H */
Commit	Line	Data
44d0a879 VB	1	/*
	2	* ALSA SoC TLV320AIC3X codec driver
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef _AIC3X_H
	13	#define _AIC3X_H
	14
	15	/* AIC3X register space */
	16	#define AIC3X_CACHEREGNUM 103
	17
	18	/* Page select register */
	19	#define AIC3X_PAGE_SELECT 0
	20	/* Software reset register */
	21	#define AIC3X_RESET 1
	22	/* Codec Sample rate select register */
	23	#define AIC3X_SAMPLE_RATE_SEL_REG 2
	24	/* PLL progrramming register A */
	25	#define AIC3X_PLL_PROGA_REG 3
	26	/* PLL progrramming register B */
	27	#define AIC3X_PLL_PROGB_REG 4
	28	/* PLL progrramming register C */
	29	#define AIC3X_PLL_PROGC_REG 5
	30	/* PLL progrramming register D */
	31	#define AIC3X_PLL_PROGD_REG 6
	32	/* Codec datapath setup register */
	33	#define AIC3X_CODEC_DATAPATH_REG 7
	34	/* Audio serial data interface control register A */
	35	#define AIC3X_ASD_INTF_CTRLA 8
	36	/* Audio serial data interface control register B */
	37	#define AIC3X_ASD_INTF_CTRLB 9
	38	/* Audio overflow status and PLL R value programming register */
	39	#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
4d20f70a JN	40	/* Audio codec digital filter control register */
4d20f70a JN	41	#define AIC3X_CODEC_DFILT_CTRL 12
44d0a879 VB	42
	43	/* ADC PGA Gain control registers */
	44	#define LADC_VOL 15
	45	#define RADC_VOL 16
	46	/* MIC3 control registers */
	47	#define MIC3LR_2_LADC_CTRL 17
	48	#define MIC3LR_2_RADC_CTRL 18
	49	/* Line1 Input control registers */
	50	#define LINE1L_2_LADC_CTRL 19
54f01916	51	#define LINE1R_2_LADC_CTRL 21
44d0a879	52	#define LINE1R_2_RADC_CTRL 22
54f01916	53	#define LINE1L_2_RADC_CTRL 24
44d0a879 VB	54	/* Line2 Input control registers */
	55	#define LINE2L_2_LADC_CTRL 20
	56	#define LINE2R_2_RADC_CTRL 23
	57	/* MICBIAS Control Register */
	58	#define MICBIAS_CTRL 25
	59
	60	/* AGC Control Registers A, B, C */
	61	#define LAGC_CTRL_A 26
	62	#define LAGC_CTRL_B 27
	63	#define LAGC_CTRL_C 28
	64	#define RAGC_CTRL_A 29
	65	#define RAGC_CTRL_B 30
	66	#define RAGC_CTRL_C 31
	67
	68	/* DAC Power and Left High Power Output control registers */
	69	#define DAC_PWR 37
	70	#define HPLCOM_CFG 37
	71	/* Right High Power Output control registers */
	72	#define HPRCOM_CFG 38
	73	/* DAC Output Switching control registers */
	74	#define DAC_LINE_MUX 41
	75	/* High Power Output Driver Pop Reduction registers */
	76	#define HPOUT_POP_REDUCTION 42
	77	/* DAC Digital control registers */
	78	#define LDAC_VOL 43
	79	#define RDAC_VOL 44
	80	/* High Power Output control registers */
	81	#define LINE2L_2_HPLOUT_VOL 45
	82	#define LINE2R_2_HPROUT_VOL 62
	83	#define PGAL_2_HPLOUT_VOL 46
54f01916 DM	84	#define PGAL_2_HPROUT_VOL 60
54f01916 DM	85	#define PGAR_2_HPLOUT_VOL 49
44d0a879 VB	86	#define PGAR_2_HPROUT_VOL 63
	87	#define DACL1_2_HPLOUT_VOL 47
	88	#define DACR1_2_HPROUT_VOL 64
	89	#define HPLOUT_CTRL 51
	90	#define HPROUT_CTRL 65
	91	/* High Power COM control registers */
	92	#define LINE2L_2_HPLCOM_VOL 52
	93	#define LINE2R_2_HPRCOM_VOL 69
	94	#define PGAL_2_HPLCOM_VOL 53
54f01916 DM	95	#define PGAR_2_HPLCOM_VOL 56
54f01916 DM	96	#define PGAL_2_HPRCOM_VOL 67
44d0a879 VB	97	#define PGAR_2_HPRCOM_VOL 70
	98	#define DACL1_2_HPLCOM_VOL 54
	99	#define DACR1_2_HPRCOM_VOL 71
	100	#define HPLCOM_CTRL 58
	101	#define HPRCOM_CTRL 72
	102	/* Mono Line Output Plus/Minus control registers */
	103	#define LINE2L_2_MONOLOPM_VOL 73
	104	#define LINE2R_2_MONOLOPM_VOL 76
	105	#define PGAL_2_MONOLOPM_VOL 74
	106	#define PGAR_2_MONOLOPM_VOL 77
	107	#define DACL1_2_MONOLOPM_VOL 75
	108	#define DACR1_2_MONOLOPM_VOL 78
	109	#define MONOLOPM_CTRL 79
	110	/* Line Output Plus/Minus control registers */
	111	#define LINE2L_2_LLOPM_VOL 80
54f01916 DM	112	#define LINE2L_2_RLOPM_VOL 87
54f01916 DM	113	#define LINE2R_2_LLOPM_VOL 83
44d0a879 VB	114	#define LINE2R_2_RLOPM_VOL 90
44d0a879 VB	115	#define PGAL_2_LLOPM_VOL 81
54f01916 DM	116	#define PGAL_2_RLOPM_VOL 88
54f01916 DM	117	#define PGAR_2_LLOPM_VOL 84
44d0a879 VB	118	#define PGAR_2_RLOPM_VOL 91
44d0a879 VB	119	#define DACL1_2_LLOPM_VOL 82
54f01916	120	#define DACL1_2_RLOPM_VOL 89
44d0a879	121	#define DACR1_2_RLOPM_VOL 92
54f01916	122	#define DACR1_2_LLOPM_VOL 85
44d0a879 VB	123	#define LLOPM_CTRL 86
44d0a879 VB	124	#define RLOPM_CTRL 93
54e7e616 DM	125	/* GPIO/IRQ registers */
	126	#define AIC3X_STICKY_IRQ_FLAGS_REG 96
	127	#define AIC3X_RT_IRQ_FLAGS_REG 97
	128	#define AIC3X_GPIO1_REG 98
	129	#define AIC3X_GPIO2_REG 99
	130	#define AIC3X_GPIOA_REG 100
4f9c16cc	131	#define AIC3X_GPIOB_REG 101
54e7e616	132	/* Clock generation control register */
44d0a879 VB	133	#define AIC3X_CLKGEN_CTRL_REG 102
	134
	135	/* Page select register bits */
	136	#define PAGE0_SELECT 0
	137	#define PAGE1_SELECT 1
	138
	139	/* Audio serial data interface control register A bits */
	140	#define BIT_CLK_MASTER 0x80
	141	#define WORD_CLK_MASTER 0x40
	142
	143	/* Codec Datapath setup register 7 */
	144	#define FSREF_44100 (1 << 7)
	145	#define FSREF_48000 (0 << 7)
	146	#define DUAL_RATE_MODE ((1 << 5) \| (1 << 6))
	147	#define LDAC2LCH (0x1 << 3)
	148	#define RDAC2RCH (0x1 << 1)
	149
	150	/* PLL registers bitfields */
	151	#define PLLP_SHIFT 0
4f9c16cc	152	#define PLLQ_SHIFT 3
44d0a879 VB	153	#define PLLR_SHIFT 0
	154	#define PLLJ_SHIFT 2
	155	#define PLLD_MSB_SHIFT 0
	156	#define PLLD_LSB_SHIFT 2
	157
	158	/* Clock generation register bits */
4f9c16cc DM	159	#define CODEC_CLKIN_PLLDIV 0
4f9c16cc DM	160	#define CODEC_CLKIN_CLKDIV 1
44d0a879 VB	161	#define PLL_CLKIN_SHIFT 4
	162	#define MCLK_SOURCE 0x0
	163	#define PLL_CLKDIV_SHIFT 0
	164
	165	/* Software reset register bits */
	166	#define SOFT_RESET 0x80
	167
	168	/* PLL progrramming register A bits */
	169	#define PLL_ENABLE 0x80
	170
	171	/* Route bits */
	172	#define ROUTE_ON 0x80
	173
	174	/* Mute bits */
	175	#define UNMUTE 0x08
	176	#define MUTE_ON 0x80
	177
	178	/* Power bits */
	179	#define LADC_PWR_ON 0x04
	180	#define RADC_PWR_ON 0x04
	181	#define LDAC_PWR_ON 0x80
	182	#define RDAC_PWR_ON 0x40
	183	#define HPLOUT_PWR_ON 0x01
	184	#define HPROUT_PWR_ON 0x01
	185	#define HPLCOM_PWR_ON 0x01
	186	#define HPRCOM_PWR_ON 0x01
	187	#define MONOLOPM_PWR_ON 0x01
	188	#define LLOPM_PWR_ON 0x01
	189	#define RLOPM_PWR_ON 0x01
	190
	191	#define INVERT_VOL(val) (0x7f - val)
	192
	193	/* Default output volume (inverted) */
	194	#define DEFAULT_VOL INVERT_VOL(0x50)
	195	/* Default input volume */
	196	#define DEFAULT_GAIN 0x20
	197
54e7e616 DM	198	/* GPIO API */
	199	enum {
	200	AIC3X_GPIO1_FUNC_DISABLED = 0,
	201	AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,
	202	AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,
	203	AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,
	204	AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,
	205	AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,
	206	AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,
	207	AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,
	208	AIC3X_GPIO1_FUNC_INPUT = 8,
	209	AIC3X_GPIO1_FUNC_OUTPUT = 9,
	210	AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,
	211	AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,
	212	AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,
	213	AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,
	214	AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,
	215	AIC3X_GPIO1_FUNC_ALL_IRQ = 16
	216	};
	217
	218	enum {
	219	AIC3X_GPIO2_FUNC_DISABLED = 0,
	220	AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,
	221	AIC3X_GPIO2_FUNC_INPUT = 3,
	222	AIC3X_GPIO2_FUNC_OUTPUT = 4,
	223	AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,
	224	AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,
	225	AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
	226	AIC3X_GPIO2_FUNC_ALL_IRQ = 10,
	227	AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
	228	AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
	229	AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,
	230	AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,
	231	AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15
	232	};
	233
	234	void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
	235	int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
	236	int aic3x_headset_detected(struct snd_soc_codec *codec);
	237
44d0a879	238	struct aic3x_setup_data {
ba8ed121	239	int i2c_bus;
44d0a879	240	unsigned short i2c_address;
54e7e616	241	unsigned int gpio_func[2];
44d0a879 VB	242	};
44d0a879 VB	243
e550e17f	244	extern struct snd_soc_dai aic3x_dai;
44d0a879 VB	245	extern struct snd_soc_codec_device soc_codec_dev_aic3x;
	246
	247	#endif /* _AIC3X_H */