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Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
93864cf0 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
c8bf93f0
PU		 5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
c8bf93f0
PU		 30#include <linux/interrupt.h>
31#include <linux/gpio.h>
3a7aaed7 32#include <linux/regulator/consumer.h>
5a0e3ad6 33#include <linux/slab.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
c8bf93f0
PU		 38#include <sound/initval.h>
39#include <sound/tlv.h>
40
41#include <sound/tlv320dac33-plat.h>
42#include "tlv320dac33.h"
43
549675ed
PU		 44/*
45 * The internal FIFO is 24576 bytes long
46 * It can be configured to hold 16bit or 24bit samples
47 * In 16bit configuration the FIFO can hold 6144 stereo samples
48 * In 24bit configuration the FIFO can hold 4096 stereo samples
49 */
50#define DAC33_FIFO_SIZE_16BIT 6144
51#define DAC33_FIFO_SIZE_24BIT 4096
52#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
4260393e 53
76f47127
PU		 54#define BURST_BASEFREQ_HZ 49152000
55
f57d2cfa 56#define SAMPLES_TO_US(rate, samples) \
c29429f3 57 (1000000000 / (((rate) * 1000) / (samples)))
f57d2cfa
PU		 58
59#define US_TO_SAMPLES(rate, us) \
c29429f3 60 ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
f57d2cfa 61
a577b318 62#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
c29429f3 63 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
a577b318 64
e6968a17
MB		 65static void dac33_calculate_times(struct snd_pcm_substream *substream,
66 struct snd_soc_codec *codec);
67static int dac33_prepare_chip(struct snd_pcm_substream *substream,
68 struct snd_soc_codec *codec);
f57d2cfa 69
c8bf93f0
PU		 70enum dac33_state {
71 DAC33_IDLE = 0,
72 DAC33_PREFILL,
73 DAC33_PLAYBACK,
74 DAC33_FLUSH,
75};
76
7427b4b9
PU		 77enum dac33_fifo_modes {
78 DAC33_FIFO_BYPASS = 0,
79 DAC33_FIFO_MODE1,
28e05d98 80 DAC33_FIFO_MODE7,
7427b4b9
PU		 81 DAC33_FIFO_LAST_MODE,
82};
83
3a7aaed7
IK		 84#define DAC33_NUM_SUPPLIES 3
85static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
86 "AVDD",
87 "DVDD",
88 "IOVDD",
89};
90
c8bf93f0
PU		 91struct tlv320dac33_priv {
92 struct mutex mutex;
93 struct workqueue_struct *dac33_wq;
94 struct work_struct work;
f0fba2ad 95 struct snd_soc_codec *codec;
3a7aaed7 96 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 97 struct snd_pcm_substream *substream;
c8bf93f0
PU		 98 int power_gpio;
99 int chip_power;
100 int irq;
101 unsigned int refclk;
102
103 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
7427b4b9 104 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
549675ed 105 unsigned int fifo_size; /* Size of the FIFO in samples */
c8bf93f0 106 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 107 int mode1_latency; /* latency caused by the i2c writes in
108 * us */
6aceabb4 109 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 110 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 111
eeb309a8
PU		 112 int keep_bclk; /* Keep the BCLK continuously running
113 * in FIFO modes */
f57d2cfa
PU		 114 spinlock_t lock;
115 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
116 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
117
118 unsigned int mode1_us_burst; /* Time to burst read n number of
119 * samples */
120 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 121
9d7db2b2
PU		 122 unsigned int uthr;
123
c8bf93f0 124 enum dac33_state state;
f0fba2ad 125 void *control_data;
c8bf93f0
PU		 126};
127
128static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1290x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1300x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1310x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1320x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1330x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1340x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1350x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1360x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1370x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1380x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1390x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1400x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1410x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1420x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1430x00, 0x00, /* 0x38 - 0x39 */
144/* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
1460x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
1480x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1490x00, 0x80, /* 0x44 - 0x45 */
150/* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
1530x80, 0x00, 0x00, /* 0x48 - 0x4a */
154/* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
1560x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1570x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1580x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1590x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1600x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1610x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1620x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1630x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1640x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1650x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1660x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1670x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1680x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171};
172
173/* Register read and write */
174static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176{
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182}
183
184static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186{
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192}
193
194static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196{
b2c812e2 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
911a0f0b 198 int val, ret = 0;
c8bf93f0
PU		 199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
911a0f0b 208 ret = val;
c8bf93f0
PU		 209 } else {
210 value[0] = val;
211 dac33_write_reg_cache(codec, reg, val);
212 }
213 } else {
214 value[0] = dac33_read_reg_cache(codec, reg);
215 }
216
911a0f0b 217 return ret;
c8bf93f0
PU		 218}
219
220static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
221 unsigned int value)
222{
b2c812e2 223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 224 u8 data[2];
225 int ret = 0;
226
227 /*
228 * data is
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
231 */
232 data[0] = reg & 0xff;
233 data[1] = value & 0xff;
234
235 dac33_write_reg_cache(codec, data[0], data[1]);
236 if (dac33->chip_power) {
237 ret = codec->hw_write(codec->control_data, data, 2);
238 if (ret != 2)
239 dev_err(codec->dev, "Write failed (%d)\n", ret);
240 else
241 ret = 0;
242 }
243
244 return ret;
245}
246
247static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
248 unsigned int value)
249{
b2c812e2 250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 251 int ret;
252
253 mutex_lock(&dac33->mutex);
254 ret = dac33_write(codec, reg, value);
255 mutex_unlock(&dac33->mutex);
256
257 return ret;
258}
259
260#define DAC33_I2C_ADDR_AUTOINC 0x80
261static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
262 unsigned int value)
263{
b2c812e2 264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 265 u8 data[3];
266 int ret = 0;
267
268 /*
269 * data is
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
273 */
274 data[0] = reg & 0xff;
275 data[1] = (value >> 8) & 0xff;
276 data[2] = value & 0xff;
277
278 dac33_write_reg_cache(codec, data[0], data[1]);
279 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
280
281 if (dac33->chip_power) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data[0] |= DAC33_I2C_ADDR_AUTOINC;
284 ret = codec->hw_write(codec->control_data, data, 3);
285 if (ret != 3)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 else
288 ret = 0;
289 }
290
291 return ret;
292}
293
ef909d67 294static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 295{
b2c812e2 296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 297
ef909d67 298 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 299 return;
300
ef909d67
PU		 301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
305 DAC33_DACSRCL_LEFT);
306 /* C : (defaults) */
307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
308
ef909d67
PU		 309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
312
ef909d67
PU		 313 /* Restore only selected registers (gains mostly) */
314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
316 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
317 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
318
319 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
399b82e4
PU		 323
324 dac33_write(codec, DAC33_OUT_AMP_CTRL,
325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
326
56a3536c
PU		 327 dac33_write(codec, DAC33_LDAC_PWR_CTRL,
328 dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL));
329 dac33_write(codec, DAC33_RDAC_PWR_CTRL,
330 dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL));
c8bf93f0
PU		 331}
332
911a0f0b 333static inline int dac33_read_id(struct snd_soc_codec *codec)
239fe55c 334{
911a0f0b 335 int i, ret = 0;
239fe55c
PU		 336 u8 reg;
337
911a0f0b
PU		 338 for (i = 0; i < 3; i++) {
339 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
340 if (ret < 0)
341 break;
342 }
343
344 return ret;
c8bf93f0
PU		 345}
346
347static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
348{
349 u8 reg;
350
351 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
352 if (power)
353 reg |= DAC33_PDNALLB;
354 else
c3746a07
PU		 355 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
356 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 357 dac33_write(codec, DAC33_PWR_CTRL, reg);
358}
359
a6cea965
PU		 360static inline void dac33_disable_digital(struct snd_soc_codec *codec)
361{
362 u8 reg;
363
364 /* Stop the DAI clock */
365 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
366 reg &= ~DAC33_BCLKON;
367 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
368
369 /* Power down the Oscillator, and DACs */
370 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
371 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
372 dac33_write(codec, DAC33_PWR_CTRL, reg);
373}
374
3a7aaed7 375static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 376{
b2c812e2 377 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 378 int ret = 0;
c8bf93f0
PU		 379
380 mutex_lock(&dac33->mutex);
ad05c03b
PU		 381
382 /* Safety check */
383 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 384 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 385 power ? "ON" : "OFF");
386 goto exit;
387 }
388
c8bf93f0 389 if (power) {
3a7aaed7
IK		 390 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
391 dac33->supplies);
392 if (ret != 0) {
393 dev_err(codec->dev,
394 "Failed to enable supplies: %d\n", ret);
395 goto exit;
c8bf93f0 396 }
3a7aaed7
IK		 397
398 if (dac33->power_gpio >= 0)
399 gpio_set_value(dac33->power_gpio, 1);
400
401 dac33->chip_power = 1;
c8bf93f0
PU		 402 } else {
403 dac33_soft_power(codec, 0);
3a7aaed7 404 if (dac33->power_gpio >= 0)
c8bf93f0 405 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 406
407 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
408 dac33->supplies);
409 if (ret != 0) {
410 dev_err(codec->dev,
411 "Failed to disable supplies: %d\n", ret);
412 goto exit;
c8bf93f0 413 }
3a7aaed7
IK		 414
415 dac33->chip_power = 0;
c8bf93f0 416 }
c8bf93f0 417
3a7aaed7
IK		 418exit:
419 mutex_unlock(&dac33->mutex);
420 return ret;
c8bf93f0
PU		 421}
422
a6cea965 423static int dac33_playback_event(struct snd_soc_dapm_widget *w,
ad05c03b
PU		 424 struct snd_kcontrol *kcontrol, int event)
425{
c61ac6b7
LPC		 426 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
427 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b
PU		 428
429 switch (event) {
430 case SND_SOC_DAPM_PRE_PMU:
431 if (likely(dac33->substream)) {
c61ac6b7
LPC		 432 dac33_calculate_times(dac33->substream, codec);
433 dac33_prepare_chip(dac33->substream, codec);
ad05c03b
PU		 434 }
435 break;
a6cea965 436 case SND_SOC_DAPM_POST_PMD:
c61ac6b7 437 dac33_disable_digital(codec);
a6cea965 438 break;
ad05c03b
PU		 439 }
440 return 0;
441}
442
7427b4b9 443static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 444 struct snd_ctl_elem_value *ucontrol)
445{
ea53bf77 446 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 447 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 448
7427b4b9 449 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 450
451 return 0;
452}
453
7427b4b9 454static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 455 struct snd_ctl_elem_value *ucontrol)
456{
ea53bf77 457 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 458 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 459 int ret = 0;
460
7427b4b9 461 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 462 return 0;
463 /* Do not allow changes while stream is running*/
5c898e74 464 if (snd_soc_codec_is_active(codec))
c8bf93f0
PU		 465 return -EPERM;
466
467 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 468 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 469 ret = -EINVAL;
470 else
7427b4b9 471 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 472
473 return ret;
474}
475
7427b4b9
PU		 476/* Codec operation modes */
477static const char *dac33_fifo_mode_texts[] = {
28e05d98 478 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 479};
480
d77c290a 481static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts);
7427b4b9 482
cf4bb698
PU		 483/* L/R Line Output Gain */
484static const char *lr_lineout_gain_texts[] = {
485 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
486 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
487};
488
d77c290a
TI		 489static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum,
490 DAC33_LDAC_PWR_CTRL, 0,
491 lr_lineout_gain_texts);
cf4bb698 492
d77c290a
TI		 493static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum,
494 DAC33_RDAC_PWR_CTRL, 0,
495 lr_lineout_gain_texts);
cf4bb698 496
c8bf93f0
PU		 497/*
498 * DACL/R digital volume control:
499 * from 0 dB to -63.5 in 0.5 dB steps
500 * Need to be inverted later on:
501 * 0x00 == 0 dB
502 * 0x7f == -63.5 dB
503 */
504static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
505
506static const struct snd_kcontrol_new dac33_snd_controls[] = {
507 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
508 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
509 0, 0x7f, 1, dac_digivol_tlv),
510 SOC_DOUBLE_R("DAC Digital Playback Switch",
511 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
512 SOC_DOUBLE_R("Line to Line Out Volume",
513 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
cf4bb698
PU		 514 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
515 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
c8bf93f0
PU		 516};
517
a577b318
PU		 518static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
519 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
520 dac33_get_fifo_mode, dac33_set_fifo_mode),
521};
522
c8bf93f0
PU		 523/* Analog bypass */
524static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
525 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
526
527static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
528 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
529
399b82e4
PU		 530/* LOP L/R invert selection */
531static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
532
d77c290a
TI		 533static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum,
534 DAC33_OUT_AMP_CTRL, 3,
535 dac33_lr_lom_texts);
399b82e4
PU		 536
537static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
538SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
539
d77c290a
TI		 540static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum,
541 DAC33_OUT_AMP_CTRL, 2,
542 dac33_lr_lom_texts);
399b82e4
PU		 543
544static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
545SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
546
c8bf93f0
PU		 547static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
548 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
549 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
550
551 SND_SOC_DAPM_INPUT("LINEL"),
552 SND_SOC_DAPM_INPUT("LINER"),
553
76eac39c
PU		 554 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
555 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
c8bf93f0
PU		 556
557 /* Analog bypass */
558 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
559 &dac33_dapm_abypassl_control),
560 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
561 &dac33_dapm_abypassr_control),
562
399b82e4
PU		 563 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
564 &dac33_dapm_left_lom_control),
565 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
566 &dac33_dapm_right_lom_control),
567 /*
568 * For DAPM path, when only the anlog bypass path is enabled, and the
569 * LOP inverted from the corresponding DAC side.
570 * This is needed, so we can attach the DAC power supply in this case.
571 */
572 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
573 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
574
9e87186f 575 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
c8bf93f0 576 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
9e87186f 577 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
c8bf93f0 578 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b 579
76eac39c
PU		 580 SND_SOC_DAPM_SUPPLY("Left DAC Power",
581 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
582 SND_SOC_DAPM_SUPPLY("Right DAC Power",
583 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
584
4b8ffdb9
PU		 585 SND_SOC_DAPM_SUPPLY("Codec Power",
586 DAC33_PWR_CTRL, 4, 0, NULL, 0),
587
a6cea965
PU		 588 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
589 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
c8bf93f0
PU		 590};
591
592static const struct snd_soc_dapm_route audio_map[] = {
593 /* Analog bypass */
594 {"Analog Left Bypass", "Switch", "LINEL"},
595 {"Analog Right Bypass", "Switch", "LINER"},
596
9e87186f
PU		 597 {"Output Left Amplifier", NULL, "DACL"},
598 {"Output Right Amplifier", NULL, "DACR"},
c8bf93f0 599
399b82e4
PU		 600 {"Left Bypass PGA", NULL, "Analog Left Bypass"},
601 {"Right Bypass PGA", NULL, "Analog Right Bypass"},
602
603 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
604 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
605 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
606 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
607
608 {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
609 {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
610
611 {"DACL", NULL, "Left DAC Power"},
612 {"DACR", NULL, "Right DAC Power"},
c8bf93f0 613
399b82e4
PU		 614 {"Left Bypass PGA", NULL, "Left DAC Power"},
615 {"Right Bypass PGA", NULL, "Right DAC Power"},
76eac39c 616
c8bf93f0 617 /* output */
9e87186f
PU		 618 {"LEFT_LO", NULL, "Output Left Amplifier"},
619 {"RIGHT_LO", NULL, "Output Right Amplifier"},
4b8ffdb9
PU		 620
621 {"LEFT_LO", NULL, "Codec Power"},
622 {"RIGHT_LO", NULL, "Codec Power"},
c8bf93f0
PU		 623};
624
c8bf93f0
PU		 625static int dac33_set_bias_level(struct snd_soc_codec *codec,
626 enum snd_soc_bias_level level)
627{
3a7aaed7
IK		 628 int ret;
629
c8bf93f0
PU		 630 switch (level) {
631 case SND_SOC_BIAS_ON:
c8bf93f0
PU		 632 break;
633 case SND_SOC_BIAS_PREPARE:
634 break;
635 case SND_SOC_BIAS_STANDBY:
37e931c1 636 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
ad05c03b 637 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 638 ret = dac33_hard_power(codec, 1);
639 if (ret != 0)
640 return ret;
3a7aaed7 641
ad05c03b
PU		 642 dac33_init_chip(codec);
643 }
c8bf93f0
PU		 644 break;
645 case SND_SOC_BIAS_OFF:
2d4cdd6f 646 /* Do not power off, when the codec is already off */
37e931c1 647 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
2d4cdd6f 648 return 0;
3a7aaed7
IK		 649 ret = dac33_hard_power(codec, 0);
650 if (ret != 0)
651 return ret;
c8bf93f0
PU		 652 break;
653 }
c8bf93f0
PU		 654
655 return 0;
656}
657
d4f102d4
PU		 658static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
659{
f0fba2ad 660 struct snd_soc_codec *codec = dac33->codec;
84eae18c 661 unsigned int delay;
a3b55791 662 unsigned long flags;
d4f102d4
PU		 663
664 switch (dac33->fifo_mode) {
665 case DAC33_FIFO_MODE1:
666 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 667 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 668
669 /* Take the timestamps */
a3b55791 670 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 671 dac33->t_stamp2 = ktime_to_us(ktime_get());
672 dac33->t_stamp1 = dac33->t_stamp2;
a3b55791 673 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 674
d4f102d4
PU		 675 dac33_write16(codec, DAC33_PREFILL_MSB,
676 DAC33_THRREG(dac33->alarm_threshold));
f4d59328 677 /* Enable Alarm Threshold IRQ with a delay */
84eae18c
PU		 678 delay = SAMPLES_TO_US(dac33->burst_rate,
679 dac33->alarm_threshold) + 1000;
680 usleep_range(delay, delay + 500);
f4d59328 681 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 682 break;
28e05d98 683 case DAC33_FIFO_MODE7:
f57d2cfa 684 /* Take the timestamp */
a3b55791 685 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 686 dac33->t_stamp1 = ktime_to_us(ktime_get());
687 /* Move back the timestamp with drain time */
688 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
a3b55791 689 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 690
28e05d98 691 dac33_write16(codec, DAC33_PREFILL_MSB,
549675ed 692 DAC33_THRREG(DAC33_MODE7_MARGIN));
f57d2cfa
PU		 693
694 /* Enable Upper Threshold IRQ */
695 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 696 break;
d4f102d4
PU		 697 default:
698 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
699 dac33->fifo_mode);
700 break;
701 }
702}
703
704static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
705{
f0fba2ad 706 struct snd_soc_codec *codec = dac33->codec;
a3b55791 707 unsigned long flags;
d4f102d4
PU		 708
709 switch (dac33->fifo_mode) {
710 case DAC33_FIFO_MODE1:
f57d2cfa 711 /* Take the timestamp */
a3b55791 712 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 713 dac33->t_stamp2 = ktime_to_us(ktime_get());
a3b55791 714 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 715
d4f102d4
PU		 716 dac33_write16(codec, DAC33_NSAMPLE_MSB,
717 DAC33_THRREG(dac33->nsample));
718 break;
28e05d98
PU		 719 case DAC33_FIFO_MODE7:
720 /* At the moment we are not using interrupts in mode7 */
721 break;
d4f102d4
PU		 722 default:
723 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
724 dac33->fifo_mode);
725 break;
726 }
727}
728
c8bf93f0
PU		 729static void dac33_work(struct work_struct *work)
730{
731 struct snd_soc_codec *codec;
732 struct tlv320dac33_priv *dac33;
733 u8 reg;
734
735 dac33 = container_of(work, struct tlv320dac33_priv, work);
f0fba2ad 736 codec = dac33->codec;
c8bf93f0
PU		 737
738 mutex_lock(&dac33->mutex);
739 switch (dac33->state) {
740 case DAC33_PREFILL:
741 dac33->state = DAC33_PLAYBACK;
d4f102d4 742 dac33_prefill_handler(dac33);
c8bf93f0
PU		 743 break;
744 case DAC33_PLAYBACK:
d4f102d4 745 dac33_playback_handler(dac33);
c8bf93f0
PU		 746 break;
747 case DAC33_IDLE:
748 break;
749 case DAC33_FLUSH:
750 dac33->state = DAC33_IDLE;
751 /* Mask all interrupts from dac33 */
752 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
753
754 /* flush fifo */
755 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
756 reg |= DAC33_FIFOFLUSH;
757 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
758 break;
759 }
760 mutex_unlock(&dac33->mutex);
761}
762
763static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
764{
765 struct snd_soc_codec *codec = dev;
b2c812e2 766 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
a3b55791 767 unsigned long flags;
c8bf93f0 768
a3b55791 769 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 770 dac33->t_stamp1 = ktime_to_us(ktime_get());
a3b55791 771 spin_unlock_irqrestore(&dac33->lock, flags);
c8bf93f0 772
f57d2cfa
PU		 773 /* Do not schedule the workqueue in Mode7 */
774 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
775 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 776
c8bf93f0 777 return IRQ_HANDLED;
c8bf93f0
PU		 778}
779
780static void dac33_oscwait(struct snd_soc_codec *codec)
781{
84eae18c 782 int timeout = 60;
c8bf93f0
PU		 783 u8 reg;
784
785 do {
84eae18c 786 usleep_range(1000, 2000);
c8bf93f0
PU		 787 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
788 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
789 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
790 dev_err(codec->dev,
791 "internal oscillator calibration failed\n");
792}
793
0b61d2b9
PU		 794static int dac33_startup(struct snd_pcm_substream *substream,
795 struct snd_soc_dai *dai)
796{
e6968a17 797 struct snd_soc_codec *codec = dai->codec;
0b61d2b9
PU		 798 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
799
800 /* Stream started, save the substream pointer */
801 dac33->substream = substream;
802
803 return 0;
804}
805
806static void dac33_shutdown(struct snd_pcm_substream *substream,
807 struct snd_soc_dai *dai)
808{
e6968a17 809 struct snd_soc_codec *codec = dai->codec;
0b61d2b9
PU		 810 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
811
812 dac33->substream = NULL;
813}
814
549675ed
PU		 815#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
816 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
c8bf93f0
PU		 817static int dac33_hw_params(struct snd_pcm_substream *substream,
818 struct snd_pcm_hw_params *params,
819 struct snd_soc_dai *dai)
820{
e6968a17 821 struct snd_soc_codec *codec = dai->codec;
549675ed 822 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 823
824 /* Check parameters for validity */
825 switch (params_rate(params)) {
826 case 44100:
827 case 48000:
828 break;
829 default:
830 dev_err(codec->dev, "unsupported rate %d\n",
831 params_rate(params));
832 return -EINVAL;
833 }
834
c60f23cb
MB		 835 switch (params_width(params)) {
836 case 16:
549675ed
PU		 837 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
838 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
c8bf93f0 839 break;
c60f23cb 840 case 32:
0d99d2b0
PU		 841 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
842 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
843 break;
c8bf93f0 844 default:
c60f23cb
MB		 845 dev_err(codec->dev, "unsupported width %d\n",
846 params_width(params));
c8bf93f0
PU		 847 return -EINVAL;
848 }
849
850 return 0;
851}
852
853#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 854 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 855#define CALC_RATIOSET(rate, refclk) ( \
856 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
857
858/*
859 * tlv320dac33 is strict on the sequence of the register writes, if the register
860 * writes happens in different order, than dac33 might end up in unknown state.
861 * Use the known, working sequence of register writes to initialize the dac33.
862 */
e6968a17
MB		 863static int dac33_prepare_chip(struct snd_pcm_substream *substream,
864 struct snd_soc_codec *codec)
c8bf93f0 865{
b2c812e2 866 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 867 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 868 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 869
870 switch (substream->runtime->rate) {
871 case 44100:
872 case 48000:
873 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
874 ratioset = CALC_RATIOSET(substream->runtime->rate,
875 dac33->refclk);
876 break;
877 default:
878 dev_err(codec->dev, "unsupported rate %d\n",
879 substream->runtime->rate);
880 return -EINVAL;
881 }
882
883
884 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
885 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 886 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 887 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 888 fifoctrl_a &= ~DAC33_FIFOFLUSH;
889
c8bf93f0
PU		 890 fifoctrl_a &= ~DAC33_WIDTH;
891 switch (substream->runtime->format) {
892 case SNDRV_PCM_FORMAT_S16_LE:
893 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
894 fifoctrl_a |= DAC33_WIDTH;
895 break;
0d99d2b0
PU		 896 case SNDRV_PCM_FORMAT_S32_LE:
897 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
898 break;
c8bf93f0
PU		 899 default:
900 dev_err(codec->dev, "unsupported format %d\n",
901 substream->runtime->format);
902 return -EINVAL;
903 }
904
905 mutex_lock(&dac33->mutex);
ad05c03b
PU		 906
907 if (!dac33->chip_power) {
908 /*
909 * Chip is not powered yet.
910 * Do the init in the dac33_set_bias_level later.
911 */
912 mutex_unlock(&dac33->mutex);
913 return 0;
914 }
915
c3746a07 916 dac33_soft_power(codec, 0);
c8bf93f0
PU		 917 dac33_soft_power(codec, 1);
918
919 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
920 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
921
922 /* Write registers 0x08 and 0x09 (MSB, LSB) */
923 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
924
82a58a8b
PU		 925 /* OSC calibration time */
926 dac33_write(codec, DAC33_CALIB_TIME, 96);
c8bf93f0
PU		 927
928 /* adjustment treshold & step */
929 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
930 DAC33_ADJSTEP(1));
931
932 /* div=4 / gain=1 / div */
933 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
934
935 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
936 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
937 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
938
939 dac33_oscwait(codec);
940
7427b4b9 941 if (dac33->fifo_mode) {
aec242dc 942 /* Generic for all FIFO modes */
c8bf93f0 943 /* 50-51 : ASRC Control registers */
fdb6b1e1 944 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 945 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
946
947 /* Write registers 0x34 and 0x35 (MSB, LSB) */
948 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
949
950 /* Set interrupts to high active */
951 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 952 } else {
aec242dc 953 /* FIFO bypass mode */
c8bf93f0
PU		 954 /* 50-51 : ASRC Control registers */
955 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
956 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
957 }
958
aec242dc
PU		 959 /* Interrupt behaviour configuration */
960 switch (dac33->fifo_mode) {
961 case DAC33_FIFO_MODE1:
962 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
963 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 964 break;
28e05d98 965 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 966 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
967 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 968 break;
aec242dc
PU		 969 default:
970 /* in FIFO bypass mode, the interrupts are not used */
971 break;
972 }
973
974 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
975
976 switch (dac33->fifo_mode) {
977 case DAC33_FIFO_MODE1:
978 /*
979 * For mode1:
980 * Disable the FIFO bypass (Enable the use of FIFO)
981 * Select nSample mode
982 * BCLK is only running when data is needed by DAC33
983 */
c8bf93f0 984 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 985 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 986 if (dac33->keep_bclk)
987 aictrl_b |= DAC33_BCLKON;
988 else
989 aictrl_b &= ~DAC33_BCLKON;
aec242dc 990 break;
28e05d98
PU		 991 case DAC33_FIFO_MODE7:
992 /*
993 * For mode1:
994 * Disable the FIFO bypass (Enable the use of FIFO)
995 * Select Threshold mode
996 * BCLK is only running when data is needed by DAC33
997 */
998 fifoctrl_a &= ~DAC33_FBYPAS;
999 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 1000 if (dac33->keep_bclk)
1001 aictrl_b |= DAC33_BCLKON;
1002 else
1003 aictrl_b &= ~DAC33_BCLKON;
28e05d98 1004 break;
aec242dc
PU		 1005 default:
1006 /*
1007 * For FIFO bypass mode:
1008 * Enable the FIFO bypass (Disable the FIFO use)
25985edc 1009 * Set the BCLK as continuous
aec242dc 1010 */
c8bf93f0 1011 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 1012 aictrl_b |= DAC33_BCLKON;
1013 break;
1014 }
c8bf93f0 1015
aec242dc 1016 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 1017 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 1018 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 1019
6aceabb4
PU		 1020 /*
1021 * BCLK divide ratio
1022 * 0: 1.5
1023 * 1: 1
1024 * 2: 2
1025 * ...
1026 * 254: 254
1027 * 255: 255
1028 */
6cd6cede 1029 if (dac33->fifo_mode)
6aceabb4
PU		 1030 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1031 dac33->burst_bclkdiv);
6cd6cede 1032 else
0d99d2b0
PU		 1033 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1034 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1035 else
1036 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
c8bf93f0 1037
6cd6cede
PU		 1038 switch (dac33->fifo_mode) {
1039 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1040 dac33_write16(codec, DAC33_ATHR_MSB,
1041 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1042 break;
28e05d98
PU		 1043 case DAC33_FIFO_MODE7:
1044 /*
1045 * Configure the threshold levels, and leave 10 sample space
1046 * at the bottom, and also at the top of the FIFO
1047 */
9d7db2b2 1048 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
549675ed
PU		 1049 dac33_write16(codec, DAC33_LTHR_MSB,
1050 DAC33_THRREG(DAC33_MODE7_MARGIN));
28e05d98 1051 break;
aec242dc 1052 default:
aec242dc 1053 break;
c8bf93f0
PU		 1054 }
1055
1056 mutex_unlock(&dac33->mutex);
1057
1058 return 0;
1059}
1060
e6968a17
MB		 1061static void dac33_calculate_times(struct snd_pcm_substream *substream,
1062 struct snd_soc_codec *codec)
c8bf93f0 1063{
b2c812e2 1064 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1065 unsigned int period_size = substream->runtime->period_size;
1066 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1067 unsigned int nsample_limit;
1068
55abb59c
PU		 1069 /* In bypass mode we don't need to calculate */
1070 if (!dac33->fifo_mode)
1071 return;
1072
f57d2cfa
PU		 1073 switch (dac33->fifo_mode) {
1074 case DAC33_FIFO_MODE1:
f430a27f
PU		 1075 /* Number of samples under i2c latency */
1076 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1077 dac33->mode1_latency);
549675ed 1078 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1bc13b2e 1079
3591f4cd 1080 if (period_size <= dac33->alarm_threshold)
a577b318 1081 /*
3591f4cd
PU		 1082 * Configure nSamaple to number of periods,
1083 * which covers the latency requironment.
a577b318 1084 */
3591f4cd
PU		 1085 dac33->nsample = period_size *
1086 ((dac33->alarm_threshold / period_size) +
1087 (dac33->alarm_threshold % period_size ?
1088 1 : 0));
1089 else if (period_size > nsample_limit)
1090 dac33->nsample = nsample_limit;
1091 else
1092 dac33->nsample = period_size;
f430a27f 1093
f57d2cfa
PU		 1094 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1095 dac33->nsample);
1096 dac33->t_stamp1 = 0;
1097 dac33->t_stamp2 = 0;
1098 break;
1099 case DAC33_FIFO_MODE7:
3591f4cd
PU		 1100 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1101 dac33->burst_rate) + 9;
549675ed
PU		 1102 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1103 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1104 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1105 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
3591f4cd 1106
f57d2cfa 1107 dac33->mode7_us_to_lthr =
9d7db2b2 1108 SAMPLES_TO_US(substream->runtime->rate,
549675ed 1109 dac33->uthr - DAC33_MODE7_MARGIN + 1);
f57d2cfa
PU		 1110 dac33->t_stamp1 = 0;
1111 break;
1112 default:
1113 break;
1114 }
c8bf93f0 1115
c8bf93f0
PU		 1116}
1117
1118static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1119 struct snd_soc_dai *dai)
1120{
e6968a17 1121 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1122 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1123 int ret = 0;
1124
1125 switch (cmd) {
1126 case SNDRV_PCM_TRIGGER_START:
1127 case SNDRV_PCM_TRIGGER_RESUME:
1128 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1129 if (dac33->fifo_mode) {
c8bf93f0
PU		 1130 dac33->state = DAC33_PREFILL;
1131 queue_work(dac33->dac33_wq, &dac33->work);
1132 }
1133 break;
1134 case SNDRV_PCM_TRIGGER_STOP:
1135 case SNDRV_PCM_TRIGGER_SUSPEND:
1136 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1137 if (dac33->fifo_mode) {
c8bf93f0
PU		 1138 dac33->state = DAC33_FLUSH;
1139 queue_work(dac33->dac33_wq, &dac33->work);
1140 }
1141 break;
1142 default:
1143 ret = -EINVAL;
1144 }
1145
1146 return ret;
1147}
1148
f57d2cfa
PU		 1149static snd_pcm_sframes_t dac33_dai_delay(
1150 struct snd_pcm_substream *substream,
1151 struct snd_soc_dai *dai)
1152{
e6968a17 1153 struct snd_soc_codec *codec = dai->codec;
f57d2cfa
PU		 1154 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1155 unsigned long long t0, t1, t_now;
9d7db2b2 1156 unsigned int time_delta, uthr;
f57d2cfa
PU		 1157 int samples_out, samples_in, samples;
1158 snd_pcm_sframes_t delay = 0;
a3b55791 1159 unsigned long flags;
f57d2cfa
PU		 1160
1161 switch (dac33->fifo_mode) {
1162 case DAC33_FIFO_BYPASS:
1163 break;
1164 case DAC33_FIFO_MODE1:
a3b55791 1165 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 1166 t0 = dac33->t_stamp1;
1167 t1 = dac33->t_stamp2;
a3b55791 1168 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa
PU		 1169 t_now = ktime_to_us(ktime_get());
1170
1171 /* We have not started to fill the FIFO yet, delay is 0 */
1172 if (!t1)
1173 goto out;
1174
1175 if (t0 > t1) {
1176 /*
1177 * Phase 1:
1178 * After Alarm threshold, and before nSample write
1179 */
1180 time_delta = t_now - t0;
1181 samples_out = time_delta ? US_TO_SAMPLES(
1182 substream->runtime->rate,
1183 time_delta) : 0;
1184
1185 if (likely(dac33->alarm_threshold > samples_out))
1186 delay = dac33->alarm_threshold - samples_out;
1187 else
1188 delay = 0;
1189 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1190 /*
1191 * Phase 2:
1192 * After nSample write (during burst operation)
1193 */
1194 time_delta = t_now - t0;
1195 samples_out = time_delta ? US_TO_SAMPLES(
1196 substream->runtime->rate,
1197 time_delta) : 0;
1198
1199 time_delta = t_now - t1;
1200 samples_in = time_delta ? US_TO_SAMPLES(
1201 dac33->burst_rate,
1202 time_delta) : 0;
1203
1204 samples = dac33->alarm_threshold;
1205 samples += (samples_in - samples_out);
1206
1207 if (likely(samples > 0))
1208 delay = samples;
1209 else
1210 delay = 0;
1211 } else {
1212 /*
1213 * Phase 3:
1214 * After burst operation, before next alarm threshold
1215 */
1216 time_delta = t_now - t0;
1217 samples_out = time_delta ? US_TO_SAMPLES(
1218 substream->runtime->rate,
1219 time_delta) : 0;
1220
1221 samples_in = dac33->nsample;
1222 samples = dac33->alarm_threshold;
1223 samples += (samples_in - samples_out);
1224
1225 if (likely(samples > 0))
549675ed
PU		 1226 delay = samples > dac33->fifo_size ?
1227 dac33->fifo_size : samples;
f57d2cfa
PU		 1228 else
1229 delay = 0;
1230 }
1231 break;
1232 case DAC33_FIFO_MODE7:
a3b55791 1233 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 1234 t0 = dac33->t_stamp1;
9d7db2b2 1235 uthr = dac33->uthr;
a3b55791 1236 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa
PU		 1237 t_now = ktime_to_us(ktime_get());
1238
1239 /* We have not started to fill the FIFO yet, delay is 0 */
1240 if (!t0)
1241 goto out;
1242
1243 if (t_now <= t0) {
1244 /*
1245 * Either the timestamps are messed or equal. Report
1246 * maximum delay
1247 */
9d7db2b2 1248 delay = uthr;
f57d2cfa
PU		 1249 goto out;
1250 }
1251
1252 time_delta = t_now - t0;
1253 if (time_delta <= dac33->mode7_us_to_lthr) {
1254 /*
1255 * Phase 1:
1256 * After burst (draining phase)
1257 */
1258 samples_out = US_TO_SAMPLES(
1259 substream->runtime->rate,
1260 time_delta);
1261
9d7db2b2
PU		 1262 if (likely(uthr > samples_out))
1263 delay = uthr - samples_out;
f57d2cfa
PU		 1264 else
1265 delay = 0;
1266 } else {
1267 /*
1268 * Phase 2:
1269 * During burst operation
1270 */
1271 time_delta = time_delta - dac33->mode7_us_to_lthr;
1272
1273 samples_out = US_TO_SAMPLES(
1274 substream->runtime->rate,
1275 time_delta);
1276 samples_in = US_TO_SAMPLES(
1277 dac33->burst_rate,
1278 time_delta);
549675ed 1279 delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
f57d2cfa 1280
9d7db2b2
PU		 1281 if (unlikely(delay > uthr))
1282 delay = uthr;
f57d2cfa
PU		 1283 }
1284 break;
1285 default:
1286 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1287 dac33->fifo_mode);
1288 break;
1289 }
1290out:
1291 return delay;
1292}
1293
c8bf93f0
PU		 1294static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1295 int clk_id, unsigned int freq, int dir)
1296{
1297 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1298 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1299 u8 ioc_reg, asrcb_reg;
1300
1301 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1302 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1303 switch (clk_id) {
1304 case TLV320DAC33_MCLK:
1305 ioc_reg |= DAC33_REFSEL;
1306 asrcb_reg |= DAC33_SRCREFSEL;
1307 break;
1308 case TLV320DAC33_SLEEPCLK:
1309 ioc_reg &= ~DAC33_REFSEL;
1310 asrcb_reg &= ~DAC33_SRCREFSEL;
1311 break;
1312 default:
1313 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1314 break;
1315 }
1316 dac33->refclk = freq;
1317
1318 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1319 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1320
1321 return 0;
1322}
1323
1324static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1325 unsigned int fmt)
1326{
1327 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1328 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1329 u8 aictrl_a, aictrl_b;
1330
1331 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1332 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1333 /* set master/slave audio interface */
1334 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1335 case SND_SOC_DAIFMT_CBM_CFM:
1336 /* Codec Master */
1337 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1338 break;
1339 case SND_SOC_DAIFMT_CBS_CFS:
1340 /* Codec Slave */
adcb8bc0
PU		 1341 if (dac33->fifo_mode) {
1342 dev_err(codec->dev, "FIFO mode requires master mode\n");
1343 return -EINVAL;
1344 } else
1345 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1346 break;
1347 default:
1348 return -EINVAL;
1349 }
1350
1351 aictrl_a &= ~DAC33_AFMT_MASK;
1352 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1353 case SND_SOC_DAIFMT_I2S:
1354 aictrl_a |= DAC33_AFMT_I2S;
1355 break;
1356 case SND_SOC_DAIFMT_DSP_A:
1357 aictrl_a |= DAC33_AFMT_DSP;
1358 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1359 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1360 break;
1361 case SND_SOC_DAIFMT_RIGHT_J:
1362 aictrl_a |= DAC33_AFMT_RIGHT_J;
1363 break;
1364 case SND_SOC_DAIFMT_LEFT_J:
1365 aictrl_a |= DAC33_AFMT_LEFT_J;
1366 break;
1367 default:
1368 dev_err(codec->dev, "Unsupported format (%u)\n",
1369 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1370 return -EINVAL;
1371 }
1372
1373 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1374 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1375
1376 return 0;
1377}
1378
f0fba2ad 1379static int dac33_soc_probe(struct snd_soc_codec *codec)
c8bf93f0 1380{
f0fba2ad 1381 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1382 int ret = 0;
1383
f0fba2ad
LG		 1384 codec->control_data = dac33->control_data;
1385 codec->hw_write = (hw_write_t) i2c_master_send;
f0fba2ad 1386 dac33->codec = codec;
c8bf93f0 1387
f0fba2ad
LG		 1388 /* Read the tlv320dac33 ID registers */
1389 ret = dac33_hard_power(codec, 1);
1390 if (ret != 0) {
1391 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1392 goto err_power;
1393 }
911a0f0b 1394 ret = dac33_read_id(codec);
f0fba2ad 1395 dac33_hard_power(codec, 0);
c8bf93f0 1396
911a0f0b
PU		 1397 if (ret < 0) {
1398 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1399 ret = -ENODEV;
1400 goto err_power;
1401 }
1402
f0fba2ad
LG		 1403 /* Check if the IRQ number is valid and request it */
1404 if (dac33->irq >= 0) {
1405 ret = request_irq(dac33->irq, dac33_interrupt_handler,
88e24c3a 1406 IRQF_TRIGGER_RISING,
f4333203 1407 codec->component.name, codec);
f0fba2ad
LG		 1408 if (ret < 0) {
1409 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1410 dac33->irq, ret);
1411 dac33->irq = -1;
1412 }
1413 if (dac33->irq != -1) {
1414 /* Setup work queue */
1415 dac33->dac33_wq =
1416 create_singlethread_workqueue("tlv320dac33");
1417 if (dac33->dac33_wq == NULL) {
1418 free_irq(dac33->irq, codec);
1419 return -ENOMEM;
1420 }
1421
1422 INIT_WORK(&dac33->work, dac33_work);
1423 }
c8bf93f0
PU		 1424 }
1425
a577b318 1426 /* Only add the FIFO controls, if we have valid IRQ number */
3591f4cd 1427 if (dac33->irq >= 0)
022658be 1428 snd_soc_add_codec_controls(codec, dac33_mode_snd_controls,
a577b318 1429 ARRAY_SIZE(dac33_mode_snd_controls));
3591f4cd 1430
f0fba2ad 1431err_power:
c8bf93f0
PU		 1432 return ret;
1433}
1434
f0fba2ad 1435static int dac33_soc_remove(struct snd_soc_codec *codec)
c8bf93f0 1436{
f0fba2ad 1437 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 1438
f0fba2ad
LG		 1439 if (dac33->irq >= 0) {
1440 free_irq(dac33->irq, dac33->codec);
1441 destroy_workqueue(dac33->dac33_wq);
1442 }
c8bf93f0
PU		 1443 return 0;
1444}
1445
f0fba2ad
LG		 1446static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1447 .read = dac33_read_reg_cache,
1448 .write = dac33_write_locked,
1449 .set_bias_level = dac33_set_bias_level,
eb3032f8 1450 .idle_bias_off = true,
f0fba2ad
LG		 1451 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1452 .reg_word_size = sizeof(u8),
1453 .reg_cache_default = dac33_reg,
c8bf93f0
PU		 1454 .probe = dac33_soc_probe,
1455 .remove = dac33_soc_remove,
8066eb55
PU		 1456
1457 .controls = dac33_snd_controls,
1458 .num_controls = ARRAY_SIZE(dac33_snd_controls),
1459 .dapm_widgets = dac33_dapm_widgets,
1460 .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets),
1461 .dapm_routes = audio_map,
1462 .num_dapm_routes = ARRAY_SIZE(audio_map),
c8bf93f0 1463};
c8bf93f0
PU		 1464
1465#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1466 SNDRV_PCM_RATE_48000)
0d99d2b0 1467#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
c8bf93f0 1468
85e7652d 1469static const struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1470 .startup = dac33_startup,
c8bf93f0
PU		 1471 .shutdown = dac33_shutdown,
1472 .hw_params = dac33_hw_params,
c8bf93f0 1473 .trigger = dac33_pcm_trigger,
f57d2cfa 1474 .delay = dac33_dai_delay,
c8bf93f0
PU		 1475 .set_sysclk = dac33_set_dai_sysclk,
1476 .set_fmt = dac33_set_dai_fmt,
1477};
1478
f0fba2ad
LG		 1479static struct snd_soc_dai_driver dac33_dai = {
1480 .name = "tlv320dac33-hifi",
c8bf93f0
PU		 1481 .playback = {
1482 .stream_name = "Playback",
1483 .channels_min = 2,
1484 .channels_max = 2,
1485 .rates = DAC33_RATES,
3a4cbf88 1486 .formats = DAC33_FORMATS,
8d725b2b 1487 .sig_bits = 24,
3a4cbf88 1488 },
c8bf93f0
PU		 1489 .ops = &dac33_dai_ops,
1490};
c8bf93f0 1491
7a79e94e
BP		 1492static int dac33_i2c_probe(struct i2c_client *client,
1493 const struct i2c_device_id *id)
c8bf93f0
PU		 1494{
1495 struct tlv320dac33_platform_data *pdata;
1496 struct tlv320dac33_priv *dac33;
3a7aaed7 1497 int ret, i;
c8bf93f0
PU		 1498
1499 if (client->dev.platform_data == NULL) {
1500 dev_err(&client->dev, "Platform data not set\n");
1501 return -ENODEV;
1502 }
1503 pdata = client->dev.platform_data;
1504
a54877d7
AL		 1505 dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
1506 GFP_KERNEL);
c8bf93f0
PU		 1507 if (dac33 == NULL)
1508 return -ENOMEM;
1509
f0fba2ad 1510 dac33->control_data = client;
c8bf93f0 1511 mutex_init(&dac33->mutex);
f57d2cfa 1512 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1513
1514 i2c_set_clientdata(client, dac33);
1515
1516 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1517 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
eeb309a8 1518 dac33->keep_bclk = pdata->keep_bclk;
f430a27f
PU		 1519 dac33->mode1_latency = pdata->mode1_latency;
1520 if (!dac33->mode1_latency)
1521 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0 1522 dac33->irq = client->irq;
c8bf93f0 1523 /* Disable FIFO use by default */
7427b4b9 1524 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0 1525
c8bf93f0
PU		 1526 /* Check if the reset GPIO number is valid and request it */
1527 if (dac33->power_gpio >= 0) {
1528 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1529 if (ret < 0) {
f0fba2ad 1530 dev_err(&client->dev,
c8bf93f0
PU		 1531 "Failed to request reset GPIO (%d)\n",
1532 dac33->power_gpio);
f0fba2ad 1533 goto err_gpio;
c8bf93f0
PU		 1534 }
1535 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1536 }
1537
3a7aaed7
IK		 1538 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1539 dac33->supplies[i].supply = dac33_supply_names[i];
1540
e9382e3b 1541 ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
3a7aaed7
IK		 1542 dac33->supplies);
1543
1544 if (ret != 0) {
f0fba2ad 1545 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
3a7aaed7
IK		 1546 goto err_get;
1547 }
1548
f0fba2ad
LG		 1549 ret = snd_soc_register_codec(&client->dev,
1550 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1551 if (ret < 0)
e9382e3b 1552 goto err_get;
c8bf93f0 1553
c8bf93f0 1554 return ret;
3a7aaed7 1555err_get:
c8bf93f0
PU		 1556 if (dac33->power_gpio >= 0)
1557 gpio_free(dac33->power_gpio);
f0fba2ad 1558err_gpio:
c8bf93f0
PU		 1559 return ret;
1560}
1561
7a79e94e 1562static int dac33_i2c_remove(struct i2c_client *client)
c8bf93f0 1563{
f0fba2ad 1564 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1565
1566 if (unlikely(dac33->chip_power))
f0fba2ad 1567 dac33_hard_power(dac33->codec, 0);
c8bf93f0
PU		 1568
1569 if (dac33->power_gpio >= 0)
1570 gpio_free(dac33->power_gpio);
c8bf93f0 1571
f0fba2ad 1572 snd_soc_unregister_codec(&client->dev);
c8bf93f0
PU		 1573 return 0;
1574}
1575
1576static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1577 {
1578 .name = "tlv320dac33",
1579 .driver_data = 0,
1580 },
1581 { },
1582};
573f26e3 1583MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
c8bf93f0
PU		 1584
1585static struct i2c_driver tlv320dac33_i2c_driver = {
1586 .driver = {
f0fba2ad 1587 .name = "tlv320dac33-codec",
c8bf93f0
PU		 1588 },
1589 .probe = dac33_i2c_probe,
7a79e94e 1590 .remove = dac33_i2c_remove,
c8bf93f0
PU		 1591 .id_table = tlv320dac33_i2c_id,
1592};
1593
63a47a75 1594module_i2c_driver(tlv320dac33_i2c_driver);
c8bf93f0
PU		 1595
1596MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
93864cf0 1597MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
c8bf93f0 1598MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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