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Merge branch 'for-2.6.29' into for-2.6.30
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
91432e97
IM		 128 if (reg >= TWL4030_CACHEREGNUM)
129 return -EIO;
130
cc17557e
SS		 131 return cache[reg];
132}
133
134/*
135 * write twl4030 register cache
136 */
137static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
138 u8 reg, u8 value)
139{
140 u8 *cache = codec->reg_cache;
141
142 if (reg >= TWL4030_CACHEREGNUM)
143 return;
144 cache[reg] = value;
145}
146
147/*
148 * write to the twl4030 register space
149 */
150static int twl4030_write(struct snd_soc_codec *codec,
151 unsigned int reg, unsigned int value)
152{
153 twl4030_write_reg_cache(codec, reg, value);
154 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
155}
156
db04e2c5 157static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e
SS		 158{
159 u8 mode;
160
161 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 162 if (enable)
163 mode |= TWL4030_CODECPDZ;
164 else
165 mode &= ~TWL4030_CODECPDZ;
cc17557e 166
db04e2c5 167 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
cc17557e
SS		 168
169 /* REVISIT: this delay is present in TI sample drivers */
170 /* but there seems to be no TRM requirement for it */
171 udelay(10);
172}
173
174static void twl4030_init_chip(struct snd_soc_codec *codec)
175{
176 int i;
177
178 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 179 twl4030_codec_enable(codec, 0);
cc17557e
SS		 180
181 /* set all audio section registers to reasonable defaults */
182 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
183 twl4030_write(codec, i, twl4030_reg[i]);
184
185}
186
006f367e
PU		 187static void twl4030_power_up(struct snd_soc_codec *codec)
188{
189 u8 anamicl, regmisc1, byte;
190 int i = 0;
191
192 /* set CODECPDZ to turn on codec */
193 twl4030_codec_enable(codec, 1);
194
195 /* initiate offset cancellation */
196 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
197 twl4030_write(codec, TWL4030_REG_ANAMICL,
198 anamicl | TWL4030_CNCL_OFFSET_START);
199
200 /* wait for offset cancellation to complete */
201 do {
202 /* this takes a little while, so don't slam i2c */
203 udelay(2000);
204 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
205 TWL4030_REG_ANAMICL);
206 } while ((i++ < 100) &&
207 ((byte & TWL4030_CNCL_OFFSET_START) ==
208 TWL4030_CNCL_OFFSET_START));
209
210 /* Make sure that the reg_cache has the same value as the HW */
211 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
212
213 /* anti-pop when changing analog gain */
214 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
215 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
216 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
217
218 /* toggle CODECPDZ as per TRM */
219 twl4030_codec_enable(codec, 0);
220 twl4030_codec_enable(codec, 1);
221}
222
223static void twl4030_power_down(struct snd_soc_codec *codec)
224{
225 /* power down */
226 twl4030_codec_enable(codec, 0);
227}
228
5e98a464
PU		 229/* Earpiece */
230static const char *twl4030_earpiece_texts[] =
2f423577 231 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 232
2f423577
PU		 233static const unsigned int twl4030_earpiece_values[] =
234 {0x0, 0x1, 0x2, 0x4};
235
cb1ace04 236static const struct soc_enum twl4030_earpiece_enum =
2f423577 237 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 238 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 239 twl4030_earpiece_texts,
240 twl4030_earpiece_values);
5e98a464
PU		 241
242static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 243SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 244
2a6f5c58
PU		 245/* PreDrive Left */
246static const char *twl4030_predrivel_texts[] =
2f423577
PU		 247 {"Off", "DACL1", "DACL2", "DACR2"};
248
249static const unsigned int twl4030_predrivel_values[] =
250 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 251
cb1ace04 252static const struct soc_enum twl4030_predrivel_enum =
2f423577 253 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 254 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 255 twl4030_predrivel_texts,
256 twl4030_predrivel_values);
2a6f5c58
PU		 257
258static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 259SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 260
261/* PreDrive Right */
262static const char *twl4030_predriver_texts[] =
2f423577 263 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 264
2f423577
PU		 265static const unsigned int twl4030_predriver_values[] =
266 {0x0, 0x1, 0x2, 0x4};
267
cb1ace04 268static const struct soc_enum twl4030_predriver_enum =
2f423577 269 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 270 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 271 twl4030_predriver_texts,
272 twl4030_predriver_values);
2a6f5c58
PU		 273
274static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 275SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 276
dfad21a2
PU		 277/* Headset Left */
278static const char *twl4030_hsol_texts[] =
279 {"Off", "DACL1", "DACL2"};
280
281static const struct soc_enum twl4030_hsol_enum =
282 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
283 ARRAY_SIZE(twl4030_hsol_texts),
284 twl4030_hsol_texts);
285
286static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
287SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
288
289/* Headset Right */
290static const char *twl4030_hsor_texts[] =
291 {"Off", "DACR1", "DACR2"};
292
293static const struct soc_enum twl4030_hsor_enum =
294 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
295 ARRAY_SIZE(twl4030_hsor_texts),
296 twl4030_hsor_texts);
297
298static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
299SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
300
5152d8c2
PU		 301/* Carkit Left */
302static const char *twl4030_carkitl_texts[] =
303 {"Off", "DACL1", "DACL2"};
304
305static const struct soc_enum twl4030_carkitl_enum =
306 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
307 ARRAY_SIZE(twl4030_carkitl_texts),
308 twl4030_carkitl_texts);
309
310static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
311SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
312
313/* Carkit Right */
314static const char *twl4030_carkitr_texts[] =
315 {"Off", "DACR1", "DACR2"};
316
317static const struct soc_enum twl4030_carkitr_enum =
318 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
319 ARRAY_SIZE(twl4030_carkitr_texts),
320 twl4030_carkitr_texts);
321
322static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
323SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
324
df339804
PU		 325/* Handsfree Left */
326static const char *twl4030_handsfreel_texts[] =
327 {"Voice", "DACL1", "DACL2", "DACR2"};
328
329static const struct soc_enum twl4030_handsfreel_enum =
330 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
331 ARRAY_SIZE(twl4030_handsfreel_texts),
332 twl4030_handsfreel_texts);
333
334static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
335SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
336
337/* Handsfree Right */
338static const char *twl4030_handsfreer_texts[] =
339 {"Voice", "DACR1", "DACR2", "DACL2"};
340
341static const struct soc_enum twl4030_handsfreer_enum =
342 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
343 ARRAY_SIZE(twl4030_handsfreer_texts),
344 twl4030_handsfreer_texts);
345
346static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
347SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
348
276c6222
PU		 349/* Left analog microphone selection */
350static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 351 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
352
353static const unsigned int twl4030_analoglmic_values[] =
354 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 355
cb1ace04 356static const struct soc_enum twl4030_analoglmic_enum =
2f423577 357 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 358 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 359 twl4030_analoglmic_texts,
360 twl4030_analoglmic_values);
276c6222
PU		 361
362static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 363SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 364
365/* Right analog microphone selection */
366static const char *twl4030_analogrmic_texts[] =
2f423577 367 {"Off", "Sub mic", "AUXR"};
276c6222 368
2f423577
PU		 369static const unsigned int twl4030_analogrmic_values[] =
370 {0x0, 0x1, 0x4};
371
cb1ace04 372static const struct soc_enum twl4030_analogrmic_enum =
2f423577 373 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 374 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 375 twl4030_analogrmic_texts,
376 twl4030_analogrmic_values);
276c6222
PU		 377
378static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 379SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 380
381/* TX1 L/R Analog/Digital microphone selection */
382static const char *twl4030_micpathtx1_texts[] =
383 {"Analog", "Digimic0"};
384
385static const struct soc_enum twl4030_micpathtx1_enum =
386 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
387 ARRAY_SIZE(twl4030_micpathtx1_texts),
388 twl4030_micpathtx1_texts);
389
390static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
391SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
392
393/* TX2 L/R Analog/Digital microphone selection */
394static const char *twl4030_micpathtx2_texts[] =
395 {"Analog", "Digimic1"};
396
397static const struct soc_enum twl4030_micpathtx2_enum =
398 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
399 ARRAY_SIZE(twl4030_micpathtx2_texts),
400 twl4030_micpathtx2_texts);
401
402static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
403SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
404
276c6222
PU		 405static int micpath_event(struct snd_soc_dapm_widget *w,
406 struct snd_kcontrol *kcontrol, int event)
407{
408 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
409 unsigned char adcmicsel, micbias_ctl;
410
411 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
412 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
413 /* Prepare the bits for the given TX path:
414 * shift_l == 0: TX1 microphone path
415 * shift_l == 2: TX2 microphone path */
416 if (e->shift_l) {
417 /* TX2 microphone path */
418 if (adcmicsel & TWL4030_TX2IN_SEL)
419 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
420 else
421 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
422 } else {
423 /* TX1 microphone path */
424 if (adcmicsel & TWL4030_TX1IN_SEL)
425 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
426 else
427 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
428 }
429
430 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
431
432 return 0;
433}
434
49d92c7d
SM		 435static int handsfree_event(struct snd_soc_dapm_widget *w,
436 struct snd_kcontrol *kcontrol, int event)
437{
438 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
439 unsigned char hs_ctl;
440
441 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
442
443 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
444 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
445 twl4030_write(w->codec, e->reg, hs_ctl);
446 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
447 twl4030_write(w->codec, e->reg, hs_ctl);
448 hs_ctl |= TWL4030_HF_CTL_HB_EN;
449 twl4030_write(w->codec, e->reg, hs_ctl);
450 } else {
451 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
452 | TWL4030_HF_CTL_HB_EN);
453 twl4030_write(w->codec, e->reg, hs_ctl);
454 }
455
456 return 0;
457}
458
aad749e5
PU		 459static int headsetl_event(struct snd_soc_dapm_widget *w,
460 struct snd_kcontrol *kcontrol, int event)
461{
462 unsigned char hs_gain, hs_pop;
463
464 /* Save the current volume */
465 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
466
467 switch (event) {
468 case SND_SOC_DAPM_POST_PMU:
469 /* Do the anti-pop/bias ramp enable according to the TRM */
470 hs_pop = TWL4030_RAMP_DELAY_645MS;
471 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
472 hs_pop |= TWL4030_VMID_EN;
473 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
474 /* Is this needed? Can we just use whatever gain here? */
475 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
476 (hs_gain & (~0x0f)) | 0x0a);
477 hs_pop |= TWL4030_RAMP_EN;
478 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
479
480 /* Restore the original volume */
481 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
482 break;
483 case SND_SOC_DAPM_POST_PMD:
484 /* Do the anti-pop/bias ramp disable according to the TRM */
485 hs_pop = twl4030_read_reg_cache(w->codec,
486 TWL4030_REG_HS_POPN_SET);
487 hs_pop &= ~TWL4030_RAMP_EN;
488 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
489 /* Bypass the reg_cache to mute the headset */
490 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
491 hs_gain & (~0x0f),
492 TWL4030_REG_HS_GAIN_SET);
493 hs_pop &= ~TWL4030_VMID_EN;
494 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
495 break;
496 }
497 return 0;
498}
499
b0bd53a7
PU		 500/*
501 * Some of the gain controls in TWL (mostly those which are associated with
502 * the outputs) are implemented in an interesting way:
503 * 0x0 : Power down (mute)
504 * 0x1 : 6dB
505 * 0x2 : 0 dB
506 * 0x3 : -6 dB
507 * Inverting not going to help with these.
508 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
509 */
510#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
511 xinvert, tlv_array) \
512{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
513 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
514 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
515 .tlv.p = (tlv_array), \
516 .info = snd_soc_info_volsw, \
517 .get = snd_soc_get_volsw_twl4030, \
518 .put = snd_soc_put_volsw_twl4030, \
519 .private_value = (unsigned long)&(struct soc_mixer_control) \
520 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
521 .max = xmax, .invert = xinvert} }
522#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
523 xinvert, tlv_array) \
524{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
525 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
526 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
527 .tlv.p = (tlv_array), \
528 .info = snd_soc_info_volsw_2r, \
529 .get = snd_soc_get_volsw_r2_twl4030,\
530 .put = snd_soc_put_volsw_r2_twl4030, \
531 .private_value = (unsigned long)&(struct soc_mixer_control) \
532 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 533 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 534#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
535 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
536 xinvert, tlv_array)
537
538static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
539 struct snd_ctl_elem_value *ucontrol)
540{
541 struct soc_mixer_control *mc =
542 (struct soc_mixer_control *)kcontrol->private_value;
543 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
544 unsigned int reg = mc->reg;
545 unsigned int shift = mc->shift;
546 unsigned int rshift = mc->rshift;
547 int max = mc->max;
548 int mask = (1 << fls(max)) - 1;
549
550 ucontrol->value.integer.value[0] =
551 (snd_soc_read(codec, reg) >> shift) & mask;
552 if (ucontrol->value.integer.value[0])
553 ucontrol->value.integer.value[0] =
554 max + 1 - ucontrol->value.integer.value[0];
555
556 if (shift != rshift) {
557 ucontrol->value.integer.value[1] =
558 (snd_soc_read(codec, reg) >> rshift) & mask;
559 if (ucontrol->value.integer.value[1])
560 ucontrol->value.integer.value[1] =
561 max + 1 - ucontrol->value.integer.value[1];
562 }
563
564 return 0;
565}
566
567static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
568 struct snd_ctl_elem_value *ucontrol)
569{
570 struct soc_mixer_control *mc =
571 (struct soc_mixer_control *)kcontrol->private_value;
572 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
573 unsigned int reg = mc->reg;
574 unsigned int shift = mc->shift;
575 unsigned int rshift = mc->rshift;
576 int max = mc->max;
577 int mask = (1 << fls(max)) - 1;
578 unsigned short val, val2, val_mask;
579
580 val = (ucontrol->value.integer.value[0] & mask);
581
582 val_mask = mask << shift;
583 if (val)
584 val = max + 1 - val;
585 val = val << shift;
586 if (shift != rshift) {
587 val2 = (ucontrol->value.integer.value[1] & mask);
588 val_mask |= mask << rshift;
589 if (val2)
590 val2 = max + 1 - val2;
591 val |= val2 << rshift;
592 }
593 return snd_soc_update_bits(codec, reg, val_mask, val);
594}
595
596static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
597 struct snd_ctl_elem_value *ucontrol)
598{
599 struct soc_mixer_control *mc =
600 (struct soc_mixer_control *)kcontrol->private_value;
601 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
602 unsigned int reg = mc->reg;
603 unsigned int reg2 = mc->rreg;
604 unsigned int shift = mc->shift;
605 int max = mc->max;
606 int mask = (1<<fls(max))-1;
607
608 ucontrol->value.integer.value[0] =
609 (snd_soc_read(codec, reg) >> shift) & mask;
610 ucontrol->value.integer.value[1] =
611 (snd_soc_read(codec, reg2) >> shift) & mask;
612
613 if (ucontrol->value.integer.value[0])
614 ucontrol->value.integer.value[0] =
615 max + 1 - ucontrol->value.integer.value[0];
616 if (ucontrol->value.integer.value[1])
617 ucontrol->value.integer.value[1] =
618 max + 1 - ucontrol->value.integer.value[1];
619
620 return 0;
621}
622
623static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
624 struct snd_ctl_elem_value *ucontrol)
625{
626 struct soc_mixer_control *mc =
627 (struct soc_mixer_control *)kcontrol->private_value;
628 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
629 unsigned int reg = mc->reg;
630 unsigned int reg2 = mc->rreg;
631 unsigned int shift = mc->shift;
632 int max = mc->max;
633 int mask = (1 << fls(max)) - 1;
634 int err;
635 unsigned short val, val2, val_mask;
636
637 val_mask = mask << shift;
638 val = (ucontrol->value.integer.value[0] & mask);
639 val2 = (ucontrol->value.integer.value[1] & mask);
640
641 if (val)
642 val = max + 1 - val;
643 if (val2)
644 val2 = max + 1 - val2;
645
646 val = val << shift;
647 val2 = val2 << shift;
648
649 err = snd_soc_update_bits(codec, reg, val_mask, val);
650 if (err < 0)
651 return err;
652
653 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
654 return err;
655}
656
c10b82cf
PU		 657/*
658 * FGAIN volume control:
659 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
660 */
d889a72c 661static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 662
0d33ea0b
PU		 663/*
664 * CGAIN volume control:
665 * 0 dB to 12 dB in 6 dB steps
666 * value 2 and 3 means 12 dB
667 */
d889a72c
PU		 668static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
669
670/*
671 * Analog playback gain
672 * -24 dB to 12 dB in 2 dB steps
673 */
674static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 675
4290239c
PU		 676/*
677 * Gain controls tied to outputs
678 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
679 */
680static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
681
381a22b5
PU		 682/*
683 * Capture gain after the ADCs
684 * from 0 dB to 31 dB in 1 dB steps
685 */
686static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
687
5920b453
GI		 688/*
689 * Gain control for input amplifiers
690 * 0 dB to 30 dB in 6 dB steps
691 */
692static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
693
cc17557e 694static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 695 /* Common playback gain controls */
696 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
697 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
698 0, 0x3f, 0, digital_fine_tlv),
699 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
700 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
701 0, 0x3f, 0, digital_fine_tlv),
702
703 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
704 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
705 6, 0x2, 0, digital_coarse_tlv),
706 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
707 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
708 6, 0x2, 0, digital_coarse_tlv),
709
710 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
711 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
712 3, 0x12, 1, analog_tlv),
713 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
714 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
715 3, 0x12, 1, analog_tlv),
44c55870
PU		 716 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
717 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
718 1, 1, 0),
719 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
720 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
721 1, 1, 0),
381a22b5 722
4290239c
PU		 723 /* Separate output gain controls */
724 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
725 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
726 4, 3, 0, output_tvl),
727
728 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
729 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
730
731 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
732 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
733 4, 3, 0, output_tvl),
734
735 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
736 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
737
381a22b5 738 /* Common capture gain controls */
276c6222 739 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 740 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
741 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 742 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
743 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
744 0, 0x1f, 0, digital_capture_tlv),
5920b453 745
276c6222 746 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 747 0, 3, 5, 0, input_gain_tlv),
cc17557e
SS		 748};
749
cc17557e 750static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 751 /* Left channel inputs */
752 SND_SOC_DAPM_INPUT("MAINMIC"),
753 SND_SOC_DAPM_INPUT("HSMIC"),
754 SND_SOC_DAPM_INPUT("AUXL"),
755 SND_SOC_DAPM_INPUT("CARKITMIC"),
756 /* Right channel inputs */
757 SND_SOC_DAPM_INPUT("SUBMIC"),
758 SND_SOC_DAPM_INPUT("AUXR"),
759 /* Digital microphones (Stereo) */
760 SND_SOC_DAPM_INPUT("DIGIMIC0"),
761 SND_SOC_DAPM_INPUT("DIGIMIC1"),
762
763 /* Outputs */
cc17557e
SS		 764 SND_SOC_DAPM_OUTPUT("OUTL"),
765 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 766 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 767 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
768 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 769 SND_SOC_DAPM_OUTPUT("HSOL"),
770 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 771 SND_SOC_DAPM_OUTPUT("CARKITL"),
772 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 773 SND_SOC_DAPM_OUTPUT("HFL"),
774 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 775
53b5047d 776 /* DACs */
1e5fa31f 777 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
53b5047d 778 TWL4030_REG_AVDAC_CTL, 0, 0),
1e5fa31f 779 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
53b5047d 780 TWL4030_REG_AVDAC_CTL, 1, 0),
1e5fa31f 781 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
53b5047d 782 TWL4030_REG_AVDAC_CTL, 2, 0),
1e5fa31f 783 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
53b5047d 784 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 785
44c55870
PU		 786 /* Analog PGAs */
787 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
788 0, 0, NULL, 0),
789 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
790 0, 0, NULL, 0),
791 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
792 0, 0, NULL, 0),
793 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
794 0, 0, NULL, 0),
795
5e98a464
PU		 796 /* Output MUX controls */
797 /* Earpiece */
2f423577
PU		 798 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
799 &twl4030_dapm_earpiece_control),
2a6f5c58 800 /* PreDrivL/R */
2f423577
PU		 801 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
802 &twl4030_dapm_predrivel_control),
803 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
804 &twl4030_dapm_predriver_control),
dfad21a2 805 /* HeadsetL/R */
aad749e5
PU		 806 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
807 &twl4030_dapm_hsol_control, headsetl_event,
808 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2
PU		 809 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
810 &twl4030_dapm_hsor_control),
5152d8c2
PU		 811 /* CarkitL/R */
812 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
813 &twl4030_dapm_carkitl_control),
814 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
815 &twl4030_dapm_carkitr_control),
df339804 816 /* HandsfreeL/R */
49d92c7d
SM		 817 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
818 &twl4030_dapm_handsfreel_control, handsfree_event,
819 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
820 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
821 &twl4030_dapm_handsfreer_control, handsfree_event,
822 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 823
276c6222
PU		 824 /* Introducing four virtual ADC, since TWL4030 have four channel for
825 capture */
826 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
827 SND_SOC_NOPM, 0, 0),
828 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
829 SND_SOC_NOPM, 0, 0),
830 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
831 SND_SOC_NOPM, 0, 0),
832 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
833 SND_SOC_NOPM, 0, 0),
834
835 /* Analog/Digital mic path selection.
836 TX1 Left/Right: either analog Left/Right or Digimic0
837 TX2 Left/Right: either analog Left/Right or Digimic1 */
838 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
839 &twl4030_dapm_micpathtx1_control, micpath_event,
840 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
841 SND_SOC_DAPM_POST_REG),
842 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
843 &twl4030_dapm_micpathtx2_control, micpath_event,
844 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
845 SND_SOC_DAPM_POST_REG),
846
fb2a2f84 847 /* Analog input muxes with switch for the capture amplifiers */
2f423577 848 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 849 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 850 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 851 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 852
fb2a2f84
PU		 853 SND_SOC_DAPM_PGA("ADC Physical Left",
854 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
855 SND_SOC_DAPM_PGA("ADC Physical Right",
856 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 857
858 SND_SOC_DAPM_PGA("Digimic0 Enable",
859 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
860 SND_SOC_DAPM_PGA("Digimic1 Enable",
861 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
862
863 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
864 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
865 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
cc17557e
SS		 866};
867
868static const struct snd_soc_dapm_route intercon[] = {
1e5fa31f
PU		 869 {"ARXL1_APGA", NULL, "DAC Left1"},
870 {"ARXR1_APGA", NULL, "DAC Right1"},
871 {"ARXL2_APGA", NULL, "DAC Left2"},
872 {"ARXR2_APGA", NULL, "DAC Right2"},
44c55870 873
5e98a464
PU		 874 /* Internal playback routings */
875 /* Earpiece */
876 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
877 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
878 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 879 /* PreDrivL */
880 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
881 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
882 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
883 /* PreDrivR */
884 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
885 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
886 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 887 /* HeadsetL */
888 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
889 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
890 /* HeadsetR */
891 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
892 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 893 /* CarkitL */
894 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
895 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
896 /* CarkitR */
897 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
898 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 899 /* HandsfreeL */
900 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
901 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
902 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
903 /* HandsfreeR */
904 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
905 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
906 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 907
cc17557e 908 /* outputs */
44c55870
PU		 909 {"OUTL", NULL, "ARXL2_APGA"},
910 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 911 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 912 {"PREDRIVEL", NULL, "PredriveL Mux"},
913 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 914 {"HSOL", NULL, "HeadsetL Mux"},
915 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 916 {"CARKITL", NULL, "CarkitL Mux"},
917 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 918 {"HFL", NULL, "HandsfreeL Mux"},
919 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 920
276c6222
PU		 921 /* Capture path */
922 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
923 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
924 {"Analog Left Capture Route", "AUXL", "AUXL"},
925 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
926
927 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
928 {"Analog Right Capture Route", "AUXR", "AUXR"},
929
fb2a2f84
PU		 930 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
931 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 932
933 {"Digimic0 Enable", NULL, "DIGIMIC0"},
934 {"Digimic1 Enable", NULL, "DIGIMIC1"},
935
936 /* TX1 Left capture path */
fb2a2f84 937 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 938 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
939 /* TX1 Right capture path */
fb2a2f84 940 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 941 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
942 /* TX2 Left capture path */
fb2a2f84 943 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 944 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
945 /* TX2 Right capture path */
fb2a2f84 946 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 947 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
948
949 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
950 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
951 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
952 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
953
cc17557e
SS		 954};
955
956static int twl4030_add_widgets(struct snd_soc_codec *codec)
957{
958 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
959 ARRAY_SIZE(twl4030_dapm_widgets));
960
961 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
962
963 snd_soc_dapm_new_widgets(codec);
964 return 0;
965}
966
cc17557e
SS		 967static int twl4030_set_bias_level(struct snd_soc_codec *codec,
968 enum snd_soc_bias_level level)
969{
970 switch (level) {
971 case SND_SOC_BIAS_ON:
972 twl4030_power_up(codec);
973 break;
974 case SND_SOC_BIAS_PREPARE:
975 /* TODO: develop a twl4030_prepare function */
976 break;
977 case SND_SOC_BIAS_STANDBY:
978 /* TODO: develop a twl4030_standby function */
979 twl4030_power_down(codec);
980 break;
981 case SND_SOC_BIAS_OFF:
982 twl4030_power_down(codec);
983 break;
984 }
985 codec->bias_level = level;
986
987 return 0;
988}
989
990static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 991 struct snd_pcm_hw_params *params,
992 struct snd_soc_dai *dai)
cc17557e
SS		 993{
994 struct snd_soc_pcm_runtime *rtd = substream->private_data;
995 struct snd_soc_device *socdev = rtd->socdev;
6627a653 996 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 997 u8 mode, old_mode, format, old_format;
998
999
1000 /* bit rate */
1001 old_mode = twl4030_read_reg_cache(codec,
1002 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1003 mode = old_mode & ~TWL4030_APLL_RATE;
1004
1005 switch (params_rate(params)) {
1006 case 8000:
1007 mode |= TWL4030_APLL_RATE_8000;
1008 break;
1009 case 11025:
1010 mode |= TWL4030_APLL_RATE_11025;
1011 break;
1012 case 12000:
1013 mode |= TWL4030_APLL_RATE_12000;
1014 break;
1015 case 16000:
1016 mode |= TWL4030_APLL_RATE_16000;
1017 break;
1018 case 22050:
1019 mode |= TWL4030_APLL_RATE_22050;
1020 break;
1021 case 24000:
1022 mode |= TWL4030_APLL_RATE_24000;
1023 break;
1024 case 32000:
1025 mode |= TWL4030_APLL_RATE_32000;
1026 break;
1027 case 44100:
1028 mode |= TWL4030_APLL_RATE_44100;
1029 break;
1030 case 48000:
1031 mode |= TWL4030_APLL_RATE_48000;
1032 break;
1033 default:
1034 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1035 params_rate(params));
1036 return -EINVAL;
1037 }
1038
1039 if (mode != old_mode) {
1040 /* change rate and set CODECPDZ */
1041 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1042 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1043 }
1044
1045 /* sample size */
1046 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1047 format = old_format;
1048 format &= ~TWL4030_DATA_WIDTH;
1049 switch (params_format(params)) {
1050 case SNDRV_PCM_FORMAT_S16_LE:
1051 format |= TWL4030_DATA_WIDTH_16S_16W;
1052 break;
1053 case SNDRV_PCM_FORMAT_S24_LE:
1054 format |= TWL4030_DATA_WIDTH_32S_24W;
1055 break;
1056 default:
1057 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1058 params_format(params));
1059 return -EINVAL;
1060 }
1061
1062 if (format != old_format) {
1063
1064 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1065 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1066
1067 /* change format */
1068 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1069
1070 /* set CODECPDZ afterwards */
db04e2c5 1071 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1072 }
1073 return 0;
1074}
1075
1076static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1077 int clk_id, unsigned int freq, int dir)
1078{
1079 struct snd_soc_codec *codec = codec_dai->codec;
1080 u8 infreq;
1081
1082 switch (freq) {
1083 case 19200000:
1084 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1085 break;
1086 case 26000000:
1087 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1088 break;
1089 case 38400000:
1090 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1091 break;
1092 default:
1093 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1094 freq);
1095 return -EINVAL;
1096 }
1097
1098 infreq |= TWL4030_APLL_EN;
1099 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1100
1101 return 0;
1102}
1103
1104static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1105 unsigned int fmt)
1106{
1107 struct snd_soc_codec *codec = codec_dai->codec;
1108 u8 old_format, format;
1109
1110 /* get format */
1111 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1112 format = old_format;
1113
1114 /* set master/slave audio interface */
1115 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1116 case SND_SOC_DAIFMT_CBM_CFM:
1117 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1118 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1119 break;
1120 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1121 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1122 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1123 break;
1124 default:
1125 return -EINVAL;
1126 }
1127
1128 /* interface format */
1129 format &= ~TWL4030_AIF_FORMAT;
1130 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1131 case SND_SOC_DAIFMT_I2S:
1132 format |= TWL4030_AIF_FORMAT_CODEC;
1133 break;
1134 default:
1135 return -EINVAL;
1136 }
1137
1138 if (format != old_format) {
1139
1140 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1141 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1142
1143 /* change format */
1144 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1145
1146 /* set CODECPDZ afterwards */
db04e2c5 1147 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1148 }
1149
1150 return 0;
1151}
1152
bbba9444 1153#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1154#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1155
1156struct snd_soc_dai twl4030_dai = {
1157 .name = "twl4030",
1158 .playback = {
1159 .stream_name = "Playback",
1160 .channels_min = 2,
1161 .channels_max = 2,
1162 .rates = TWL4030_RATES,
1163 .formats = TWL4030_FORMATS,},
1164 .capture = {
1165 .stream_name = "Capture",
1166 .channels_min = 2,
1167 .channels_max = 2,
1168 .rates = TWL4030_RATES,
1169 .formats = TWL4030_FORMATS,},
1170 .ops = {
1171 .hw_params = twl4030_hw_params,
cc17557e
SS		 1172 .set_sysclk = twl4030_set_dai_sysclk,
1173 .set_fmt = twl4030_set_dai_fmt,
1174 }
1175};
1176EXPORT_SYMBOL_GPL(twl4030_dai);
1177
1178static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1179{
1180 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1181 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1182
1183 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1184
1185 return 0;
1186}
1187
1188static int twl4030_resume(struct platform_device *pdev)
1189{
1190 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1191 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1192
1193 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1194 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1195 return 0;
1196}
1197
1198/*
1199 * initialize the driver
1200 * register the mixer and dsp interfaces with the kernel
1201 */
1202
1203static int twl4030_init(struct snd_soc_device *socdev)
1204{
6627a653 1205 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1206 int ret = 0;
1207
1208 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1209
1210 codec->name = "twl4030";
1211 codec->owner = THIS_MODULE;
1212 codec->read = twl4030_read_reg_cache;
1213 codec->write = twl4030_write;
1214 codec->set_bias_level = twl4030_set_bias_level;
1215 codec->dai = &twl4030_dai;
1216 codec->num_dai = 1;
1217 codec->reg_cache_size = sizeof(twl4030_reg);
1218 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1219 GFP_KERNEL);
1220 if (codec->reg_cache == NULL)
1221 return -ENOMEM;
1222
1223 /* register pcms */
1224 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1225 if (ret < 0) {
1226 printk(KERN_ERR "twl4030: failed to create pcms\n");
1227 goto pcm_err;
1228 }
1229
1230 twl4030_init_chip(codec);
1231
1232 /* power on device */
1233 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1234
3e8e1952
IM		 1235 snd_soc_add_controls(codec, twl4030_snd_controls,
1236 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1237 twl4030_add_widgets(codec);
1238
968a6025 1239 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1240 if (ret < 0) {
1241 printk(KERN_ERR "twl4030: failed to register card\n");
1242 goto card_err;
1243 }
1244
1245 return ret;
1246
1247card_err:
1248 snd_soc_free_pcms(socdev);
1249 snd_soc_dapm_free(socdev);
1250pcm_err:
1251 kfree(codec->reg_cache);
1252 return ret;
1253}
1254
1255static struct snd_soc_device *twl4030_socdev;
1256
1257static int twl4030_probe(struct platform_device *pdev)
1258{
1259 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1260 struct snd_soc_codec *codec;
1261
1262 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1263 if (codec == NULL)
1264 return -ENOMEM;
1265
6627a653 1266 socdev->card->codec = codec;
cc17557e
SS		 1267 mutex_init(&codec->mutex);
1268 INIT_LIST_HEAD(&codec->dapm_widgets);
1269 INIT_LIST_HEAD(&codec->dapm_paths);
1270
1271 twl4030_socdev = socdev;
1272 twl4030_init(socdev);
1273
1274 return 0;
1275}
1276
1277static int twl4030_remove(struct platform_device *pdev)
1278{
1279 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1280 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1281
1282 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
c6d1662b
PU		 1283 snd_soc_free_pcms(socdev);
1284 snd_soc_dapm_free(socdev);
cc17557e
SS		 1285 kfree(codec);
1286
1287 return 0;
1288}
1289
1290struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1291 .probe = twl4030_probe,
1292 .remove = twl4030_remove,
1293 .suspend = twl4030_suspend,
1294 .resume = twl4030_resume,
1295};
1296EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1297
24e07db8 1298static int __init twl4030_modinit(void)
64089b84
MB		 1299{
1300 return snd_soc_register_dai(&twl4030_dai);
1301}
24e07db8 1302module_init(twl4030_modinit);
64089b84
MB		 1303
1304static void __exit twl4030_exit(void)
1305{
1306 snd_soc_unregister_dai(&twl4030_dai);
1307}
1308module_exit(twl4030_exit);
1309
cc17557e
SS		 1310MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1311MODULE_AUTHOR("Steve Sakoman");
1312MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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