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ASoC: SDP4030: Use the twl4030_setup_data for headset pop-removal
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
7220b9f4
PU		 125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
6943c92e
PU		 133
134 unsigned int sysclk;
135
136 /* Headset output state handling */
137 unsigned int hsl_enabled;
138 unsigned int hsr_enabled;
7393958f
PU		 139};
140
cc17557e
SS		 141/*
142 * read twl4030 register cache
143 */
144static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
145 unsigned int reg)
146{
147 u8 *cache = codec->reg_cache;
148
91432e97
IM		 149 if (reg >= TWL4030_CACHEREGNUM)
150 return -EIO;
151
cc17557e
SS		 152 return cache[reg];
153}
154
155/*
156 * write twl4030 register cache
157 */
158static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
159 u8 reg, u8 value)
160{
161 u8 *cache = codec->reg_cache;
162
163 if (reg >= TWL4030_CACHEREGNUM)
164 return;
165 cache[reg] = value;
166}
167
168/*
169 * write to the twl4030 register space
170 */
171static int twl4030_write(struct snd_soc_codec *codec,
172 unsigned int reg, unsigned int value)
173{
174 twl4030_write_reg_cache(codec, reg, value);
175 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
176}
177
db04e2c5 178static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 179{
7393958f 180 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 181 u8 mode;
182
7393958f
PU		 183 if (enable == twl4030->codec_powered)
184 return;
185
cc17557e 186 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 187 if (enable)
188 mode |= TWL4030_CODECPDZ;
189 else
190 mode &= ~TWL4030_CODECPDZ;
cc17557e 191
db04e2c5 192 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 193 twl4030->codec_powered = enable;
cc17557e
SS		 194
195 /* REVISIT: this delay is present in TI sample drivers */
196 /* but there seems to be no TRM requirement for it */
197 udelay(10);
198}
199
200static void twl4030_init_chip(struct snd_soc_codec *codec)
201{
202 int i;
203
204 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 205 twl4030_codec_enable(codec, 0);
cc17557e
SS		 206
207 /* set all audio section registers to reasonable defaults */
208 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
209 twl4030_write(codec, i, twl4030_reg[i]);
210
211}
212
7393958f
PU		 213static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
214{
215 struct twl4030_priv *twl4030 = codec->private_data;
216 u8 reg_val;
217
218 if (mute == twl4030->codec_muted)
219 return;
220
221 if (mute) {
222 /* Bypass the reg_cache and mute the volumes
223 * Headset mute is done in it's own event handler
224 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
225 */
226 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
227 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
228 reg_val & (~TWL4030_EAR_GAIN),
229 TWL4030_REG_EAR_CTL);
230
231 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
232 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
233 reg_val & (~TWL4030_PREDL_GAIN),
234 TWL4030_REG_PREDL_CTL);
235 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
236 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
237 reg_val & (~TWL4030_PREDR_GAIN),
238 TWL4030_REG_PREDL_CTL);
239
240 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
241 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
242 reg_val & (~TWL4030_PRECKL_GAIN),
243 TWL4030_REG_PRECKL_CTL);
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
245 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 246 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 247 TWL4030_REG_PRECKR_CTL);
248
249 /* Disable PLL */
250 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
251 reg_val &= ~TWL4030_APLL_EN;
252 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
253 } else {
254 /* Restore the volumes
255 * Headset mute is done in it's own event handler
256 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
257 */
258 twl4030_write(codec, TWL4030_REG_EAR_CTL,
259 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
260
261 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
262 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
263 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
264 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
265
266 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
267 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
268 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
269 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
270
271 /* Enable PLL */
272 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
273 reg_val |= TWL4030_APLL_EN;
274 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
275 }
276
277 twl4030->codec_muted = mute;
278}
279
006f367e
PU		 280static void twl4030_power_up(struct snd_soc_codec *codec)
281{
7393958f 282 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 283 u8 anamicl, regmisc1, byte;
284 int i = 0;
285
7393958f
PU		 286 if (twl4030->codec_powered)
287 return;
288
006f367e
PU		 289 /* set CODECPDZ to turn on codec */
290 twl4030_codec_enable(codec, 1);
291
292 /* initiate offset cancellation */
293 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
294 twl4030_write(codec, TWL4030_REG_ANAMICL,
295 anamicl | TWL4030_CNCL_OFFSET_START);
296
297 /* wait for offset cancellation to complete */
298 do {
299 /* this takes a little while, so don't slam i2c */
300 udelay(2000);
301 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
302 TWL4030_REG_ANAMICL);
303 } while ((i++ < 100) &&
304 ((byte & TWL4030_CNCL_OFFSET_START) ==
305 TWL4030_CNCL_OFFSET_START));
306
307 /* Make sure that the reg_cache has the same value as the HW */
308 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
309
310 /* anti-pop when changing analog gain */
311 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
312 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
313 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
314
315 /* toggle CODECPDZ as per TRM */
316 twl4030_codec_enable(codec, 0);
317 twl4030_codec_enable(codec, 1);
318}
319
7393958f
PU		 320/*
321 * Unconditional power down
322 */
006f367e
PU		 323static void twl4030_power_down(struct snd_soc_codec *codec)
324{
325 /* power down */
326 twl4030_codec_enable(codec, 0);
327}
328
5e98a464 329/* Earpiece */
1a787e7a
JS		 330static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
331 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
332 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
333 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
334 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
335};
5e98a464 336
2a6f5c58 337/* PreDrive Left */
1a787e7a
JS		 338static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
339 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
340 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
341 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
342 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
343};
2a6f5c58
PU		 344
345/* PreDrive Right */
1a787e7a
JS		 346static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
347 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
348 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
349 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
350 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
351};
2a6f5c58 352
dfad21a2 353/* Headset Left */
1a787e7a
JS		 354static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
355 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
356 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
357 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
358};
dfad21a2
PU		 359
360/* Headset Right */
1a787e7a
JS		 361static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
362 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
363 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
364 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
365};
dfad21a2 366
5152d8c2 367/* Carkit Left */
1a787e7a
JS		 368static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
369 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
370 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
371 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
372};
5152d8c2
PU		 373
374/* Carkit Right */
1a787e7a
JS		 375static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
376 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
377 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
378 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
379};
5152d8c2 380
df339804
PU		 381/* Handsfree Left */
382static const char *twl4030_handsfreel_texts[] =
1a787e7a 383 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 384
385static const struct soc_enum twl4030_handsfreel_enum =
386 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
387 ARRAY_SIZE(twl4030_handsfreel_texts),
388 twl4030_handsfreel_texts);
389
390static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
391SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
392
393/* Handsfree Right */
394static const char *twl4030_handsfreer_texts[] =
1a787e7a 395 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 396
397static const struct soc_enum twl4030_handsfreer_enum =
398 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
399 ARRAY_SIZE(twl4030_handsfreer_texts),
400 twl4030_handsfreer_texts);
401
402static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
403SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
404
376f7839
PU		 405/* Vibra */
406/* Vibra audio path selection */
407static const char *twl4030_vibra_texts[] =
408 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
409
410static const struct soc_enum twl4030_vibra_enum =
411 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
412 ARRAY_SIZE(twl4030_vibra_texts),
413 twl4030_vibra_texts);
414
415static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
416SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
417
418/* Vibra path selection: local vibrator (PWM) or audio driven */
419static const char *twl4030_vibrapath_texts[] =
420 {"Local vibrator", "Audio"};
421
422static const struct soc_enum twl4030_vibrapath_enum =
423 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
424 ARRAY_SIZE(twl4030_vibrapath_texts),
425 twl4030_vibrapath_texts);
426
427static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
428SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
429
276c6222 430/* Left analog microphone selection */
97b8096d
JS		 431static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
432 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
433 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
434 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
435 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
436};
276c6222
PU		 437
438/* Right analog microphone selection */
97b8096d
JS		 439static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
440 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 441 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 442};
276c6222
PU		 443
444/* TX1 L/R Analog/Digital microphone selection */
445static const char *twl4030_micpathtx1_texts[] =
446 {"Analog", "Digimic0"};
447
448static const struct soc_enum twl4030_micpathtx1_enum =
449 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
450 ARRAY_SIZE(twl4030_micpathtx1_texts),
451 twl4030_micpathtx1_texts);
452
453static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
454SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
455
456/* TX2 L/R Analog/Digital microphone selection */
457static const char *twl4030_micpathtx2_texts[] =
458 {"Analog", "Digimic1"};
459
460static const struct soc_enum twl4030_micpathtx2_enum =
461 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
462 ARRAY_SIZE(twl4030_micpathtx2_texts),
463 twl4030_micpathtx2_texts);
464
465static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
466SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
467
7393958f
PU		 468/* Analog bypass for AudioR1 */
469static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
470 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
471
472/* Analog bypass for AudioL1 */
473static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
474 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
475
476/* Analog bypass for AudioR2 */
477static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
478 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
479
480/* Analog bypass for AudioL2 */
481static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
482 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
483
fcd274a3
LCM		 484/* Analog bypass for Voice */
485static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
486 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
487
6bab83fd
PU		 488/* Digital bypass gain, 0 mutes the bypass */
489static const unsigned int twl4030_dapm_dbypass_tlv[] = {
490 TLV_DB_RANGE_HEAD(2),
491 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
492 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
493};
494
495/* Digital bypass left (TX1L -> RX2L) */
496static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
497 SOC_DAPM_SINGLE_TLV("Volume",
498 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
499 twl4030_dapm_dbypass_tlv);
500
501/* Digital bypass right (TX1R -> RX2R) */
502static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
503 SOC_DAPM_SINGLE_TLV("Volume",
504 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
505 twl4030_dapm_dbypass_tlv);
506
ee8f6894
LCM		 507/*
508 * Voice Sidetone GAIN volume control:
509 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
510 */
511static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
512
513/* Digital bypass voice: sidetone (VUL -> VDL)*/
514static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
515 SOC_DAPM_SINGLE_TLV("Volume",
516 TWL4030_REG_VSTPGA, 0, 0x29, 0,
517 twl4030_dapm_dbypassv_tlv);
518
276c6222
PU		 519static int micpath_event(struct snd_soc_dapm_widget *w,
520 struct snd_kcontrol *kcontrol, int event)
521{
522 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
523 unsigned char adcmicsel, micbias_ctl;
524
525 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
526 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
527 /* Prepare the bits for the given TX path:
528 * shift_l == 0: TX1 microphone path
529 * shift_l == 2: TX2 microphone path */
530 if (e->shift_l) {
531 /* TX2 microphone path */
532 if (adcmicsel & TWL4030_TX2IN_SEL)
533 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
534 else
535 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
536 } else {
537 /* TX1 microphone path */
538 if (adcmicsel & TWL4030_TX1IN_SEL)
539 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
540 else
541 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
542 }
543
544 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
545
546 return 0;
547}
548
49d92c7d
SM		 549static int handsfree_event(struct snd_soc_dapm_widget *w,
550 struct snd_kcontrol *kcontrol, int event)
551{
552 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
553 unsigned char hs_ctl;
554
555 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
556
557 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
558 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
559 twl4030_write(w->codec, e->reg, hs_ctl);
560 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
561 twl4030_write(w->codec, e->reg, hs_ctl);
562 hs_ctl |= TWL4030_HF_CTL_HB_EN;
563 twl4030_write(w->codec, e->reg, hs_ctl);
564 } else {
565 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
566 | TWL4030_HF_CTL_HB_EN);
567 twl4030_write(w->codec, e->reg, hs_ctl);
568 }
569
570 return 0;
571}
572
6943c92e 573static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 574{
575 unsigned char hs_gain, hs_pop;
6943c92e
PU		 576 struct twl4030_priv *twl4030 = codec->private_data;
577 /* Base values for ramp delay calculation: 2^19 - 2^26 */
578 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
579 8388608, 16777216, 33554432, 67108864};
aad749e5 580
6943c92e
PU		 581 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
582 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 583
6943c92e
PU		 584 if (ramp) {
585 /* Headset ramp-up according to the TRM */
aad749e5 586 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 587 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
588 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 589 hs_pop |= TWL4030_RAMP_EN;
6943c92e
PU		 590 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
591 } else {
592 /* Headset ramp-down _not_ according to
593 * the TRM, but in a way that it is working */
aad749e5 594 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 595 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
596 /* Wait ramp delay time + 1, so the VMID can settle */
597 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
598 twl4030->sysclk) + 1);
aad749e5
PU		 599 /* Bypass the reg_cache to mute the headset */
600 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
601 hs_gain & (~0x0f),
602 TWL4030_REG_HS_GAIN_SET);
6943c92e 603
aad749e5 604 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 605 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
606 }
607}
608
609static int headsetlpga_event(struct snd_soc_dapm_widget *w,
610 struct snd_kcontrol *kcontrol, int event)
611{
612 struct twl4030_priv *twl4030 = w->codec->private_data;
613
614 switch (event) {
615 case SND_SOC_DAPM_POST_PMU:
616 /* Do the ramp-up only once */
617 if (!twl4030->hsr_enabled)
618 headset_ramp(w->codec, 1);
619
620 twl4030->hsl_enabled = 1;
621 break;
622 case SND_SOC_DAPM_POST_PMD:
623 /* Do the ramp-down only if both headsetL/R is disabled */
624 if (!twl4030->hsr_enabled)
625 headset_ramp(w->codec, 0);
626
627 twl4030->hsl_enabled = 0;
628 break;
629 }
630 return 0;
631}
632
633static int headsetrpga_event(struct snd_soc_dapm_widget *w,
634 struct snd_kcontrol *kcontrol, int event)
635{
636 struct twl4030_priv *twl4030 = w->codec->private_data;
637
638 switch (event) {
639 case SND_SOC_DAPM_POST_PMU:
640 /* Do the ramp-up only once */
641 if (!twl4030->hsl_enabled)
642 headset_ramp(w->codec, 1);
643
644 twl4030->hsr_enabled = 1;
645 break;
646 case SND_SOC_DAPM_POST_PMD:
647 /* Do the ramp-down only if both headsetL/R is disabled */
648 if (!twl4030->hsl_enabled)
649 headset_ramp(w->codec, 0);
650
651 twl4030->hsr_enabled = 0;
aad749e5
PU		 652 break;
653 }
654 return 0;
655}
656
7393958f
PU		 657static int bypass_event(struct snd_soc_dapm_widget *w,
658 struct snd_kcontrol *kcontrol, int event)
659{
660 struct soc_mixer_control *m =
661 (struct soc_mixer_control *)w->kcontrols->private_value;
662 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 663 unsigned char reg, misc;
7393958f
PU		 664
665 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 666
667 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
668 /* Analog bypass */
669 if (reg & (1 << m->shift))
670 twl4030->bypass_state |=
671 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
672 else
673 twl4030->bypass_state &=
674 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 675 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
676 /* Analog voice bypass */
677 if (reg & (1 << m->shift))
678 twl4030->bypass_state |= (1 << 4);
679 else
680 twl4030->bypass_state &= ~(1 << 4);
ee8f6894
LCM		 681 } else if (m->reg == TWL4030_REG_VSTPGA) {
682 /* Voice digital bypass */
683 if (reg)
684 twl4030->bypass_state |= (1 << 5);
685 else
686 twl4030->bypass_state &= ~(1 << 5);
6bab83fd
PU		 687 } else {
688 /* Digital bypass */
689 if (reg & (0x7 << m->shift))
ee8f6894 690 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 691 else
ee8f6894 692 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 693 }
7393958f 694
fcd274a3
LCM		 695 /* Enable master analog loopback mode if any analog switch is enabled*/
696 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
697 if (twl4030->bypass_state & 0x1F)
698 misc |= TWL4030_FMLOOP_EN;
699 else
700 misc &= ~TWL4030_FMLOOP_EN;
701 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
702
7393958f
PU		 703 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
704 if (twl4030->bypass_state)
705 twl4030_codec_mute(w->codec, 0);
706 else
707 twl4030_codec_mute(w->codec, 1);
708 }
709 return 0;
710}
711
b0bd53a7
PU		 712/*
713 * Some of the gain controls in TWL (mostly those which are associated with
714 * the outputs) are implemented in an interesting way:
715 * 0x0 : Power down (mute)
716 * 0x1 : 6dB
717 * 0x2 : 0 dB
718 * 0x3 : -6 dB
719 * Inverting not going to help with these.
720 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
721 */
722#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
723 xinvert, tlv_array) \
724{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
725 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
726 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
727 .tlv.p = (tlv_array), \
728 .info = snd_soc_info_volsw, \
729 .get = snd_soc_get_volsw_twl4030, \
730 .put = snd_soc_put_volsw_twl4030, \
731 .private_value = (unsigned long)&(struct soc_mixer_control) \
732 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
733 .max = xmax, .invert = xinvert} }
734#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
735 xinvert, tlv_array) \
736{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
737 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
738 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
739 .tlv.p = (tlv_array), \
740 .info = snd_soc_info_volsw_2r, \
741 .get = snd_soc_get_volsw_r2_twl4030,\
742 .put = snd_soc_put_volsw_r2_twl4030, \
743 .private_value = (unsigned long)&(struct soc_mixer_control) \
744 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 745 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 746#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
747 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
748 xinvert, tlv_array)
749
750static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_value *ucontrol)
752{
753 struct soc_mixer_control *mc =
754 (struct soc_mixer_control *)kcontrol->private_value;
755 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
756 unsigned int reg = mc->reg;
757 unsigned int shift = mc->shift;
758 unsigned int rshift = mc->rshift;
759 int max = mc->max;
760 int mask = (1 << fls(max)) - 1;
761
762 ucontrol->value.integer.value[0] =
763 (snd_soc_read(codec, reg) >> shift) & mask;
764 if (ucontrol->value.integer.value[0])
765 ucontrol->value.integer.value[0] =
766 max + 1 - ucontrol->value.integer.value[0];
767
768 if (shift != rshift) {
769 ucontrol->value.integer.value[1] =
770 (snd_soc_read(codec, reg) >> rshift) & mask;
771 if (ucontrol->value.integer.value[1])
772 ucontrol->value.integer.value[1] =
773 max + 1 - ucontrol->value.integer.value[1];
774 }
775
776 return 0;
777}
778
779static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
780 struct snd_ctl_elem_value *ucontrol)
781{
782 struct soc_mixer_control *mc =
783 (struct soc_mixer_control *)kcontrol->private_value;
784 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
785 unsigned int reg = mc->reg;
786 unsigned int shift = mc->shift;
787 unsigned int rshift = mc->rshift;
788 int max = mc->max;
789 int mask = (1 << fls(max)) - 1;
790 unsigned short val, val2, val_mask;
791
792 val = (ucontrol->value.integer.value[0] & mask);
793
794 val_mask = mask << shift;
795 if (val)
796 val = max + 1 - val;
797 val = val << shift;
798 if (shift != rshift) {
799 val2 = (ucontrol->value.integer.value[1] & mask);
800 val_mask |= mask << rshift;
801 if (val2)
802 val2 = max + 1 - val2;
803 val |= val2 << rshift;
804 }
805 return snd_soc_update_bits(codec, reg, val_mask, val);
806}
807
808static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
809 struct snd_ctl_elem_value *ucontrol)
810{
811 struct soc_mixer_control *mc =
812 (struct soc_mixer_control *)kcontrol->private_value;
813 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
814 unsigned int reg = mc->reg;
815 unsigned int reg2 = mc->rreg;
816 unsigned int shift = mc->shift;
817 int max = mc->max;
818 int mask = (1<<fls(max))-1;
819
820 ucontrol->value.integer.value[0] =
821 (snd_soc_read(codec, reg) >> shift) & mask;
822 ucontrol->value.integer.value[1] =
823 (snd_soc_read(codec, reg2) >> shift) & mask;
824
825 if (ucontrol->value.integer.value[0])
826 ucontrol->value.integer.value[0] =
827 max + 1 - ucontrol->value.integer.value[0];
828 if (ucontrol->value.integer.value[1])
829 ucontrol->value.integer.value[1] =
830 max + 1 - ucontrol->value.integer.value[1];
831
832 return 0;
833}
834
835static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
836 struct snd_ctl_elem_value *ucontrol)
837{
838 struct soc_mixer_control *mc =
839 (struct soc_mixer_control *)kcontrol->private_value;
840 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
841 unsigned int reg = mc->reg;
842 unsigned int reg2 = mc->rreg;
843 unsigned int shift = mc->shift;
844 int max = mc->max;
845 int mask = (1 << fls(max)) - 1;
846 int err;
847 unsigned short val, val2, val_mask;
848
849 val_mask = mask << shift;
850 val = (ucontrol->value.integer.value[0] & mask);
851 val2 = (ucontrol->value.integer.value[1] & mask);
852
853 if (val)
854 val = max + 1 - val;
855 if (val2)
856 val2 = max + 1 - val2;
857
858 val = val << shift;
859 val2 = val2 << shift;
860
861 err = snd_soc_update_bits(codec, reg, val_mask, val);
862 if (err < 0)
863 return err;
864
865 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
866 return err;
867}
868
b74bd40f
LCM		 869/* Codec operation modes */
870static const char *twl4030_op_modes_texts[] = {
871 "Option 2 (voice/audio)", "Option 1 (audio)"
872};
873
874static const struct soc_enum twl4030_op_modes_enum =
875 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
876 ARRAY_SIZE(twl4030_op_modes_texts),
877 twl4030_op_modes_texts);
878
879int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
880 struct snd_ctl_elem_value *ucontrol)
881{
882 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
883 struct twl4030_priv *twl4030 = codec->private_data;
884 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
885 unsigned short val;
886 unsigned short mask, bitmask;
887
888 if (twl4030->configured) {
889 printk(KERN_ERR "twl4030 operation mode cannot be "
890 "changed on-the-fly\n");
891 return -EBUSY;
892 }
893
894 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
895 ;
896 if (ucontrol->value.enumerated.item[0] > e->max - 1)
897 return -EINVAL;
898
899 val = ucontrol->value.enumerated.item[0] << e->shift_l;
900 mask = (bitmask - 1) << e->shift_l;
901 if (e->shift_l != e->shift_r) {
902 if (ucontrol->value.enumerated.item[1] > e->max - 1)
903 return -EINVAL;
904 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
905 mask |= (bitmask - 1) << e->shift_r;
906 }
907
908 return snd_soc_update_bits(codec, e->reg, mask, val);
909}
910
c10b82cf
PU		 911/*
912 * FGAIN volume control:
913 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
914 */
d889a72c 915static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 916
0d33ea0b
PU		 917/*
918 * CGAIN volume control:
919 * 0 dB to 12 dB in 6 dB steps
920 * value 2 and 3 means 12 dB
921 */
d889a72c
PU		 922static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
923
1a787e7a
JS		 924/*
925 * Voice Downlink GAIN volume control:
926 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
927 */
928static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
929
d889a72c
PU		 930/*
931 * Analog playback gain
932 * -24 dB to 12 dB in 2 dB steps
933 */
934static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 935
4290239c
PU		 936/*
937 * Gain controls tied to outputs
938 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
939 */
940static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
941
18cc8d8d
JS		 942/*
943 * Gain control for earpiece amplifier
944 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
945 */
946static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
947
381a22b5
PU		 948/*
949 * Capture gain after the ADCs
950 * from 0 dB to 31 dB in 1 dB steps
951 */
952static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
953
5920b453
GI		 954/*
955 * Gain control for input amplifiers
956 * 0 dB to 30 dB in 6 dB steps
957 */
958static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
959
89492be8
PU		 960static const char *twl4030_rampdelay_texts[] = {
961 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
962 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
963 "3495/2581/1748 ms"
964};
965
966static const struct soc_enum twl4030_rampdelay_enum =
967 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
968 ARRAY_SIZE(twl4030_rampdelay_texts),
969 twl4030_rampdelay_texts);
970
376f7839
PU		 971/* Vibra H-bridge direction mode */
972static const char *twl4030_vibradirmode_texts[] = {
973 "Vibra H-bridge direction", "Audio data MSB",
974};
975
976static const struct soc_enum twl4030_vibradirmode_enum =
977 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
978 ARRAY_SIZE(twl4030_vibradirmode_texts),
979 twl4030_vibradirmode_texts);
980
981/* Vibra H-bridge direction */
982static const char *twl4030_vibradir_texts[] = {
983 "Positive polarity", "Negative polarity",
984};
985
986static const struct soc_enum twl4030_vibradir_enum =
987 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
988 ARRAY_SIZE(twl4030_vibradir_texts),
989 twl4030_vibradir_texts);
990
cc17557e 991static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 992 /* Codec operation mode control */
993 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
994 snd_soc_get_enum_double,
995 snd_soc_put_twl4030_opmode_enum_double),
996
d889a72c
PU		 997 /* Common playback gain controls */
998 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
999 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1000 0, 0x3f, 0, digital_fine_tlv),
1001 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1002 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1003 0, 0x3f, 0, digital_fine_tlv),
1004
1005 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1006 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1007 6, 0x2, 0, digital_coarse_tlv),
1008 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1009 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1010 6, 0x2, 0, digital_coarse_tlv),
1011
1012 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1013 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1014 3, 0x12, 1, analog_tlv),
1015 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1016 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1017 3, 0x12, 1, analog_tlv),
44c55870
PU		 1018 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1019 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1020 1, 1, 0),
1021 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1022 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1023 1, 1, 0),
381a22b5 1024
1a787e7a
JS		 1025 /* Common voice downlink gain controls */
1026 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1027 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1028
1029 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1030 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1031
1032 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1033 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1034
4290239c
PU		 1035 /* Separate output gain controls */
1036 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1037 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1038 4, 3, 0, output_tvl),
1039
1040 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1041 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1042
1043 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1044 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1045 4, 3, 0, output_tvl),
1046
1047 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1048 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1049
381a22b5 1050 /* Common capture gain controls */
276c6222 1051 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1052 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1053 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1054 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1055 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1056 0, 0x1f, 0, digital_capture_tlv),
5920b453 1057
276c6222 1058 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1059 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 1060
1061 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1062
1063 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1064 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1065};
1066
cc17557e 1067static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1068 /* Left channel inputs */
1069 SND_SOC_DAPM_INPUT("MAINMIC"),
1070 SND_SOC_DAPM_INPUT("HSMIC"),
1071 SND_SOC_DAPM_INPUT("AUXL"),
1072 SND_SOC_DAPM_INPUT("CARKITMIC"),
1073 /* Right channel inputs */
1074 SND_SOC_DAPM_INPUT("SUBMIC"),
1075 SND_SOC_DAPM_INPUT("AUXR"),
1076 /* Digital microphones (Stereo) */
1077 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1078 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1079
1080 /* Outputs */
cc17557e
SS		 1081 SND_SOC_DAPM_OUTPUT("OUTL"),
1082 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1083 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1084 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1085 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1086 SND_SOC_DAPM_OUTPUT("HSOL"),
1087 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1088 SND_SOC_DAPM_OUTPUT("CARKITL"),
1089 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1090 SND_SOC_DAPM_OUTPUT("HFL"),
1091 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1092 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1093
53b5047d 1094 /* DACs */
1e5fa31f 1095 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 1096 SND_SOC_NOPM, 0, 0),
1e5fa31f 1097 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 1098 SND_SOC_NOPM, 0, 0),
1e5fa31f 1099 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 1100 SND_SOC_NOPM, 0, 0),
1e5fa31f 1101 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 1102 SND_SOC_NOPM, 0, 0),
1a787e7a 1103 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1104 SND_SOC_NOPM, 0, 0),
cc17557e 1105
7393958f
PU		 1106 /* Analog bypasses */
1107 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1108 &twl4030_dapm_abypassr1_control, bypass_event,
1109 SND_SOC_DAPM_POST_REG),
1110 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1111 &twl4030_dapm_abypassl1_control,
1112 bypass_event, SND_SOC_DAPM_POST_REG),
1113 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1114 &twl4030_dapm_abypassr2_control,
1115 bypass_event, SND_SOC_DAPM_POST_REG),
1116 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1117 &twl4030_dapm_abypassl2_control,
1118 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1119 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1120 &twl4030_dapm_abypassv_control,
1121 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1122
6bab83fd
PU		 1123 /* Digital bypasses */
1124 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1125 &twl4030_dapm_dbypassl_control, bypass_event,
1126 SND_SOC_DAPM_POST_REG),
1127 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1128 &twl4030_dapm_dbypassr_control, bypass_event,
1129 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1130 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1131 &twl4030_dapm_dbypassv_control, bypass_event,
1132 SND_SOC_DAPM_POST_REG),
6bab83fd 1133
4005d39a
PU		 1134 /* Digital mixers, power control for the physical DACs */
1135 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1136 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1137 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1138 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1139 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1140 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1141 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1142 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1143 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1144 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1145
1146 /* Analog mixers, power control for the physical PGAs */
1147 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1148 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1149 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1150 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1151 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1152 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1153 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1154 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1155 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1156 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1157
1a787e7a 1158 /* Output MIXER controls */
5e98a464 1159 /* Earpiece */
1a787e7a
JS		 1160 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1161 &twl4030_dapm_earpiece_controls[0],
1162 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1163 /* PreDrivL/R */
1a787e7a
JS		 1164 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1165 &twl4030_dapm_predrivel_controls[0],
1166 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1167 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1168 &twl4030_dapm_predriver_controls[0],
1169 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1170 /* HeadsetL/R */
6943c92e 1171 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1172 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1173 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1174 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1175 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1176 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1177 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1178 &twl4030_dapm_hsor_controls[0],
1179 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1180 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1181 0, 0, NULL, 0, headsetrpga_event,
1182 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1183 /* CarkitL/R */
1a787e7a
JS		 1184 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1185 &twl4030_dapm_carkitl_controls[0],
1186 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1187 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1188 &twl4030_dapm_carkitr_controls[0],
1189 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1190
1191 /* Output MUX controls */
df339804 1192 /* HandsfreeL/R */
49d92c7d
SM		 1193 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1194 &twl4030_dapm_handsfreel_control, handsfree_event,
1195 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1196 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1197 &twl4030_dapm_handsfreer_control, handsfree_event,
1198 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1199 /* Vibra */
1200 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1201 &twl4030_dapm_vibra_control),
1202 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1203 &twl4030_dapm_vibrapath_control),
5e98a464 1204
276c6222
PU		 1205 /* Introducing four virtual ADC, since TWL4030 have four channel for
1206 capture */
1207 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1208 SND_SOC_NOPM, 0, 0),
1209 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1210 SND_SOC_NOPM, 0, 0),
1211 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1212 SND_SOC_NOPM, 0, 0),
1213 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1214 SND_SOC_NOPM, 0, 0),
1215
1216 /* Analog/Digital mic path selection.
1217 TX1 Left/Right: either analog Left/Right or Digimic0
1218 TX2 Left/Right: either analog Left/Right or Digimic1 */
1219 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1220 &twl4030_dapm_micpathtx1_control, micpath_event,
1221 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1222 SND_SOC_DAPM_POST_REG),
1223 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1224 &twl4030_dapm_micpathtx2_control, micpath_event,
1225 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1226 SND_SOC_DAPM_POST_REG),
1227
97b8096d
JS		 1228 /* Analog input mixers for the capture amplifiers */
1229 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1230 TWL4030_REG_ANAMICL, 4, 0,
1231 &twl4030_dapm_analoglmic_controls[0],
1232 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1233 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1234 TWL4030_REG_ANAMICR, 4, 0,
1235 &twl4030_dapm_analogrmic_controls[0],
1236 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1237
fb2a2f84
PU		 1238 SND_SOC_DAPM_PGA("ADC Physical Left",
1239 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1240 SND_SOC_DAPM_PGA("ADC Physical Right",
1241 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1242
1243 SND_SOC_DAPM_PGA("Digimic0 Enable",
1244 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1245 SND_SOC_DAPM_PGA("Digimic1 Enable",
1246 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1247
1248 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1249 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1250 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1251
cc17557e
SS		 1252};
1253
1254static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1255 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1256 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1257 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1258 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1259 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1260
1261 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1262 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1263 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1264 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1265 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1266
5e98a464
PU		 1267 /* Internal playback routings */
1268 /* Earpiece */
4005d39a
PU		 1269 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1270 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1271 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1272 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
2a6f5c58 1273 /* PreDrivL */
4005d39a
PU		 1274 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1275 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1276 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1277 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
2a6f5c58 1278 /* PreDrivR */
4005d39a
PU		 1279 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1280 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1281 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1282 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
dfad21a2 1283 /* HeadsetL */
4005d39a
PU		 1284 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1285 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1286 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1287 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1288 /* HeadsetR */
4005d39a
PU		 1289 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1290 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1291 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1292 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1293 /* CarkitL */
4005d39a
PU		 1294 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1295 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1296 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
5152d8c2 1297 /* CarkitR */
4005d39a
PU		 1298 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1299 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1300 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1301 /* HandsfreeL */
4005d39a
PU		 1302 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1303 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1304 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1305 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1306 /* HandsfreeR */
4005d39a
PU		 1307 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1308 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1309 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1310 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
376f7839
PU		 1311 /* Vibra */
1312 {"Vibra Mux", "AudioL1", "DAC Left1"},
1313 {"Vibra Mux", "AudioR1", "DAC Right1"},
1314 {"Vibra Mux", "AudioL2", "DAC Left2"},
1315 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1316
cc17557e 1317 /* outputs */
4005d39a
PU		 1318 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1319 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1a787e7a
JS		 1320 {"EARPIECE", NULL, "Earpiece Mixer"},
1321 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1322 {"PREDRIVER", NULL, "PredriveR Mixer"},
6943c92e
PU		 1323 {"HSOL", NULL, "HeadsetL PGA"},
1324 {"HSOR", NULL, "HeadsetR PGA"},
1a787e7a
JS		 1325 {"CARKITL", NULL, "CarkitL Mixer"},
1326 {"CARKITR", NULL, "CarkitR Mixer"},
df339804
PU		 1327 {"HFL", NULL, "HandsfreeL Mux"},
1328 {"HFR", NULL, "HandsfreeR Mux"},
376f7839
PU		 1329 {"Vibra Route", "Audio", "Vibra Mux"},
1330 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1331
276c6222
PU		 1332 /* Capture path */
1333 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1334 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1335 {"Analog Left Capture Route", "AUXL", "AUXL"},
1336 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1337
1338 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1339 {"Analog Right Capture Route", "AUXR", "AUXR"},
1340
fb2a2f84
PU		 1341 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1342 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1343
1344 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1345 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1346
1347 /* TX1 Left capture path */
fb2a2f84 1348 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1349 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1350 /* TX1 Right capture path */
fb2a2f84 1351 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1352 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1353 /* TX2 Left capture path */
fb2a2f84 1354 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1355 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1356 /* TX2 Right capture path */
fb2a2f84 1357 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1358 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1359
1360 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1361 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1362 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1363 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1364
7393958f
PU		 1365 /* Analog bypass routes */
1366 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1367 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1368 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1369 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1370 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1371
1372 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1373 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1374 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1375 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1376 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1377
6bab83fd
PU		 1378 /* Digital bypass routes */
1379 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1380 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1381 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1382
4005d39a
PU		 1383 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1384 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1385 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1386
cc17557e
SS		 1387};
1388
1389static int twl4030_add_widgets(struct snd_soc_codec *codec)
1390{
1391 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1392 ARRAY_SIZE(twl4030_dapm_widgets));
1393
1394 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1395
1396 snd_soc_dapm_new_widgets(codec);
1397 return 0;
1398}
1399
cc17557e
SS		 1400static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1401 enum snd_soc_bias_level level)
1402{
7393958f
PU		 1403 struct twl4030_priv *twl4030 = codec->private_data;
1404
cc17557e
SS		 1405 switch (level) {
1406 case SND_SOC_BIAS_ON:
7393958f 1407 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1408 break;
1409 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1410 twl4030_power_up(codec);
1411 if (twl4030->bypass_state)
1412 twl4030_codec_mute(codec, 0);
1413 else
1414 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1415 break;
1416 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1417 twl4030_power_up(codec);
1418 if (twl4030->bypass_state)
1419 twl4030_codec_mute(codec, 0);
1420 else
1421 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1422 break;
1423 case SND_SOC_BIAS_OFF:
1424 twl4030_power_down(codec);
1425 break;
1426 }
1427 codec->bias_level = level;
1428
1429 return 0;
1430}
1431
6b87a91f
PU		 1432static void twl4030_constraints(struct twl4030_priv *twl4030,
1433 struct snd_pcm_substream *mst_substream)
1434{
1435 struct snd_pcm_substream *slv_substream;
1436
1437 /* Pick the stream, which need to be constrained */
1438 if (mst_substream == twl4030->master_substream)
1439 slv_substream = twl4030->slave_substream;
1440 else if (mst_substream == twl4030->slave_substream)
1441 slv_substream = twl4030->master_substream;
1442 else /* This should not happen.. */
1443 return;
1444
1445 /* Set the constraints according to the already configured stream */
1446 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1447 SNDRV_PCM_HW_PARAM_RATE,
1448 twl4030->rate,
1449 twl4030->rate);
1450
1451 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1452 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1453 twl4030->sample_bits,
1454 twl4030->sample_bits);
1455
1456 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1457 SNDRV_PCM_HW_PARAM_CHANNELS,
1458 twl4030->channels,
1459 twl4030->channels);
1460}
1461
8a1f936a
PU		 1462/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1463 * capture has to be enabled/disabled. */
1464static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1465 int enable)
1466{
1467 u8 reg, mask;
1468
1469 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1470
1471 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1472 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1473 else
1474 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1475
1476 if (enable)
1477 reg |= mask;
1478 else
1479 reg &= ~mask;
1480
1481 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1482}
1483
d6648da1
PU		 1484static int twl4030_startup(struct snd_pcm_substream *substream,
1485 struct snd_soc_dai *dai)
7220b9f4
PU		 1486{
1487 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1488 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1489 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1490 struct twl4030_priv *twl4030 = codec->private_data;
1491
7220b9f4 1492 if (twl4030->master_substream) {
7220b9f4 1493 twl4030->slave_substream = substream;
6b87a91f
PU		 1494 /* The DAI has one configuration for playback and capture, so
1495 * if the DAI has been already configured then constrain this
1496 * substream to match it. */
1497 if (twl4030->configured)
1498 twl4030_constraints(twl4030, twl4030->master_substream);
1499 } else {
8a1f936a
PU		 1500 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1501 TWL4030_OPTION_1)) {
1502 /* In option2 4 channel is not supported, set the
1503 * constraint for the first stream for channels, the
1504 * second stream will 'inherit' this cosntraint */
1505 snd_pcm_hw_constraint_minmax(substream->runtime,
1506 SNDRV_PCM_HW_PARAM_CHANNELS,
1507 2, 2);
1508 }
7220b9f4 1509 twl4030->master_substream = substream;
6b87a91f 1510 }
7220b9f4
PU		 1511
1512 return 0;
1513}
1514
d6648da1
PU		 1515static void twl4030_shutdown(struct snd_pcm_substream *substream,
1516 struct snd_soc_dai *dai)
7220b9f4
PU		 1517{
1518 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1519 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1520 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1521 struct twl4030_priv *twl4030 = codec->private_data;
1522
1523 if (twl4030->master_substream == substream)
1524 twl4030->master_substream = twl4030->slave_substream;
1525
1526 twl4030->slave_substream = NULL;
6b87a91f
PU		 1527
1528 /* If all streams are closed, or the remaining stream has not yet
1529 * been configured than set the DAI as not configured. */
1530 if (!twl4030->master_substream)
1531 twl4030->configured = 0;
1532 else if (!twl4030->master_substream->runtime->channels)
1533 twl4030->configured = 0;
8a1f936a
PU		 1534
1535 /* If the closing substream had 4 channel, do the necessary cleanup */
1536 if (substream->runtime->channels == 4)
1537 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1538}
1539
cc17557e 1540static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1541 struct snd_pcm_hw_params *params,
1542 struct snd_soc_dai *dai)
cc17557e
SS		 1543{
1544 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1545 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1546 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1547 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1548 u8 mode, old_mode, format, old_format;
1549
8a1f936a
PU		 1550 /* If the substream has 4 channel, do the necessary setup */
1551 if (params_channels(params) == 4) {
1552 /* Safety check: are we in the correct operating mode? */
1553 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1554 TWL4030_OPTION_1))
1555 twl4030_tdm_enable(codec, substream->stream, 1);
1556 else
1557 return -EINVAL;
1558 }
1559
6b87a91f
PU		 1560 if (twl4030->configured)
1561 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1562 return 0;
1563
cc17557e
SS		 1564 /* bit rate */
1565 old_mode = twl4030_read_reg_cache(codec,
1566 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1567 mode = old_mode & ~TWL4030_APLL_RATE;
1568
1569 switch (params_rate(params)) {
1570 case 8000:
1571 mode |= TWL4030_APLL_RATE_8000;
1572 break;
1573 case 11025:
1574 mode |= TWL4030_APLL_RATE_11025;
1575 break;
1576 case 12000:
1577 mode |= TWL4030_APLL_RATE_12000;
1578 break;
1579 case 16000:
1580 mode |= TWL4030_APLL_RATE_16000;
1581 break;
1582 case 22050:
1583 mode |= TWL4030_APLL_RATE_22050;
1584 break;
1585 case 24000:
1586 mode |= TWL4030_APLL_RATE_24000;
1587 break;
1588 case 32000:
1589 mode |= TWL4030_APLL_RATE_32000;
1590 break;
1591 case 44100:
1592 mode |= TWL4030_APLL_RATE_44100;
1593 break;
1594 case 48000:
1595 mode |= TWL4030_APLL_RATE_48000;
1596 break;
103f211d
PU		 1597 case 96000:
1598 mode |= TWL4030_APLL_RATE_96000;
1599 break;
cc17557e
SS		 1600 default:
1601 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1602 params_rate(params));
1603 return -EINVAL;
1604 }
1605
1606 if (mode != old_mode) {
1607 /* change rate and set CODECPDZ */
7393958f 1608 twl4030_codec_enable(codec, 0);
cc17557e 1609 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1610 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1611 }
1612
1613 /* sample size */
1614 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1615 format = old_format;
1616 format &= ~TWL4030_DATA_WIDTH;
1617 switch (params_format(params)) {
1618 case SNDRV_PCM_FORMAT_S16_LE:
1619 format |= TWL4030_DATA_WIDTH_16S_16W;
1620 break;
1621 case SNDRV_PCM_FORMAT_S24_LE:
1622 format |= TWL4030_DATA_WIDTH_32S_24W;
1623 break;
1624 default:
1625 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1626 params_format(params));
1627 return -EINVAL;
1628 }
1629
1630 if (format != old_format) {
1631
1632 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1633 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1634
1635 /* change format */
1636 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1637
1638 /* set CODECPDZ afterwards */
db04e2c5 1639 twl4030_codec_enable(codec, 1);
cc17557e 1640 }
6b87a91f
PU		 1641
1642 /* Store the important parameters for the DAI configuration and set
1643 * the DAI as configured */
1644 twl4030->configured = 1;
1645 twl4030->rate = params_rate(params);
1646 twl4030->sample_bits = hw_param_interval(params,
1647 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1648 twl4030->channels = params_channels(params);
1649
1650 /* If both playback and capture streams are open, and one of them
1651 * is setting the hw parameters right now (since we are here), set
1652 * constraints to the other stream to match the current one. */
1653 if (twl4030->slave_substream)
1654 twl4030_constraints(twl4030, substream);
1655
cc17557e
SS		 1656 return 0;
1657}
1658
1659static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1660 int clk_id, unsigned int freq, int dir)
1661{
1662 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1663 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1664 u8 infreq;
1665
1666 switch (freq) {
1667 case 19200000:
1668 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1669 twl4030->sysclk = 19200;
cc17557e
SS		 1670 break;
1671 case 26000000:
1672 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1673 twl4030->sysclk = 26000;
cc17557e
SS		 1674 break;
1675 case 38400000:
1676 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1677 twl4030->sysclk = 38400;
cc17557e
SS		 1678 break;
1679 default:
1680 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1681 freq);
1682 return -EINVAL;
1683 }
1684
1685 infreq |= TWL4030_APLL_EN;
1686 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1687
1688 return 0;
1689}
1690
1691static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1692 unsigned int fmt)
1693{
1694 struct snd_soc_codec *codec = codec_dai->codec;
1695 u8 old_format, format;
1696
1697 /* get format */
1698 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1699 format = old_format;
1700
1701 /* set master/slave audio interface */
1702 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1703 case SND_SOC_DAIFMT_CBM_CFM:
1704 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1705 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1706 break;
1707 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1708 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1709 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1710 break;
1711 default:
1712 return -EINVAL;
1713 }
1714
1715 /* interface format */
1716 format &= ~TWL4030_AIF_FORMAT;
1717 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1718 case SND_SOC_DAIFMT_I2S:
1719 format |= TWL4030_AIF_FORMAT_CODEC;
1720 break;
8a1f936a
PU		 1721 case SND_SOC_DAIFMT_DSP_A:
1722 format |= TWL4030_AIF_FORMAT_TDM;
1723 break;
cc17557e
SS		 1724 default:
1725 return -EINVAL;
1726 }
1727
1728 if (format != old_format) {
1729
1730 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1731 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1732
1733 /* change format */
1734 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1735
1736 /* set CODECPDZ afterwards */
db04e2c5 1737 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1738 }
1739
1740 return 0;
1741}
1742
b7a755a8
MLC		 1743/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1744 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1745static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1746 int enable)
1747{
1748 u8 reg, mask;
1749
1750 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1751
1752 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1753 mask = TWL4030_ARXL1_VRX_EN;
1754 else
1755 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1756
1757 if (enable)
1758 reg |= mask;
1759 else
1760 reg &= ~mask;
1761
1762 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1763}
1764
7154b3e8
JS		 1765static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1766 struct snd_soc_dai *dai)
1767{
1768 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1769 struct snd_soc_device *socdev = rtd->socdev;
1770 struct snd_soc_codec *codec = socdev->card->codec;
1771 u8 infreq;
1772 u8 mode;
1773
1774 /* If the system master clock is not 26MHz, the voice PCM interface is
1775 * not avilable.
1776 */
1777 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1778 & TWL4030_APLL_INFREQ;
1779
1780 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1781 printk(KERN_ERR "TWL4030 voice startup: "
1782 "MCLK is not 26MHz, call set_sysclk() on init\n");
1783 return -EINVAL;
1784 }
1785
1786 /* If the codec mode is not option2, the voice PCM interface is not
1787 * avilable.
1788 */
1789 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1790 & TWL4030_OPT_MODE;
1791
1792 if (mode != TWL4030_OPTION_2) {
1793 printk(KERN_ERR "TWL4030 voice startup: "
1794 "the codec mode is not option2\n");
1795 return -EINVAL;
1796 }
1797
1798 return 0;
1799}
1800
b7a755a8
MLC		 1801static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1802 struct snd_soc_dai *dai)
1803{
1804 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1805 struct snd_soc_device *socdev = rtd->socdev;
1806 struct snd_soc_codec *codec = socdev->card->codec;
1807
1808 /* Enable voice digital filters */
1809 twl4030_voice_enable(codec, substream->stream, 0);
1810}
1811
7154b3e8
JS		 1812static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1813 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1814{
1815 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1816 struct snd_soc_device *socdev = rtd->socdev;
1817 struct snd_soc_codec *codec = socdev->card->codec;
1818 u8 old_mode, mode;
1819
b7a755a8
MLC		 1820 /* Enable voice digital filters */
1821 twl4030_voice_enable(codec, substream->stream, 1);
1822
7154b3e8
JS		 1823 /* bit rate */
1824 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1825 & ~(TWL4030_CODECPDZ);
1826 mode = old_mode;
1827
1828 switch (params_rate(params)) {
1829 case 8000:
1830 mode &= ~(TWL4030_SEL_16K);
1831 break;
1832 case 16000:
1833 mode |= TWL4030_SEL_16K;
1834 break;
1835 default:
1836 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1837 params_rate(params));
1838 return -EINVAL;
1839 }
1840
1841 if (mode != old_mode) {
1842 /* change rate and set CODECPDZ */
1843 twl4030_codec_enable(codec, 0);
1844 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1845 twl4030_codec_enable(codec, 1);
1846 }
1847
1848 return 0;
1849}
1850
1851static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1852 int clk_id, unsigned int freq, int dir)
1853{
1854 struct snd_soc_codec *codec = codec_dai->codec;
1855 u8 infreq;
1856
1857 switch (freq) {
1858 case 26000000:
1859 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1860 break;
1861 default:
1862 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1863 freq);
1864 return -EINVAL;
1865 }
1866
1867 infreq |= TWL4030_APLL_EN;
1868 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1869
1870 return 0;
1871}
1872
1873static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1874 unsigned int fmt)
1875{
1876 struct snd_soc_codec *codec = codec_dai->codec;
1877 u8 old_format, format;
1878
1879 /* get format */
1880 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1881 format = old_format;
1882
1883 /* set master/slave audio interface */
1884 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1885 case SND_SOC_DAIFMT_CBS_CFM:
1886 format &= ~(TWL4030_VIF_SLAVE_EN);
1887 break;
1888 case SND_SOC_DAIFMT_CBS_CFS:
1889 format |= TWL4030_VIF_SLAVE_EN;
1890 break;
1891 default:
1892 return -EINVAL;
1893 }
1894
1895 /* clock inversion */
1896 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1897 case SND_SOC_DAIFMT_IB_NF:
1898 format &= ~(TWL4030_VIF_FORMAT);
1899 break;
1900 case SND_SOC_DAIFMT_NB_IF:
1901 format |= TWL4030_VIF_FORMAT;
1902 break;
1903 default:
1904 return -EINVAL;
1905 }
1906
1907 if (format != old_format) {
1908 /* change format and set CODECPDZ */
1909 twl4030_codec_enable(codec, 0);
1910 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1911 twl4030_codec_enable(codec, 1);
1912 }
1913
1914 return 0;
1915}
1916
bbba9444 1917#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1918#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1919
10d9e3d9 1920static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1921 .startup = twl4030_startup,
1922 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1923 .hw_params = twl4030_hw_params,
1924 .set_sysclk = twl4030_set_dai_sysclk,
1925 .set_fmt = twl4030_set_dai_fmt,
1926};
1927
7154b3e8
JS		 1928static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1929 .startup = twl4030_voice_startup,
b7a755a8 1930 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 1931 .hw_params = twl4030_voice_hw_params,
1932 .set_sysclk = twl4030_voice_set_dai_sysclk,
1933 .set_fmt = twl4030_voice_set_dai_fmt,
1934};
1935
1936struct snd_soc_dai twl4030_dai[] = {
1937{
cc17557e
SS		 1938 .name = "twl4030",
1939 .playback = {
1940 .stream_name = "Playback",
1941 .channels_min = 2,
8a1f936a 1942 .channels_max = 4,
31ad0f31 1943 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 1944 .formats = TWL4030_FORMATS,},
1945 .capture = {
1946 .stream_name = "Capture",
1947 .channels_min = 2,
8a1f936a 1948 .channels_max = 4,
cc17557e
SS		 1949 .rates = TWL4030_RATES,
1950 .formats = TWL4030_FORMATS,},
10d9e3d9 1951 .ops = &twl4030_dai_ops,
7154b3e8
JS		 1952},
1953{
1954 .name = "twl4030 Voice",
1955 .playback = {
1956 .stream_name = "Playback",
1957 .channels_min = 1,
1958 .channels_max = 1,
1959 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1960 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1961 .capture = {
1962 .stream_name = "Capture",
1963 .channels_min = 1,
1964 .channels_max = 2,
1965 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1966 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1967 .ops = &twl4030_dai_voice_ops,
1968},
cc17557e
SS		 1969};
1970EXPORT_SYMBOL_GPL(twl4030_dai);
1971
1972static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1973{
1974 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1975 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1976
1977 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1978
1979 return 0;
1980}
1981
1982static int twl4030_resume(struct platform_device *pdev)
1983{
1984 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1985 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1986
1987 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1988 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1989 return 0;
1990}
1991
1992/*
1993 * initialize the driver
1994 * register the mixer and dsp interfaces with the kernel
1995 */
1996
1997static int twl4030_init(struct snd_soc_device *socdev)
1998{
6627a653 1999 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2000 struct twl4030_setup_data *setup = socdev->codec_data;
2001 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2002 int ret = 0;
2003
2004 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2005
2006 codec->name = "twl4030";
2007 codec->owner = THIS_MODULE;
2008 codec->read = twl4030_read_reg_cache;
2009 codec->write = twl4030_write;
2010 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2011 codec->dai = twl4030_dai;
2012 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2013 codec->reg_cache_size = sizeof(twl4030_reg);
2014 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2015 GFP_KERNEL);
2016 if (codec->reg_cache == NULL)
2017 return -ENOMEM;
2018
9da28c7b
PU		 2019 /* Configuration for headset ramp delay from setup data */
2020 if (setup) {
2021 unsigned char hs_pop;
2022
2023 if (setup->sysclk)
2024 twl4030->sysclk = setup->sysclk;
2025 else
2026 twl4030->sysclk = 26000;
2027
2028 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2029 hs_pop &= ~TWL4030_RAMP_DELAY;
2030 hs_pop |= (setup->ramp_delay_value << 2);
2031 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2032 } else {
2033 twl4030->sysclk = 26000;
2034 }
2035
cc17557e
SS		 2036 /* register pcms */
2037 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2038 if (ret < 0) {
2039 printk(KERN_ERR "twl4030: failed to create pcms\n");
2040 goto pcm_err;
2041 }
2042
2043 twl4030_init_chip(codec);
2044
2045 /* power on device */
2046 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2047
3e8e1952
IM		 2048 snd_soc_add_controls(codec, twl4030_snd_controls,
2049 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2050 twl4030_add_widgets(codec);
2051
968a6025 2052 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2053 if (ret < 0) {
2054 printk(KERN_ERR "twl4030: failed to register card\n");
2055 goto card_err;
2056 }
2057
2058 return ret;
2059
2060card_err:
2061 snd_soc_free_pcms(socdev);
2062 snd_soc_dapm_free(socdev);
2063pcm_err:
2064 kfree(codec->reg_cache);
2065 return ret;
2066}
2067
2068static struct snd_soc_device *twl4030_socdev;
2069
2070static int twl4030_probe(struct platform_device *pdev)
2071{
2072 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2073 struct snd_soc_codec *codec;
7393958f 2074 struct twl4030_priv *twl4030;
cc17557e
SS		 2075
2076 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2077 if (codec == NULL)
2078 return -ENOMEM;
2079
7393958f
PU		 2080 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2081 if (twl4030 == NULL) {
2082 kfree(codec);
2083 return -ENOMEM;
2084 }
2085
2086 codec->private_data = twl4030;
6627a653 2087 socdev->card->codec = codec;
cc17557e
SS		 2088 mutex_init(&codec->mutex);
2089 INIT_LIST_HEAD(&codec->dapm_widgets);
2090 INIT_LIST_HEAD(&codec->dapm_paths);
2091
2092 twl4030_socdev = socdev;
2093 twl4030_init(socdev);
2094
2095 return 0;
2096}
2097
2098static int twl4030_remove(struct platform_device *pdev)
2099{
2100 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2101 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2102
2103 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2104 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2105 snd_soc_free_pcms(socdev);
2106 snd_soc_dapm_free(socdev);
7393958f 2107 kfree(codec->private_data);
cc17557e
SS		 2108 kfree(codec);
2109
2110 return 0;
2111}
2112
2113struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2114 .probe = twl4030_probe,
2115 .remove = twl4030_remove,
2116 .suspend = twl4030_suspend,
2117 .resume = twl4030_resume,
2118};
2119EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2120
24e07db8 2121static int __init twl4030_modinit(void)
64089b84 2122{
7154b3e8 2123 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2124}
24e07db8 2125module_init(twl4030_modinit);
64089b84
MB		 2126
2127static void __exit twl4030_exit(void)
2128{
7154b3e8 2129 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2130}
2131module_exit(twl4030_exit);
2132
cc17557e
SS		 2133MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2134MODULE_AUTHOR("Steve Sakoman");
2135MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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