Commit | Line | Data |
---|---|---|
1cad1de1 CP |
1 | /* |
2 | * uda134x.c -- UDA134X ALSA SoC Codec driver | |
3 | * | |
4 | * Modifications by Christian Pellegrin <chripell@evolware.org> | |
5 | * | |
6 | * Copyright 2007 Dension Audio Systems Ltd. | |
7 | * Author: Zoltan Devai | |
8 | * | |
9 | * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/delay.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
1cad1de1 CP |
19 | #include <sound/pcm.h> |
20 | #include <sound/pcm_params.h> | |
21 | #include <sound/soc.h> | |
1cad1de1 CP |
22 | #include <sound/initval.h> |
23 | ||
24 | #include <sound/uda134x.h> | |
25 | #include <sound/l3.h> | |
26 | ||
72f2b894 | 27 | #include "uda134x.h" |
1cad1de1 CP |
28 | |
29 | ||
1cad1de1 CP |
30 | #define UDA134X_RATES SNDRV_PCM_RATE_8000_48000 |
31 | #define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
32 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE) | |
33 | ||
34 | struct uda134x_priv { | |
35 | int sysclk; | |
36 | int dai_fmt; | |
37 | ||
38 | struct snd_pcm_substream *master_substream; | |
39 | struct snd_pcm_substream *slave_substream; | |
f33c340a LPC |
40 | |
41 | struct regmap *regmap; | |
42 | struct uda134x_platform_data *pd; | |
1cad1de1 CP |
43 | }; |
44 | ||
f33c340a LPC |
45 | static const struct reg_default uda134x_reg_defaults[] = { |
46 | { UDA134X_EA000, 0x04 }, | |
47 | { UDA134X_EA001, 0x04 }, | |
48 | { UDA134X_EA010, 0x04 }, | |
49 | { UDA134X_EA011, 0x00 }, | |
50 | { UDA134X_EA100, 0x00 }, | |
51 | { UDA134X_EA101, 0x00 }, | |
52 | { UDA134X_EA110, 0x00 }, | |
53 | { UDA134X_EA111, 0x00 }, | |
54 | { UDA134X_STATUS0, 0x00 }, | |
55 | { UDA134X_STATUS1, 0x03 }, | |
56 | { UDA134X_DATA000, 0x00 }, | |
57 | { UDA134X_DATA001, 0x00 }, | |
58 | { UDA134X_DATA010, 0x00 }, | |
59 | { UDA134X_DATA011, 0x00 }, | |
60 | { UDA134X_DATA1, 0x00 }, | |
1cad1de1 CP |
61 | }; |
62 | ||
1cad1de1 CP |
63 | /* |
64 | * Write to the uda134x registers | |
65 | * | |
66 | */ | |
f33c340a | 67 | static int uda134x_regmap_write(void *context, unsigned int reg, |
1cad1de1 CP |
68 | unsigned int value) |
69 | { | |
f33c340a | 70 | struct uda134x_platform_data *pd = context; |
1cad1de1 CP |
71 | int ret; |
72 | u8 addr; | |
73 | u8 data = value; | |
1cad1de1 CP |
74 | |
75 | switch (reg) { | |
76 | case UDA134X_STATUS0: | |
77 | case UDA134X_STATUS1: | |
78 | addr = UDA134X_STATUS_ADDR; | |
82c7b531 | 79 | data |= (reg - UDA134X_STATUS0) << 7; |
1cad1de1 CP |
80 | break; |
81 | case UDA134X_DATA000: | |
82 | case UDA134X_DATA001: | |
83 | case UDA134X_DATA010: | |
ed632ad3 | 84 | case UDA134X_DATA011: |
1cad1de1 | 85 | addr = UDA134X_DATA0_ADDR; |
82c7b531 | 86 | data |= (reg - UDA134X_DATA000) << 6; |
1cad1de1 CP |
87 | break; |
88 | case UDA134X_DATA1: | |
89 | addr = UDA134X_DATA1_ADDR; | |
90 | break; | |
91 | default: | |
92 | /* It's an extended address register */ | |
93 | addr = (reg | UDA134X_EXTADDR_PREFIX); | |
94 | ||
95 | ret = l3_write(&pd->l3, | |
96 | UDA134X_DATA0_ADDR, &addr, 1); | |
97 | if (ret != 1) | |
98 | return -EIO; | |
99 | ||
100 | addr = UDA134X_DATA0_ADDR; | |
101 | data = (value | UDA134X_EXTDATA_PREFIX); | |
102 | break; | |
103 | } | |
104 | ||
105 | ret = l3_write(&pd->l3, | |
106 | addr, &data, 1); | |
107 | if (ret != 1) | |
108 | return -EIO; | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | static inline void uda134x_reset(struct snd_soc_codec *codec) | |
114 | { | |
ef3355d2 LPC |
115 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
116 | unsigned int mask = 1<<6; | |
117 | ||
118 | regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, mask); | |
1cad1de1 | 119 | msleep(1); |
ef3355d2 | 120 | regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, 0); |
1cad1de1 CP |
121 | } |
122 | ||
123 | static int uda134x_mute(struct snd_soc_dai *dai, int mute) | |
124 | { | |
ef3355d2 LPC |
125 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(dai->codec); |
126 | unsigned int mask = 1<<2; | |
127 | unsigned int val; | |
1cad1de1 CP |
128 | |
129 | pr_debug("%s mute: %d\n", __func__, mute); | |
130 | ||
131 | if (mute) | |
ef3355d2 | 132 | val = mask; |
1cad1de1 | 133 | else |
ef3355d2 | 134 | val = 0; |
1cad1de1 | 135 | |
ef3355d2 | 136 | return regmap_update_bits(uda134x->regmap, UDA134X_DATA010, mask, val); |
1cad1de1 CP |
137 | } |
138 | ||
dee89c4d MB |
139 | static int uda134x_startup(struct snd_pcm_substream *substream, |
140 | struct snd_soc_dai *dai) | |
1cad1de1 | 141 | { |
e6968a17 | 142 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 143 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
1cad1de1 CP |
144 | struct snd_pcm_runtime *master_runtime; |
145 | ||
146 | if (uda134x->master_substream) { | |
147 | master_runtime = uda134x->master_substream->runtime; | |
148 | ||
149 | pr_debug("%s constraining to %d bits at %d\n", __func__, | |
150 | master_runtime->sample_bits, | |
151 | master_runtime->rate); | |
152 | ||
0de8ab98 | 153 | snd_pcm_hw_constraint_single(substream->runtime, |
1cad1de1 | 154 | SNDRV_PCM_HW_PARAM_RATE, |
1cad1de1 CP |
155 | master_runtime->rate); |
156 | ||
0de8ab98 | 157 | snd_pcm_hw_constraint_single(substream->runtime, |
1cad1de1 | 158 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, |
1cad1de1 CP |
159 | master_runtime->sample_bits); |
160 | ||
161 | uda134x->slave_substream = substream; | |
162 | } else | |
163 | uda134x->master_substream = substream; | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
dee89c4d MB |
168 | static void uda134x_shutdown(struct snd_pcm_substream *substream, |
169 | struct snd_soc_dai *dai) | |
1cad1de1 | 170 | { |
e6968a17 | 171 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 172 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
1cad1de1 CP |
173 | |
174 | if (uda134x->master_substream == substream) | |
175 | uda134x->master_substream = uda134x->slave_substream; | |
176 | ||
177 | uda134x->slave_substream = NULL; | |
178 | } | |
179 | ||
180 | static int uda134x_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
181 | struct snd_pcm_hw_params *params, |
182 | struct snd_soc_dai *dai) | |
1cad1de1 | 183 | { |
ab64246c | 184 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 185 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
ef3355d2 | 186 | unsigned int hw_params = 0; |
1cad1de1 CP |
187 | |
188 | if (substream == uda134x->slave_substream) { | |
189 | pr_debug("%s ignoring hw_params for slave substream\n", | |
190 | __func__); | |
191 | return 0; | |
192 | } | |
193 | ||
1cad1de1 CP |
194 | pr_debug("%s sysclk: %d, rate:%d\n", __func__, |
195 | uda134x->sysclk, params_rate(params)); | |
196 | ||
197 | /* set SYSCLK / fs ratio */ | |
198 | switch (uda134x->sysclk / params_rate(params)) { | |
199 | case 512: | |
200 | break; | |
201 | case 384: | |
202 | hw_params |= (1<<4); | |
203 | break; | |
204 | case 256: | |
205 | hw_params |= (1<<5); | |
206 | break; | |
207 | default: | |
208 | printk(KERN_ERR "%s unsupported fs\n", __func__); | |
209 | return -EINVAL; | |
210 | } | |
211 | ||
212 | pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__, | |
213 | uda134x->dai_fmt, params_format(params)); | |
214 | ||
215 | /* set DAI format and word length */ | |
216 | switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
217 | case SND_SOC_DAIFMT_I2S: | |
218 | break; | |
219 | case SND_SOC_DAIFMT_RIGHT_J: | |
aa9ffad6 MB |
220 | switch (params_width(params)) { |
221 | case 16: | |
1cad1de1 CP |
222 | hw_params |= (1<<1); |
223 | break; | |
aa9ffad6 | 224 | case 18: |
1cad1de1 CP |
225 | hw_params |= (1<<2); |
226 | break; | |
aa9ffad6 | 227 | case 20: |
1cad1de1 CP |
228 | hw_params |= ((1<<2) | (1<<1)); |
229 | break; | |
230 | default: | |
231 | printk(KERN_ERR "%s unsupported format (right)\n", | |
232 | __func__); | |
233 | return -EINVAL; | |
234 | } | |
235 | break; | |
236 | case SND_SOC_DAIFMT_LEFT_J: | |
237 | hw_params |= (1<<3); | |
238 | break; | |
239 | default: | |
240 | printk(KERN_ERR "%s unsupported format\n", __func__); | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
ef3355d2 LPC |
244 | return regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, |
245 | STATUS0_SYSCLK_MASK | STATUS0_DAIFMT_MASK, hw_params); | |
1cad1de1 CP |
246 | } |
247 | ||
248 | static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
249 | int clk_id, unsigned int freq, int dir) | |
250 | { | |
251 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 252 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
1cad1de1 | 253 | |
449bd54d | 254 | pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__, |
1cad1de1 CP |
255 | clk_id, freq, dir); |
256 | ||
257 | /* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable | |
258 | because the codec is slave. Of course limitations of the clock | |
259 | master (the IIS controller) apply. | |
260 | We'll error out on set_hw_params if it's not OK */ | |
261 | if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) { | |
262 | uda134x->sysclk = freq; | |
263 | return 0; | |
264 | } | |
265 | ||
266 | printk(KERN_ERR "%s unsupported sysclk\n", __func__); | |
267 | return -EINVAL; | |
268 | } | |
269 | ||
270 | static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
271 | unsigned int fmt) | |
272 | { | |
273 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 274 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
1cad1de1 CP |
275 | |
276 | pr_debug("%s fmt: %08X\n", __func__, fmt); | |
277 | ||
278 | /* codec supports only full slave mode */ | |
279 | if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) { | |
280 | printk(KERN_ERR "%s unsupported slave mode\n", __func__); | |
281 | return -EINVAL; | |
282 | } | |
283 | ||
284 | /* no support for clock inversion */ | |
285 | if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) { | |
286 | printk(KERN_ERR "%s unsupported clock inversion\n", __func__); | |
287 | return -EINVAL; | |
288 | } | |
289 | ||
290 | /* We can't setup DAI format here as it depends on the word bit num */ | |
291 | /* so let's just store the value for later */ | |
292 | uda134x->dai_fmt = fmt; | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int uda134x_set_bias_level(struct snd_soc_codec *codec, | |
298 | enum snd_soc_bias_level level) | |
299 | { | |
f33c340a LPC |
300 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
301 | struct uda134x_platform_data *pd = uda134x->pd; | |
1cad1de1 CP |
302 | pr_debug("%s bias level %d\n", __func__, level); |
303 | ||
304 | switch (level) { | |
305 | case SND_SOC_BIAS_ON: | |
1cad1de1 CP |
306 | break; |
307 | case SND_SOC_BIAS_PREPARE: | |
308 | /* power on */ | |
309 | if (pd->power) { | |
310 | pd->power(1); | |
f33c340a | 311 | regcache_sync(uda134x->regmap); |
1cad1de1 CP |
312 | } |
313 | break; | |
314 | case SND_SOC_BIAS_STANDBY: | |
1cad1de1 CP |
315 | break; |
316 | case SND_SOC_BIAS_OFF: | |
317 | /* power off */ | |
f33c340a | 318 | if (pd->power) { |
1cad1de1 | 319 | pd->power(0); |
f33c340a LPC |
320 | regcache_mark_dirty(uda134x->regmap); |
321 | } | |
1cad1de1 CP |
322 | break; |
323 | } | |
1cad1de1 CP |
324 | return 0; |
325 | } | |
326 | ||
327 | static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1", | |
328 | "Minimum2", "Maximum"}; | |
329 | static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; | |
330 | static const char *uda134x_mixmode[] = {"Differential", "Analog1", | |
331 | "Analog2", "Both"}; | |
332 | ||
333 | static const struct soc_enum uda134x_mixer_enum[] = { | |
334 | SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting), | |
335 | SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph), | |
336 | SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode), | |
337 | }; | |
338 | ||
339 | static const struct snd_kcontrol_new uda1341_snd_controls[] = { | |
340 | SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1), | |
341 | SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0), | |
342 | SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1), | |
343 | SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1), | |
344 | ||
345 | SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0), | |
346 | SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0), | |
347 | ||
348 | SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0), | |
349 | SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0), | |
350 | ||
351 | SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]), | |
352 | SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]), | |
353 | SOC_ENUM("Input Mux", uda134x_mixer_enum[2]), | |
354 | ||
355 | SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0), | |
356 | SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1), | |
357 | SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0), | |
358 | ||
359 | SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0), | |
360 | SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0), | |
361 | SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0), | |
362 | SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0), | |
363 | SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0), | |
364 | SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0), | |
365 | }; | |
366 | ||
367 | static const struct snd_kcontrol_new uda1340_snd_controls[] = { | |
368 | SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1), | |
369 | ||
370 | SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0), | |
371 | SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0), | |
372 | ||
373 | SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]), | |
374 | SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]), | |
375 | ||
376 | SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0), | |
377 | }; | |
378 | ||
b28528a1 VZ |
379 | static const struct snd_kcontrol_new uda1345_snd_controls[] = { |
380 | SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1), | |
381 | ||
382 | SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]), | |
383 | ||
384 | SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0), | |
385 | }; | |
386 | ||
113591e4 RK |
387 | /* UDA1341 has the DAC/ADC power down in STATUS1 */ |
388 | static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = { | |
389 | SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0), | |
390 | SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0), | |
391 | }; | |
392 | ||
393 | /* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */ | |
394 | static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = { | |
395 | SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0), | |
396 | SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0), | |
397 | }; | |
398 | ||
399 | /* Common DAPM widgets */ | |
400 | static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = { | |
401 | SND_SOC_DAPM_INPUT("VINL1"), | |
402 | SND_SOC_DAPM_INPUT("VINR1"), | |
403 | SND_SOC_DAPM_INPUT("VINL2"), | |
404 | SND_SOC_DAPM_INPUT("VINR2"), | |
405 | SND_SOC_DAPM_OUTPUT("VOUTL"), | |
406 | SND_SOC_DAPM_OUTPUT("VOUTR"), | |
407 | }; | |
408 | ||
409 | static const struct snd_soc_dapm_route uda134x_dapm_routes[] = { | |
410 | { "ADC", NULL, "VINL1" }, | |
411 | { "ADC", NULL, "VINR1" }, | |
412 | { "ADC", NULL, "VINL2" }, | |
413 | { "ADC", NULL, "VINR2" }, | |
414 | { "VOUTL", NULL, "DAC" }, | |
415 | { "VOUTR", NULL, "DAC" }, | |
416 | }; | |
417 | ||
85e7652d | 418 | static const struct snd_soc_dai_ops uda134x_dai_ops = { |
6335d055 EM |
419 | .startup = uda134x_startup, |
420 | .shutdown = uda134x_shutdown, | |
421 | .hw_params = uda134x_hw_params, | |
422 | .digital_mute = uda134x_mute, | |
423 | .set_sysclk = uda134x_set_dai_sysclk, | |
424 | .set_fmt = uda134x_set_dai_fmt, | |
425 | }; | |
426 | ||
f0fba2ad LG |
427 | static struct snd_soc_dai_driver uda134x_dai = { |
428 | .name = "uda134x-hifi", | |
1cad1de1 CP |
429 | /* playback capabilities */ |
430 | .playback = { | |
431 | .stream_name = "Playback", | |
432 | .channels_min = 1, | |
433 | .channels_max = 2, | |
434 | .rates = UDA134X_RATES, | |
435 | .formats = UDA134X_FORMATS, | |
436 | }, | |
437 | /* capture capabilities */ | |
438 | .capture = { | |
439 | .stream_name = "Capture", | |
440 | .channels_min = 1, | |
441 | .channels_max = 2, | |
442 | .rates = UDA134X_RATES, | |
443 | .formats = UDA134X_FORMATS, | |
444 | }, | |
445 | /* pcm operations */ | |
6335d055 | 446 | .ops = &uda134x_dai_ops, |
1cad1de1 | 447 | }; |
1cad1de1 | 448 | |
f0fba2ad | 449 | static int uda134x_soc_probe(struct snd_soc_codec *codec) |
1cad1de1 | 450 | { |
81024b11 | 451 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
f15c444e | 452 | struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); |
f33c340a | 453 | struct uda134x_platform_data *pd = uda134x->pd; |
113591e4 RK |
454 | const struct snd_soc_dapm_widget *widgets; |
455 | unsigned num_widgets; | |
f0fba2ad | 456 | int ret; |
1cad1de1 CP |
457 | |
458 | printk(KERN_INFO "UDA134X SoC Audio Codec\n"); | |
459 | ||
1cad1de1 CP |
460 | switch (pd->model) { |
461 | case UDA134X_UDA1340: | |
462 | case UDA134X_UDA1341: | |
463 | case UDA134X_UDA1344: | |
b28528a1 | 464 | case UDA134X_UDA1345: |
1cad1de1 CP |
465 | break; |
466 | default: | |
467 | printk(KERN_ERR "UDA134X SoC codec: " | |
468 | "unsupported model %d\n", | |
469 | pd->model); | |
470 | return -EINVAL; | |
471 | } | |
472 | ||
1cad1de1 CP |
473 | if (pd->power) |
474 | pd->power(1); | |
475 | ||
476 | uda134x_reset(codec); | |
477 | ||
113591e4 RK |
478 | if (pd->model == UDA134X_UDA1341) { |
479 | widgets = uda1341_dapm_widgets; | |
480 | num_widgets = ARRAY_SIZE(uda1341_dapm_widgets); | |
481 | } else { | |
482 | widgets = uda1340_dapm_widgets; | |
483 | num_widgets = ARRAY_SIZE(uda1340_dapm_widgets); | |
484 | } | |
485 | ||
81024b11 | 486 | ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets); |
113591e4 RK |
487 | if (ret) { |
488 | printk(KERN_ERR "%s failed to register dapm controls: %d", | |
489 | __func__, ret); | |
113591e4 RK |
490 | return ret; |
491 | } | |
492 | ||
3e8e1952 IM |
493 | switch (pd->model) { |
494 | case UDA134X_UDA1340: | |
495 | case UDA134X_UDA1344: | |
022658be | 496 | ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls, |
3e8e1952 IM |
497 | ARRAY_SIZE(uda1340_snd_controls)); |
498 | break; | |
499 | case UDA134X_UDA1341: | |
022658be | 500 | ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls, |
3e8e1952 IM |
501 | ARRAY_SIZE(uda1341_snd_controls)); |
502 | break; | |
b28528a1 | 503 | case UDA134X_UDA1345: |
022658be | 504 | ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls, |
b28528a1 VZ |
505 | ARRAY_SIZE(uda1345_snd_controls)); |
506 | break; | |
3e8e1952 | 507 | default: |
af901ca1 | 508 | printk(KERN_ERR "%s unknown codec type: %d", |
3e8e1952 | 509 | __func__, pd->model); |
f0fba2ad | 510 | return -EINVAL; |
3e8e1952 IM |
511 | } |
512 | ||
1cad1de1 CP |
513 | if (ret < 0) { |
514 | printk(KERN_ERR "UDA134X: failed to register controls\n"); | |
f0fba2ad | 515 | return ret; |
1cad1de1 CP |
516 | } |
517 | ||
1cad1de1 | 518 | return 0; |
1cad1de1 CP |
519 | } |
520 | ||
f0fba2ad | 521 | static struct snd_soc_codec_driver soc_codec_dev_uda134x = { |
1cad1de1 | 522 | .probe = uda134x_soc_probe, |
f0fba2ad | 523 | .set_bias_level = uda134x_set_bias_level, |
e03b9755 LPC |
524 | .suspend_bias_off = true, |
525 | ||
113591e4 RK |
526 | .dapm_widgets = uda134x_dapm_widgets, |
527 | .num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets), | |
528 | .dapm_routes = uda134x_dapm_routes, | |
529 | .num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes), | |
f0fba2ad LG |
530 | }; |
531 | ||
f33c340a LPC |
532 | static const struct regmap_config uda134x_regmap_config = { |
533 | .reg_bits = 8, | |
534 | .val_bits = 8, | |
535 | .max_register = UDA134X_DATA1, | |
536 | .reg_defaults = uda134x_reg_defaults, | |
537 | .num_reg_defaults = ARRAY_SIZE(uda134x_reg_defaults), | |
538 | .cache_type = REGCACHE_RBTREE, | |
539 | ||
540 | .reg_write = uda134x_regmap_write, | |
541 | }; | |
542 | ||
7a79e94e | 543 | static int uda134x_codec_probe(struct platform_device *pdev) |
f0fba2ad | 544 | { |
f33c340a | 545 | struct uda134x_platform_data *pd = pdev->dev.platform_data; |
f15c444e LPC |
546 | struct uda134x_priv *uda134x; |
547 | ||
f33c340a LPC |
548 | if (!pd) { |
549 | dev_err(&pdev->dev, "Missing L3 bitbang function\n"); | |
550 | return -ENODEV; | |
551 | } | |
552 | ||
f15c444e LPC |
553 | uda134x = devm_kzalloc(&pdev->dev, sizeof(*uda134x), GFP_KERNEL); |
554 | if (!uda134x) | |
555 | return -ENOMEM; | |
556 | ||
f33c340a | 557 | uda134x->pd = pd; |
f15c444e LPC |
558 | platform_set_drvdata(pdev, uda134x); |
559 | ||
f33c340a LPC |
560 | uda134x->regmap = devm_regmap_init(&pdev->dev, NULL, pd, |
561 | &uda134x_regmap_config); | |
562 | if (IS_ERR(uda134x->regmap)) | |
563 | return PTR_ERR(uda134x->regmap); | |
564 | ||
f0fba2ad LG |
565 | return snd_soc_register_codec(&pdev->dev, |
566 | &soc_codec_dev_uda134x, &uda134x_dai, 1); | |
567 | } | |
568 | ||
7a79e94e | 569 | static int uda134x_codec_remove(struct platform_device *pdev) |
f0fba2ad LG |
570 | { |
571 | snd_soc_unregister_codec(&pdev->dev); | |
572 | return 0; | |
573 | } | |
574 | ||
575 | static struct platform_driver uda134x_codec_driver = { | |
576 | .driver = { | |
577 | .name = "uda134x-codec", | |
f0fba2ad LG |
578 | }, |
579 | .probe = uda134x_codec_probe, | |
7a79e94e | 580 | .remove = uda134x_codec_remove, |
1cad1de1 | 581 | }; |
1cad1de1 | 582 | |
5bbcc3c0 | 583 | module_platform_driver(uda134x_codec_driver); |
64089b84 | 584 | |
1cad1de1 CP |
585 | MODULE_DESCRIPTION("UDA134X ALSA soc codec driver"); |
586 | MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>"); | |
587 | MODULE_LICENSE("GPL"); |