projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq
[deliverable/linux.git] / sound / soc / codecs / wm8750.c
CommitLineData
abadfc92
RP		 1/*
2 * wm8750.c -- WM8750 ALSA SoC audio driver
3 *
4 * Copyright 2005 Openedhand Ltd.
5 *
6 * Author: Richard Purdie <richard@openedhand.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
abadfc92
RP		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28
29#include "wm8750.h"
30
31#define AUDIO_NAME "WM8750"
4422b606 32#define WM8750_VERSION "0.12"
abadfc92 33
4422b606
LG		 34/* codec private data */
35struct wm8750_priv {
36 unsigned int sysclk;
37};
38
abadfc92
RP		 39/*
40 * wm8750 register cache
41 * We can't read the WM8750 register space when we
42 * are using 2 wire for device control, so we cache them instead.
43 */
44static const u16 wm8750_reg[] = {
45 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
46 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
47 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
48 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
49 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
50 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
51 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
52 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
53 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
54 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
55 0x0079, 0x0079, 0x0079, /* 40 */
56};
57
abadfc92
RP		 58/*
59 * read wm8750 register cache
60 */
61static inline unsigned int wm8750_read_reg_cache(struct snd_soc_codec *codec,
62 unsigned int reg)
63{
64 u16 *cache = codec->reg_cache;
65 if (reg > WM8750_CACHE_REGNUM)
66 return -1;
67 return cache[reg];
68}
69
70/*
71 * write wm8750 register cache
72 */
73static inline void wm8750_write_reg_cache(struct snd_soc_codec *codec,
74 unsigned int reg, unsigned int value)
75{
76 u16 *cache = codec->reg_cache;
77 if (reg > WM8750_CACHE_REGNUM)
78 return;
79 cache[reg] = value;
80}
81
82static int wm8750_write(struct snd_soc_codec *codec, unsigned int reg,
83 unsigned int value)
84{
85 u8 data[2];
86
87 /* data is
88 * D15..D9 WM8753 register offset
89 * D8...D0 register data
90 */
91 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
92 data[1] = value & 0x00ff;
93
42f3030f 94 wm8750_write_reg_cache(codec, reg, value);
abadfc92
RP		 95 if (codec->hw_write(codec->control_data, data, 2) == 2)
96 return 0;
97 else
98 return -EIO;
99}
100
101#define wm8750_reset(c) wm8750_write(c, WM8750_RESET, 0)
102
103/*
104 * WM8750 Controls
105 */
106static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
107static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
108static const char *wm8750_treble[] = {"8kHz", "4kHz"};
109static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
110static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
111static const char *wm8750_3d_func[] = {"Capture", "Playback"};
112static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
113static const char *wm8750_ng_type[] = {"Constant PGA Gain",
114 "Mute ADC Output"};
115static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
116 "Differential"};
117static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
118 "Differential"};
119static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
120 "ROUT1"};
121static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
122static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
123 "L + R Invert"};
124static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
125static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
126 "Mono (Right)", "Digital Mono"};
127
128static const struct soc_enum wm8750_enum[] = {
129SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
130SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
131SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
132SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
133SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
134SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
135SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
136SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
137SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
138SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
139SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
140SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
141SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
142SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
143SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
144SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
145SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
146
147};
148
149static const struct snd_kcontrol_new wm8750_snd_controls[] = {
150
151SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
152SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
153SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
154
bd903b6e 155SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
abadfc92 156 WM8750_ROUT1V, 7, 1, 0),
bd903b6e 157SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
abadfc92
RP		 158 WM8750_ROUT2V, 7, 1, 0),
159
160SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
161
162SOC_ENUM("Capture Polarity", wm8750_enum[14]),
163SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
164SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
165
166SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
167
168SOC_ENUM("Bass Boost", wm8750_enum[0]),
169SOC_ENUM("Bass Filter", wm8750_enum[1]),
170SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
171
6a7b8cf4 172SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
abadfc92
RP		 173SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
174
175SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
176SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
177SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
178SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
179SOC_ENUM("3D Mode", wm8750_enum[5]),
180
181SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
182SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
183SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
184SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
185SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
186SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
187SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
188SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
189SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
190SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
191
192SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
193SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
194
195SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
196SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
197
bd903b6e 198SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
abadfc92
RP		 199
200/* Unimplemented */
201/* ADCDAC Bit 0 - ADCHPD */
202/* ADCDAC Bit 4 - HPOR */
203/* ADCTL1 Bit 2,3 - DATSEL */
204/* ADCTL1 Bit 4,5 - DMONOMIX */
205/* ADCTL1 Bit 6,7 - VSEL */
206/* ADCTL2 Bit 2 - LRCM */
207/* ADCTL2 Bit 3 - TRI */
208/* ADCTL3 Bit 5 - HPFLREN */
209/* ADCTL3 Bit 6 - VROI */
210/* ADCTL3 Bit 7,8 - ADCLRM */
211/* ADCIN Bit 4 - LDCM */
212/* ADCIN Bit 5 - RDCM */
213
214SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
215
216SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
217 WM8750_LOUTM2, 4, 7, 1),
218SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
219 WM8750_ROUTM2, 4, 7, 1),
220SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
221 WM8750_MOUTM2, 4, 7, 1),
222
223SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
224
bd903b6e
LG		 225SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
226 0, 127, 0),
227SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
228 0, 127, 0),
abadfc92
RP		 229
230SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
231
232};
233
234/* add non dapm controls */
235static int wm8750_add_controls(struct snd_soc_codec *codec)
236{
237 int err, i;
238
239 for (i = 0; i < ARRAY_SIZE(wm8750_snd_controls); i++) {
240 err = snd_ctl_add(codec->card,
42f3030f
MB		 241 snd_soc_cnew(&wm8750_snd_controls[i],
242 codec, NULL));
abadfc92
RP		 243 if (err < 0)
244 return err;
245 }
246 return 0;
247}
248
249/*
250 * DAPM Controls
251 */
252
253/* Left Mixer */
254static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
255SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
256SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
257SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
258SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
259};
260
261/* Right Mixer */
262static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
263SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
264SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
265SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
266SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
267};
268
269/* Mono Mixer */
270static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
271SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
272SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
273SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
274SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
275};
276
277/* Left Line Mux */
278static const struct snd_kcontrol_new wm8750_left_line_controls =
279SOC_DAPM_ENUM("Route", wm8750_enum[8]);
280
281/* Right Line Mux */
282static const struct snd_kcontrol_new wm8750_right_line_controls =
283SOC_DAPM_ENUM("Route", wm8750_enum[9]);
284
285/* Left PGA Mux */
286static const struct snd_kcontrol_new wm8750_left_pga_controls =
287SOC_DAPM_ENUM("Route", wm8750_enum[10]);
288
289/* Right PGA Mux */
290static const struct snd_kcontrol_new wm8750_right_pga_controls =
291SOC_DAPM_ENUM("Route", wm8750_enum[11]);
292
293/* Out 3 Mux */
294static const struct snd_kcontrol_new wm8750_out3_controls =
295SOC_DAPM_ENUM("Route", wm8750_enum[12]);
296
297/* Differential Mux */
298static const struct snd_kcontrol_new wm8750_diffmux_controls =
299SOC_DAPM_ENUM("Route", wm8750_enum[13]);
300
301/* Mono ADC Mux */
302static const struct snd_kcontrol_new wm8750_monomux_controls =
303SOC_DAPM_ENUM("Route", wm8750_enum[16]);
304
305static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
306 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
307 &wm8750_left_mixer_controls[0],
308 ARRAY_SIZE(wm8750_left_mixer_controls)),
309 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
310 &wm8750_right_mixer_controls[0],
311 ARRAY_SIZE(wm8750_right_mixer_controls)),
312 SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
313 &wm8750_mono_mixer_controls[0],
314 ARRAY_SIZE(wm8750_mono_mixer_controls)),
315
316 SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
317 SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
318 SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
319 SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
320 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
321 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
322
323 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
324 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
325 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
326
327 SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
328 &wm8750_left_pga_controls),
329 SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
330 &wm8750_right_pga_controls),
331 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
332 &wm8750_left_line_controls),
333 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
334 &wm8750_right_line_controls),
335
336 SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
337 SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
338 SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
339
340 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
341 &wm8750_diffmux_controls),
342 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
343 &wm8750_monomux_controls),
344 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
345 &wm8750_monomux_controls),
346
347 SND_SOC_DAPM_OUTPUT("LOUT1"),
348 SND_SOC_DAPM_OUTPUT("ROUT1"),
349 SND_SOC_DAPM_OUTPUT("LOUT2"),
350 SND_SOC_DAPM_OUTPUT("ROUT2"),
351 SND_SOC_DAPM_OUTPUT("MONO"),
352 SND_SOC_DAPM_OUTPUT("OUT3"),
353
354 SND_SOC_DAPM_INPUT("LINPUT1"),
355 SND_SOC_DAPM_INPUT("LINPUT2"),
356 SND_SOC_DAPM_INPUT("LINPUT3"),
357 SND_SOC_DAPM_INPUT("RINPUT1"),
358 SND_SOC_DAPM_INPUT("RINPUT2"),
359 SND_SOC_DAPM_INPUT("RINPUT3"),
360};
361
a65f0568 362static const struct snd_soc_dapm_route audio_map[] = {
abadfc92
RP		 363 /* left mixer */
364 {"Left Mixer", "Playback Switch", "Left DAC"},
365 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
366 {"Left Mixer", "Right Playback Switch", "Right DAC"},
367 {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
368
369 /* right mixer */
370 {"Right Mixer", "Left Playback Switch", "Left DAC"},
371 {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
372 {"Right Mixer", "Playback Switch", "Right DAC"},
373 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
374
375 /* left out 1 */
376 {"Left Out 1", NULL, "Left Mixer"},
377 {"LOUT1", NULL, "Left Out 1"},
378
379 /* left out 2 */
380 {"Left Out 2", NULL, "Left Mixer"},
381 {"LOUT2", NULL, "Left Out 2"},
382
383 /* right out 1 */
384 {"Right Out 1", NULL, "Right Mixer"},
385 {"ROUT1", NULL, "Right Out 1"},
386
387 /* right out 2 */
388 {"Right Out 2", NULL, "Right Mixer"},
389 {"ROUT2", NULL, "Right Out 2"},
390
391 /* mono mixer */
392 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
393 {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
394 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
395 {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
396
397 /* mono out */
398 {"Mono Out 1", NULL, "Mono Mixer"},
399 {"MONO1", NULL, "Mono Out 1"},
400
401 /* out 3 */
402 {"Out3 Mux", "VREF", "VREF"},
403 {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
404 {"Out3 Mux", "ROUT1", "Right Mixer"},
405 {"Out3 Mux", "MonoOut", "MONO1"},
406 {"Out 3", NULL, "Out3 Mux"},
407 {"OUT3", NULL, "Out 3"},
408
409 /* Left Line Mux */
410 {"Left Line Mux", "Line 1", "LINPUT1"},
411 {"Left Line Mux", "Line 2", "LINPUT2"},
412 {"Left Line Mux", "Line 3", "LINPUT3"},
413 {"Left Line Mux", "PGA", "Left PGA Mux"},
414 {"Left Line Mux", "Differential", "Differential Mux"},
415
416 /* Right Line Mux */
417 {"Right Line Mux", "Line 1", "RINPUT1"},
418 {"Right Line Mux", "Line 2", "RINPUT2"},
419 {"Right Line Mux", "Line 3", "RINPUT3"},
420 {"Right Line Mux", "PGA", "Right PGA Mux"},
421 {"Right Line Mux", "Differential", "Differential Mux"},
422
423 /* Left PGA Mux */
424 {"Left PGA Mux", "Line 1", "LINPUT1"},
425 {"Left PGA Mux", "Line 2", "LINPUT2"},
426 {"Left PGA Mux", "Line 3", "LINPUT3"},
427 {"Left PGA Mux", "Differential", "Differential Mux"},
428
429 /* Right PGA Mux */
430 {"Right PGA Mux", "Line 1", "RINPUT1"},
431 {"Right PGA Mux", "Line 2", "RINPUT2"},
432 {"Right PGA Mux", "Line 3", "RINPUT3"},
433 {"Right PGA Mux", "Differential", "Differential Mux"},
434
435 /* Differential Mux */
436 {"Differential Mux", "Line 1", "LINPUT1"},
437 {"Differential Mux", "Line 1", "RINPUT1"},
438 {"Differential Mux", "Line 2", "LINPUT2"},
439 {"Differential Mux", "Line 2", "RINPUT2"},
440
441 /* Left ADC Mux */
442 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
443 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
444 {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
445
446 /* Right ADC Mux */
447 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
448 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
449 {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
450
451 /* ADC */
452 {"Left ADC", NULL, "Left ADC Mux"},
453 {"Right ADC", NULL, "Right ADC Mux"},
abadfc92
RP		 454};
455
456static int wm8750_add_widgets(struct snd_soc_codec *codec)
457{
a65f0568
MB		 458 snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets,
459 ARRAY_SIZE(wm8750_dapm_widgets));
abadfc92 460
a65f0568 461 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
abadfc92
RP		 462
463 snd_soc_dapm_new_widgets(codec);
464 return 0;
465}
466
467struct _coeff_div {
468 u32 mclk;
469 u32 rate;
470 u16 fs;
471 u8 sr:5;
472 u8 usb:1;
473};
474
475/* codec hifi mclk clock divider coefficients */
476static const struct _coeff_div coeff_div[] = {
477 /* 8k */
478 {12288000, 8000, 1536, 0x6, 0x0},
479 {11289600, 8000, 1408, 0x16, 0x0},
480 {18432000, 8000, 2304, 0x7, 0x0},
481 {16934400, 8000, 2112, 0x17, 0x0},
482 {12000000, 8000, 1500, 0x6, 0x1},
483
484 /* 11.025k */
485 {11289600, 11025, 1024, 0x18, 0x0},
486 {16934400, 11025, 1536, 0x19, 0x0},
487 {12000000, 11025, 1088, 0x19, 0x1},
488
489 /* 16k */
490 {12288000, 16000, 768, 0xa, 0x0},
491 {18432000, 16000, 1152, 0xb, 0x0},
492 {12000000, 16000, 750, 0xa, 0x1},
493
494 /* 22.05k */
495 {11289600, 22050, 512, 0x1a, 0x0},
496 {16934400, 22050, 768, 0x1b, 0x0},
497 {12000000, 22050, 544, 0x1b, 0x1},
498
499 /* 32k */
500 {12288000, 32000, 384, 0xc, 0x0},
501 {18432000, 32000, 576, 0xd, 0x0},
502 {12000000, 32000, 375, 0xa, 0x1},
503
504 /* 44.1k */
505 {11289600, 44100, 256, 0x10, 0x0},
506 {16934400, 44100, 384, 0x11, 0x0},
507 {12000000, 44100, 272, 0x11, 0x1},
508
509 /* 48k */
510 {12288000, 48000, 256, 0x0, 0x0},
511 {18432000, 48000, 384, 0x1, 0x0},
512 {12000000, 48000, 250, 0x0, 0x1},
513
514 /* 88.2k */
515 {11289600, 88200, 128, 0x1e, 0x0},
516 {16934400, 88200, 192, 0x1f, 0x0},
517 {12000000, 88200, 136, 0x1f, 0x1},
518
519 /* 96k */
520 {12288000, 96000, 128, 0xe, 0x0},
521 {18432000, 96000, 192, 0xf, 0x0},
522 {12000000, 96000, 125, 0xe, 0x1},
523};
524
525static inline int get_coeff(int mclk, int rate)
526{
527 int i;
528
529 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
530 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
531 return i;
532 }
a71a468a
LG		 533
534 printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
535 mclk, rate);
abadfc92
RP		 536 return -EINVAL;
537}
538
e550e17f 539static int wm8750_set_dai_sysclk(struct snd_soc_dai *codec_dai,
4422b606 540 int clk_id, unsigned int freq, int dir)
abadfc92 541{
4422b606
LG		 542 struct snd_soc_codec *codec = codec_dai->codec;
543 struct wm8750_priv *wm8750 = codec->private_data;
544
545 switch (freq) {
546 case 11289600:
547 case 12000000:
548 case 12288000:
549 case 16934400:
550 case 18432000:
551 wm8750->sysclk = freq;
552 return 0;
553 }
554 return -EINVAL;
abadfc92
RP		 555}
556
e550e17f 557static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
4422b606 558 unsigned int fmt)
abadfc92 559{
4422b606
LG		 560 struct snd_soc_codec *codec = codec_dai->codec;
561 u16 iface = 0;
abadfc92
RP		 562
563 /* set master/slave audio interface */
4422b606 564 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
abadfc92
RP		 565 case SND_SOC_DAIFMT_CBM_CFM:
566 iface = 0x0040;
567 break;
568 case SND_SOC_DAIFMT_CBS_CFS:
569 break;
4422b606
LG		 570 default:
571 return -EINVAL;
abadfc92
RP		 572 }
573
574 /* interface format */
4422b606 575 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
abadfc92
RP		 576 case SND_SOC_DAIFMT_I2S:
577 iface |= 0x0002;
578 break;
579 case SND_SOC_DAIFMT_RIGHT_J:
580 break;
581 case SND_SOC_DAIFMT_LEFT_J:
582 iface |= 0x0001;
583 break;
584 case SND_SOC_DAIFMT_DSP_A:
585 iface |= 0x0003;
586 break;
587 case SND_SOC_DAIFMT_DSP_B:
588 iface |= 0x0013;
589 break;
4422b606
LG		 590 default:
591 return -EINVAL;
abadfc92
RP		 592 }
593
594 /* clock inversion */
4422b606 595 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
abadfc92
RP		 596 case SND_SOC_DAIFMT_NB_NF:
597 break;
598 case SND_SOC_DAIFMT_IB_IF:
599 iface |= 0x0090;
600 break;
601 case SND_SOC_DAIFMT_IB_NF:
602 iface |= 0x0080;
603 break;
604 case SND_SOC_DAIFMT_NB_IF:
605 iface |= 0x0010;
606 break;
4422b606
LG		 607 default:
608 return -EINVAL;
abadfc92
RP		 609 }
610
4422b606
LG		 611 wm8750_write(codec, WM8750_IFACE, iface);
612 return 0;
613}
614
615static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
616 struct snd_pcm_hw_params *params)
617{
618 struct snd_soc_pcm_runtime *rtd = substream->private_data;
619 struct snd_soc_device *socdev = rtd->socdev;
620 struct snd_soc_codec *codec = socdev->codec;
621 struct wm8750_priv *wm8750 = codec->private_data;
622 u16 iface = wm8750_read_reg_cache(codec, WM8750_IFACE) & 0x1f3;
623 u16 srate = wm8750_read_reg_cache(codec, WM8750_SRATE) & 0x1c0;
624 int coeff = get_coeff(wm8750->sysclk, params_rate(params));
625
626 /* bit size */
627 switch (params_format(params)) {
628 case SNDRV_PCM_FORMAT_S16_LE:
abadfc92 629 break;
4422b606
LG		 630 case SNDRV_PCM_FORMAT_S20_3LE:
631 iface |= 0x0004;
abadfc92 632 break;
4422b606
LG		 633 case SNDRV_PCM_FORMAT_S24_LE:
634 iface |= 0x0008;
abadfc92 635 break;
4422b606
LG		 636 case SNDRV_PCM_FORMAT_S32_LE:
637 iface |= 0x000c;
abadfc92
RP		 638 break;
639 }
640
641 /* set iface & srate */
642 wm8750_write(codec, WM8750_IFACE, iface);
4422b606
LG		 643 if (coeff >= 0)
644 wm8750_write(codec, WM8750_SRATE, srate |
645 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
abadfc92
RP		 646
647 return 0;
648}
649
e550e17f 650static int wm8750_mute(struct snd_soc_dai *dai, int mute)
abadfc92 651{
4422b606 652 struct snd_soc_codec *codec = dai->codec;
abadfc92 653 u16 mute_reg = wm8750_read_reg_cache(codec, WM8750_ADCDAC) & 0xfff7;
4422b606 654
abadfc92
RP		 655 if (mute)
656 wm8750_write(codec, WM8750_ADCDAC, mute_reg | 0x8);
657 else
658 wm8750_write(codec, WM8750_ADCDAC, mute_reg);
659 return 0;
660}
661
0be9898a
MB		 662static int wm8750_set_bias_level(struct snd_soc_codec *codec,
663 enum snd_soc_bias_level level)
abadfc92
RP		 664{
665 u16 pwr_reg = wm8750_read_reg_cache(codec, WM8750_PWR1) & 0xfe3e;
666
0be9898a
MB		 667 switch (level) {
668 case SND_SOC_BIAS_ON:
abadfc92
RP		 669 /* set vmid to 50k and unmute dac */
670 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x00c0);
671 break;
0be9898a 672 case SND_SOC_BIAS_PREPARE:
abadfc92
RP		 673 /* set vmid to 5k for quick power up */
674 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
675 break;
0be9898a 676 case SND_SOC_BIAS_STANDBY:
abadfc92
RP		 677 /* mute dac and set vmid to 500k, enable VREF */
678 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x0141);
679 break;
0be9898a 680 case SND_SOC_BIAS_OFF:
abadfc92
RP		 681 wm8750_write(codec, WM8750_PWR1, 0x0001);
682 break;
683 }
0be9898a 684 codec->bias_level = level;
abadfc92
RP		 685 return 0;
686}
687
4422b606 688#define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
42f3030f
MB		 689 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
690 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
4422b606
LG		 691
692#define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
693 SNDRV_PCM_FMTBIT_S24_LE)
694
e550e17f 695struct snd_soc_dai wm8750_dai = {
abadfc92
RP		 696 .name = "WM8750",
697 .playback = {
698 .stream_name = "Playback",
699 .channels_min = 1,
700 .channels_max = 2,
4422b606
LG		 701 .rates = WM8750_RATES,
702 .formats = WM8750_FORMATS,},
abadfc92
RP		 703 .capture = {
704 .stream_name = "Capture",
705 .channels_min = 1,
706 .channels_max = 2,
4422b606
LG		 707 .rates = WM8750_RATES,
708 .formats = WM8750_FORMATS,},
abadfc92 709 .ops = {
4422b606 710 .hw_params = wm8750_pcm_hw_params,
abadfc92 711 },
4422b606
LG		 712 .dai_ops = {
713 .digital_mute = wm8750_mute,
714 .set_fmt = wm8750_set_dai_fmt,
715 .set_sysclk = wm8750_set_dai_sysclk,
abadfc92
RP		 716 },
717};
718EXPORT_SYMBOL_GPL(wm8750_dai);
719
1321b160 720static void wm8750_work(struct work_struct *work)
abadfc92 721{
1321b160
TI		 722 struct snd_soc_codec *codec =
723 container_of(work, struct snd_soc_codec, delayed_work.work);
0be9898a 724 wm8750_set_bias_level(codec, codec->bias_level);
abadfc92
RP		 725}
726
727static int wm8750_suspend(struct platform_device *pdev, pm_message_t state)
728{
729 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
730 struct snd_soc_codec *codec = socdev->codec;
731
0be9898a 732 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
abadfc92
RP		 733 return 0;
734}
735
736static int wm8750_resume(struct platform_device *pdev)
737{
738 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
739 struct snd_soc_codec *codec = socdev->codec;
740 int i;
741 u8 data[2];
742 u16 *cache = codec->reg_cache;
743
744 /* Sync reg_cache with the hardware */
745 for (i = 0; i < ARRAY_SIZE(wm8750_reg); i++) {
746 if (i == WM8750_RESET)
747 continue;
748 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
749 data[1] = cache[i] & 0x00ff;
750 codec->hw_write(codec->control_data, data, 2);
751 }
752
0be9898a 753 wm8750_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
abadfc92
RP		 754
755 /* charge wm8750 caps */
0be9898a
MB		 756 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
757 wm8750_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
758 codec->bias_level = SND_SOC_BIAS_ON;
42f3030f
MB		 759 schedule_delayed_work(&codec->delayed_work,
760 msecs_to_jiffies(1000));
abadfc92
RP		 761 }
762
763 return 0;
764}
765
766/*
767 * initialise the WM8750 driver
768 * register the mixer and dsp interfaces with the kernel
769 */
770static int wm8750_init(struct snd_soc_device *socdev)
771{
772 struct snd_soc_codec *codec = socdev->codec;
773 int reg, ret = 0;
774
775 codec->name = "WM8750";
776 codec->owner = THIS_MODULE;
777 codec->read = wm8750_read_reg_cache;
778 codec->write = wm8750_write;
0be9898a 779 codec->set_bias_level = wm8750_set_bias_level;
abadfc92
RP		 780 codec->dai = &wm8750_dai;
781 codec->num_dai = 1;
d751b233 782 codec->reg_cache_size = ARRAY_SIZE(wm8750_reg);
713fb939 783 codec->reg_cache = kmemdup(wm8750_reg, sizeof(wm8750_reg), GFP_KERNEL);
abadfc92
RP		 784 if (codec->reg_cache == NULL)
785 return -ENOMEM;
abadfc92
RP		 786
787 wm8750_reset(codec);
788
789 /* register pcms */
790 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
791 if (ret < 0) {
e35115a5
LG		 792 printk(KERN_ERR "wm8750: failed to create pcms\n");
793 goto pcm_err;
abadfc92
RP		 794 }
795
796 /* charge output caps */
0be9898a
MB		 797 wm8750_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
798 codec->bias_level = SND_SOC_BIAS_STANDBY;
1321b160 799 schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000));
abadfc92
RP		 800
801 /* set the update bits */
802 reg = wm8750_read_reg_cache(codec, WM8750_LDAC);
803 wm8750_write(codec, WM8750_LDAC, reg | 0x0100);
804 reg = wm8750_read_reg_cache(codec, WM8750_RDAC);
805 wm8750_write(codec, WM8750_RDAC, reg | 0x0100);
806 reg = wm8750_read_reg_cache(codec, WM8750_LOUT1V);
807 wm8750_write(codec, WM8750_LOUT1V, reg | 0x0100);
808 reg = wm8750_read_reg_cache(codec, WM8750_ROUT1V);
809 wm8750_write(codec, WM8750_ROUT1V, reg | 0x0100);
810 reg = wm8750_read_reg_cache(codec, WM8750_LOUT2V);
811 wm8750_write(codec, WM8750_LOUT2V, reg | 0x0100);
812 reg = wm8750_read_reg_cache(codec, WM8750_ROUT2V);
813 wm8750_write(codec, WM8750_ROUT2V, reg | 0x0100);
814 reg = wm8750_read_reg_cache(codec, WM8750_LINVOL);
815 wm8750_write(codec, WM8750_LINVOL, reg | 0x0100);
816 reg = wm8750_read_reg_cache(codec, WM8750_RINVOL);
817 wm8750_write(codec, WM8750_RINVOL, reg | 0x0100);
818
819 wm8750_add_controls(codec);
820 wm8750_add_widgets(codec);
821 ret = snd_soc_register_card(socdev);
822 if (ret < 0) {
e35115a5
LG		 823 printk(KERN_ERR "wm8750: failed to register card\n");
824 goto card_err;
abadfc92 825 }
e35115a5 826 return ret;
abadfc92 827
e35115a5
LG		 828card_err:
829 snd_soc_free_pcms(socdev);
830 snd_soc_dapm_free(socdev);
831pcm_err:
832 kfree(codec->reg_cache);
abadfc92
RP		 833 return ret;
834}
835
836/* If the i2c layer weren't so broken, we could pass this kind of data
837 around */
838static struct snd_soc_device *wm8750_socdev;
839
42f3030f 840#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 841
842/*
843 * WM8731 2 wire address is determined by GPIO5
844 * state during powerup.
845 * low = 0x1a
846 * high = 0x1b
847 */
848static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
849
850/* Magic definition of all other variables and things */
851I2C_CLIENT_INSMOD;
852
853static struct i2c_driver wm8750_i2c_driver;
854static struct i2c_client client_template;
855
856static int wm8750_codec_probe(struct i2c_adapter *adap, int addr, int kind)
857{
858 struct snd_soc_device *socdev = wm8750_socdev;
859 struct wm8750_setup_data *setup = socdev->codec_data;
860 struct snd_soc_codec *codec = socdev->codec;
861 struct i2c_client *i2c;
862 int ret;
863
864 if (addr != setup->i2c_address)
865 return -ENODEV;
866
867 client_template.adapter = adap;
868 client_template.addr = addr;
869
88cb4290 870 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
abadfc92
RP		 871 if (i2c == NULL) {
872 kfree(codec);
873 return -ENOMEM;
874 }
abadfc92
RP		 875 i2c_set_clientdata(i2c, codec);
876 codec->control_data = i2c;
877
878 ret = i2c_attach_client(i2c);
879 if (ret < 0) {
a5c95e90 880 pr_err("failed to attach codec at addr %x\n", addr);
abadfc92
RP		 881 goto err;
882 }
883
884 ret = wm8750_init(socdev);
885 if (ret < 0) {
a5c95e90 886 pr_err("failed to initialise WM8750\n");
abadfc92
RP		 887 goto err;
888 }
889 return ret;
890
891err:
892 kfree(codec);
893 kfree(i2c);
894 return ret;
895}
896
897static int wm8750_i2c_detach(struct i2c_client *client)
898{
899 struct snd_soc_codec *codec = i2c_get_clientdata(client);
900 i2c_detach_client(client);
901 kfree(codec->reg_cache);
902 kfree(client);
903 return 0;
904}
905
906static int wm8750_i2c_attach(struct i2c_adapter *adap)
907{
908 return i2c_probe(adap, &addr_data, wm8750_codec_probe);
909}
910
911/* corgi i2c codec control layer */
912static struct i2c_driver wm8750_i2c_driver = {
913 .driver = {
914 .name = "WM8750 I2C Codec",
915 .owner = THIS_MODULE,
916 },
917 .id = I2C_DRIVERID_WM8750,
918 .attach_adapter = wm8750_i2c_attach,
919 .detach_client = wm8750_i2c_detach,
920 .command = NULL,
921};
922
923static struct i2c_client client_template = {
924 .name = "WM8750",
925 .driver = &wm8750_i2c_driver,
926};
927#endif
928
929static int wm8750_probe(struct platform_device *pdev)
930{
931 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
932 struct wm8750_setup_data *setup = socdev->codec_data;
933 struct snd_soc_codec *codec;
4422b606 934 struct wm8750_priv *wm8750;
abadfc92
RP		 935 int ret = 0;
936
a5c95e90 937 pr_info("WM8750 Audio Codec %s", WM8750_VERSION);
abadfc92
RP		 938 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
939 if (codec == NULL)
940 return -ENOMEM;
941
4422b606
LG		 942 wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
943 if (wm8750 == NULL) {
944 kfree(codec);
945 return -ENOMEM;
946 }
947
948 codec->private_data = wm8750;
abadfc92
RP		 949 socdev->codec = codec;
950 mutex_init(&codec->mutex);
951 INIT_LIST_HEAD(&codec->dapm_widgets);
952 INIT_LIST_HEAD(&codec->dapm_paths);
953 wm8750_socdev = socdev;
1321b160 954 INIT_DELAYED_WORK(&codec->delayed_work, wm8750_work);
42f3030f
MB		 955
956#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 957 if (setup->i2c_address) {
958 normal_i2c[0] = setup->i2c_address;
959 codec->hw_write = (hw_write_t)i2c_master_send;
960 ret = i2c_add_driver(&wm8750_i2c_driver);
961 if (ret != 0)
962 printk(KERN_ERR "can't add i2c driver");
963 }
964#else
965 /* Add other interfaces here */
966#endif
967
968 return ret;
969}
970
4422b606
LG		 971/*
972 * This function forces any delayed work to be queued and run.
973 */
974static int run_delayed_work(struct delayed_work *dwork)
975{
976 int ret;
977
978 /* cancel any work waiting to be queued. */
979 ret = cancel_delayed_work(dwork);
980
981 /* if there was any work waiting then we run it now and
982 * wait for it's completion */
983 if (ret) {
984 schedule_delayed_work(dwork, 0);
985 flush_scheduled_work();
986 }
987 return ret;
988}
989
abadfc92
RP		 990/* power down chip */
991static int wm8750_remove(struct platform_device *pdev)
992{
993 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
994 struct snd_soc_codec *codec = socdev->codec;
995
996 if (codec->control_data)
0be9898a 997 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
4422b606 998 run_delayed_work(&codec->delayed_work);
abadfc92
RP		 999 snd_soc_free_pcms(socdev);
1000 snd_soc_dapm_free(socdev);
42f3030f 1001#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 1002 i2c_del_driver(&wm8750_i2c_driver);
1003#endif
4422b606 1004 kfree(codec->private_data);
abadfc92
RP		 1005 kfree(codec);
1006
1007 return 0;
1008}
1009
1010struct snd_soc_codec_device soc_codec_dev_wm8750 = {
1011 .probe = wm8750_probe,
1012 .remove = wm8750_remove,
1013 .suspend = wm8750_suspend,
1014 .resume = wm8750_resume,
1015};
abadfc92
RP		 1016EXPORT_SYMBOL_GPL(soc_codec_dev_wm8750);
1017
1018MODULE_DESCRIPTION("ASoC WM8750 driver");
1019MODULE_AUTHOR("Liam Girdwood");
1020MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.241487 seconds and 5 git commands to generate.