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Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / codecs / wm8900.c
CommitLineData
0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
49992624 26#include <linux/regmap.h>
f0fba2ad 27#include <linux/spi/spi.h>
5a0e3ad6 28#include <linux/slab.h>
0e0e16a8
MB		 29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
0e0e16a8
MB		 33#include <sound/initval.h>
34#include <sound/tlv.h>
35
36#include "wm8900.h"
37
38/* WM8900 register space */
39#define WM8900_REG_RESET 0x0
40#define WM8900_REG_ID 0x0
41#define WM8900_REG_POWER1 0x1
42#define WM8900_REG_POWER2 0x2
43#define WM8900_REG_POWER3 0x3
44#define WM8900_REG_AUDIO1 0x4
45#define WM8900_REG_AUDIO2 0x5
46#define WM8900_REG_CLOCKING1 0x6
47#define WM8900_REG_CLOCKING2 0x7
48#define WM8900_REG_AUDIO3 0x8
49#define WM8900_REG_AUDIO4 0x9
50#define WM8900_REG_DACCTRL 0xa
51#define WM8900_REG_LDAC_DV 0xb
52#define WM8900_REG_RDAC_DV 0xc
53#define WM8900_REG_SIDETONE 0xd
54#define WM8900_REG_ADCCTRL 0xe
55#define WM8900_REG_LADC_DV 0xf
56#define WM8900_REG_RADC_DV 0x10
57#define WM8900_REG_GPIO 0x12
58#define WM8900_REG_INCTL 0x15
59#define WM8900_REG_LINVOL 0x16
60#define WM8900_REG_RINVOL 0x17
61#define WM8900_REG_INBOOSTMIX1 0x18
62#define WM8900_REG_INBOOSTMIX2 0x19
63#define WM8900_REG_ADCPATH 0x1a
64#define WM8900_REG_AUXBOOST 0x1b
65#define WM8900_REG_ADDCTL 0x1e
66#define WM8900_REG_FLLCTL1 0x24
67#define WM8900_REG_FLLCTL2 0x25
68#define WM8900_REG_FLLCTL3 0x26
69#define WM8900_REG_FLLCTL4 0x27
70#define WM8900_REG_FLLCTL5 0x28
71#define WM8900_REG_FLLCTL6 0x29
72#define WM8900_REG_LOUTMIXCTL1 0x2c
73#define WM8900_REG_ROUTMIXCTL1 0x2d
74#define WM8900_REG_BYPASS1 0x2e
75#define WM8900_REG_BYPASS2 0x2f
76#define WM8900_REG_AUXOUT_CTL 0x30
77#define WM8900_REG_LOUT1CTL 0x33
78#define WM8900_REG_ROUT1CTL 0x34
79#define WM8900_REG_LOUT2CTL 0x35
80#define WM8900_REG_ROUT2CTL 0x36
81#define WM8900_REG_HPCTL1 0x3a
82#define WM8900_REG_OUTBIASCTL 0x73
83
84#define WM8900_MAXREG 0x80
85
86#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88#define WM8900_REG_ADDCTL_VMID_DIS 0x20
89#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91#define WM8900_REG_ADDCTL_TEMP_SD 0x02
92
93#define WM8900_REG_GPIO_TEMP_ENA 0x2
94
95#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96#define WM8900_REG_POWER1_BIAS_ENA 0x0008
97#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98#define WM8900_REG_POWER1_FLL_ENA 0x0040
99
100#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101#define WM8900_REG_POWER2_ADCL_ENA 0x0002
102#define WM8900_REG_POWER2_ADCR_ENA 0x0001
103
104#define WM8900_REG_POWER3_DACL_ENA 0x0002
105#define WM8900_REG_POWER3_DACR_ENA 0x0001
106
107#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110
111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
de5035b1
AL		 113#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
114#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
0e0e16a8
MB		 115
116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118
119#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 120#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 121#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
122
123#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
124
125#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
126
127#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
128
129#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
130
131#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
134#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
135#define WM8900_REG_HPCTL1_HP_SHORT 0x08
136#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
137
de5035b1 138#define WM8900_LRC_MASK 0x03ff
0e0e16a8 139
0e0e16a8 140struct wm8900_priv {
49992624 141 struct regmap *regmap;
78e19a39 142
0e0e16a8
MB		 143 u32 fll_in; /* FLL input frequency */
144 u32 fll_out; /* FLL output frequency */
145};
146
147/*
148 * wm8900 register cache. We can't read the entire register space and we
149 * have slow control buses so we cache the registers.
150 */
49992624
MB		 151static const struct reg_default wm8900_reg_defaults[] = {
152 { 1, 0x0000 },
153 { 2, 0xc000 },
154 { 3, 0x0000 },
155 { 4, 0x4050 },
156 { 5, 0x4000 },
157 { 6, 0x0008 },
158 { 7, 0x0000 },
159 { 8, 0x0040 },
160 { 9, 0x0040 },
161 { 10, 0x1004 },
162 { 11, 0x00c0 },
163 { 12, 0x00c0 },
164 { 13, 0x0000 },
165 { 14, 0x0100 },
166 { 15, 0x00c0 },
167 { 16, 0x00c0 },
168 { 17, 0x0000 },
169 { 18, 0xb001 },
170 { 19, 0x0000 },
171 { 20, 0x0000 },
172 { 21, 0x0044 },
173 { 22, 0x004c },
174 { 23, 0x004c },
175 { 24, 0x0044 },
176 { 25, 0x0044 },
177 { 26, 0x0000 },
178 { 27, 0x0044 },
179 { 28, 0x0000 },
180 { 29, 0x0000 },
181 { 30, 0x0002 },
182 { 31, 0x0000 },
183 { 32, 0x0000 },
184 { 33, 0x0000 },
185 { 34, 0x0000 },
186 { 35, 0x0000 },
187 { 36, 0x0008 },
188 { 37, 0x0000 },
189 { 38, 0x0000 },
190 { 39, 0x0008 },
191 { 40, 0x0097 },
192 { 41, 0x0100 },
193 { 42, 0x0000 },
194 { 43, 0x0000 },
195 { 44, 0x0050 },
196 { 45, 0x0050 },
197 { 46, 0x0055 },
198 { 47, 0x0055 },
199 { 48, 0x0055 },
200 { 49, 0x0000 },
201 { 50, 0x0000 },
202 { 51, 0x0079 },
203 { 52, 0x0079 },
204 { 53, 0x0079 },
205 { 54, 0x0079 },
206 { 55, 0x0000 },
0e0e16a8
MB		 207};
208
49992624 209static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
0e0e16a8
MB		 210{
211 switch (reg) {
212 case WM8900_REG_ID:
49992624 213 return true;
0e0e16a8 214 default:
49992624 215 return false;
0e0e16a8
MB		 216 }
217}
218
219static void wm8900_reset(struct snd_soc_codec *codec)
220{
8d50e447 221 snd_soc_write(codec, WM8900_REG_RESET, 0);
0e0e16a8
MB		 222}
223
224static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
225 struct snd_kcontrol *kcontrol, int event)
226{
2de4d649 227 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
8d50e447 228 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
0e0e16a8
MB		 229
230 switch (event) {
231 case SND_SOC_DAPM_PRE_PMU:
232 /* Clamp headphone outputs */
233 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
234 WM8900_REG_HPCTL1_HP_CLAMP_OP;
8d50e447 235 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 236 break;
237
238 case SND_SOC_DAPM_POST_PMU:
239 /* Enable the input stage */
240 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
241 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
242 WM8900_REG_HPCTL1_HP_SHORT2 |
243 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 245
246 msleep(400);
247
248 /* Enable the output stage */
249 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
250 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 251 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 252
253 /* Remove the shorts */
254 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
8d50e447 255 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8 256 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 257 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 258 break;
259
260 case SND_SOC_DAPM_PRE_PMD:
261 /* Short the output */
262 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 263 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 264
265 /* Disable the output stage */
266 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 267 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 268
269 /* Clamp the outputs and power down input */
270 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
271 WM8900_REG_HPCTL1_HP_CLAMP_OP;
272 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 273 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 274 break;
275
276 case SND_SOC_DAPM_POST_PMD:
277 /* Disable everything */
8d50e447 278 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 279 break;
280
281 default:
d9dea396
TI		 282 WARN(1, "Invalid event %d\n", event);
283 break;
0e0e16a8
MB		 284 }
285
286 return 0;
287}
288
289static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
290
291static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
292
293static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
294
295static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
296
297static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
298
299static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
300
301static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
302
303static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
304
305static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
306
9d166314
TI		 307static SOC_ENUM_SINGLE_DECL(mic_bias_level,
308 WM8900_REG_INCTL, 8, mic_bias_level_txt);
0e0e16a8
MB		 309
310static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
311
9d166314
TI		 312static SOC_ENUM_SINGLE_DECL(dac_mute_rate,
313 WM8900_REG_DACCTRL, 7, dac_mute_rate_txt);
0e0e16a8
MB		 314
315static const char *dac_deemphasis_txt[] = {
316 "Disabled", "32kHz", "44.1kHz", "48kHz"
317};
318
9d166314
TI		 319static SOC_ENUM_SINGLE_DECL(dac_deemphasis,
320 WM8900_REG_DACCTRL, 4, dac_deemphasis_txt);
0e0e16a8
MB		 321
322static const char *adc_hpf_cut_txt[] = {
323 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
324};
325
9d166314
TI		 326static SOC_ENUM_SINGLE_DECL(adc_hpf_cut,
327 WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt);
0e0e16a8
MB		 328
329static const char *lr_txt[] = {
330 "Left", "Right"
331};
332
9d166314
TI		 333static SOC_ENUM_SINGLE_DECL(aifl_src,
334 WM8900_REG_AUDIO1, 15, lr_txt);
0e0e16a8 335
9d166314
TI		 336static SOC_ENUM_SINGLE_DECL(aifr_src,
337 WM8900_REG_AUDIO1, 14, lr_txt);
0e0e16a8 338
9d166314
TI		 339static SOC_ENUM_SINGLE_DECL(dacl_src,
340 WM8900_REG_AUDIO2, 15, lr_txt);
0e0e16a8 341
9d166314
TI		 342static SOC_ENUM_SINGLE_DECL(dacr_src,
343 WM8900_REG_AUDIO2, 14, lr_txt);
0e0e16a8
MB		 344
345static const char *sidetone_txt[] = {
346 "Disabled", "Left ADC", "Right ADC"
347};
348
9d166314
TI		 349static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
350 WM8900_REG_SIDETONE, 2, sidetone_txt);
0e0e16a8 351
9d166314
TI		 352static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
353 WM8900_REG_SIDETONE, 0, sidetone_txt);
0e0e16a8
MB		 354
355static const struct snd_kcontrol_new wm8900_snd_controls[] = {
356SOC_ENUM("Mic Bias Level", mic_bias_level),
357
358SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
359 in_pga_tlv),
360SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
361SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
362
363SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
364 in_pga_tlv),
365SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
366SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
367
368SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
369SOC_ENUM("DAC Mute Rate", dac_mute_rate),
370SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
371SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 372SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
373 12, 1, 0),
374
375SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
376SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
377SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
378SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
379 adc_svol_tlv),
380SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
381 adc_svol_tlv),
382SOC_ENUM("Left Digital Audio Source", aifl_src),
383SOC_ENUM("Right Digital Audio Source", aifr_src),
384
385SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
386 dac_boost_tlv),
387SOC_ENUM("Left DAC Source", dacl_src),
388SOC_ENUM("Right DAC Source", dacr_src),
389SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
390SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
391SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
392
393SOC_DOUBLE_R_TLV("Digital Playback Volume",
394 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
395 1, 96, 0, dac_tlv),
396SOC_DOUBLE_R_TLV("Digital Capture Volume",
397 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
398
399SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
400 out_mix_tlv),
401SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
402 out_mix_tlv),
403SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
404 out_mix_tlv),
405SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
406 out_mix_tlv),
407
408SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
409 out_mix_tlv),
410SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
411 out_mix_tlv),
412SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
413 out_mix_tlv),
414SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
415 out_mix_tlv),
416
417SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
418 in_boost_tlv),
419SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
420 in_boost_tlv),
421SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
422 in_boost_tlv),
423SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
424 in_boost_tlv),
425SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
426 in_boost_tlv),
427SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
428 in_boost_tlv),
429
430SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
431 0, 63, 0, out_pga_tlv),
432SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
433 6, 1, 1),
434SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
435 7, 1, 0),
436
437SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
438 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
439 0, 63, 0, out_pga_tlv),
440SOC_DOUBLE_R("LINEOUT2 Switch",
441 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
442SOC_DOUBLE_R("LINEOUT2 ZC Switch",
443 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
444SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
445 0, 1, 1),
446
447};
448
0e0e16a8
MB		 449static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
450SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
451
452static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
453SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
454
455static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
456SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
457SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
458SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
459SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
460SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
461};
462
463static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
464SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
465SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
466SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
467SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
468SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
469};
470
471static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
472SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
473SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
474SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
475SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
476};
477
478static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
479SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
480SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
481SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
482SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
483};
484
485static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
486SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
487SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
488SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
489};
490
491static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
492SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
493SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
494SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
495};
496
7e94ca47 497static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
0e0e16a8 498
9d166314
TI		 499static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux,
500 WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux);
0e0e16a8
MB		 501
502static const struct snd_kcontrol_new wm8900_lineout2_lp =
503SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
504
505static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
506
507/* Externally visible pins */
508SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
509SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
510SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
511SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
512SND_SOC_DAPM_OUTPUT("HP_L"),
513SND_SOC_DAPM_OUTPUT("HP_R"),
514
515SND_SOC_DAPM_INPUT("RINPUT1"),
516SND_SOC_DAPM_INPUT("LINPUT1"),
517SND_SOC_DAPM_INPUT("RINPUT2"),
518SND_SOC_DAPM_INPUT("LINPUT2"),
519SND_SOC_DAPM_INPUT("RINPUT3"),
520SND_SOC_DAPM_INPUT("LINPUT3"),
521SND_SOC_DAPM_INPUT("AUX"),
522
523SND_SOC_DAPM_VMID("VMID"),
524
525/* Input */
526SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
527 wm8900_linpga_controls,
528 ARRAY_SIZE(wm8900_linpga_controls)),
529SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
530 wm8900_rinpga_controls,
531 ARRAY_SIZE(wm8900_rinpga_controls)),
532
533SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
534 wm8900_linmix_controls,
535 ARRAY_SIZE(wm8900_linmix_controls)),
536SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
537 wm8900_rinmix_controls,
538 ARRAY_SIZE(wm8900_rinmix_controls)),
539
8a709d92 540SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
0e0e16a8
MB		 541
542SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
543SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
544
545/* Output */
546SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
547SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
548
549SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
550 wm8900_hp_event,
551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
552 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
553
554SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
555SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
556
557SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
558SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
559SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
560
561SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
562 wm8900_loutmix_controls,
563 ARRAY_SIZE(wm8900_loutmix_controls)),
564SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
565 wm8900_routmix_controls,
566 ARRAY_SIZE(wm8900_routmix_controls)),
567};
568
569/* Target, Path, Source */
46ce904f 570static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
0e0e16a8
MB		 571/* Inputs */
572{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
573{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
574{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
575
576{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
577{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
578{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
579
580{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
581{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
582{"Left Input Mixer", "AUX Switch", "AUX"},
583{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
584
585{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
586{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
587{"Right Input Mixer", "AUX Switch", "AUX"},
588{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
589
590{"ADCL", NULL, "Left Input Mixer"},
591{"ADCR", NULL, "Right Input Mixer"},
592
593/* Outputs */
594{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
595{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
596{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
597{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
598
599{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
600{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
601{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
602{"LINEOUT2L", NULL, "LINEOUT2 LP"},
603
604{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
605{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
606{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
607{"LINEOUT2R", NULL, "LINEOUT2 LP"},
608
609{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
610{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
611{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
612{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
613{"Left Output Mixer", "DACL Switch", "DACL"},
614
615{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
616{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
617{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
618{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
619{"Right Output Mixer", "DACR Switch", "DACR"},
620
621/* Note that the headphone output stage needs to be connected
622 * externally to LINEOUT2 via DC blocking capacitors. Other
623 * configurations are not supported.
624 *
625 * Note also that left and right headphone paths are treated as a
626 * mono path.
627 */
628{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
629{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
630{"HP_L", NULL, "Headphone Amplifier"},
631{"HP_R", NULL, "Headphone Amplifier"},
632};
633
0e0e16a8 634static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 635 struct snd_pcm_hw_params *params,
636 struct snd_soc_dai *dai)
0e0e16a8 637{
e6968a17 638 struct snd_soc_codec *codec = dai->codec;
0e0e16a8
MB		 639 u16 reg;
640
8d50e447 641 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
0e0e16a8 642
0cd44891
MB		 643 switch (params_width(params)) {
644 case 16:
0e0e16a8 645 break;
0cd44891 646 case 20:
0e0e16a8
MB		 647 reg |= 0x20;
648 break;
0cd44891 649 case 24:
0e0e16a8
MB		 650 reg |= 0x40;
651 break;
0cd44891 652 case 32:
0e0e16a8
MB		 653 reg |= 0x60;
654 break;
655 default:
656 return -EINVAL;
657 }
658
8d50e447 659 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
0e0e16a8 660
21002e20 661 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
8d50e447 662 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
21002e20
MB		 663
664 if (params_rate(params) <= 24000)
665 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
666 else
667 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
668
8d50e447 669 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
21002e20
MB		 670 }
671
0e0e16a8
MB		 672 return 0;
673}
674
675/* FLL divisors */
676struct _fll_div {
677 u16 fll_ratio;
678 u16 fllclk_div;
679 u16 fll_slow_lock_ref;
680 u16 n;
681 u16 k;
682};
683
684/* The size in bits of the FLL divide multiplied by 10
685 * to allow rounding later */
686#define FIXED_FLL_SIZE ((1 << 16) * 10)
687
688static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
689 unsigned int Fout)
690{
691 u64 Kpart;
692 unsigned int K, Ndiv, Nmod, target;
693 unsigned int div;
694
246e884b
TI		 695 if (WARN_ON(!Fout))
696 return -EINVAL;
0e0e16a8
MB		 697
698 /* The FLL must run at 90-100MHz which is then scaled down to
699 * the output value by FLLCLK_DIV. */
700 target = Fout;
701 div = 1;
702 while (target < 90000000) {
703 div *= 2;
704 target *= 2;
705 }
706
707 if (target > 100000000)
449bd54d
RK		 708 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
709 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 710 if (div > 32) {
711 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 712 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 713 div, Fref, Fout, target);
714 return -EINVAL;
715 }
716
717 fll_div->fllclk_div = div >> 2;
718
719 if (Fref < 48000)
720 fll_div->fll_slow_lock_ref = 1;
721 else
722 fll_div->fll_slow_lock_ref = 0;
723
724 Ndiv = target / Fref;
725
726 if (Fref < 1000000)
727 fll_div->fll_ratio = 8;
728 else
729 fll_div->fll_ratio = 1;
730
731 fll_div->n = Ndiv / fll_div->fll_ratio;
732 Nmod = (target / fll_div->fll_ratio) % Fref;
733
734 /* Calculate fractional part - scale up so we can round. */
735 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
736
737 do_div(Kpart, Fref);
738
739 K = Kpart & 0xFFFFFFFF;
740
741 if ((K % 10) >= 5)
742 K += 5;
743
744 /* Move down to proper range now rounding is done */
745 fll_div->k = K / 10;
746
246e884b
TI		 747 if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
748 WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
749 return -EINVAL;
0e0e16a8
MB		 750
751 return 0;
752}
753
754static int wm8900_set_fll(struct snd_soc_codec *codec,
755 int fll_id, unsigned int freq_in, unsigned int freq_out)
756{
b2c812e2 757 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8 758 struct _fll_div fll_div;
0e0e16a8
MB		 759
760 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
761 return 0;
762
763 /* The digital side should be disabled during any change. */
29c6a01d
AL		 764 snd_soc_update_bits(codec, WM8900_REG_POWER1,
765 WM8900_REG_POWER1_FLL_ENA, 0);
0e0e16a8
MB		 766
767 /* Disable the FLL? */
768 if (!freq_in || !freq_out) {
29c6a01d
AL		 769 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
770 WM8900_REG_CLOCKING1_MCLK_SRC, 0);
771 snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
772 WM8900_REG_FLLCTL1_OSC_ENA, 0);
0e0e16a8
MB		 773 wm8900->fll_in = freq_in;
774 wm8900->fll_out = freq_out;
775
776 return 0;
777 }
778
779 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
780 goto reenable;
781
782 wm8900->fll_in = freq_in;
783 wm8900->fll_out = freq_out;
784
785 /* The osclilator *MUST* be enabled before we enable the
786 * digital circuit. */
8d50e447 787 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 788 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
789
8d50e447
MB		 790 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
791 snd_soc_write(codec, WM8900_REG_FLLCTL5,
0e0e16a8
MB		 792 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
793
794 if (fll_div.k) {
8d50e447 795 snd_soc_write(codec, WM8900_REG_FLLCTL2,
0e0e16a8 796 (fll_div.k >> 8) | 0x100);
8d50e447 797 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0e0e16a8 798 } else
8d50e447 799 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
0e0e16a8
MB		 800
801 if (fll_div.fll_slow_lock_ref)
8d50e447 802 snd_soc_write(codec, WM8900_REG_FLLCTL6,
0e0e16a8
MB		 803 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
804 else
8d50e447 805 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
0e0e16a8 806
29c6a01d
AL		 807 snd_soc_update_bits(codec, WM8900_REG_POWER1,
808 WM8900_REG_POWER1_FLL_ENA,
809 WM8900_REG_POWER1_FLL_ENA);
0e0e16a8
MB		 810
811reenable:
29c6a01d
AL		 812 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
813 WM8900_REG_CLOCKING1_MCLK_SRC,
814 WM8900_REG_CLOCKING1_MCLK_SRC);
0e0e16a8
MB		 815 return 0;
816}
817
85488037
MB		 818static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
819 int source, unsigned int freq_in, unsigned int freq_out)
0e0e16a8
MB		 820{
821 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
822}
823
824static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
825 int div_id, int div)
826{
827 struct snd_soc_codec *codec = codec_dai->codec;
0e0e16a8
MB		 828
829 switch (div_id) {
830 case WM8900_BCLK_DIV:
29c6a01d
AL		 831 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
832 WM8900_REG_CLOCKING1_BCLK_MASK, div);
0e0e16a8
MB		 833 break;
834 case WM8900_OPCLK_DIV:
29c6a01d
AL		 835 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
836 WM8900_REG_CLOCKING1_OPCLK_MASK, div);
0e0e16a8
MB		 837 break;
838 case WM8900_DAC_LRCLK:
29c6a01d
AL		 839 snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
840 WM8900_LRC_MASK, div);
0e0e16a8
MB		 841 break;
842 case WM8900_ADC_LRCLK:
29c6a01d
AL		 843 snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
844 WM8900_LRC_MASK, div);
0e0e16a8
MB		 845 break;
846 case WM8900_DAC_CLKDIV:
29c6a01d
AL		 847 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
848 WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
0e0e16a8
MB		 849 break;
850 case WM8900_ADC_CLKDIV:
29c6a01d
AL		 851 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
852 WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
0e0e16a8
MB		 853 break;
854 case WM8900_LRCLK_MODE:
29c6a01d
AL		 855 snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
856 WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
0e0e16a8
MB		 857 break;
858 default:
859 return -EINVAL;
860 }
861
862 return 0;
863}
864
865
866static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
867 unsigned int fmt)
868{
869 struct snd_soc_codec *codec = codec_dai->codec;
870 unsigned int clocking1, aif1, aif3, aif4;
871
8d50e447
MB		 872 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
873 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
874 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
875 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
0e0e16a8
MB		 876
877 /* set master/slave audio interface */
878 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
879 case SND_SOC_DAIFMT_CBS_CFS:
880 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
881 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
882 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
883 break;
884 case SND_SOC_DAIFMT_CBS_CFM:
885 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
886 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
887 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
888 break;
889 case SND_SOC_DAIFMT_CBM_CFM:
890 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
891 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
892 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
893 break;
894 case SND_SOC_DAIFMT_CBM_CFS:
895 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
896 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
897 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
898 break;
899 default:
900 return -EINVAL;
901 }
902
903 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
904 case SND_SOC_DAIFMT_DSP_A:
905 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
906 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
907 break;
908 case SND_SOC_DAIFMT_DSP_B:
909 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
910 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
911 break;
912 case SND_SOC_DAIFMT_I2S:
913 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
914 aif1 |= 0x10;
915 break;
916 case SND_SOC_DAIFMT_RIGHT_J:
917 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
918 break;
919 case SND_SOC_DAIFMT_LEFT_J:
920 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
921 aif1 |= 0x8;
922 break;
923 default:
924 return -EINVAL;
925 }
926
927 /* Clock inversion */
928 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
929 case SND_SOC_DAIFMT_DSP_A:
930 case SND_SOC_DAIFMT_DSP_B:
931 /* frame inversion not valid for DSP modes */
932 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
933 case SND_SOC_DAIFMT_NB_NF:
934 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
935 break;
936 case SND_SOC_DAIFMT_IB_NF:
937 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
938 break;
939 default:
940 return -EINVAL;
941 }
942 break;
943 case SND_SOC_DAIFMT_I2S:
944 case SND_SOC_DAIFMT_RIGHT_J:
945 case SND_SOC_DAIFMT_LEFT_J:
946 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
947 case SND_SOC_DAIFMT_NB_NF:
948 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
949 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
950 break;
951 case SND_SOC_DAIFMT_IB_IF:
952 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
953 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
954 break;
955 case SND_SOC_DAIFMT_IB_NF:
956 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
957 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
958 break;
959 case SND_SOC_DAIFMT_NB_IF:
960 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
961 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
962 break;
963 default:
964 return -EINVAL;
965 }
966 break;
967 default:
968 return -EINVAL;
969 }
970
8d50e447
MB		 971 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
972 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
973 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
974 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
0e0e16a8
MB		 975
976 return 0;
977}
978
979static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
980{
981 struct snd_soc_codec *codec = codec_dai->codec;
982 u16 reg;
983
8d50e447 984 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
0e0e16a8
MB		 985
986 if (mute)
987 reg |= WM8900_REG_DACCTRL_MUTE;
988 else
989 reg &= ~WM8900_REG_DACCTRL_MUTE;
990
8d50e447 991 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
0e0e16a8
MB		 992
993 return 0;
994}
995
996#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
997 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
998 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
999
1000#define WM8900_PCM_FORMATS \
e712bfca
MS		 1001 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1002 SNDRV_PCM_FMTBIT_S24_LE)
0e0e16a8 1003
85e7652d 1004static const struct snd_soc_dai_ops wm8900_dai_ops = {
6335d055
EM		 1005 .hw_params = wm8900_hw_params,
1006 .set_clkdiv = wm8900_set_dai_clkdiv,
1007 .set_pll = wm8900_set_dai_pll,
1008 .set_fmt = wm8900_set_dai_fmt,
1009 .digital_mute = wm8900_digital_mute,
1010};
1011
f0fba2ad
LG		 1012static struct snd_soc_dai_driver wm8900_dai = {
1013 .name = "wm8900-hifi",
0e0e16a8
MB		 1014 .playback = {
1015 .stream_name = "HiFi Playback",
1016 .channels_min = 1,
1017 .channels_max = 2,
1018 .rates = WM8900_RATES,
1019 .formats = WM8900_PCM_FORMATS,
1020 },
1021 .capture = {
1022 .stream_name = "HiFi Capture",
1023 .channels_min = 1,
1024 .channels_max = 2,
1025 .rates = WM8900_RATES,
1026 .formats = WM8900_PCM_FORMATS,
1027 },
6335d055 1028 .ops = &wm8900_dai_ops,
0e0e16a8 1029};
0e0e16a8
MB		 1030
1031static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1032 enum snd_soc_bias_level level)
1033{
1034 u16 reg;
1035
1036 switch (level) {
1037 case SND_SOC_BIAS_ON:
1038 /* Enable thermal shutdown */
29c6a01d
AL		 1039 snd_soc_update_bits(codec, WM8900_REG_GPIO,
1040 WM8900_REG_GPIO_TEMP_ENA,
1041 WM8900_REG_GPIO_TEMP_ENA);
1042 snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
1043 WM8900_REG_ADDCTL_TEMP_SD,
1044 WM8900_REG_ADDCTL_TEMP_SD);
0e0e16a8
MB		 1045 break;
1046
1047 case SND_SOC_BIAS_PREPARE:
1048 break;
1049
1050 case SND_SOC_BIAS_STANDBY:
1051 /* Charge capacitors if initial power up */
eee53c35 1052 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
0e0e16a8 1053 /* STARTUP_BIAS_ENA on */
8d50e447 1054 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1055 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1056
1057 /* Startup bias mode */
8d50e447 1058 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1059 WM8900_REG_ADDCTL_BIAS_SRC |
1060 WM8900_REG_ADDCTL_VMID_SOFTST);
1061
1062 /* VMID 2x50k */
8d50e447 1063 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1064 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1065
1066 /* Allow capacitors to charge */
1067 schedule_timeout_interruptible(msecs_to_jiffies(400));
1068
1069 /* Enable bias */
8d50e447 1070 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1071 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1072 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1073
8d50e447 1074 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
0e0e16a8 1075
8d50e447 1076 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1077 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1078 }
1079
8d50e447
MB		 1080 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1081 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1082 (reg & WM8900_REG_POWER1_FLL_ENA) |
1083 WM8900_REG_POWER1_BIAS_ENA | 0x1);
8d50e447 1084 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8 1085 WM8900_REG_POWER2_SYSCLK_ENA);
8d50e447 1086 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1087 break;
1088
1089 case SND_SOC_BIAS_OFF:
1090 /* Startup bias enable */
8d50e447
MB		 1091 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1092 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8 1093 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
8d50e447 1094 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1095 WM8900_REG_ADDCTL_BIAS_SRC |
1096 WM8900_REG_ADDCTL_VMID_SOFTST);
1097
1098 /* Discharge caps */
8d50e447 1099 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1100 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1101 schedule_timeout_interruptible(msecs_to_jiffies(500));
1102
1103 /* Remove clamp */
8d50e447 1104 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 1105
1106 /* Power down */
8d50e447
MB		 1107 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1108 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1109 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1110 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1111
1112 /* Need to let things settle before stopping the clock
1113 * to ensure that restart works, see "Stopping the
1114 * master clock" in the datasheet. */
1115 schedule_timeout_interruptible(msecs_to_jiffies(1));
8d50e447 1116 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8
MB		 1117 WM8900_REG_POWER2_SYSCLK_ENA);
1118 break;
1119 }
0e0e16a8
MB		 1120 return 0;
1121}
1122
84b315ee 1123static int wm8900_suspend(struct snd_soc_codec *codec)
0e0e16a8 1124{
b2c812e2 1125 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1126 int fll_out = wm8900->fll_out;
1127 int fll_in = wm8900->fll_in;
1128 int ret;
1129
1130 /* Stop the FLL in an orderly fashion */
1131 ret = wm8900_set_fll(codec, 0, 0, 0);
1132 if (ret != 0) {
f0fba2ad 1133 dev_err(codec->dev, "Failed to stop FLL\n");
0e0e16a8
MB		 1134 return ret;
1135 }
1136
1137 wm8900->fll_out = fll_out;
1138 wm8900->fll_in = fll_in;
1139
bd1204cb 1140 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
0e0e16a8
MB		 1141
1142 return 0;
1143}
1144
f0fba2ad 1145static int wm8900_resume(struct snd_soc_codec *codec)
0e0e16a8 1146{
b2c812e2 1147 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
49992624 1148 int ret;
0e0e16a8
MB		 1149
1150 wm8900_reset(codec);
49992624
MB		 1151
1152 ret = regcache_sync(wm8900->regmap);
1153 if (ret != 0) {
1154 dev_err(codec->dev, "Failed to restore cache: %d\n", ret);
1155 return ret;
1156 }
1157
bd1204cb 1158 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
0e0e16a8
MB		 1159
1160 /* Restart the FLL? */
1161 if (wm8900->fll_out) {
1162 int fll_out = wm8900->fll_out;
1163 int fll_in = wm8900->fll_in;
1164
1165 wm8900->fll_in = 0;
1166 wm8900->fll_out = 0;
1167
1168 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1169 if (ret != 0) {
f0fba2ad 1170 dev_err(codec->dev, "Failed to restart FLL\n");
0e0e16a8
MB		 1171 return ret;
1172 }
1173 }
1174
0e0e16a8
MB		 1175 return 0;
1176}
1177
f0fba2ad 1178static int wm8900_probe(struct snd_soc_codec *codec)
0e0e16a8 1179{
5d6be5aa 1180 int reg;
8d50e447
MB		 1181
1182 reg = snd_soc_read(codec, WM8900_REG_ID);
0e0e16a8 1183 if (reg != 0x8900) {
f0fba2ad
LG		 1184 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1185 return -ENODEV;
0e0e16a8
MB		 1186 }
1187
0e0e16a8
MB		 1188 wm8900_reset(codec);
1189
78e19a39 1190 /* Turn the chip on */
bd1204cb 1191 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
78e19a39 1192
0e0e16a8 1193 /* Latch the volume update bits */
29c6a01d
AL		 1194 snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
1195 snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
1196 snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1197 snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1198 snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1199 snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1200 snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
1201 snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
1202 snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
1203 snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
0e0e16a8
MB		 1204
1205 /* Set the DAC and mixer output bias */
8d50e447 1206 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
0e0e16a8 1207
f0fba2ad
LG		 1208 return 0;
1209}
0e0e16a8 1210
f0fba2ad
LG		 1211static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1212 .probe = wm8900_probe,
f0fba2ad
LG		 1213 .suspend = wm8900_suspend,
1214 .resume = wm8900_resume,
1215 .set_bias_level = wm8900_set_bias_level,
46ce904f
MB		 1216
1217 .controls = wm8900_snd_controls,
1218 .num_controls = ARRAY_SIZE(wm8900_snd_controls),
1219 .dapm_widgets = wm8900_dapm_widgets,
1220 .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
1221 .dapm_routes = wm8900_dapm_routes,
1222 .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
f0fba2ad 1223};
0e0e16a8 1224
49992624
MB		 1225static const struct regmap_config wm8900_regmap = {
1226 .reg_bits = 8,
1227 .val_bits = 16,
1228 .max_register = WM8900_MAXREG,
1229
1230 .reg_defaults = wm8900_reg_defaults,
1231 .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
1232 .cache_type = REGCACHE_RBTREE,
1233
1234 .volatile_reg = wm8900_volatile_register,
1235};
1236
f0fba2ad 1237#if defined(CONFIG_SPI_MASTER)
7a79e94e 1238static int wm8900_spi_probe(struct spi_device *spi)
f0fba2ad
LG		 1239{
1240 struct wm8900_priv *wm8900;
1241 int ret;
1242
6a58870d
MB		 1243 wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
1244 GFP_KERNEL);
f0fba2ad
LG		 1245 if (wm8900 == NULL)
1246 return -ENOMEM;
0e0e16a8 1247
49992624
MB		 1248 wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
1249 if (IS_ERR(wm8900->regmap))
1250 return PTR_ERR(wm8900->regmap);
1251
f0fba2ad
LG		 1252 spi_set_drvdata(spi, wm8900);
1253
1254 ret = snd_soc_register_codec(&spi->dev,
1255 &soc_codec_dev_wm8900, &wm8900_dai, 1);
6a58870d 1256
78e19a39 1257 return ret;
0e0e16a8
MB		 1258}
1259
7a79e94e 1260static int wm8900_spi_remove(struct spi_device *spi)
0e0e16a8 1261{
f0fba2ad 1262 snd_soc_unregister_codec(&spi->dev);
f0fba2ad
LG		 1263 return 0;
1264}
78e19a39 1265
f0fba2ad
LG		 1266static struct spi_driver wm8900_spi_driver = {
1267 .driver = {
091edccf 1268 .name = "wm8900",
f0fba2ad
LG		 1269 .owner = THIS_MODULE,
1270 },
1271 .probe = wm8900_spi_probe,
7a79e94e 1272 .remove = wm8900_spi_remove,
f0fba2ad
LG		 1273};
1274#endif /* CONFIG_SPI_MASTER */
1275
f25cf349 1276#if IS_ENABLED(CONFIG_I2C)
7a79e94e
BP		 1277static int wm8900_i2c_probe(struct i2c_client *i2c,
1278 const struct i2c_device_id *id)
f0fba2ad
LG		 1279{
1280 struct wm8900_priv *wm8900;
1281 int ret;
1282
6a58870d
MB		 1283 wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
1284 GFP_KERNEL);
f0fba2ad
LG		 1285 if (wm8900 == NULL)
1286 return -ENOMEM;
1287
49992624
MB		 1288 wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
1289 if (IS_ERR(wm8900->regmap))
1290 return PTR_ERR(wm8900->regmap);
1291
f0fba2ad 1292 i2c_set_clientdata(i2c, wm8900);
78e19a39 1293
f0fba2ad
LG		 1294 ret = snd_soc_register_codec(&i2c->dev,
1295 &soc_codec_dev_wm8900, &wm8900_dai, 1);
6a58870d 1296
f0fba2ad
LG		 1297 return ret;
1298}
78e19a39 1299
7a79e94e 1300static int wm8900_i2c_remove(struct i2c_client *client)
f0fba2ad
LG		 1301{
1302 snd_soc_unregister_codec(&client->dev);
0e0e16a8
MB		 1303 return 0;
1304}
1305
8ae6a552
JD		 1306static const struct i2c_device_id wm8900_i2c_id[] = {
1307 { "wm8900", 0 },
1308 { }
1309};
1310MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1311
0e0e16a8
MB		 1312static struct i2c_driver wm8900_i2c_driver = {
1313 .driver = {
091edccf 1314 .name = "wm8900",
0e0e16a8 1315 },
f0fba2ad 1316 .probe = wm8900_i2c_probe,
7a79e94e 1317 .remove = wm8900_i2c_remove,
8ae6a552 1318 .id_table = wm8900_i2c_id,
0e0e16a8 1319};
f0fba2ad 1320#endif
0e0e16a8 1321
f0fba2ad 1322static int __init wm8900_modinit(void)
0e0e16a8 1323{
0e0e16a8 1324 int ret = 0;
f25cf349 1325#if IS_ENABLED(CONFIG_I2C)
f0fba2ad
LG		 1326 ret = i2c_add_driver(&wm8900_i2c_driver);
1327 if (ret != 0) {
1328 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1329 ret);
f0752331 1330 }
f0fba2ad
LG		 1331#endif
1332#if defined(CONFIG_SPI_MASTER)
1333 ret = spi_register_driver(&wm8900_spi_driver);
1334 if (ret != 0) {
1335 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1336 ret);
78e19a39 1337 }
f0fba2ad 1338#endif
0e0e16a8
MB		 1339 return ret;
1340}
64089b84
MB		 1341module_init(wm8900_modinit);
1342
1343static void __exit wm8900_exit(void)
1344{
f25cf349 1345#if IS_ENABLED(CONFIG_I2C)
f0752331 1346 i2c_del_driver(&wm8900_i2c_driver);
f0fba2ad
LG		 1347#endif
1348#if defined(CONFIG_SPI_MASTER)
1349 spi_unregister_driver(&wm8900_spi_driver);
1350#endif
64089b84
MB		 1351}
1352module_exit(wm8900_exit);
1353
0e0e16a8
MB		 1354MODULE_DESCRIPTION("ASoC WM8900 driver");
1355MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1356MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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