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ASoC: Actively manage WM8903 DC servo configuration
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
c5b6a9fe
MB		 226 int dcs_pending;
227 int dcs_cache[4];
228
f2c1fe09 229 /* Reference count */
d58d5d55 230 int class_w_users;
d58d5d55 231
8abd16a6
MB		 232 struct completion wseq;
233
7245387e
MB		 234 struct snd_soc_jack *mic_jack;
235 int mic_det;
236 int mic_short;
237 int mic_last_report;
238 int mic_delay;
7cfe5617
SW		 239
240#ifdef CONFIG_GPIOLIB
241 struct gpio_chip gpio_chip;
242#endif
d58d5d55
MB		 243};
244
d4754ec9 245static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 246{
247 switch (reg) {
248 case WM8903_SW_RESET_AND_ID:
249 case WM8903_REVISION_NUMBER:
250 case WM8903_INTERRUPT_STATUS_1:
251 case WM8903_WRITE_SEQUENCER_4:
13a9983e
MB		 252 case WM8903_POWER_MANAGEMENT_3:
253 case WM8903_POWER_MANAGEMENT_2:
c5b6a9fe
MB		 254 case WM8903_DC_SERVO_READBACK_1:
255 case WM8903_DC_SERVO_READBACK_2:
256 case WM8903_DC_SERVO_READBACK_3:
257 case WM8903_DC_SERVO_READBACK_4:
8d50e447 258 return 1;
f1c0a02f
MB		 259
260 default:
f1c0a02f 261 return 0;
8d50e447 262 }
f1c0a02f
MB		 263}
264
265static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
266{
267 u16 reg[5];
b2c812e2 268 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 269
270 BUG_ON(start > 48);
271
37f88e84 272 /* Enable the sequencer if it's not already on */
8d50e447 273 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 274 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
275 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 276
f0fba2ad 277 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 278
8d50e447 279 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 280 start | WM8903_WSEQ_START);
281
282 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 283 * that will break us out of the poll early.
f1c0a02f
MB		 284 */
285 do {
8abd16a6
MB		 286 wait_for_completion_timeout(&wm8903->wseq,
287 msecs_to_jiffies(10));
f1c0a02f 288
8d50e447 289 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 290 } while (reg[4] & WM8903_WSEQ_BUSY);
291
f0fba2ad 292 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 293
37f88e84
MB		 294 /* Disable the sequencer again if we enabled it */
295 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 296
297 return 0;
298}
299
300static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
301{
302 int i;
303
304 /* There really ought to be something better we can do here :/ */
305 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 306 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 307}
308
309static void wm8903_reset(struct snd_soc_codec *codec)
310{
8d50e447 311 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 312 memcpy(codec->reg_cache, wm8903_reg_defaults,
313 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 314}
315
42768a12
MB		 316static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
317 struct snd_kcontrol *kcontrol, int event)
318{
319 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
320 mdelay(4);
321
322 return 0;
323}
324
c5b6a9fe
MB		 325static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
326 struct snd_kcontrol *kcontrol, int event)
327{
328 struct snd_soc_codec *codec = w->codec;
329 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
330
331 switch (event) {
332 case SND_SOC_DAPM_POST_PMU:
333 wm8903->dcs_pending |= 1 << w->shift;
334 break;
335 case SND_SOC_DAPM_PRE_PMD:
336 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
337 1 << w->shift, 0);
338 break;
339 }
340
341 return 0;
342}
343
344#define WM8903_DCS_MODE_WRITE_STOP 0
345#define WM8903_DCS_MODE_START_STOP 2
346
347static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
348 enum snd_soc_dapm_type event, int subseq)
349{
350 struct snd_soc_codec *codec = container_of(dapm,
351 struct snd_soc_codec, dapm);
352 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
353 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
354 int i, val;
355
356 /* Complete any pending DC servo starts */
357 if (wm8903->dcs_pending) {
358 dev_dbg(codec->dev, "Starting DC servo for %x\n",
359 wm8903->dcs_pending);
360
361 /* If we've no cached values then we need to do startup */
362 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
363 if (!(wm8903->dcs_pending & (1 << i)))
364 continue;
365
366 if (wm8903->dcs_cache[i]) {
367 dev_dbg(codec->dev,
368 "Restore DC servo %d value %x\n",
369 3 - i, wm8903->dcs_cache[i]);
370
371 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
372 wm8903->dcs_cache[i] & 0xff);
373 } else {
374 dev_dbg(codec->dev,
375 "Calibrate DC servo %d\n", 3 - i);
376 dcs_mode = WM8903_DCS_MODE_START_STOP;
377 }
378 }
379
380 /* Don't trust the cache for analogue */
381 if (wm8903->class_w_users)
382 dcs_mode = WM8903_DCS_MODE_START_STOP;
383
384 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
385 WM8903_DCS_MODE_MASK, dcs_mode);
386
387 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
388 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
389
390 switch (dcs_mode) {
391 case WM8903_DCS_MODE_WRITE_STOP:
392 break;
393
394 case WM8903_DCS_MODE_START_STOP:
395 msleep(270);
396
397 /* Cache the measured offsets for digital */
398 if (wm8903->class_w_users)
399 break;
400
401 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
402 if (!(wm8903->dcs_pending & (1 << i)))
403 continue;
404
405 val = snd_soc_read(codec,
406 WM8903_DC_SERVO_READBACK_1 + i);
407 dev_dbg(codec->dev, "DC servo %d: %x\n",
408 3 - i, val);
409 wm8903->dcs_cache[i] = val;
410 }
411 break;
412
413 default:
414 pr_warn("DCS mode %d delay not set\n", dcs_mode);
415 break;
416 }
417
418 wm8903->dcs_pending = 0;
419 }
420}
421
f1c0a02f
MB		 422/*
423 * When used with DAC outputs only the WM8903 charge pump supports
424 * operation in class W mode, providing very low power consumption
425 * when used with digital sources. Enable and disable this mode
426 * automatically depending on the mixer configuration.
427 *
428 * All the relevant controls are simple switches.
429 */
430static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
431 struct snd_ctl_elem_value *ucontrol)
432{
433 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
434 struct snd_soc_codec *codec = widget->codec;
b2c812e2 435 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 436 u16 reg;
437 int ret;
438
8d50e447 439 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 440
441 /* Turn it off if we're about to enable bypass */
442 if (ucontrol->value.integer.value[0]) {
443 if (wm8903->class_w_users == 0) {
f0fba2ad 444 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 445 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 446 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
447 }
448 wm8903->class_w_users++;
449 }
450
451 /* Implement the change */
452 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
453
454 /* If we've just disabled the last bypass path turn Class W on */
455 if (!ucontrol->value.integer.value[0]) {
456 if (wm8903->class_w_users == 1) {
f0fba2ad 457 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 458 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 459 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
460 }
461 wm8903->class_w_users--;
462 }
463
f0fba2ad 464 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 465 wm8903->class_w_users);
466
467 return ret;
468}
469
470#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
471{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
472 .info = snd_soc_info_volsw, \
473 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
474 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
475
476
69fff9bb
MB		 477static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
478
479static int wm8903_set_deemph(struct snd_soc_codec *codec)
480{
481 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
482 int val, i, best;
483
484 /* If we're using deemphasis select the nearest available sample
485 * rate.
486 */
487 if (wm8903->deemph) {
488 best = 1;
489 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
490 if (abs(wm8903_deemph[i] - wm8903->fs) <
491 abs(wm8903_deemph[best] - wm8903->fs))
492 best = i;
493 }
494
495 val = best << WM8903_DEEMPH_SHIFT;
496 } else {
497 best = 0;
498 val = 0;
499 }
500
501 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
502 best, wm8903_deemph[best]);
503
504 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
505 WM8903_DEEMPH_MASK, val);
506}
507
508static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
509 struct snd_ctl_elem_value *ucontrol)
510{
511 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
512 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
513
514 ucontrol->value.enumerated.item[0] = wm8903->deemph;
515
516 return 0;
517}
518
519static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
520 struct snd_ctl_elem_value *ucontrol)
521{
522 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
523 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
524 int deemph = ucontrol->value.enumerated.item[0];
525 int ret = 0;
526
527 if (deemph > 1)
528 return -EINVAL;
529
530 mutex_lock(&codec->mutex);
531 if (wm8903->deemph != deemph) {
532 wm8903->deemph = deemph;
533
534 wm8903_set_deemph(codec);
535
536 ret = 1;
537 }
538 mutex_unlock(&codec->mutex);
539
540 return ret;
541}
542
f1c0a02f
MB		 543/* ALSA can only do steps of .01dB */
544static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
545
291ce18c 546static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 547static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
548
549static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
550static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
551static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
552static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
553static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
554
460f4aae
MB		 555static const char *hpf_mode_text[] = {
556 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
557};
558
559static const struct soc_enum hpf_mode =
560 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
561
dcf9ada3
MB		 562static const char *osr_text[] = {
563 "Low power", "High performance"
564};
565
566static const struct soc_enum adc_osr =
567 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
568
569static const struct soc_enum dac_osr =
570 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
571
f1c0a02f
MB		 572static const char *drc_slope_text[] = {
573 "1", "1/2", "1/4", "1/8", "1/16", "0"
574};
575
576static const struct soc_enum drc_slope_r0 =
577 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
578
579static const struct soc_enum drc_slope_r1 =
580 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
581
582static const char *drc_attack_text[] = {
583 "instantaneous",
584 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
585 "46.4ms", "92.8ms", "185.6ms"
586};
587
588static const struct soc_enum drc_attack =
589 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
590
591static const char *drc_decay_text[] = {
592 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
593 "23.87s", "47.56s"
594};
595
596static const struct soc_enum drc_decay =
597 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
598
599static const char *drc_ff_delay_text[] = {
600 "5 samples", "9 samples"
601};
602
603static const struct soc_enum drc_ff_delay =
604 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
605
606static const char *drc_qr_decay_text[] = {
607 "0.725ms", "1.45ms", "5.8ms"
608};
609
610static const struct soc_enum drc_qr_decay =
611 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
612
613static const char *drc_smoothing_text[] = {
614 "Low", "Medium", "High"
615};
616
617static const struct soc_enum drc_smoothing =
618 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
619
620static const char *soft_mute_text[] = {
621 "Fast (fs/2)", "Slow (fs/32)"
622};
623
624static const struct soc_enum soft_mute =
625 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
626
627static const char *mute_mode_text[] = {
628 "Hard", "Soft"
629};
630
631static const struct soc_enum mute_mode =
632 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
633
f1c0a02f
MB		 634static const char *companding_text[] = {
635 "ulaw", "alaw"
636};
637
638static const struct soc_enum dac_companding =
639 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
640
641static const struct soc_enum adc_companding =
642 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
643
644static const char *input_mode_text[] = {
645 "Single-Ended", "Differential Line", "Differential Mic"
646};
647
648static const struct soc_enum linput_mode_enum =
649 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
650
651static const struct soc_enum rinput_mode_enum =
652 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
653
654static const char *linput_mux_text[] = {
655 "IN1L", "IN2L", "IN3L"
656};
657
658static const struct soc_enum linput_enum =
659 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
660
661static const struct soc_enum linput_inv_enum =
662 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
663
664static const char *rinput_mux_text[] = {
665 "IN1R", "IN2R", "IN3R"
666};
667
668static const struct soc_enum rinput_enum =
669 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
670
671static const struct soc_enum rinput_inv_enum =
672 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
673
674
291ce18c
MB		 675static const char *sidetone_text[] = {
676 "None", "Left", "Right"
677};
678
679static const struct soc_enum lsidetone_enum =
680 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
681
682static const struct soc_enum rsidetone_enum =
683 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
684
1e113bf9
MB		 685static const char *aif_text[] = {
686 "Left", "Right"
687};
688
689static const struct soc_enum lcapture_enum =
690 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
691
692static const struct soc_enum rcapture_enum =
693 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
694
695static const struct soc_enum lplay_enum =
696 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
697
698static const struct soc_enum rplay_enum =
699 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
700
f1c0a02f
MB		 701static const struct snd_kcontrol_new wm8903_snd_controls[] = {
702
703/* Input PGAs - No TLV since the scale depends on PGA mode */
704SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 705 7, 1, 1),
f1c0a02f
MB		 706SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
707 0, 31, 0),
708SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
709 6, 1, 0),
710
711SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 712 7, 1, 1),
f1c0a02f
MB		 713SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
714 0, 31, 0),
715SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
716 6, 1, 0),
717
718/* ADCs */
dcf9ada3 719SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 720SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
721SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 722SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
723SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
724SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 725SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 726 drc_tlv_thresh),
727SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
728SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
729SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
730SOC_ENUM("DRC Attack Rate", drc_attack),
731SOC_ENUM("DRC Decay Rate", drc_decay),
732SOC_ENUM("DRC FF Delay", drc_ff_delay),
733SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
734SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 735SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 736SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
737SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
738SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 739SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 740SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
741
742SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
743 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
744SOC_ENUM("ADC Companding Mode", adc_companding),
745SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
746
291ce18c
MB		 747SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
748 12, 0, digital_sidetone_tlv),
749
f1c0a02f 750/* DAC */
dcf9ada3 751SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 752SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
753 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
754SOC_ENUM("DAC Soft Mute Rate", soft_mute),
755SOC_ENUM("DAC Mute Mode", mute_mode),
756SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 757SOC_ENUM("DAC Companding Mode", dac_companding),
758SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 759SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
760 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 761
762/* Headphones */
763SOC_DOUBLE_R("Headphone Switch",
764 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
765 8, 1, 1),
766SOC_DOUBLE_R("Headphone ZC Switch",
767 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
768 6, 1, 0),
769SOC_DOUBLE_R_TLV("Headphone Volume",
770 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
771 0, 63, 0, out_tlv),
772
773/* Line out */
774SOC_DOUBLE_R("Line Out Switch",
775 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
776 8, 1, 1),
777SOC_DOUBLE_R("Line Out ZC Switch",
778 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
779 6, 1, 0),
780SOC_DOUBLE_R_TLV("Line Out Volume",
781 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
782 0, 63, 0, out_tlv),
783
784/* Speaker */
785SOC_DOUBLE_R("Speaker Switch",
786 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
787SOC_DOUBLE_R("Speaker ZC Switch",
788 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
789SOC_DOUBLE_R_TLV("Speaker Volume",
790 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
791 0, 63, 0, out_tlv),
792};
793
f1c0a02f
MB		 794static const struct snd_kcontrol_new linput_mode_mux =
795 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
796
797static const struct snd_kcontrol_new rinput_mode_mux =
798 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
799
800static const struct snd_kcontrol_new linput_mux =
801 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
802
803static const struct snd_kcontrol_new linput_inv_mux =
804 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
805
806static const struct snd_kcontrol_new rinput_mux =
807 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
808
809static const struct snd_kcontrol_new rinput_inv_mux =
810 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
811
291ce18c
MB		 812static const struct snd_kcontrol_new lsidetone_mux =
813 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
814
815static const struct snd_kcontrol_new rsidetone_mux =
816 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
817
1e113bf9
MB		 818static const struct snd_kcontrol_new lcapture_mux =
819 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
820
821static const struct snd_kcontrol_new rcapture_mux =
822 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
823
824static const struct snd_kcontrol_new lplay_mux =
825 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
826
827static const struct snd_kcontrol_new rplay_mux =
828 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
829
f1c0a02f
MB		 830static const struct snd_kcontrol_new left_output_mixer[] = {
831SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
832SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
833SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 834SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 835};
836
837static const struct snd_kcontrol_new right_output_mixer[] = {
838SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
839SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
840SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 841SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 842};
843
844static const struct snd_kcontrol_new left_speaker_mixer[] = {
845SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
846SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
847SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
848SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 849 0, 1, 0),
f1c0a02f
MB		 850};
851
852static const struct snd_kcontrol_new right_speaker_mixer[] = {
853SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
854SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
855SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
856 1, 1, 0),
857SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 858 0, 1, 0),
f1c0a02f
MB		 859};
860
861static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
862SND_SOC_DAPM_INPUT("IN1L"),
863SND_SOC_DAPM_INPUT("IN1R"),
864SND_SOC_DAPM_INPUT("IN2L"),
865SND_SOC_DAPM_INPUT("IN2R"),
866SND_SOC_DAPM_INPUT("IN3L"),
867SND_SOC_DAPM_INPUT("IN3R"),
868
869SND_SOC_DAPM_OUTPUT("HPOUTL"),
870SND_SOC_DAPM_OUTPUT("HPOUTR"),
871SND_SOC_DAPM_OUTPUT("LINEOUTL"),
872SND_SOC_DAPM_OUTPUT("LINEOUTR"),
873SND_SOC_DAPM_OUTPUT("LOP"),
874SND_SOC_DAPM_OUTPUT("LON"),
875SND_SOC_DAPM_OUTPUT("ROP"),
876SND_SOC_DAPM_OUTPUT("RON"),
877
878SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
879
880SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
881SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
882 &linput_inv_mux),
883SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
884
885SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
886SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
887 &rinput_inv_mux),
888SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
889
890SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
891SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
892
1e113bf9
MB		 893SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
894SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
895
896SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
897SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
898
899SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
900SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 901
291ce18c
MB		 902SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
903SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
904
1e113bf9
MB		 905SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
906SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
907
908SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
909SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
910
911SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
912SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 913
914SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
915 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
916SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
917 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
918
919SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
920 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
921SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
922 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
923
13a9983e
MB		 924SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
925 4, 0, NULL, 0),
926SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
927 0, 0, NULL, 0),
928
929SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
930 NULL, 0),
931SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
932 NULL, 0),
933
934SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
935SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
936SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
937SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
938SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
939SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
940
941SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
942 NULL, 0),
943SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
944 NULL, 0),
945SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
946 NULL, 0),
947SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
948 NULL, 0),
949SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
950 NULL, 0),
951SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
952 NULL, 0),
953
c5b6a9fe
MB		 954SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
955SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
956 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
957SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
958 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
959SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
960 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
961SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
962 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 963
964SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
965 NULL, 0),
966SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
967 NULL, 0),
968
42768a12
MB		 969SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
970 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 971SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 972SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 973};
974
975static const struct snd_soc_dapm_route intercon[] = {
976
2c8be5a2
MB		 977 { "CLK_DSP", NULL, "CLK_SYS" },
978 { "Mic Bias", NULL, "CLK_SYS" },
979 { "HPL_DCS", NULL, "CLK_SYS" },
980 { "HPR_DCS", NULL, "CLK_SYS" },
981 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
982 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
983
f1c0a02f
MB		 984 { "Left Input Mux", "IN1L", "IN1L" },
985 { "Left Input Mux", "IN2L", "IN2L" },
986 { "Left Input Mux", "IN3L", "IN3L" },
987
988 { "Left Input Inverting Mux", "IN1L", "IN1L" },
989 { "Left Input Inverting Mux", "IN2L", "IN2L" },
990 { "Left Input Inverting Mux", "IN3L", "IN3L" },
991
992 { "Right Input Mux", "IN1R", "IN1R" },
993 { "Right Input Mux", "IN2R", "IN2R" },
994 { "Right Input Mux", "IN3R", "IN3R" },
995
996 { "Right Input Inverting Mux", "IN1R", "IN1R" },
997 { "Right Input Inverting Mux", "IN2R", "IN2R" },
998 { "Right Input Inverting Mux", "IN3R", "IN3R" },
999
1000 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
1001 { "Left Input Mode Mux", "Differential Line",
1002 "Left Input Mux" },
1003 { "Left Input Mode Mux", "Differential Line",
1004 "Left Input Inverting Mux" },
1005 { "Left Input Mode Mux", "Differential Mic",
1006 "Left Input Mux" },
1007 { "Left Input Mode Mux", "Differential Mic",
1008 "Left Input Inverting Mux" },
1009
1010 { "Right Input Mode Mux", "Single-Ended",
1011 "Right Input Inverting Mux" },
1012 { "Right Input Mode Mux", "Differential Line",
1013 "Right Input Mux" },
1014 { "Right Input Mode Mux", "Differential Line",
1015 "Right Input Inverting Mux" },
1016 { "Right Input Mode Mux", "Differential Mic",
1017 "Right Input Mux" },
1018 { "Right Input Mode Mux", "Differential Mic",
1019 "Right Input Inverting Mux" },
1020
1021 { "Left Input PGA", NULL, "Left Input Mode Mux" },
1022 { "Right Input PGA", NULL, "Right Input Mode Mux" },
1023
1e113bf9
MB		 1024 { "Left Capture Mux", "Left", "ADCL" },
1025 { "Left Capture Mux", "Right", "ADCR" },
1026
1027 { "Right Capture Mux", "Left", "ADCL" },
1028 { "Right Capture Mux", "Right", "ADCR" },
1029
1030 { "AIFTXL", NULL, "Left Capture Mux" },
1031 { "AIFTXR", NULL, "Right Capture Mux" },
1032
f1c0a02f 1033 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 1034 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 1035 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 1036 { "ADCR", NULL, "CLK_DSP" },
1037
1e113bf9
MB		 1038 { "Left Playback Mux", "Left", "AIFRXL" },
1039 { "Left Playback Mux", "Right", "AIFRXR" },
1040
1041 { "Right Playback Mux", "Left", "AIFRXL" },
1042 { "Right Playback Mux", "Right", "AIFRXR" },
1043
291ce18c
MB		 1044 { "DACL Sidetone", "Left", "ADCL" },
1045 { "DACL Sidetone", "Right", "ADCR" },
1046 { "DACR Sidetone", "Left", "ADCL" },
1047 { "DACR Sidetone", "Right", "ADCR" },
1048
1e113bf9 1049 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1050 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1051 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1052
1053 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1054 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1055 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1056
1057 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1058 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1059 { "Left Output Mixer", "DACL Switch", "DACL" },
1060 { "Left Output Mixer", "DACR Switch", "DACR" },
1061
1062 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1063 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1064 { "Right Output Mixer", "DACL Switch", "DACL" },
1065 { "Right Output Mixer", "DACR Switch", "DACR" },
1066
1067 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1068 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1069 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1070 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1071
1072 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1073 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1074 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1075 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1076
1077 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1078 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1079
1080 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1081 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1082
1083 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1084 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1085
13a9983e
MB		 1086 { "HPL_ENA_DLY", NULL, "Left Headphone Output PGA" },
1087 { "HPR_ENA_DLY", NULL, "Right Headphone Output PGA" },
1088 { "LINEOUTL_ENA_DLY", NULL, "Left Line Output PGA" },
1089 { "LINEOUTR_ENA_DLY", NULL, "Right Line Output PGA" },
1090
c5b6a9fe
MB		 1091 { "HPL_DCS", NULL, "DCS Master" },
1092 { "HPR_DCS", NULL, "DCS Master" },
1093 { "LINEOUTL_DCS", NULL, "DCS Master" },
1094 { "LINEOUTR_DCS", NULL, "DCS Master" },
1095
13a9983e
MB		 1096 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1097 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1098 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1099 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1100
1101 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1102 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1103 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1104 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1105
1106 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1107 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1108 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1109 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1110
1111 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1112 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1113 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1114 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1115
1116 { "LOP", NULL, "Left Speaker PGA" },
1117 { "LON", NULL, "Left Speaker PGA" },
1118
1119 { "ROP", NULL, "Right Speaker PGA" },
1120 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1121
1122 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1123 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1124 { "Left Line Output PGA", NULL, "Charge Pump" },
1125 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1126};
1127
1128static int wm8903_add_widgets(struct snd_soc_codec *codec)
1129{
ce6120cc 1130 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1131
ce6120cc
LG		 1132 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1133 ARRAY_SIZE(wm8903_dapm_widgets));
1134 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1135
f1c0a02f
MB		 1136 return 0;
1137}
1138
1139static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1140 enum snd_soc_bias_level level)
1141{
524d7692 1142 u16 reg;
f1c0a02f
MB		 1143
1144 switch (level) {
1145 case SND_SOC_BIAS_ON:
1146 case SND_SOC_BIAS_PREPARE:
8d50e447 1147 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1148 reg &= ~(WM8903_VMID_RES_MASK);
1149 reg |= WM8903_VMID_RES_50K;
8d50e447 1150 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1151 break;
1152
1153 case SND_SOC_BIAS_STANDBY:
ce6120cc 1154 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1155 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1156 WM8903_CLK_SYS_ENA);
1157
4dbfe809 1158 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1159 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1160 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1161 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1162
f1c0a02f
MB		 1163 wm8903_run_sequence(codec, 0);
1164 wm8903_sync_reg_cache(codec, codec->reg_cache);
1165
f1c0a02f
MB		 1166 /* By default no bypass paths are enabled so
1167 * enable Class W support.
1168 */
f0fba2ad 1169 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1170 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1171 WM8903_CP_DYN_FREQ |
1172 WM8903_CP_DYN_V,
1173 WM8903_CP_DYN_FREQ |
1174 WM8903_CP_DYN_V);
f1c0a02f
MB		 1175 }
1176
8d50e447 1177 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1178 reg &= ~(WM8903_VMID_RES_MASK);
1179 reg |= WM8903_VMID_RES_250K;
8d50e447 1180 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1181 break;
1182
1183 case SND_SOC_BIAS_OFF:
2c8be5a2
MB		 1184 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1185 WM8903_CLK_SYS_ENA, WM8903_CLK_SYS_ENA);
f1c0a02f 1186 wm8903_run_sequence(codec, 32);
2c8be5a2
MB		 1187 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1188 WM8903_CLK_SYS_ENA, 0);
f1c0a02f
MB		 1189 break;
1190 }
1191
ce6120cc 1192 codec->dapm.bias_level = level;
f1c0a02f
MB		 1193
1194 return 0;
1195}
1196
1197static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1198 int clk_id, unsigned int freq, int dir)
1199{
1200 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1201 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1202
1203 wm8903->sysclk = freq;
1204
1205 return 0;
1206}
1207
1208static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1209 unsigned int fmt)
1210{
1211 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1212 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1213
1214 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1215 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1216
1217 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1218 case SND_SOC_DAIFMT_CBS_CFS:
1219 break;
1220 case SND_SOC_DAIFMT_CBS_CFM:
1221 aif1 |= WM8903_LRCLK_DIR;
1222 break;
1223 case SND_SOC_DAIFMT_CBM_CFM:
1224 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1225 break;
1226 case SND_SOC_DAIFMT_CBM_CFS:
1227 aif1 |= WM8903_BCLK_DIR;
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232
1233 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1234 case SND_SOC_DAIFMT_DSP_A:
1235 aif1 |= 0x3;
1236 break;
1237 case SND_SOC_DAIFMT_DSP_B:
1238 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1239 break;
1240 case SND_SOC_DAIFMT_I2S:
1241 aif1 |= 0x2;
1242 break;
1243 case SND_SOC_DAIFMT_RIGHT_J:
1244 aif1 |= 0x1;
1245 break;
1246 case SND_SOC_DAIFMT_LEFT_J:
1247 break;
1248 default:
1249 return -EINVAL;
1250 }
1251
1252 /* Clock inversion */
1253 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1254 case SND_SOC_DAIFMT_DSP_A:
1255 case SND_SOC_DAIFMT_DSP_B:
1256 /* frame inversion not valid for DSP modes */
1257 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1258 case SND_SOC_DAIFMT_NB_NF:
1259 break;
1260 case SND_SOC_DAIFMT_IB_NF:
1261 aif1 |= WM8903_AIF_BCLK_INV;
1262 break;
1263 default:
1264 return -EINVAL;
1265 }
1266 break;
1267 case SND_SOC_DAIFMT_I2S:
1268 case SND_SOC_DAIFMT_RIGHT_J:
1269 case SND_SOC_DAIFMT_LEFT_J:
1270 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1271 case SND_SOC_DAIFMT_NB_NF:
1272 break;
1273 case SND_SOC_DAIFMT_IB_IF:
1274 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1275 break;
1276 case SND_SOC_DAIFMT_IB_NF:
1277 aif1 |= WM8903_AIF_BCLK_INV;
1278 break;
1279 case SND_SOC_DAIFMT_NB_IF:
1280 aif1 |= WM8903_AIF_LRCLK_INV;
1281 break;
1282 default:
1283 return -EINVAL;
1284 }
1285 break;
1286 default:
1287 return -EINVAL;
1288 }
1289
8d50e447 1290 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1291
1292 return 0;
1293}
1294
1295static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1296{
1297 struct snd_soc_codec *codec = codec_dai->codec;
1298 u16 reg;
1299
8d50e447 1300 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1301
1302 if (mute)
1303 reg |= WM8903_DAC_MUTE;
1304 else
1305 reg &= ~WM8903_DAC_MUTE;
1306
8d50e447 1307 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1308
1309 return 0;
1310}
1311
1312/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1313 * for optimal performance so we list the lower rates first and match
1314 * on the last match we find. */
1315static struct {
1316 int div;
1317 int rate;
1318 int mode;
1319 int mclk_div;
1320} clk_sys_ratios[] = {
1321 { 64, 0x0, 0x0, 1 },
1322 { 68, 0x0, 0x1, 1 },
1323 { 125, 0x0, 0x2, 1 },
1324 { 128, 0x1, 0x0, 1 },
1325 { 136, 0x1, 0x1, 1 },
1326 { 192, 0x2, 0x0, 1 },
1327 { 204, 0x2, 0x1, 1 },
1328
1329 { 64, 0x0, 0x0, 2 },
1330 { 68, 0x0, 0x1, 2 },
1331 { 125, 0x0, 0x2, 2 },
1332 { 128, 0x1, 0x0, 2 },
1333 { 136, 0x1, 0x1, 2 },
1334 { 192, 0x2, 0x0, 2 },
1335 { 204, 0x2, 0x1, 2 },
1336
1337 { 250, 0x2, 0x2, 1 },
1338 { 256, 0x3, 0x0, 1 },
1339 { 272, 0x3, 0x1, 1 },
1340 { 384, 0x4, 0x0, 1 },
1341 { 408, 0x4, 0x1, 1 },
1342 { 375, 0x4, 0x2, 1 },
1343 { 512, 0x5, 0x0, 1 },
1344 { 544, 0x5, 0x1, 1 },
1345 { 500, 0x5, 0x2, 1 },
1346 { 768, 0x6, 0x0, 1 },
1347 { 816, 0x6, 0x1, 1 },
1348 { 750, 0x6, 0x2, 1 },
1349 { 1024, 0x7, 0x0, 1 },
1350 { 1088, 0x7, 0x1, 1 },
1351 { 1000, 0x7, 0x2, 1 },
1352 { 1408, 0x8, 0x0, 1 },
1353 { 1496, 0x8, 0x1, 1 },
1354 { 1536, 0x9, 0x0, 1 },
1355 { 1632, 0x9, 0x1, 1 },
1356 { 1500, 0x9, 0x2, 1 },
1357
1358 { 250, 0x2, 0x2, 2 },
1359 { 256, 0x3, 0x0, 2 },
1360 { 272, 0x3, 0x1, 2 },
1361 { 384, 0x4, 0x0, 2 },
1362 { 408, 0x4, 0x1, 2 },
1363 { 375, 0x4, 0x2, 2 },
1364 { 512, 0x5, 0x0, 2 },
1365 { 544, 0x5, 0x1, 2 },
1366 { 500, 0x5, 0x2, 2 },
1367 { 768, 0x6, 0x0, 2 },
1368 { 816, 0x6, 0x1, 2 },
1369 { 750, 0x6, 0x2, 2 },
1370 { 1024, 0x7, 0x0, 2 },
1371 { 1088, 0x7, 0x1, 2 },
1372 { 1000, 0x7, 0x2, 2 },
1373 { 1408, 0x8, 0x0, 2 },
1374 { 1496, 0x8, 0x1, 2 },
1375 { 1536, 0x9, 0x0, 2 },
1376 { 1632, 0x9, 0x1, 2 },
1377 { 1500, 0x9, 0x2, 2 },
1378};
1379
1380/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1381static struct {
1382 int ratio;
1383 int div;
1384} bclk_divs[] = {
1385 { 10, 0 },
f1c0a02f
MB		 1386 { 20, 2 },
1387 { 30, 3 },
1388 { 40, 4 },
1389 { 50, 5 },
f1c0a02f
MB		 1390 { 60, 7 },
1391 { 80, 8 },
1392 { 100, 9 },
f1c0a02f
MB		 1393 { 120, 11 },
1394 { 160, 12 },
1395 { 200, 13 },
1396 { 220, 14 },
1397 { 240, 15 },
f1c0a02f
MB		 1398 { 300, 17 },
1399 { 320, 18 },
1400 { 440, 19 },
1401 { 480, 20 },
1402};
1403
1404/* Sample rates for DSP */
1405static struct {
1406 int rate;
1407 int value;
1408} sample_rates[] = {
1409 { 8000, 0 },
1410 { 11025, 1 },
1411 { 12000, 2 },
1412 { 16000, 3 },
1413 { 22050, 4 },
1414 { 24000, 5 },
1415 { 32000, 6 },
1416 { 44100, 7 },
1417 { 48000, 8 },
1418 { 88200, 9 },
1419 { 96000, 10 },
1420 { 0, 0 },
1421};
1422
f1c0a02f 1423static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1424 struct snd_pcm_hw_params *params,
1425 struct snd_soc_dai *dai)
f1c0a02f
MB		 1426{
1427 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1428 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1429 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1430 int fs = params_rate(params);
1431 int bclk;
1432 int bclk_div;
1433 int i;
1434 int dsp_config;
1435 int clk_config;
1436 int best_val;
1437 int cur_val;
1438 int clk_sys;
1439
8d50e447
MB		 1440 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1441 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1442 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1443 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1444 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1445 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1446
9e79261f
MB		 1447 /* Enable sloping stopband filter for low sample rates */
1448 if (fs <= 24000)
1449 dac_digital1 |= WM8903_DAC_SB_FILT;
1450 else
1451 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1452
f1c0a02f
MB		 1453 /* Configure sample rate logic for DSP - choose nearest rate */
1454 dsp_config = 0;
1455 best_val = abs(sample_rates[dsp_config].rate - fs);
1456 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1457 cur_val = abs(sample_rates[i].rate - fs);
1458 if (cur_val <= best_val) {
1459 dsp_config = i;
1460 best_val = cur_val;
1461 }
1462 }
1463
f0fba2ad 1464 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1465 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1466 clock1 |= sample_rates[dsp_config].value;
1467
1468 aif1 &= ~WM8903_AIF_WL_MASK;
1469 bclk = 2 * fs;
1470 switch (params_format(params)) {
1471 case SNDRV_PCM_FORMAT_S16_LE:
1472 bclk *= 16;
1473 break;
1474 case SNDRV_PCM_FORMAT_S20_3LE:
1475 bclk *= 20;
1476 aif1 |= 0x4;
1477 break;
1478 case SNDRV_PCM_FORMAT_S24_LE:
1479 bclk *= 24;
1480 aif1 |= 0x8;
1481 break;
1482 case SNDRV_PCM_FORMAT_S32_LE:
1483 bclk *= 32;
1484 aif1 |= 0xc;
1485 break;
1486 default:
1487 return -EINVAL;
1488 }
1489
f0fba2ad 1490 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1491 wm8903->sysclk, fs);
1492
1493 /* We may not have an MCLK which allows us to generate exactly
1494 * the clock we want, particularly with USB derived inputs, so
1495 * approximate.
1496 */
1497 clk_config = 0;
1498 best_val = abs((wm8903->sysclk /
1499 (clk_sys_ratios[0].mclk_div *
1500 clk_sys_ratios[0].div)) - fs);
1501 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1502 cur_val = abs((wm8903->sysclk /
1503 (clk_sys_ratios[i].mclk_div *
1504 clk_sys_ratios[i].div)) - fs);
1505
1506 if (cur_val <= best_val) {
1507 clk_config = i;
1508 best_val = cur_val;
1509 }
1510 }
1511
1512 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1513 clock0 |= WM8903_MCLKDIV2;
1514 clk_sys = wm8903->sysclk / 2;
1515 } else {
1516 clock0 &= ~WM8903_MCLKDIV2;
1517 clk_sys = wm8903->sysclk;
1518 }
1519
1520 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1521 WM8903_CLK_SYS_MODE_MASK);
1522 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1523 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1524
f0fba2ad 1525 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1526 clk_sys_ratios[clk_config].rate,
1527 clk_sys_ratios[clk_config].mode,
1528 clk_sys_ratios[clk_config].div);
1529
f0fba2ad 1530 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1531
1532 /* We may not get quite the right frequency if using
1533 * approximate clocks so look for the closest match that is
1534 * higher than the target (we need to ensure that there enough
1535 * BCLKs to clock out the samples).
1536 */
1537 bclk_div = 0;
1538 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1539 i = 1;
1540 while (i < ARRAY_SIZE(bclk_divs)) {
1541 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1542 if (cur_val < 0) /* BCLK table is sorted */
1543 break;
1544 bclk_div = i;
1545 best_val = cur_val;
1546 i++;
1547 }
1548
1549 aif2 &= ~WM8903_BCLK_DIV_MASK;
1550 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1551
f0fba2ad 1552 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1553 bclk_divs[bclk_div].ratio / 10, bclk,
1554 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1555
1556 aif2 |= bclk_divs[bclk_div].div;
1557 aif3 |= bclk / fs;
1558
69fff9bb
MB		 1559 wm8903->fs = params_rate(params);
1560 wm8903_set_deemph(codec);
1561
8d50e447
MB		 1562 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1563 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1564 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1565 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1566 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1567 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1568
1569 return 0;
1570}
1571
7245387e
MB		 1572/**
1573 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1574 *
1575 * @codec: WM8903 codec
1576 * @jack: jack to report detection events on
1577 * @det: value to report for presence detection
1578 * @shrt: value to report for short detection
1579 *
1580 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1581 * being used to bring out signals to the processor then only platform
1582 * data configuration is needed for WM8903 and processor GPIOs should
1583 * be configured using snd_soc_jack_add_gpios() instead.
1584 *
1585 * The current threasholds for detection should be configured using
1586 * micdet_cfg in the platform data. Using this function will force on
1587 * the microphone bias for the device.
1588 */
1589int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1590 int det, int shrt)
1591{
b2c812e2 1592 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1593 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1594
1595 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1596 det, shrt);
1597
1598 /* Store the configuration */
1599 wm8903->mic_jack = jack;
1600 wm8903->mic_det = det;
1601 wm8903->mic_short = shrt;
1602
1603 /* Enable interrupts we've got a report configured for */
1604 if (det)
1605 irq_mask &= ~WM8903_MICDET_EINT;
1606 if (shrt)
1607 irq_mask &= ~WM8903_MICSHRT_EINT;
1608
1609 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1610 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1611 irq_mask);
1612
69266866
MB		 1613 if (det && shrt) {
1614 /* Enable mic detection, this may not have been set through
1615 * platform data (eg, if the defaults are OK). */
1616 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1617 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1618 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1619 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1620 } else {
1621 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1622 WM8903_MICDET_ENA, 0);
1623 }
7245387e
MB		 1624
1625 return 0;
1626}
1627EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1628
8abd16a6
MB		 1629static irqreturn_t wm8903_irq(int irq, void *data)
1630{
f0fba2ad
LG		 1631 struct snd_soc_codec *codec = data;
1632 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1633 int mic_report;
1634 int int_pol;
1635 int int_val = 0;
1636 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1637
7245387e 1638 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1639
7245387e 1640 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1641 dev_dbg(codec->dev, "Write sequencer done\n");
1642 complete(&wm8903->wseq);
1643 }
1644
7245387e
MB		 1645 /*
1646 * The rest is microphone jack detection. We need to manually
1647 * invert the polarity of the interrupt after each event - to
1648 * simplify the code keep track of the last state we reported
1649 * and just invert the relevant bits in both the report and
1650 * the polarity register.
1651 */
1652 mic_report = wm8903->mic_last_report;
1653 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1654
1435b940 1655#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1656 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1657 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1658#endif
2bbb5d66 1659
7245387e
MB		 1660 if (int_val & WM8903_MICSHRT_EINT) {
1661 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1662
1663 mic_report ^= wm8903->mic_short;
1664 int_pol ^= WM8903_MICSHRT_INV;
1665 }
1666
1667 if (int_val & WM8903_MICDET_EINT) {
1668 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1669
1670 mic_report ^= wm8903->mic_det;
1671 int_pol ^= WM8903_MICDET_INV;
1672
1673 msleep(wm8903->mic_delay);
1674 }
1675
1676 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1677 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1678
1679 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1680 wm8903->mic_short | wm8903->mic_det);
1681
1682 wm8903->mic_last_report = mic_report;
1683
8abd16a6
MB		 1684 return IRQ_HANDLED;
1685}
1686
f1c0a02f
MB		 1687#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1688 SNDRV_PCM_RATE_11025 | \
1689 SNDRV_PCM_RATE_16000 | \
1690 SNDRV_PCM_RATE_22050 | \
1691 SNDRV_PCM_RATE_32000 | \
1692 SNDRV_PCM_RATE_44100 | \
1693 SNDRV_PCM_RATE_48000 | \
1694 SNDRV_PCM_RATE_88200 | \
1695 SNDRV_PCM_RATE_96000)
1696
1697#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1698 SNDRV_PCM_RATE_11025 | \
1699 SNDRV_PCM_RATE_16000 | \
1700 SNDRV_PCM_RATE_22050 | \
1701 SNDRV_PCM_RATE_32000 | \
1702 SNDRV_PCM_RATE_44100 | \
1703 SNDRV_PCM_RATE_48000)
1704
1705#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1706 SNDRV_PCM_FMTBIT_S20_3LE |\
1707 SNDRV_PCM_FMTBIT_S24_LE)
1708
6335d055 1709static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1710 .hw_params = wm8903_hw_params,
1711 .digital_mute = wm8903_digital_mute,
1712 .set_fmt = wm8903_set_dai_fmt,
1713 .set_sysclk = wm8903_set_dai_sysclk,
1714};
1715
f0fba2ad
LG		 1716static struct snd_soc_dai_driver wm8903_dai = {
1717 .name = "wm8903-hifi",
f1c0a02f
MB		 1718 .playback = {
1719 .stream_name = "Playback",
1720 .channels_min = 2,
1721 .channels_max = 2,
1722 .rates = WM8903_PLAYBACK_RATES,
1723 .formats = WM8903_FORMATS,
1724 },
1725 .capture = {
1726 .stream_name = "Capture",
1727 .channels_min = 2,
1728 .channels_max = 2,
1729 .rates = WM8903_CAPTURE_RATES,
1730 .formats = WM8903_FORMATS,
1731 },
6335d055 1732 .ops = &wm8903_dai_ops,
0d960e88 1733 .symmetric_rates = 1,
f1c0a02f 1734};
f1c0a02f 1735
f0fba2ad 1736static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1737{
f1c0a02f
MB		 1738 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1739
1740 return 0;
1741}
1742
f0fba2ad 1743static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1744{
f1c0a02f
MB		 1745 int i;
1746 u16 *reg_cache = codec->reg_cache;
40aa7030 1747 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1748 GFP_KERNEL);
1749
1750 /* Bring the codec back up to standby first to minimise pop/clicks */
1751 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1752
1753 /* Sync back everything else */
1754 if (tmp_cache) {
1755 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1756 if (tmp_cache[i] != reg_cache[i])
8d50e447 1757 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1758 kfree(tmp_cache);
f1c0a02f 1759 } else {
f0fba2ad 1760 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1761 }
1762
1763 return 0;
1764}
1765
7cfe5617
SW		 1766#ifdef CONFIG_GPIOLIB
1767static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1768{
1769 return container_of(chip, struct wm8903_priv, gpio_chip);
1770}
1771
1772static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1773{
1774 if (offset >= WM8903_NUM_GPIO)
1775 return -EINVAL;
1776
1777 return 0;
1778}
1779
1780static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1781{
1782 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1783 struct snd_soc_codec *codec = wm8903->codec;
1784 unsigned int mask, val;
1785
1786 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1787 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1788 WM8903_GP1_DIR;
1789
1790 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1791 mask, val);
1792}
1793
1794static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1795{
1796 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1797 struct snd_soc_codec *codec = wm8903->codec;
1798 int reg;
1799
1800 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1801
1802 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1803}
1804
1805static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1806 unsigned offset, int value)
1807{
1808 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1809 struct snd_soc_codec *codec = wm8903->codec;
1810 unsigned int mask, val;
1811
1812 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1813 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1814 (value << WM8903_GP2_LVL_SHIFT);
1815
1816 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1817 mask, val);
1818}
1819
1820static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1821{
1822 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1823 struct snd_soc_codec *codec = wm8903->codec;
1824
1825 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1826 WM8903_GP1_LVL_MASK,
1827 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1828}
1829
1830static struct gpio_chip wm8903_template_chip = {
1831 .label = "wm8903",
1832 .owner = THIS_MODULE,
1833 .request = wm8903_gpio_request,
1834 .direction_input = wm8903_gpio_direction_in,
1835 .get = wm8903_gpio_get,
1836 .direction_output = wm8903_gpio_direction_out,
1837 .set = wm8903_gpio_set,
1838 .can_sleep = 1,
1839};
1840
1841static void wm8903_init_gpio(struct snd_soc_codec *codec)
1842{
1843 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1844 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1845 int ret;
1846
1847 wm8903->gpio_chip = wm8903_template_chip;
1848 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1849 wm8903->gpio_chip.dev = codec->dev;
1850
1851 if (pdata && pdata->gpio_base)
1852 wm8903->gpio_chip.base = pdata->gpio_base;
1853 else
1854 wm8903->gpio_chip.base = -1;
1855
1856 ret = gpiochip_add(&wm8903->gpio_chip);
1857 if (ret != 0)
1858 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1859}
1860
1861static void wm8903_free_gpio(struct snd_soc_codec *codec)
1862{
1863 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1864 int ret;
1865
1866 ret = gpiochip_remove(&wm8903->gpio_chip);
1867 if (ret != 0)
1868 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1869}
1870#else
1871static void wm8903_init_gpio(struct snd_soc_codec *codec)
1872{
1873}
1874
1875static void wm8903_free_gpio(struct snd_soc_codec *codec)
1876{
1877}
1878#endif
1879
f0fba2ad 1880static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1881{
f0fba2ad
LG		 1882 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1883 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1884 int ret, i;
8abd16a6 1885 int trigger, irq_pol;
f1c0a02f
MB		 1886 u16 val;
1887
7cfe5617 1888 wm8903->codec = codec;
8abd16a6 1889 init_completion(&wm8903->wseq);
d58d5d55 1890
8d50e447
MB		 1891 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1892 if (ret != 0) {
f0fba2ad
LG		 1893 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1894 return ret;
8d50e447
MB		 1895 }
1896
1897 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1898 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1899 dev_err(codec->dev,
d58d5d55
MB		 1900 "Device with ID register %x is not a WM8903\n", val);
1901 return -ENODEV;
f1c0a02f
MB		 1902 }
1903
8d50e447 1904 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1905 dev_info(codec->dev, "WM8903 revision %c\n",
1906 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1907
1908 wm8903_reset(codec);
1909
37f88e84 1910 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1911 if (pdata) {
1912 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1913 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1914 continue;
1915
1916 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1917 pdata->gpio_cfg[i] & 0xffff);
1918 }
37f88e84
MB		 1919
1920 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1921 pdata->micdet_cfg);
1922
1923 /* Microphone detection needs the WSEQ clock */
1924 if (pdata->micdet_cfg)
1925 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1926 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1927
1928 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1929 }
8abd16a6 1930
f0fba2ad 1931 if (wm8903->irq) {
8abd16a6
MB		 1932 if (pdata && pdata->irq_active_low) {
1933 trigger = IRQF_TRIGGER_LOW;
1934 irq_pol = WM8903_IRQ_POL;
1935 } else {
1936 trigger = IRQF_TRIGGER_HIGH;
1937 irq_pol = 0;
1938 }
1939
1940 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1941 WM8903_IRQ_POL, irq_pol);
1942
f0fba2ad 1943 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1944 trigger | IRQF_ONESHOT,
f0fba2ad 1945 "wm8903", codec);
8abd16a6 1946 if (ret != 0) {
f0fba2ad 1947 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1948 ret);
f0fba2ad 1949 return ret;
8abd16a6
MB		 1950 }
1951
1952 /* Enable write sequencer interrupts */
1953 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1954 WM8903_IM_WSEQ_BUSY_EINT, 0);
1955 }
73b34ead 1956
f1c0a02f
MB		 1957 /* power on device */
1958 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1959
1960 /* Latch volume update bits */
8d50e447 1961 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1962 val |= WM8903_ADCVU;
8d50e447
MB		 1963 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1964 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1965
8d50e447 1966 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1967 val |= WM8903_DACVU;
8d50e447
MB		 1968 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1969 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1970
8d50e447 1971 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1972 val |= WM8903_HPOUTVU;
8d50e447
MB		 1973 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1974 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1975
8d50e447 1976 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1977 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1978 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1979 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1980
8d50e447 1981 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1982 val |= WM8903_SPKVU;
8d50e447
MB		 1983 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1984 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1985
1986 /* Enable DAC soft mute by default */
e12adab0
MB		 1987 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
1988 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
1989 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 1990
f0fba2ad
LG		 1991 snd_soc_add_controls(codec, wm8903_snd_controls,
1992 ARRAY_SIZE(wm8903_snd_controls));
1993 wm8903_add_widgets(codec);
f1c0a02f 1994
7cfe5617
SW		 1995 wm8903_init_gpio(codec);
1996
f1c0a02f
MB		 1997 return ret;
1998}
1999
f0fba2ad
LG		 2000/* power down chip */
2001static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2002{
7cfe5617 2003 wm8903_free_gpio(codec);
f0fba2ad
LG		 2004 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
2005 return 0;
2006}
f1c0a02f 2007
f0fba2ad
LG		 2008static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2009 .probe = wm8903_probe,
2010 .remove = wm8903_remove,
2011 .suspend = wm8903_suspend,
2012 .resume = wm8903_resume,
2013 .set_bias_level = wm8903_set_bias_level,
2014 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2015 .reg_word_size = sizeof(u16),
2016 .reg_cache_default = wm8903_reg_defaults,
2017 .volatile_register = wm8903_volatile_register,
c5b6a9fe 2018 .seq_notifier = wm8903_seq_notifier,
f0fba2ad 2019};
f1c0a02f 2020
f0fba2ad
LG		 2021#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2022static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2023 const struct i2c_device_id *id)
2024{
2025 struct wm8903_priv *wm8903;
2026 int ret;
f1c0a02f 2027
f0fba2ad
LG		 2028 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
2029 if (wm8903 == NULL)
2030 return -ENOMEM;
8abd16a6 2031
f0fba2ad 2032 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2033 wm8903->irq = i2c->irq;
d58d5d55 2034
f0fba2ad
LG		 2035 ret = snd_soc_register_codec(&i2c->dev,
2036 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2037 if (ret < 0)
2038 kfree(wm8903);
2039 return ret;
2040}
f1c0a02f 2041
f0fba2ad
LG		 2042static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2043{
2044 snd_soc_unregister_codec(&client->dev);
2045 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 2046 return 0;
2047}
2048
f1c0a02f 2049static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2050 { "wm8903", 0 },
2051 { }
f1c0a02f
MB		 2052};
2053MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2054
2055static struct i2c_driver wm8903_i2c_driver = {
2056 .driver = {
4b592c91 2057 .name = "wm8903",
f1c0a02f
MB		 2058 .owner = THIS_MODULE,
2059 },
f0fba2ad
LG		 2060 .probe = wm8903_i2c_probe,
2061 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2062 .id_table = wm8903_i2c_id,
2063};
f0fba2ad 2064#endif
f1c0a02f 2065
f0fba2ad 2066static int __init wm8903_modinit(void)
f1c0a02f 2067{
f1c0a02f 2068 int ret = 0;
f0fba2ad
LG		 2069#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2070 ret = i2c_add_driver(&wm8903_i2c_driver);
2071 if (ret != 0) {
2072 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2073 ret);
f1c0a02f 2074 }
f0fba2ad 2075#endif
f1c0a02f 2076 return ret;
64089b84
MB		 2077}
2078module_init(wm8903_modinit);
2079
2080static void __exit wm8903_exit(void)
2081{
f0fba2ad 2082#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 2083 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 2084#endif
64089b84
MB		 2085}
2086module_exit(wm8903_exit);
2087
f1c0a02f
MB		 2088MODULE_DESCRIPTION("ASoC WM8903 driver");
2089MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2090MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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