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ASoC: Convert WM8903 to direct regmap API usage
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
ee244ce4 26#include <linux/regmap.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f 40/* Register defaults at reset */
ee244ce4
MB		 41static const struct reg_default wm8903_reg_defaults[] = {
42 { 4, 0x0018 }, /* R4 - Bias Control 0 */
43 { 5, 0x0000 }, /* R5 - VMID Control 0 */
44 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
45 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
46 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
47 { 12, 0x0000 }, /* R12 - Power Management 0 */
48 { 13, 0x0000 }, /* R13 - Power Management 1 */
49 { 14, 0x0000 }, /* R14 - Power Management 2 */
50 { 15, 0x0000 }, /* R15 - Power Management 3 */
51 { 16, 0x0000 }, /* R16 - Power Management 4 */
52 { 17, 0x0000 }, /* R17 - Power Management 5 */
53 { 18, 0x0000 }, /* R18 - Power Management 6 */
54 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
55 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
56 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
57 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
58 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
59 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
60 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
61 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
62 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
63 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
64 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
65 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
66 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
67 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
68 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
69 { 40, 0x09BF }, /* R40 - DRC 0 */
70 { 41, 0x3241 }, /* R41 - DRC 1 */
71 { 42, 0x0020 }, /* R42 - DRC 2 */
72 { 43, 0x0000 }, /* R43 - DRC 3 */
73 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
74 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
75 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
76 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
77 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
78 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
79 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
80 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
81 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
82 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
83 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
84 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
85 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
86 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
87 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
88 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
89 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
90 { 67, 0x0010 }, /* R67 - DC Servo 0 */
91 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
92 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
93 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
94 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
95 { 104, 0x0000 }, /* R104 - Class W 0 */
96 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
97 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
98 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
99 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
100 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
101 { 114, 0x0000 }, /* R114 - Control Interface */
102 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
103 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
104 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
105 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
106 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
107 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
108 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
109 { 126, 0x0000 }, /* R126 - Interrupt Control */
110 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
111 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
112 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
113 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
f1c0a02f
MB		 114};
115
d58d5d55 116struct wm8903_priv {
7cfe5617 117 struct snd_soc_codec *codec;
ee244ce4 118 struct regmap *regmap;
f0fba2ad 119
d58d5d55 120 int sysclk;
f0fba2ad 121 int irq;
d58d5d55 122
69fff9bb
MB		 123 int fs;
124 int deemph;
125
c5b6a9fe
MB		 126 int dcs_pending;
127 int dcs_cache[4];
128
f2c1fe09 129 /* Reference count */
d58d5d55 130 int class_w_users;
d58d5d55 131
7245387e
MB		 132 struct snd_soc_jack *mic_jack;
133 int mic_det;
134 int mic_short;
135 int mic_last_report;
136 int mic_delay;
7cfe5617
SW		 137
138#ifdef CONFIG_GPIOLIB
139 struct gpio_chip gpio_chip;
140#endif
d58d5d55
MB		 141};
142
ee244ce4
MB		 143static bool wm8903_readable_register(struct device *dev, unsigned int reg)
144{
145 switch (reg) {
146 case WM8903_SW_RESET_AND_ID:
147 case WM8903_REVISION_NUMBER:
148 case WM8903_BIAS_CONTROL_0:
149 case WM8903_VMID_CONTROL_0:
150 case WM8903_MIC_BIAS_CONTROL_0:
151 case WM8903_ANALOGUE_DAC_0:
152 case WM8903_ANALOGUE_ADC_0:
153 case WM8903_POWER_MANAGEMENT_0:
154 case WM8903_POWER_MANAGEMENT_1:
155 case WM8903_POWER_MANAGEMENT_2:
156 case WM8903_POWER_MANAGEMENT_3:
157 case WM8903_POWER_MANAGEMENT_4:
158 case WM8903_POWER_MANAGEMENT_5:
159 case WM8903_POWER_MANAGEMENT_6:
160 case WM8903_CLOCK_RATES_0:
161 case WM8903_CLOCK_RATES_1:
162 case WM8903_CLOCK_RATES_2:
163 case WM8903_AUDIO_INTERFACE_0:
164 case WM8903_AUDIO_INTERFACE_1:
165 case WM8903_AUDIO_INTERFACE_2:
166 case WM8903_AUDIO_INTERFACE_3:
167 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
168 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
169 case WM8903_DAC_DIGITAL_0:
170 case WM8903_DAC_DIGITAL_1:
171 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
172 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
173 case WM8903_ADC_DIGITAL_0:
174 case WM8903_DIGITAL_MICROPHONE_0:
175 case WM8903_DRC_0:
176 case WM8903_DRC_1:
177 case WM8903_DRC_2:
178 case WM8903_DRC_3:
179 case WM8903_ANALOGUE_LEFT_INPUT_0:
180 case WM8903_ANALOGUE_RIGHT_INPUT_0:
181 case WM8903_ANALOGUE_LEFT_INPUT_1:
182 case WM8903_ANALOGUE_RIGHT_INPUT_1:
183 case WM8903_ANALOGUE_LEFT_MIX_0:
184 case WM8903_ANALOGUE_RIGHT_MIX_0:
185 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
186 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
187 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
188 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
189 case WM8903_ANALOGUE_OUT1_LEFT:
190 case WM8903_ANALOGUE_OUT1_RIGHT:
191 case WM8903_ANALOGUE_OUT2_LEFT:
192 case WM8903_ANALOGUE_OUT2_RIGHT:
193 case WM8903_ANALOGUE_OUT3_LEFT:
194 case WM8903_ANALOGUE_OUT3_RIGHT:
195 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
196 case WM8903_DC_SERVO_0:
197 case WM8903_DC_SERVO_2:
198 case WM8903_DC_SERVO_READBACK_1:
199 case WM8903_DC_SERVO_READBACK_2:
200 case WM8903_DC_SERVO_READBACK_3:
201 case WM8903_DC_SERVO_READBACK_4:
202 case WM8903_ANALOGUE_HP_0:
203 case WM8903_ANALOGUE_LINEOUT_0:
204 case WM8903_CHARGE_PUMP_0:
205 case WM8903_CLASS_W_0:
206 case WM8903_WRITE_SEQUENCER_0:
207 case WM8903_WRITE_SEQUENCER_1:
208 case WM8903_WRITE_SEQUENCER_2:
209 case WM8903_WRITE_SEQUENCER_3:
210 case WM8903_WRITE_SEQUENCER_4:
211 case WM8903_CONTROL_INTERFACE:
212 case WM8903_GPIO_CONTROL_1:
213 case WM8903_GPIO_CONTROL_2:
214 case WM8903_GPIO_CONTROL_3:
215 case WM8903_GPIO_CONTROL_4:
216 case WM8903_GPIO_CONTROL_5:
217 case WM8903_INTERRUPT_STATUS_1:
218 case WM8903_INTERRUPT_STATUS_1_MASK:
219 case WM8903_INTERRUPT_POLARITY_1:
220 case WM8903_INTERRUPT_CONTROL:
221 case WM8903_CLOCK_RATE_TEST_4:
222 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
223 return true;
224 default:
225 return false;
226 }
227}
228
229static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
f1c0a02f
MB		 230{
231 switch (reg) {
232 case WM8903_SW_RESET_AND_ID:
233 case WM8903_REVISION_NUMBER:
234 case WM8903_INTERRUPT_STATUS_1:
235 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 236 case WM8903_DC_SERVO_READBACK_1:
237 case WM8903_DC_SERVO_READBACK_2:
238 case WM8903_DC_SERVO_READBACK_3:
239 case WM8903_DC_SERVO_READBACK_4:
8d50e447 240 return 1;
f1c0a02f
MB		 241
242 default:
f1c0a02f 243 return 0;
8d50e447 244 }
f1c0a02f
MB		 245}
246
f1c0a02f
MB		 247static void wm8903_reset(struct snd_soc_codec *codec)
248{
8d50e447 249 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
f1c0a02f
MB		 250}
251
42768a12
MB		 252static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
253 struct snd_kcontrol *kcontrol, int event)
254{
255 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
256 mdelay(4);
257
258 return 0;
259}
260
c5b6a9fe
MB		 261static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
262 struct snd_kcontrol *kcontrol, int event)
263{
264 struct snd_soc_codec *codec = w->codec;
265 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
266
267 switch (event) {
268 case SND_SOC_DAPM_POST_PMU:
269 wm8903->dcs_pending |= 1 << w->shift;
270 break;
271 case SND_SOC_DAPM_PRE_PMD:
272 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
273 1 << w->shift, 0);
274 break;
275 }
276
277 return 0;
278}
279
280#define WM8903_DCS_MODE_WRITE_STOP 0
281#define WM8903_DCS_MODE_START_STOP 2
282
283static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
284 enum snd_soc_dapm_type event, int subseq)
285{
286 struct snd_soc_codec *codec = container_of(dapm,
287 struct snd_soc_codec, dapm);
288 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
289 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
290 int i, val;
291
292 /* Complete any pending DC servo starts */
293 if (wm8903->dcs_pending) {
294 dev_dbg(codec->dev, "Starting DC servo for %x\n",
295 wm8903->dcs_pending);
296
297 /* If we've no cached values then we need to do startup */
298 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
299 if (!(wm8903->dcs_pending & (1 << i)))
300 continue;
301
302 if (wm8903->dcs_cache[i]) {
303 dev_dbg(codec->dev,
304 "Restore DC servo %d value %x\n",
305 3 - i, wm8903->dcs_cache[i]);
306
307 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
308 wm8903->dcs_cache[i] & 0xff);
309 } else {
310 dev_dbg(codec->dev,
311 "Calibrate DC servo %d\n", 3 - i);
312 dcs_mode = WM8903_DCS_MODE_START_STOP;
313 }
314 }
315
316 /* Don't trust the cache for analogue */
317 if (wm8903->class_w_users)
318 dcs_mode = WM8903_DCS_MODE_START_STOP;
319
320 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
321 WM8903_DCS_MODE_MASK, dcs_mode);
322
323 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
324 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
325
326 switch (dcs_mode) {
327 case WM8903_DCS_MODE_WRITE_STOP:
328 break;
329
330 case WM8903_DCS_MODE_START_STOP:
331 msleep(270);
332
333 /* Cache the measured offsets for digital */
334 if (wm8903->class_w_users)
335 break;
336
337 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
338 if (!(wm8903->dcs_pending & (1 << i)))
339 continue;
340
341 val = snd_soc_read(codec,
342 WM8903_DC_SERVO_READBACK_1 + i);
343 dev_dbg(codec->dev, "DC servo %d: %x\n",
344 3 - i, val);
345 wm8903->dcs_cache[i] = val;
346 }
347 break;
348
349 default:
350 pr_warn("DCS mode %d delay not set\n", dcs_mode);
351 break;
352 }
353
354 wm8903->dcs_pending = 0;
355 }
356}
357
f1c0a02f
MB		 358/*
359 * When used with DAC outputs only the WM8903 charge pump supports
360 * operation in class W mode, providing very low power consumption
361 * when used with digital sources. Enable and disable this mode
362 * automatically depending on the mixer configuration.
363 *
364 * All the relevant controls are simple switches.
365 */
366static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
367 struct snd_ctl_elem_value *ucontrol)
368{
9d03545d
JN		 369 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
370 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 371 struct snd_soc_codec *codec = widget->codec;
b2c812e2 372 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 373 u16 reg;
374 int ret;
375
8d50e447 376 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 377
378 /* Turn it off if we're about to enable bypass */
379 if (ucontrol->value.integer.value[0]) {
380 if (wm8903->class_w_users == 0) {
f0fba2ad 381 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 382 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 383 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
384 }
385 wm8903->class_w_users++;
386 }
387
388 /* Implement the change */
389 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
390
391 /* If we've just disabled the last bypass path turn Class W on */
392 if (!ucontrol->value.integer.value[0]) {
393 if (wm8903->class_w_users == 1) {
f0fba2ad 394 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 395 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 396 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
397 }
398 wm8903->class_w_users--;
399 }
400
f0fba2ad 401 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 402 wm8903->class_w_users);
403
404 return ret;
405}
406
407#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
408{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
409 .info = snd_soc_info_volsw, \
410 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
411 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
412
413
69fff9bb
MB		 414static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
415
416static int wm8903_set_deemph(struct snd_soc_codec *codec)
417{
418 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
419 int val, i, best;
420
421 /* If we're using deemphasis select the nearest available sample
422 * rate.
423 */
424 if (wm8903->deemph) {
425 best = 1;
426 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
427 if (abs(wm8903_deemph[i] - wm8903->fs) <
428 abs(wm8903_deemph[best] - wm8903->fs))
429 best = i;
430 }
431
432 val = best << WM8903_DEEMPH_SHIFT;
433 } else {
434 best = 0;
435 val = 0;
436 }
437
438 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
439 best, wm8903_deemph[best]);
440
441 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
442 WM8903_DEEMPH_MASK, val);
443}
444
445static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
446 struct snd_ctl_elem_value *ucontrol)
447{
448 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
449 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
450
451 ucontrol->value.enumerated.item[0] = wm8903->deemph;
452
453 return 0;
454}
455
456static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
457 struct snd_ctl_elem_value *ucontrol)
458{
459 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
460 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
461 int deemph = ucontrol->value.enumerated.item[0];
462 int ret = 0;
463
464 if (deemph > 1)
465 return -EINVAL;
466
467 mutex_lock(&codec->mutex);
468 if (wm8903->deemph != deemph) {
469 wm8903->deemph = deemph;
470
471 wm8903_set_deemph(codec);
472
473 ret = 1;
474 }
475 mutex_unlock(&codec->mutex);
476
477 return ret;
478}
479
f1c0a02f
MB		 480/* ALSA can only do steps of .01dB */
481static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
482
291ce18c 483static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 484static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
485
486static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
487static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
488static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
489static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
490static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
491
460f4aae
MB		 492static const char *hpf_mode_text[] = {
493 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
494};
495
496static const struct soc_enum hpf_mode =
497 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
498
dcf9ada3
MB		 499static const char *osr_text[] = {
500 "Low power", "High performance"
501};
502
503static const struct soc_enum adc_osr =
504 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
505
506static const struct soc_enum dac_osr =
507 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
508
f1c0a02f
MB		 509static const char *drc_slope_text[] = {
510 "1", "1/2", "1/4", "1/8", "1/16", "0"
511};
512
513static const struct soc_enum drc_slope_r0 =
514 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
515
516static const struct soc_enum drc_slope_r1 =
517 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
518
519static const char *drc_attack_text[] = {
520 "instantaneous",
521 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
522 "46.4ms", "92.8ms", "185.6ms"
523};
524
525static const struct soc_enum drc_attack =
526 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
527
528static const char *drc_decay_text[] = {
529 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
530 "23.87s", "47.56s"
531};
532
533static const struct soc_enum drc_decay =
534 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
535
536static const char *drc_ff_delay_text[] = {
537 "5 samples", "9 samples"
538};
539
540static const struct soc_enum drc_ff_delay =
541 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
542
543static const char *drc_qr_decay_text[] = {
544 "0.725ms", "1.45ms", "5.8ms"
545};
546
547static const struct soc_enum drc_qr_decay =
548 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
549
550static const char *drc_smoothing_text[] = {
551 "Low", "Medium", "High"
552};
553
554static const struct soc_enum drc_smoothing =
555 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
556
557static const char *soft_mute_text[] = {
558 "Fast (fs/2)", "Slow (fs/32)"
559};
560
561static const struct soc_enum soft_mute =
562 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
563
564static const char *mute_mode_text[] = {
565 "Hard", "Soft"
566};
567
568static const struct soc_enum mute_mode =
569 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
570
f1c0a02f
MB		 571static const char *companding_text[] = {
572 "ulaw", "alaw"
573};
574
575static const struct soc_enum dac_companding =
576 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
577
578static const struct soc_enum adc_companding =
579 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
580
581static const char *input_mode_text[] = {
582 "Single-Ended", "Differential Line", "Differential Mic"
583};
584
585static const struct soc_enum linput_mode_enum =
586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
587
588static const struct soc_enum rinput_mode_enum =
589 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
590
591static const char *linput_mux_text[] = {
592 "IN1L", "IN2L", "IN3L"
593};
594
595static const struct soc_enum linput_enum =
596 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
597
598static const struct soc_enum linput_inv_enum =
599 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
600
601static const char *rinput_mux_text[] = {
602 "IN1R", "IN2R", "IN3R"
603};
604
605static const struct soc_enum rinput_enum =
606 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
607
608static const struct soc_enum rinput_inv_enum =
609 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
610
611
291ce18c
MB		 612static const char *sidetone_text[] = {
613 "None", "Left", "Right"
614};
615
616static const struct soc_enum lsidetone_enum =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
618
619static const struct soc_enum rsidetone_enum =
620 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
621
97945c46
SW		 622static const char *adcinput_text[] = {
623 "ADC", "DMIC"
624};
625
626static const struct soc_enum adcinput_enum =
627 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
628
1e113bf9
MB		 629static const char *aif_text[] = {
630 "Left", "Right"
631};
632
633static const struct soc_enum lcapture_enum =
634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
635
636static const struct soc_enum rcapture_enum =
637 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
638
639static const struct soc_enum lplay_enum =
640 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
641
642static const struct soc_enum rplay_enum =
643 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
644
f1c0a02f
MB		 645static const struct snd_kcontrol_new wm8903_snd_controls[] = {
646
647/* Input PGAs - No TLV since the scale depends on PGA mode */
648SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 649 7, 1, 1),
f1c0a02f
MB		 650SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
651 0, 31, 0),
652SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
653 6, 1, 0),
654
655SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 656 7, 1, 1),
f1c0a02f
MB		 657SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
658 0, 31, 0),
659SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
660 6, 1, 0),
661
662/* ADCs */
dcf9ada3 663SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 664SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
665SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 666SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
667SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
668SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 669SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 670 drc_tlv_thresh),
671SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
672SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
673SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
674SOC_ENUM("DRC Attack Rate", drc_attack),
675SOC_ENUM("DRC Decay Rate", drc_decay),
676SOC_ENUM("DRC FF Delay", drc_ff_delay),
677SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
678SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 679SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 680SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
681SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
682SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 683SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 684SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
685
686SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 687 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 688SOC_ENUM("ADC Companding Mode", adc_companding),
689SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
690
291ce18c
MB		 691SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
692 12, 0, digital_sidetone_tlv),
693
f1c0a02f 694/* DAC */
dcf9ada3 695SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 696SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
697 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
698SOC_ENUM("DAC Soft Mute Rate", soft_mute),
699SOC_ENUM("DAC Mute Mode", mute_mode),
700SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 701SOC_ENUM("DAC Companding Mode", dac_companding),
702SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 703SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
704 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 705
706/* Headphones */
707SOC_DOUBLE_R("Headphone Switch",
708 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
709 8, 1, 1),
710SOC_DOUBLE_R("Headphone ZC Switch",
711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
712 6, 1, 0),
713SOC_DOUBLE_R_TLV("Headphone Volume",
714 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
715 0, 63, 0, out_tlv),
716
717/* Line out */
718SOC_DOUBLE_R("Line Out Switch",
719 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
720 8, 1, 1),
721SOC_DOUBLE_R("Line Out ZC Switch",
722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
723 6, 1, 0),
724SOC_DOUBLE_R_TLV("Line Out Volume",
725 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
726 0, 63, 0, out_tlv),
727
728/* Speaker */
729SOC_DOUBLE_R("Speaker Switch",
730 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
731SOC_DOUBLE_R("Speaker ZC Switch",
732 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
733SOC_DOUBLE_R_TLV("Speaker Volume",
734 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
735 0, 63, 0, out_tlv),
736};
737
f1c0a02f
MB		 738static const struct snd_kcontrol_new linput_mode_mux =
739 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
740
741static const struct snd_kcontrol_new rinput_mode_mux =
742 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
743
744static const struct snd_kcontrol_new linput_mux =
745 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
746
747static const struct snd_kcontrol_new linput_inv_mux =
748 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
749
750static const struct snd_kcontrol_new rinput_mux =
751 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
752
753static const struct snd_kcontrol_new rinput_inv_mux =
754 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
755
291ce18c
MB		 756static const struct snd_kcontrol_new lsidetone_mux =
757 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
758
759static const struct snd_kcontrol_new rsidetone_mux =
760 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
761
97945c46
SW		 762static const struct snd_kcontrol_new adcinput_mux =
763 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
764
1e113bf9
MB		 765static const struct snd_kcontrol_new lcapture_mux =
766 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
767
768static const struct snd_kcontrol_new rcapture_mux =
769 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
770
771static const struct snd_kcontrol_new lplay_mux =
772 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
773
774static const struct snd_kcontrol_new rplay_mux =
775 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
776
f1c0a02f
MB		 777static const struct snd_kcontrol_new left_output_mixer[] = {
778SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
779SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
780SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 781SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 782};
783
784static const struct snd_kcontrol_new right_output_mixer[] = {
785SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
786SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
787SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 788SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 789};
790
791static const struct snd_kcontrol_new left_speaker_mixer[] = {
792SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
793SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
794SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
795SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 796 0, 1, 0),
f1c0a02f
MB		 797};
798
799static const struct snd_kcontrol_new right_speaker_mixer[] = {
800SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
801SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
802SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
803 1, 1, 0),
804SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 805 0, 1, 0),
f1c0a02f
MB		 806};
807
808static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
809SND_SOC_DAPM_INPUT("IN1L"),
810SND_SOC_DAPM_INPUT("IN1R"),
811SND_SOC_DAPM_INPUT("IN2L"),
812SND_SOC_DAPM_INPUT("IN2R"),
813SND_SOC_DAPM_INPUT("IN3L"),
814SND_SOC_DAPM_INPUT("IN3R"),
97945c46 815SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 816
817SND_SOC_DAPM_OUTPUT("HPOUTL"),
818SND_SOC_DAPM_OUTPUT("HPOUTR"),
819SND_SOC_DAPM_OUTPUT("LINEOUTL"),
820SND_SOC_DAPM_OUTPUT("LINEOUTR"),
821SND_SOC_DAPM_OUTPUT("LOP"),
822SND_SOC_DAPM_OUTPUT("LON"),
823SND_SOC_DAPM_OUTPUT("ROP"),
824SND_SOC_DAPM_OUTPUT("RON"),
825
5032dc34 826SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 827
828SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
829SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
830 &linput_inv_mux),
831SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
832
833SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
834SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
835 &rinput_inv_mux),
836SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
837
838SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
839SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
840
97945c46
SW		 841SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
842SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
843
1e113bf9
MB		 844SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
845SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
846
847SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
848SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
849
850SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
851SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 852
291ce18c
MB		 853SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
854SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
855
1e113bf9
MB		 856SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
857SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
858
859SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
860SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
861
862SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
863SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 864
865SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
866 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
867SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
868 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
869
870SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
871 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
872SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
873 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
874
1b877cb5
DL		 875SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
876 1, 0, NULL, 0),
877SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 878 0, 0, NULL, 0),
879
1b877cb5 880SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 881 NULL, 0),
1b877cb5 882SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 883 NULL, 0),
884
885SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
886SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 887SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
888SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 889SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
890SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 891SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
892SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 893
894SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
895 NULL, 0),
896SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
897 NULL, 0),
1b877cb5
DL		 898SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
899 NULL, 0),
900SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 901 NULL, 0),
902SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
903 NULL, 0),
904SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
905 NULL, 0),
1b877cb5
DL		 906SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
907 NULL, 0),
908SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 909 NULL, 0),
910
c5b6a9fe
MB		 911SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
912SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
913 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
914SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
915 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
916SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
917 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
918SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
919 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 920
921SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
922 NULL, 0),
923SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
924 NULL, 0),
925
42768a12
MB		 926SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
927 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 928SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 929SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 930};
931
ecd01512 932static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 933
2c8be5a2 934 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 935 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 936 { "HPL_DCS", NULL, "CLK_SYS" },
937 { "HPR_DCS", NULL, "CLK_SYS" },
938 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
939 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
940
f1c0a02f
MB		 941 { "Left Input Mux", "IN1L", "IN1L" },
942 { "Left Input Mux", "IN2L", "IN2L" },
943 { "Left Input Mux", "IN3L", "IN3L" },
944
945 { "Left Input Inverting Mux", "IN1L", "IN1L" },
946 { "Left Input Inverting Mux", "IN2L", "IN2L" },
947 { "Left Input Inverting Mux", "IN3L", "IN3L" },
948
949 { "Right Input Mux", "IN1R", "IN1R" },
950 { "Right Input Mux", "IN2R", "IN2R" },
951 { "Right Input Mux", "IN3R", "IN3R" },
952
953 { "Right Input Inverting Mux", "IN1R", "IN1R" },
954 { "Right Input Inverting Mux", "IN2R", "IN2R" },
955 { "Right Input Inverting Mux", "IN3R", "IN3R" },
956
957 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
958 { "Left Input Mode Mux", "Differential Line",
959 "Left Input Mux" },
960 { "Left Input Mode Mux", "Differential Line",
961 "Left Input Inverting Mux" },
962 { "Left Input Mode Mux", "Differential Mic",
963 "Left Input Mux" },
964 { "Left Input Mode Mux", "Differential Mic",
965 "Left Input Inverting Mux" },
966
967 { "Right Input Mode Mux", "Single-Ended",
968 "Right Input Inverting Mux" },
969 { "Right Input Mode Mux", "Differential Line",
970 "Right Input Mux" },
971 { "Right Input Mode Mux", "Differential Line",
972 "Right Input Inverting Mux" },
973 { "Right Input Mode Mux", "Differential Mic",
974 "Right Input Mux" },
975 { "Right Input Mode Mux", "Differential Mic",
976 "Right Input Inverting Mux" },
977
978 { "Left Input PGA", NULL, "Left Input Mode Mux" },
979 { "Right Input PGA", NULL, "Right Input Mode Mux" },
980
97945c46
SW		 981 { "Left ADC Input", "ADC", "Left Input PGA" },
982 { "Left ADC Input", "DMIC", "DMICDAT" },
983 { "Right ADC Input", "ADC", "Right Input PGA" },
984 { "Right ADC Input", "DMIC", "DMICDAT" },
985
1e113bf9
MB		 986 { "Left Capture Mux", "Left", "ADCL" },
987 { "Left Capture Mux", "Right", "ADCR" },
988
989 { "Right Capture Mux", "Left", "ADCL" },
990 { "Right Capture Mux", "Right", "ADCR" },
991
992 { "AIFTXL", NULL, "Left Capture Mux" },
993 { "AIFTXR", NULL, "Right Capture Mux" },
994
97945c46 995 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 996 { "ADCL", NULL, "CLK_DSP" },
97945c46 997 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 998 { "ADCR", NULL, "CLK_DSP" },
999
1e113bf9
MB		 1000 { "Left Playback Mux", "Left", "AIFRXL" },
1001 { "Left Playback Mux", "Right", "AIFRXR" },
1002
1003 { "Right Playback Mux", "Left", "AIFRXL" },
1004 { "Right Playback Mux", "Right", "AIFRXR" },
1005
291ce18c
MB		 1006 { "DACL Sidetone", "Left", "ADCL" },
1007 { "DACL Sidetone", "Right", "ADCR" },
1008 { "DACR Sidetone", "Left", "ADCL" },
1009 { "DACR Sidetone", "Right", "ADCR" },
1010
1e113bf9 1011 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1012 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1013 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1014
1015 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1016 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1017 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1018
1019 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1020 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1021 { "Left Output Mixer", "DACL Switch", "DACL" },
1022 { "Left Output Mixer", "DACR Switch", "DACR" },
1023
1024 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1025 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1026 { "Right Output Mixer", "DACL Switch", "DACL" },
1027 { "Right Output Mixer", "DACR Switch", "DACR" },
1028
1029 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1030 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1031 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1032 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1033
1034 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1035 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1036 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1037 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1038
1039 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1040 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1041
1042 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1043 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1044
1045 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1046 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1047
1b877cb5
DL		 1048 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1049 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1050 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1051 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1052 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1053 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1054 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1055 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1056
c5b6a9fe
MB		 1057 { "HPL_DCS", NULL, "DCS Master" },
1058 { "HPR_DCS", NULL, "DCS Master" },
1059 { "LINEOUTL_DCS", NULL, "DCS Master" },
1060 { "LINEOUTR_DCS", NULL, "DCS Master" },
1061
13a9983e
MB		 1062 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1063 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1064 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1065 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1066
1067 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1068 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1069 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1070 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1071
1072 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1073 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1074 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1075 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1076
1077 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1078 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1079 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1080 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1081
1082 { "LOP", NULL, "Left Speaker PGA" },
1083 { "LON", NULL, "Left Speaker PGA" },
1084
1085 { "ROP", NULL, "Right Speaker PGA" },
1086 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1087
1088 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1089 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1090 { "Left Line Output PGA", NULL, "Charge Pump" },
1091 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1092};
1093
f1c0a02f
MB		 1094static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1095 enum snd_soc_bias_level level)
1096{
f1c0a02f
MB		 1097 switch (level) {
1098 case SND_SOC_BIAS_ON:
66daaa59 1099 break;
22f226dd 1100
f1c0a02f 1101 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1102 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1103 WM8903_VMID_RES_MASK,
1104 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1105 break;
1106
1107 case SND_SOC_BIAS_STANDBY:
ce6120cc 1108 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1109 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1110 WM8903_POBCTRL | WM8903_ISEL_MASK |
1111 WM8903_STARTUP_BIAS_ENA |
1112 WM8903_BIAS_ENA,
1113 WM8903_POBCTRL |
1114 (2 << WM8903_ISEL_SHIFT) |
1115 WM8903_STARTUP_BIAS_ENA);
1116
1117 snd_soc_update_bits(codec,
1118 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1119 WM8903_SPK_DISCHARGE,
1120 WM8903_SPK_DISCHARGE);
1121
1122 msleep(33);
1123
1124 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1125 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1126 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1127
1128 snd_soc_update_bits(codec,
1129 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1130 WM8903_SPK_DISCHARGE, 0);
1131
1132 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1133 WM8903_VMID_TIE_ENA |
1134 WM8903_BUFIO_ENA |
1135 WM8903_VMID_IO_ENA |
1136 WM8903_VMID_SOFT_MASK |
1137 WM8903_VMID_RES_MASK |
1138 WM8903_VMID_BUF_ENA,
1139 WM8903_VMID_TIE_ENA |
1140 WM8903_BUFIO_ENA |
1141 WM8903_VMID_IO_ENA |
1142 (2 << WM8903_VMID_SOFT_SHIFT) |
1143 WM8903_VMID_RES_250K |
1144 WM8903_VMID_BUF_ENA);
1145
1146 msleep(129);
1147
1148 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1149 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1150 0);
1151
1152 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1153 WM8903_VMID_SOFT_MASK, 0);
1154
1155 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1156 WM8903_VMID_RES_MASK,
1157 WM8903_VMID_RES_50K);
1158
1159 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1160 WM8903_BIAS_ENA | WM8903_POBCTRL,
1161 WM8903_BIAS_ENA);
f1c0a02f 1162
f1c0a02f
MB		 1163 /* By default no bypass paths are enabled so
1164 * enable Class W support.
1165 */
f0fba2ad 1166 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1167 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1168 WM8903_CP_DYN_FREQ |
1169 WM8903_CP_DYN_V,
1170 WM8903_CP_DYN_FREQ |
1171 WM8903_CP_DYN_V);
f1c0a02f
MB		 1172 }
1173
66daaa59
MB		 1174 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1175 WM8903_VMID_RES_MASK,
1176 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1177 break;
1178
1179 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1180 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1181 WM8903_BIAS_ENA, 0);
1182
1183 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1184 WM8903_VMID_SOFT_MASK,
1185 2 << WM8903_VMID_SOFT_SHIFT);
1186
1187 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1188 WM8903_VMID_BUF_ENA, 0);
1189
1190 msleep(290);
1191
1192 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1193 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1194 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1195 WM8903_VMID_SOFT_MASK |
1196 WM8903_VMID_BUF_ENA, 0);
1197
1198 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1199 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1200 break;
1201 }
1202
ce6120cc 1203 codec->dapm.bias_level = level;
f1c0a02f
MB		 1204
1205 return 0;
1206}
1207
1208static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1209 int clk_id, unsigned int freq, int dir)
1210{
1211 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1212 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1213
1214 wm8903->sysclk = freq;
1215
1216 return 0;
1217}
1218
1219static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1220 unsigned int fmt)
1221{
1222 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1223 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1224
1225 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1226 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1227
1228 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1229 case SND_SOC_DAIFMT_CBS_CFS:
1230 break;
1231 case SND_SOC_DAIFMT_CBS_CFM:
1232 aif1 |= WM8903_LRCLK_DIR;
1233 break;
1234 case SND_SOC_DAIFMT_CBM_CFM:
1235 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1236 break;
1237 case SND_SOC_DAIFMT_CBM_CFS:
1238 aif1 |= WM8903_BCLK_DIR;
1239 break;
1240 default:
1241 return -EINVAL;
1242 }
1243
1244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1245 case SND_SOC_DAIFMT_DSP_A:
1246 aif1 |= 0x3;
1247 break;
1248 case SND_SOC_DAIFMT_DSP_B:
1249 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1250 break;
1251 case SND_SOC_DAIFMT_I2S:
1252 aif1 |= 0x2;
1253 break;
1254 case SND_SOC_DAIFMT_RIGHT_J:
1255 aif1 |= 0x1;
1256 break;
1257 case SND_SOC_DAIFMT_LEFT_J:
1258 break;
1259 default:
1260 return -EINVAL;
1261 }
1262
1263 /* Clock inversion */
1264 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1265 case SND_SOC_DAIFMT_DSP_A:
1266 case SND_SOC_DAIFMT_DSP_B:
1267 /* frame inversion not valid for DSP modes */
1268 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1269 case SND_SOC_DAIFMT_NB_NF:
1270 break;
1271 case SND_SOC_DAIFMT_IB_NF:
1272 aif1 |= WM8903_AIF_BCLK_INV;
1273 break;
1274 default:
1275 return -EINVAL;
1276 }
1277 break;
1278 case SND_SOC_DAIFMT_I2S:
1279 case SND_SOC_DAIFMT_RIGHT_J:
1280 case SND_SOC_DAIFMT_LEFT_J:
1281 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1282 case SND_SOC_DAIFMT_NB_NF:
1283 break;
1284 case SND_SOC_DAIFMT_IB_IF:
1285 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1286 break;
1287 case SND_SOC_DAIFMT_IB_NF:
1288 aif1 |= WM8903_AIF_BCLK_INV;
1289 break;
1290 case SND_SOC_DAIFMT_NB_IF:
1291 aif1 |= WM8903_AIF_LRCLK_INV;
1292 break;
1293 default:
1294 return -EINVAL;
1295 }
1296 break;
1297 default:
1298 return -EINVAL;
1299 }
1300
8d50e447 1301 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1302
1303 return 0;
1304}
1305
1306static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1307{
1308 struct snd_soc_codec *codec = codec_dai->codec;
1309 u16 reg;
1310
8d50e447 1311 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1312
1313 if (mute)
1314 reg |= WM8903_DAC_MUTE;
1315 else
1316 reg &= ~WM8903_DAC_MUTE;
1317
8d50e447 1318 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1319
1320 return 0;
1321}
1322
1323/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1324 * for optimal performance so we list the lower rates first and match
1325 * on the last match we find. */
1326static struct {
1327 int div;
1328 int rate;
1329 int mode;
1330 int mclk_div;
1331} clk_sys_ratios[] = {
1332 { 64, 0x0, 0x0, 1 },
1333 { 68, 0x0, 0x1, 1 },
1334 { 125, 0x0, 0x2, 1 },
1335 { 128, 0x1, 0x0, 1 },
1336 { 136, 0x1, 0x1, 1 },
1337 { 192, 0x2, 0x0, 1 },
1338 { 204, 0x2, 0x1, 1 },
1339
1340 { 64, 0x0, 0x0, 2 },
1341 { 68, 0x0, 0x1, 2 },
1342 { 125, 0x0, 0x2, 2 },
1343 { 128, 0x1, 0x0, 2 },
1344 { 136, 0x1, 0x1, 2 },
1345 { 192, 0x2, 0x0, 2 },
1346 { 204, 0x2, 0x1, 2 },
1347
1348 { 250, 0x2, 0x2, 1 },
1349 { 256, 0x3, 0x0, 1 },
1350 { 272, 0x3, 0x1, 1 },
1351 { 384, 0x4, 0x0, 1 },
1352 { 408, 0x4, 0x1, 1 },
1353 { 375, 0x4, 0x2, 1 },
1354 { 512, 0x5, 0x0, 1 },
1355 { 544, 0x5, 0x1, 1 },
1356 { 500, 0x5, 0x2, 1 },
1357 { 768, 0x6, 0x0, 1 },
1358 { 816, 0x6, 0x1, 1 },
1359 { 750, 0x6, 0x2, 1 },
1360 { 1024, 0x7, 0x0, 1 },
1361 { 1088, 0x7, 0x1, 1 },
1362 { 1000, 0x7, 0x2, 1 },
1363 { 1408, 0x8, 0x0, 1 },
1364 { 1496, 0x8, 0x1, 1 },
1365 { 1536, 0x9, 0x0, 1 },
1366 { 1632, 0x9, 0x1, 1 },
1367 { 1500, 0x9, 0x2, 1 },
1368
1369 { 250, 0x2, 0x2, 2 },
1370 { 256, 0x3, 0x0, 2 },
1371 { 272, 0x3, 0x1, 2 },
1372 { 384, 0x4, 0x0, 2 },
1373 { 408, 0x4, 0x1, 2 },
1374 { 375, 0x4, 0x2, 2 },
1375 { 512, 0x5, 0x0, 2 },
1376 { 544, 0x5, 0x1, 2 },
1377 { 500, 0x5, 0x2, 2 },
1378 { 768, 0x6, 0x0, 2 },
1379 { 816, 0x6, 0x1, 2 },
1380 { 750, 0x6, 0x2, 2 },
1381 { 1024, 0x7, 0x0, 2 },
1382 { 1088, 0x7, 0x1, 2 },
1383 { 1000, 0x7, 0x2, 2 },
1384 { 1408, 0x8, 0x0, 2 },
1385 { 1496, 0x8, 0x1, 2 },
1386 { 1536, 0x9, 0x0, 2 },
1387 { 1632, 0x9, 0x1, 2 },
1388 { 1500, 0x9, 0x2, 2 },
1389};
1390
1391/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1392static struct {
1393 int ratio;
1394 int div;
1395} bclk_divs[] = {
1396 { 10, 0 },
f1c0a02f
MB		 1397 { 20, 2 },
1398 { 30, 3 },
1399 { 40, 4 },
1400 { 50, 5 },
f1c0a02f
MB		 1401 { 60, 7 },
1402 { 80, 8 },
1403 { 100, 9 },
f1c0a02f
MB		 1404 { 120, 11 },
1405 { 160, 12 },
1406 { 200, 13 },
1407 { 220, 14 },
1408 { 240, 15 },
f1c0a02f
MB		 1409 { 300, 17 },
1410 { 320, 18 },
1411 { 440, 19 },
1412 { 480, 20 },
1413};
1414
1415/* Sample rates for DSP */
1416static struct {
1417 int rate;
1418 int value;
1419} sample_rates[] = {
1420 { 8000, 0 },
1421 { 11025, 1 },
1422 { 12000, 2 },
1423 { 16000, 3 },
1424 { 22050, 4 },
1425 { 24000, 5 },
1426 { 32000, 6 },
1427 { 44100, 7 },
1428 { 48000, 8 },
1429 { 88200, 9 },
1430 { 96000, 10 },
1431 { 0, 0 },
1432};
1433
f1c0a02f 1434static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1435 struct snd_pcm_hw_params *params,
1436 struct snd_soc_dai *dai)
f1c0a02f
MB		 1437{
1438 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1439 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1440 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1441 int fs = params_rate(params);
1442 int bclk;
1443 int bclk_div;
1444 int i;
1445 int dsp_config;
1446 int clk_config;
1447 int best_val;
1448 int cur_val;
1449 int clk_sys;
1450
8d50e447
MB		 1451 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1452 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1453 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1454 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1455 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1456 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1457
9e79261f
MB		 1458 /* Enable sloping stopband filter for low sample rates */
1459 if (fs <= 24000)
1460 dac_digital1 |= WM8903_DAC_SB_FILT;
1461 else
1462 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1463
f1c0a02f
MB		 1464 /* Configure sample rate logic for DSP - choose nearest rate */
1465 dsp_config = 0;
1466 best_val = abs(sample_rates[dsp_config].rate - fs);
1467 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1468 cur_val = abs(sample_rates[i].rate - fs);
1469 if (cur_val <= best_val) {
1470 dsp_config = i;
1471 best_val = cur_val;
1472 }
1473 }
1474
f0fba2ad 1475 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1476 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1477 clock1 |= sample_rates[dsp_config].value;
1478
1479 aif1 &= ~WM8903_AIF_WL_MASK;
1480 bclk = 2 * fs;
1481 switch (params_format(params)) {
1482 case SNDRV_PCM_FORMAT_S16_LE:
1483 bclk *= 16;
1484 break;
1485 case SNDRV_PCM_FORMAT_S20_3LE:
1486 bclk *= 20;
1487 aif1 |= 0x4;
1488 break;
1489 case SNDRV_PCM_FORMAT_S24_LE:
1490 bclk *= 24;
1491 aif1 |= 0x8;
1492 break;
1493 case SNDRV_PCM_FORMAT_S32_LE:
1494 bclk *= 32;
1495 aif1 |= 0xc;
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
f0fba2ad 1501 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1502 wm8903->sysclk, fs);
1503
1504 /* We may not have an MCLK which allows us to generate exactly
1505 * the clock we want, particularly with USB derived inputs, so
1506 * approximate.
1507 */
1508 clk_config = 0;
1509 best_val = abs((wm8903->sysclk /
1510 (clk_sys_ratios[0].mclk_div *
1511 clk_sys_ratios[0].div)) - fs);
1512 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1513 cur_val = abs((wm8903->sysclk /
1514 (clk_sys_ratios[i].mclk_div *
1515 clk_sys_ratios[i].div)) - fs);
1516
1517 if (cur_val <= best_val) {
1518 clk_config = i;
1519 best_val = cur_val;
1520 }
1521 }
1522
1523 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1524 clock0 |= WM8903_MCLKDIV2;
1525 clk_sys = wm8903->sysclk / 2;
1526 } else {
1527 clock0 &= ~WM8903_MCLKDIV2;
1528 clk_sys = wm8903->sysclk;
1529 }
1530
1531 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1532 WM8903_CLK_SYS_MODE_MASK);
1533 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1534 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1535
f0fba2ad 1536 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1537 clk_sys_ratios[clk_config].rate,
1538 clk_sys_ratios[clk_config].mode,
1539 clk_sys_ratios[clk_config].div);
1540
f0fba2ad 1541 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1542
1543 /* We may not get quite the right frequency if using
1544 * approximate clocks so look for the closest match that is
1545 * higher than the target (we need to ensure that there enough
1546 * BCLKs to clock out the samples).
1547 */
1548 bclk_div = 0;
1549 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1550 i = 1;
1551 while (i < ARRAY_SIZE(bclk_divs)) {
1552 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1553 if (cur_val < 0) /* BCLK table is sorted */
1554 break;
1555 bclk_div = i;
1556 best_val = cur_val;
1557 i++;
1558 }
1559
1560 aif2 &= ~WM8903_BCLK_DIV_MASK;
1561 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1562
f0fba2ad 1563 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1564 bclk_divs[bclk_div].ratio / 10, bclk,
1565 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1566
1567 aif2 |= bclk_divs[bclk_div].div;
1568 aif3 |= bclk / fs;
1569
69fff9bb
MB		 1570 wm8903->fs = params_rate(params);
1571 wm8903_set_deemph(codec);
1572
8d50e447
MB		 1573 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1574 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1575 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1576 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1577 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1578 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1579
1580 return 0;
1581}
1582
7245387e
MB		 1583/**
1584 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1585 *
1586 * @codec: WM8903 codec
1587 * @jack: jack to report detection events on
1588 * @det: value to report for presence detection
1589 * @shrt: value to report for short detection
1590 *
1591 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1592 * being used to bring out signals to the processor then only platform
1593 * data configuration is needed for WM8903 and processor GPIOs should
1594 * be configured using snd_soc_jack_add_gpios() instead.
1595 *
1596 * The current threasholds for detection should be configured using
1597 * micdet_cfg in the platform data. Using this function will force on
1598 * the microphone bias for the device.
1599 */
1600int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1601 int det, int shrt)
1602{
b2c812e2 1603 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1604 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1605
1606 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1607 det, shrt);
1608
1609 /* Store the configuration */
1610 wm8903->mic_jack = jack;
1611 wm8903->mic_det = det;
1612 wm8903->mic_short = shrt;
1613
1614 /* Enable interrupts we've got a report configured for */
1615 if (det)
1616 irq_mask &= ~WM8903_MICDET_EINT;
1617 if (shrt)
1618 irq_mask &= ~WM8903_MICSHRT_EINT;
1619
1620 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1621 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1622 irq_mask);
1623
3088e3b4 1624 if (det || shrt) {
69266866
MB		 1625 /* Enable mic detection, this may not have been set through
1626 * platform data (eg, if the defaults are OK). */
1627 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1628 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1629 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1630 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1631 } else {
1632 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1633 WM8903_MICDET_ENA, 0);
1634 }
7245387e
MB		 1635
1636 return 0;
1637}
1638EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1639
8abd16a6
MB		 1640static irqreturn_t wm8903_irq(int irq, void *data)
1641{
f0fba2ad
LG		 1642 struct snd_soc_codec *codec = data;
1643 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1644 int mic_report;
1645 int int_pol;
1646 int int_val = 0;
1647 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1648
7245387e 1649 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1650
7245387e 1651 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1652 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1653 }
1654
7245387e
MB		 1655 /*
1656 * The rest is microphone jack detection. We need to manually
1657 * invert the polarity of the interrupt after each event - to
1658 * simplify the code keep track of the last state we reported
1659 * and just invert the relevant bits in both the report and
1660 * the polarity register.
1661 */
1662 mic_report = wm8903->mic_last_report;
1663 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1664
1435b940 1665#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1666 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1667 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1668#endif
2bbb5d66 1669
7245387e
MB		 1670 if (int_val & WM8903_MICSHRT_EINT) {
1671 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1672
1673 mic_report ^= wm8903->mic_short;
1674 int_pol ^= WM8903_MICSHRT_INV;
1675 }
1676
1677 if (int_val & WM8903_MICDET_EINT) {
1678 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1679
1680 mic_report ^= wm8903->mic_det;
1681 int_pol ^= WM8903_MICDET_INV;
1682
1683 msleep(wm8903->mic_delay);
1684 }
1685
1686 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1687 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1688
1689 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1690 wm8903->mic_short | wm8903->mic_det);
1691
1692 wm8903->mic_last_report = mic_report;
1693
8abd16a6
MB		 1694 return IRQ_HANDLED;
1695}
1696
f1c0a02f
MB		 1697#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1698 SNDRV_PCM_RATE_11025 | \
1699 SNDRV_PCM_RATE_16000 | \
1700 SNDRV_PCM_RATE_22050 | \
1701 SNDRV_PCM_RATE_32000 | \
1702 SNDRV_PCM_RATE_44100 | \
1703 SNDRV_PCM_RATE_48000 | \
1704 SNDRV_PCM_RATE_88200 | \
1705 SNDRV_PCM_RATE_96000)
1706
1707#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1708 SNDRV_PCM_RATE_11025 | \
1709 SNDRV_PCM_RATE_16000 | \
1710 SNDRV_PCM_RATE_22050 | \
1711 SNDRV_PCM_RATE_32000 | \
1712 SNDRV_PCM_RATE_44100 | \
1713 SNDRV_PCM_RATE_48000)
1714
1715#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1716 SNDRV_PCM_FMTBIT_S20_3LE |\
1717 SNDRV_PCM_FMTBIT_S24_LE)
1718
85e7652d 1719static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1720 .hw_params = wm8903_hw_params,
1721 .digital_mute = wm8903_digital_mute,
1722 .set_fmt = wm8903_set_dai_fmt,
1723 .set_sysclk = wm8903_set_dai_sysclk,
1724};
1725
f0fba2ad
LG		 1726static struct snd_soc_dai_driver wm8903_dai = {
1727 .name = "wm8903-hifi",
f1c0a02f
MB		 1728 .playback = {
1729 .stream_name = "Playback",
1730 .channels_min = 2,
1731 .channels_max = 2,
1732 .rates = WM8903_PLAYBACK_RATES,
1733 .formats = WM8903_FORMATS,
1734 },
1735 .capture = {
1736 .stream_name = "Capture",
1737 .channels_min = 2,
1738 .channels_max = 2,
1739 .rates = WM8903_CAPTURE_RATES,
1740 .formats = WM8903_FORMATS,
1741 },
6335d055 1742 .ops = &wm8903_dai_ops,
0d960e88 1743 .symmetric_rates = 1,
f1c0a02f 1744};
f1c0a02f 1745
84b315ee 1746static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1747{
f1c0a02f
MB		 1748 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1749
1750 return 0;
1751}
1752
f0fba2ad 1753static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1754{
45e96755 1755 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1756
ee244ce4 1757 regcache_sync(wm8903->regmap);
f1c0a02f 1758
45e96755 1759 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1760
1761 return 0;
1762}
1763
7cfe5617
SW		 1764#ifdef CONFIG_GPIOLIB
1765static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1766{
1767 return container_of(chip, struct wm8903_priv, gpio_chip);
1768}
1769
1770static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1771{
1772 if (offset >= WM8903_NUM_GPIO)
1773 return -EINVAL;
1774
1775 return 0;
1776}
1777
1778static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1779{
1780 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1781 struct snd_soc_codec *codec = wm8903->codec;
1782 unsigned int mask, val;
1783
1784 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1785 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1786 WM8903_GP1_DIR;
1787
1788 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1789 mask, val);
1790}
1791
1792static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1793{
1794 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1795 struct snd_soc_codec *codec = wm8903->codec;
1796 int reg;
1797
1798 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1799
1800 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1801}
1802
1803static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1804 unsigned offset, int value)
1805{
1806 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1807 struct snd_soc_codec *codec = wm8903->codec;
1808 unsigned int mask, val;
1809
1810 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1811 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1812 (value << WM8903_GP2_LVL_SHIFT);
1813
1814 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1815 mask, val);
1816}
1817
1818static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1819{
1820 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1821 struct snd_soc_codec *codec = wm8903->codec;
1822
1823 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1824 WM8903_GP1_LVL_MASK,
1825 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1826}
1827
1828static struct gpio_chip wm8903_template_chip = {
1829 .label = "wm8903",
1830 .owner = THIS_MODULE,
1831 .request = wm8903_gpio_request,
1832 .direction_input = wm8903_gpio_direction_in,
1833 .get = wm8903_gpio_get,
1834 .direction_output = wm8903_gpio_direction_out,
1835 .set = wm8903_gpio_set,
1836 .can_sleep = 1,
1837};
1838
1839static void wm8903_init_gpio(struct snd_soc_codec *codec)
1840{
1841 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1842 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1843 int ret;
1844
1845 wm8903->gpio_chip = wm8903_template_chip;
1846 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1847 wm8903->gpio_chip.dev = codec->dev;
1848
1849 if (pdata && pdata->gpio_base)
1850 wm8903->gpio_chip.base = pdata->gpio_base;
1851 else
1852 wm8903->gpio_chip.base = -1;
1853
1854 ret = gpiochip_add(&wm8903->gpio_chip);
1855 if (ret != 0)
1856 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1857}
1858
1859static void wm8903_free_gpio(struct snd_soc_codec *codec)
1860{
1861 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1862 int ret;
1863
1864 ret = gpiochip_remove(&wm8903->gpio_chip);
1865 if (ret != 0)
1866 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1867}
1868#else
1869static void wm8903_init_gpio(struct snd_soc_codec *codec)
1870{
1871}
1872
1873static void wm8903_free_gpio(struct snd_soc_codec *codec)
1874{
1875}
1876#endif
1877
f0fba2ad 1878static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1879{
f0fba2ad
LG		 1880 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1881 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1882 int ret, i;
8abd16a6 1883 int trigger, irq_pol;
f1c0a02f
MB		 1884 u16 val;
1885
7cfe5617 1886 wm8903->codec = codec;
ee244ce4 1887 codec->control_data = wm8903->regmap;
d58d5d55 1888
ee244ce4 1889 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
8d50e447 1890 if (ret != 0) {
f0fba2ad
LG		 1891 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1892 return ret;
8d50e447
MB		 1893 }
1894
1895 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
ee244ce4 1896 if (val != 0x8903) {
f0fba2ad 1897 dev_err(codec->dev,
d58d5d55
MB		 1898 "Device with ID register %x is not a WM8903\n", val);
1899 return -ENODEV;
f1c0a02f
MB		 1900 }
1901
8d50e447 1902 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1903 dev_info(codec->dev, "WM8903 revision %c\n",
1904 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1905
1906 wm8903_reset(codec);
1907
37f88e84 1908 /* Set up GPIOs and microphone detection */
73b34ead 1909 if (pdata) {
905f6952
MB		 1910 bool mic_gpio = false;
1911
73b34ead 1912 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
6f526f0a 1913 if (pdata->gpio_cfg[i] > 0x7fff)
73b34ead
MB		 1914 continue;
1915
1916 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
6f526f0a 1917 pdata->gpio_cfg[i] & 0x7fff);
905f6952
MB		 1918
1919 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1920 >> WM8903_GP1_FN_SHIFT;
1921
1922 switch (val) {
1923 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1924 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1925 mic_gpio = true;
1926 break;
1927 default:
1928 break;
1929 }
73b34ead 1930 }
37f88e84
MB		 1931
1932 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1933 pdata->micdet_cfg);
1934
1935 /* Microphone detection needs the WSEQ clock */
1936 if (pdata->micdet_cfg)
1937 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1938 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1939
905f6952
MB		 1940 /* If microphone detection is enabled by pdata but
1941 * detected via IRQ then interrupts can be lost before
1942 * the machine driver has set up microphone detection
1943 * IRQs as the IRQs are clear on read. The detection
1944 * will be enabled when the machine driver configures.
1945 */
1946 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
1947
37f88e84 1948 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1949 }
8abd16a6 1950
f0fba2ad 1951 if (wm8903->irq) {
8abd16a6
MB		 1952 if (pdata && pdata->irq_active_low) {
1953 trigger = IRQF_TRIGGER_LOW;
1954 irq_pol = WM8903_IRQ_POL;
1955 } else {
1956 trigger = IRQF_TRIGGER_HIGH;
1957 irq_pol = 0;
1958 }
1959
1960 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1961 WM8903_IRQ_POL, irq_pol);
1962
f0fba2ad 1963 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1964 trigger | IRQF_ONESHOT,
f0fba2ad 1965 "wm8903", codec);
8abd16a6 1966 if (ret != 0) {
f0fba2ad 1967 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1968 ret);
f0fba2ad 1969 return ret;
8abd16a6
MB		 1970 }
1971
1972 /* Enable write sequencer interrupts */
1973 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1974 WM8903_IM_WSEQ_BUSY_EINT, 0);
1975 }
73b34ead 1976
f1c0a02f
MB		 1977 /* power on device */
1978 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1979
1980 /* Latch volume update bits */
8d50e447 1981 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1982 val |= WM8903_ADCVU;
8d50e447
MB		 1983 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1984 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1985
8d50e447 1986 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1987 val |= WM8903_DACVU;
8d50e447
MB		 1988 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1989 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1990
8d50e447 1991 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1992 val |= WM8903_HPOUTVU;
8d50e447
MB		 1993 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1994 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1995
8d50e447 1996 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1997 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1998 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1999 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 2000
8d50e447 2001 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 2002 val |= WM8903_SPKVU;
8d50e447
MB		 2003 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
2004 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 2005
2006 /* Enable DAC soft mute by default */
e12adab0
MB		 2007 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
2008 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2009 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 2010
7cfe5617
SW		 2011 wm8903_init_gpio(codec);
2012
f1c0a02f
MB		 2013 return ret;
2014}
2015
f0fba2ad
LG		 2016/* power down chip */
2017static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2018{
f99847a6
SW		 2019 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2020
7cfe5617 2021 wm8903_free_gpio(codec);
f0fba2ad 2022 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6
SW		 2023 if (wm8903->irq)
2024 free_irq(wm8903->irq, codec);
2025
f0fba2ad
LG		 2026 return 0;
2027}
f1c0a02f 2028
f0fba2ad
LG		 2029static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2030 .probe = wm8903_probe,
2031 .remove = wm8903_remove,
2032 .suspend = wm8903_suspend,
2033 .resume = wm8903_resume,
2034 .set_bias_level = wm8903_set_bias_level,
c5b6a9fe 2035 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 2036 .controls = wm8903_snd_controls,
2037 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 2038 .dapm_widgets = wm8903_dapm_widgets,
2039 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2040 .dapm_routes = wm8903_intercon,
2041 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2042};
f1c0a02f 2043
ee244ce4
MB		 2044static const struct regmap_config wm8903_regmap = {
2045 .reg_bits = 8,
2046 .val_bits = 16,
2047
2048 .max_register = WM8903_MAX_REGISTER,
2049 .volatile_reg = wm8903_volatile_register,
2050 .readable_reg = wm8903_readable_register,
2051
2052 .cache_type = REGCACHE_RBTREE,
2053 .reg_defaults = wm8903_reg_defaults,
2054 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
2055};
2056
f0fba2ad
LG		 2057static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2058 const struct i2c_device_id *id)
2059{
2060 struct wm8903_priv *wm8903;
2061 int ret;
f1c0a02f 2062
2950cd22
MB		 2063 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2064 GFP_KERNEL);
f0fba2ad
LG		 2065 if (wm8903 == NULL)
2066 return -ENOMEM;
8abd16a6 2067
ee244ce4
MB		 2068 wm8903->regmap = regmap_init_i2c(i2c, &wm8903_regmap);
2069 if (IS_ERR(wm8903->regmap)) {
2070 ret = PTR_ERR(wm8903->regmap);
2071 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2072 ret);
2073 return ret;
2074 }
2075
f0fba2ad 2076 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2077 wm8903->irq = i2c->irq;
d58d5d55 2078
f0fba2ad
LG		 2079 ret = snd_soc_register_codec(&i2c->dev,
2080 &soc_codec_dev_wm8903, &wm8903_dai, 1);
ee244ce4
MB		 2081 if (ret != 0)
2082 goto err;
2950cd22 2083
ee244ce4
MB		 2084 return 0;
2085err:
2086 regmap_exit(wm8903->regmap);
f0fba2ad
LG		 2087 return ret;
2088}
f1c0a02f 2089
f0fba2ad
LG		 2090static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2091{
ee244ce4
MB		 2092 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2093
2094 regmap_exit(wm8903->regmap);
f0fba2ad 2095 snd_soc_unregister_codec(&client->dev);
ee244ce4 2096
f1c0a02f
MB		 2097 return 0;
2098}
2099
f1c0a02f 2100static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2101 { "wm8903", 0 },
2102 { }
f1c0a02f
MB		 2103};
2104MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2105
2106static struct i2c_driver wm8903_i2c_driver = {
2107 .driver = {
4b592c91 2108 .name = "wm8903",
f1c0a02f
MB		 2109 .owner = THIS_MODULE,
2110 },
f0fba2ad
LG		 2111 .probe = wm8903_i2c_probe,
2112 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2113 .id_table = wm8903_i2c_id,
2114};
2115
f0fba2ad 2116static int __init wm8903_modinit(void)
f1c0a02f 2117{
f1c0a02f 2118 int ret = 0;
f0fba2ad
LG		 2119 ret = i2c_add_driver(&wm8903_i2c_driver);
2120 if (ret != 0) {
2121 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2122 ret);
f1c0a02f 2123 }
f1c0a02f 2124 return ret;
64089b84
MB		 2125}
2126module_init(wm8903_modinit);
2127
2128static void __exit wm8903_exit(void)
2129{
d58d5d55 2130 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 2131}
2132module_exit(wm8903_exit);
2133
f1c0a02f
MB		 2134MODULE_DESCRIPTION("ASoC WM8903 driver");
2135MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2136MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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