Commit | Line | Data |
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f2644a2c MB |
1 | /* |
2 | * wm8960.c -- WM8960 ALSA SoC Audio driver | |
3 | * | |
656baaeb MB |
4 | * Copyright 2007-11 Wolfson Microelectronics, plc |
5 | * | |
f2644a2c MB |
6 | * Author: Liam Girdwood |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/pm.h> | |
75aa8868 | 18 | #include <linux/clk.h> |
f2644a2c | 19 | #include <linux/i2c.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
f2644a2c MB |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/soc.h> | |
f2644a2c MB |
25 | #include <sound/initval.h> |
26 | #include <sound/tlv.h> | |
b6877a47 | 27 | #include <sound/wm8960.h> |
f2644a2c MB |
28 | |
29 | #include "wm8960.h" | |
30 | ||
f2644a2c | 31 | /* R25 - Power 1 */ |
913d7b4c | 32 | #define WM8960_VMID_MASK 0x180 |
f2644a2c MB |
33 | #define WM8960_VREF 0x40 |
34 | ||
913d7b4c MB |
35 | /* R26 - Power 2 */ |
36 | #define WM8960_PWR2_LOUT1 0x40 | |
37 | #define WM8960_PWR2_ROUT1 0x20 | |
38 | #define WM8960_PWR2_OUT3 0x02 | |
39 | ||
f2644a2c MB |
40 | /* R28 - Anti-pop 1 */ |
41 | #define WM8960_POBCTRL 0x80 | |
42 | #define WM8960_BUFDCOPEN 0x10 | |
43 | #define WM8960_BUFIOEN 0x08 | |
44 | #define WM8960_SOFT_ST 0x04 | |
45 | #define WM8960_HPSTBY 0x01 | |
46 | ||
47 | /* R29 - Anti-pop 2 */ | |
48 | #define WM8960_DISOP 0x40 | |
913d7b4c | 49 | #define WM8960_DRES_MASK 0x30 |
f2644a2c | 50 | |
3176bf2d ZW |
51 | static bool is_pll_freq_available(unsigned int source, unsigned int target); |
52 | static int wm8960_set_pll(struct snd_soc_codec *codec, | |
53 | unsigned int freq_in, unsigned int freq_out); | |
f2644a2c MB |
54 | /* |
55 | * wm8960 register cache | |
56 | * We can't read the WM8960 register space when we are | |
57 | * using 2 wire for device control, so we cache them instead. | |
58 | */ | |
0ebe36c6 | 59 | static const struct reg_default wm8960_reg_defaults[] = { |
b3df026e MB |
60 | { 0x0, 0x00a7 }, |
61 | { 0x1, 0x00a7 }, | |
0ebe36c6 MB |
62 | { 0x2, 0x0000 }, |
63 | { 0x3, 0x0000 }, | |
64 | { 0x4, 0x0000 }, | |
65 | { 0x5, 0x0008 }, | |
66 | { 0x6, 0x0000 }, | |
67 | { 0x7, 0x000a }, | |
68 | { 0x8, 0x01c0 }, | |
69 | { 0x9, 0x0000 }, | |
70 | { 0xa, 0x00ff }, | |
71 | { 0xb, 0x00ff }, | |
72 | ||
73 | { 0x10, 0x0000 }, | |
74 | { 0x11, 0x007b }, | |
75 | { 0x12, 0x0100 }, | |
76 | { 0x13, 0x0032 }, | |
77 | { 0x14, 0x0000 }, | |
78 | { 0x15, 0x00c3 }, | |
79 | { 0x16, 0x00c3 }, | |
80 | { 0x17, 0x01c0 }, | |
81 | { 0x18, 0x0000 }, | |
82 | { 0x19, 0x0000 }, | |
83 | { 0x1a, 0x0000 }, | |
84 | { 0x1b, 0x0000 }, | |
85 | { 0x1c, 0x0000 }, | |
86 | { 0x1d, 0x0000 }, | |
87 | ||
88 | { 0x20, 0x0100 }, | |
89 | { 0x21, 0x0100 }, | |
90 | { 0x22, 0x0050 }, | |
91 | ||
92 | { 0x25, 0x0050 }, | |
93 | { 0x26, 0x0000 }, | |
94 | { 0x27, 0x0000 }, | |
95 | { 0x28, 0x0000 }, | |
96 | { 0x29, 0x0000 }, | |
97 | { 0x2a, 0x0040 }, | |
98 | { 0x2b, 0x0000 }, | |
99 | { 0x2c, 0x0000 }, | |
100 | { 0x2d, 0x0050 }, | |
101 | { 0x2e, 0x0050 }, | |
102 | { 0x2f, 0x0000 }, | |
103 | { 0x30, 0x0002 }, | |
104 | { 0x31, 0x0037 }, | |
105 | ||
106 | { 0x33, 0x0080 }, | |
107 | { 0x34, 0x0008 }, | |
108 | { 0x35, 0x0031 }, | |
109 | { 0x36, 0x0026 }, | |
110 | { 0x37, 0x00e9 }, | |
f2644a2c MB |
111 | }; |
112 | ||
0ebe36c6 MB |
113 | static bool wm8960_volatile(struct device *dev, unsigned int reg) |
114 | { | |
115 | switch (reg) { | |
116 | case WM8960_RESET: | |
117 | return true; | |
118 | default: | |
119 | return false; | |
120 | } | |
121 | } | |
122 | ||
f2644a2c | 123 | struct wm8960_priv { |
75aa8868 | 124 | struct clk *mclk; |
0ebe36c6 | 125 | struct regmap *regmap; |
f0fba2ad LG |
126 | int (*set_bias_level)(struct snd_soc_codec *, |
127 | enum snd_soc_bias_level level); | |
913d7b4c MB |
128 | struct snd_soc_dapm_widget *lout1; |
129 | struct snd_soc_dapm_widget *rout1; | |
130 | struct snd_soc_dapm_widget *out3; | |
afd6d36a | 131 | bool deemph; |
3176bf2d | 132 | int lrclk; |
0e50b51a ZW |
133 | int bclk; |
134 | int sysclk; | |
3176bf2d ZW |
135 | int clk_id; |
136 | int freq_in; | |
137 | bool is_stream_in_use[2]; | |
e2280c90 | 138 | struct wm8960_data pdata; |
f2644a2c MB |
139 | }; |
140 | ||
3ad5e861 | 141 | #define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0) |
f2644a2c MB |
142 | |
143 | /* enumerated controls */ | |
f2644a2c MB |
144 | static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted", |
145 | "Right Inverted", "Stereo Inversion"}; | |
146 | static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"}; | |
147 | static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"}; | |
148 | static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"}; | |
149 | static const char *wm8960_alcmode[] = {"ALC", "Limiter"}; | |
4a5893cf ZW |
150 | static const char *wm8960_adc_data_output_sel[] = { |
151 | "Left Data = Left ADC; Right Data = Right ADC", | |
152 | "Left Data = Left ADC; Right Data = Left ADC", | |
153 | "Left Data = Right ADC; Right Data = Right ADC", | |
154 | "Left Data = Right ADC; Right Data = Left ADC", | |
155 | }; | |
defbf708 | 156 | static const char *wm8960_dmonomix[] = {"Stereo", "Mono"}; |
f2644a2c MB |
157 | |
158 | static const struct soc_enum wm8960_enum[] = { | |
f2644a2c MB |
159 | SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity), |
160 | SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity), | |
161 | SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff), | |
162 | SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff), | |
163 | SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc), | |
164 | SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode), | |
4a5893cf | 165 | SOC_ENUM_SINGLE(WM8960_ADDCTL1, 2, 4, wm8960_adc_data_output_sel), |
defbf708 | 166 | SOC_ENUM_SINGLE(WM8960_ADDCTL1, 4, 2, wm8960_dmonomix), |
f2644a2c MB |
167 | }; |
168 | ||
afd6d36a MB |
169 | static const int deemph_settings[] = { 0, 32000, 44100, 48000 }; |
170 | ||
171 | static int wm8960_set_deemph(struct snd_soc_codec *codec) | |
172 | { | |
173 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
174 | int val, i, best; | |
175 | ||
176 | /* If we're using deemphasis select the nearest available sample | |
177 | * rate. | |
178 | */ | |
179 | if (wm8960->deemph) { | |
180 | best = 1; | |
181 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
3176bf2d ZW |
182 | if (abs(deemph_settings[i] - wm8960->lrclk) < |
183 | abs(deemph_settings[best] - wm8960->lrclk)) | |
afd6d36a MB |
184 | best = i; |
185 | } | |
186 | ||
187 | val = best << 1; | |
188 | } else { | |
189 | val = 0; | |
190 | } | |
191 | ||
192 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
193 | ||
194 | return snd_soc_update_bits(codec, WM8960_DACCTL1, | |
195 | 0x6, val); | |
196 | } | |
197 | ||
198 | static int wm8960_get_deemph(struct snd_kcontrol *kcontrol, | |
199 | struct snd_ctl_elem_value *ucontrol) | |
200 | { | |
ea53bf77 | 201 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
afd6d36a MB |
202 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
203 | ||
b4a18c8b | 204 | ucontrol->value.integer.value[0] = wm8960->deemph; |
3f343f85 | 205 | return 0; |
afd6d36a MB |
206 | } |
207 | ||
208 | static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, | |
209 | struct snd_ctl_elem_value *ucontrol) | |
210 | { | |
ea53bf77 | 211 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
afd6d36a | 212 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
c1fe81f2 | 213 | unsigned int deemph = ucontrol->value.integer.value[0]; |
afd6d36a MB |
214 | |
215 | if (deemph > 1) | |
216 | return -EINVAL; | |
217 | ||
218 | wm8960->deemph = deemph; | |
219 | ||
220 | return wm8960_set_deemph(codec); | |
221 | } | |
222 | ||
3758ff5f | 223 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1); |
7e90f9b2 | 224 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0); |
3758ff5f | 225 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); |
f2644a2c MB |
226 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0); |
227 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
7e90f9b2 ZW |
228 | static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1); |
229 | static const unsigned int micboost_tlv[] = { | |
230 | TLV_DB_RANGE_HEAD(2), | |
231 | 0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0), | |
232 | 2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0), | |
233 | }; | |
f2644a2c MB |
234 | |
235 | static const struct snd_kcontrol_new wm8960_snd_controls[] = { | |
236 | SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL, | |
7e90f9b2 | 237 | 0, 63, 0, inpga_tlv), |
f2644a2c MB |
238 | SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL, |
239 | 6, 1, 0), | |
240 | SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL, | |
41a59cae | 241 | 7, 1, 1), |
f2644a2c | 242 | |
95826a37 | 243 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume", |
7e90f9b2 | 244 | WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv), |
95826a37 | 245 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume", |
7e90f9b2 | 246 | WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv), |
95826a37 | 247 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume", |
7e90f9b2 | 248 | WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv), |
95826a37 | 249 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume", |
7e90f9b2 ZW |
250 | WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv), |
251 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume", | |
8524bb0c | 252 | WM8960_RINPATH, 4, 3, 0, micboost_tlv), |
7e90f9b2 | 253 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume", |
8524bb0c | 254 | WM8960_LINPATH, 4, 3, 0, micboost_tlv), |
21eb2693 | 255 | |
f2644a2c MB |
256 | SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC, |
257 | 0, 255, 0, dac_tlv), | |
258 | ||
259 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1, | |
260 | 0, 127, 0, out_tlv), | |
261 | SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1, | |
262 | 7, 1, 0), | |
263 | ||
264 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2, | |
265 | 0, 127, 0, out_tlv), | |
266 | SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2, | |
267 | 7, 1, 0), | |
268 | SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0), | |
269 | SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0), | |
270 | ||
271 | SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0), | |
4faaa8d9 | 272 | SOC_ENUM("ADC Polarity", wm8960_enum[0]), |
f2644a2c MB |
273 | SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0), |
274 | ||
a077e81e | 275 | SOC_ENUM("DAC Polarity", wm8960_enum[1]), |
afd6d36a MB |
276 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, |
277 | wm8960_get_deemph, wm8960_put_deemph), | |
f2644a2c | 278 | |
4faaa8d9 MB |
279 | SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]), |
280 | SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]), | |
f2644a2c MB |
281 | SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0), |
282 | SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0), | |
283 | ||
4faaa8d9 | 284 | SOC_ENUM("ALC Function", wm8960_enum[4]), |
f2644a2c MB |
285 | SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0), |
286 | SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1), | |
287 | SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0), | |
288 | SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0), | |
4faaa8d9 | 289 | SOC_ENUM("ALC Mode", wm8960_enum[5]), |
f2644a2c MB |
290 | SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0), |
291 | SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0), | |
292 | ||
293 | SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0), | |
294 | SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0), | |
295 | ||
c324aac0 MH |
296 | SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC, |
297 | 0, 255, 0, adc_tlv), | |
f2644a2c MB |
298 | |
299 | SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume", | |
300 | WM8960_BYPASS1, 4, 7, 1, bypass_tlv), | |
301 | SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume", | |
302 | WM8960_LOUTMIX, 4, 7, 1, bypass_tlv), | |
303 | SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume", | |
304 | WM8960_BYPASS2, 4, 7, 1, bypass_tlv), | |
305 | SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume", | |
306 | WM8960_ROUTMIX, 4, 7, 1, bypass_tlv), | |
4a5893cf ZW |
307 | |
308 | SOC_ENUM("ADC Data Output Select", wm8960_enum[6]), | |
defbf708 | 309 | SOC_ENUM("DAC Mono Mix", wm8960_enum[7]), |
f2644a2c MB |
310 | }; |
311 | ||
312 | static const struct snd_kcontrol_new wm8960_lin_boost[] = { | |
313 | SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0), | |
314 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0), | |
315 | SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0), | |
316 | }; | |
317 | ||
318 | static const struct snd_kcontrol_new wm8960_lin[] = { | |
319 | SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0), | |
320 | }; | |
321 | ||
322 | static const struct snd_kcontrol_new wm8960_rin_boost[] = { | |
323 | SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0), | |
324 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0), | |
325 | SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0), | |
326 | }; | |
327 | ||
328 | static const struct snd_kcontrol_new wm8960_rin[] = { | |
329 | SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0), | |
330 | }; | |
331 | ||
332 | static const struct snd_kcontrol_new wm8960_loutput_mixer[] = { | |
333 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0), | |
334 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0), | |
335 | SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0), | |
336 | }; | |
337 | ||
338 | static const struct snd_kcontrol_new wm8960_routput_mixer[] = { | |
339 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0), | |
340 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0), | |
341 | SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0), | |
342 | }; | |
343 | ||
344 | static const struct snd_kcontrol_new wm8960_mono_out[] = { | |
345 | SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0), | |
346 | SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0), | |
347 | }; | |
348 | ||
349 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = { | |
350 | SND_SOC_DAPM_INPUT("LINPUT1"), | |
351 | SND_SOC_DAPM_INPUT("RINPUT1"), | |
352 | SND_SOC_DAPM_INPUT("LINPUT2"), | |
353 | SND_SOC_DAPM_INPUT("RINPUT2"), | |
354 | SND_SOC_DAPM_INPUT("LINPUT3"), | |
355 | SND_SOC_DAPM_INPUT("RINPUT3"), | |
356 | ||
187774cb | 357 | SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0), |
f2644a2c MB |
358 | |
359 | SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0, | |
360 | wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)), | |
361 | SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0, | |
362 | wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)), | |
363 | ||
364 | SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0, | |
365 | wm8960_lin, ARRAY_SIZE(wm8960_lin)), | |
366 | SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0, | |
367 | wm8960_rin, ARRAY_SIZE(wm8960_rin)), | |
368 | ||
44426de4 MB |
369 | SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0), |
370 | SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0), | |
f2644a2c MB |
371 | |
372 | SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0), | |
373 | SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0), | |
374 | ||
375 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0, | |
376 | &wm8960_loutput_mixer[0], | |
377 | ARRAY_SIZE(wm8960_loutput_mixer)), | |
378 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0, | |
379 | &wm8960_routput_mixer[0], | |
380 | ARRAY_SIZE(wm8960_routput_mixer)), | |
381 | ||
f2644a2c MB |
382 | SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0), |
383 | SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0), | |
384 | ||
385 | SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0), | |
386 | SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0), | |
387 | ||
388 | SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0), | |
389 | SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0), | |
390 | ||
391 | SND_SOC_DAPM_OUTPUT("SPK_LP"), | |
392 | SND_SOC_DAPM_OUTPUT("SPK_LN"), | |
393 | SND_SOC_DAPM_OUTPUT("HP_L"), | |
394 | SND_SOC_DAPM_OUTPUT("HP_R"), | |
395 | SND_SOC_DAPM_OUTPUT("SPK_RP"), | |
396 | SND_SOC_DAPM_OUTPUT("SPK_RN"), | |
397 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
398 | }; | |
399 | ||
913d7b4c MB |
400 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = { |
401 | SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0, | |
402 | &wm8960_mono_out[0], | |
403 | ARRAY_SIZE(wm8960_mono_out)), | |
404 | }; | |
405 | ||
406 | /* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */ | |
407 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = { | |
408 | SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0), | |
409 | }; | |
410 | ||
f2644a2c MB |
411 | static const struct snd_soc_dapm_route audio_paths[] = { |
412 | { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" }, | |
413 | { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" }, | |
414 | { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" }, | |
415 | ||
2d4a3260 ZW |
416 | { "Left Input Mixer", "Boost Switch", "Left Boost Mixer" }, |
417 | { "Left Input Mixer", "Boost Switch", "LINPUT1" }, /* Really Boost Switch */ | |
f2644a2c MB |
418 | { "Left Input Mixer", NULL, "LINPUT2" }, |
419 | { "Left Input Mixer", NULL, "LINPUT3" }, | |
420 | ||
421 | { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" }, | |
422 | { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" }, | |
423 | { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" }, | |
424 | ||
2d4a3260 ZW |
425 | { "Right Input Mixer", "Boost Switch", "Right Boost Mixer" }, |
426 | { "Right Input Mixer", "Boost Switch", "RINPUT1" }, /* Really Boost Switch */ | |
f2644a2c | 427 | { "Right Input Mixer", NULL, "RINPUT2" }, |
85e36a1f | 428 | { "Right Input Mixer", NULL, "RINPUT3" }, |
f2644a2c MB |
429 | |
430 | { "Left ADC", NULL, "Left Input Mixer" }, | |
431 | { "Right ADC", NULL, "Right Input Mixer" }, | |
432 | ||
433 | { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" }, | |
2d4a3260 | 434 | { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer" }, |
f2644a2c MB |
435 | { "Left Output Mixer", "PCM Playback Switch", "Left DAC" }, |
436 | ||
437 | { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" }, | |
2d4a3260 | 438 | { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" }, |
f2644a2c MB |
439 | { "Right Output Mixer", "PCM Playback Switch", "Right DAC" }, |
440 | ||
f2644a2c MB |
441 | { "LOUT1 PGA", NULL, "Left Output Mixer" }, |
442 | { "ROUT1 PGA", NULL, "Right Output Mixer" }, | |
443 | ||
444 | { "HP_L", NULL, "LOUT1 PGA" }, | |
445 | { "HP_R", NULL, "ROUT1 PGA" }, | |
446 | ||
447 | { "Left Speaker PGA", NULL, "Left Output Mixer" }, | |
448 | { "Right Speaker PGA", NULL, "Right Output Mixer" }, | |
449 | ||
450 | { "Left Speaker Output", NULL, "Left Speaker PGA" }, | |
451 | { "Right Speaker Output", NULL, "Right Speaker PGA" }, | |
452 | ||
453 | { "SPK_LN", NULL, "Left Speaker Output" }, | |
454 | { "SPK_LP", NULL, "Left Speaker Output" }, | |
455 | { "SPK_RN", NULL, "Right Speaker Output" }, | |
456 | { "SPK_RP", NULL, "Right Speaker Output" }, | |
913d7b4c MB |
457 | }; |
458 | ||
459 | static const struct snd_soc_dapm_route audio_paths_out3[] = { | |
460 | { "Mono Output Mixer", "Left Switch", "Left Output Mixer" }, | |
461 | { "Mono Output Mixer", "Right Switch", "Right Output Mixer" }, | |
f2644a2c MB |
462 | |
463 | { "OUT3", NULL, "Mono Output Mixer", } | |
464 | }; | |
465 | ||
913d7b4c MB |
466 | static const struct snd_soc_dapm_route audio_paths_capless[] = { |
467 | { "HP_L", NULL, "OUT3 VMID" }, | |
468 | { "HP_R", NULL, "OUT3 VMID" }, | |
469 | ||
470 | { "OUT3 VMID", NULL, "Left Output Mixer" }, | |
471 | { "OUT3 VMID", NULL, "Right Output Mixer" }, | |
472 | }; | |
473 | ||
f2644a2c MB |
474 | static int wm8960_add_widgets(struct snd_soc_codec *codec) |
475 | { | |
b2c812e2 | 476 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
e2280c90 | 477 | struct wm8960_data *pdata = &wm8960->pdata; |
93f32f53 | 478 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
913d7b4c MB |
479 | struct snd_soc_dapm_widget *w; |
480 | ||
ce6120cc | 481 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets, |
f2644a2c MB |
482 | ARRAY_SIZE(wm8960_dapm_widgets)); |
483 | ||
ce6120cc | 484 | snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); |
f2644a2c | 485 | |
913d7b4c MB |
486 | /* In capless mode OUT3 is used to provide VMID for the |
487 | * headphone outputs, otherwise it is used as a mono mixer. | |
488 | */ | |
489 | if (pdata && pdata->capless) { | |
ce6120cc | 490 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless, |
913d7b4c MB |
491 | ARRAY_SIZE(wm8960_dapm_widgets_capless)); |
492 | ||
ce6120cc | 493 | snd_soc_dapm_add_routes(dapm, audio_paths_capless, |
913d7b4c MB |
494 | ARRAY_SIZE(audio_paths_capless)); |
495 | } else { | |
ce6120cc | 496 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3, |
913d7b4c MB |
497 | ARRAY_SIZE(wm8960_dapm_widgets_out3)); |
498 | ||
ce6120cc | 499 | snd_soc_dapm_add_routes(dapm, audio_paths_out3, |
913d7b4c MB |
500 | ARRAY_SIZE(audio_paths_out3)); |
501 | } | |
502 | ||
503 | /* We need to power up the headphone output stage out of | |
504 | * sequence for capless mode. To save scanning the widget | |
505 | * list each time to find the desired power state do so now | |
506 | * and save the result. | |
507 | */ | |
00200107 | 508 | list_for_each_entry(w, &codec->component.card->widgets, list) { |
93f32f53 | 509 | if (w->dapm != dapm) |
97c866de | 510 | continue; |
913d7b4c MB |
511 | if (strcmp(w->name, "LOUT1 PGA") == 0) |
512 | wm8960->lout1 = w; | |
513 | if (strcmp(w->name, "ROUT1 PGA") == 0) | |
514 | wm8960->rout1 = w; | |
515 | if (strcmp(w->name, "OUT3 VMID") == 0) | |
516 | wm8960->out3 = w; | |
517 | } | |
518 | ||
f2644a2c MB |
519 | return 0; |
520 | } | |
521 | ||
522 | static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
523 | unsigned int fmt) | |
524 | { | |
525 | struct snd_soc_codec *codec = codec_dai->codec; | |
526 | u16 iface = 0; | |
527 | ||
528 | /* set master/slave audio interface */ | |
529 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
530 | case SND_SOC_DAIFMT_CBM_CFM: | |
531 | iface |= 0x0040; | |
532 | break; | |
533 | case SND_SOC_DAIFMT_CBS_CFS: | |
534 | break; | |
535 | default: | |
536 | return -EINVAL; | |
537 | } | |
538 | ||
539 | /* interface format */ | |
540 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
541 | case SND_SOC_DAIFMT_I2S: | |
542 | iface |= 0x0002; | |
543 | break; | |
544 | case SND_SOC_DAIFMT_RIGHT_J: | |
545 | break; | |
546 | case SND_SOC_DAIFMT_LEFT_J: | |
547 | iface |= 0x0001; | |
548 | break; | |
549 | case SND_SOC_DAIFMT_DSP_A: | |
550 | iface |= 0x0003; | |
551 | break; | |
552 | case SND_SOC_DAIFMT_DSP_B: | |
553 | iface |= 0x0013; | |
554 | break; | |
555 | default: | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
559 | /* clock inversion */ | |
560 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
561 | case SND_SOC_DAIFMT_NB_NF: | |
562 | break; | |
563 | case SND_SOC_DAIFMT_IB_IF: | |
564 | iface |= 0x0090; | |
565 | break; | |
566 | case SND_SOC_DAIFMT_IB_NF: | |
567 | iface |= 0x0080; | |
568 | break; | |
569 | case SND_SOC_DAIFMT_NB_IF: | |
570 | iface |= 0x0010; | |
571 | break; | |
572 | default: | |
573 | return -EINVAL; | |
574 | } | |
575 | ||
576 | /* set iface */ | |
17a52fd6 | 577 | snd_soc_write(codec, WM8960_IFACE1, iface); |
f2644a2c MB |
578 | return 0; |
579 | } | |
580 | ||
db059c0f MB |
581 | static struct { |
582 | int rate; | |
583 | unsigned int val; | |
584 | } alc_rates[] = { | |
585 | { 48000, 0 }, | |
586 | { 44100, 0 }, | |
587 | { 32000, 1 }, | |
588 | { 22050, 2 }, | |
589 | { 24000, 2 }, | |
590 | { 16000, 3 }, | |
22ee76da | 591 | { 11025, 4 }, |
db059c0f MB |
592 | { 12000, 4 }, |
593 | { 8000, 5 }, | |
594 | }; | |
595 | ||
3176bf2d ZW |
596 | /* -1 for reserved value */ |
597 | static const int sysclk_divs[] = { 1, -1, 2, -1 }; | |
598 | ||
0e50b51a ZW |
599 | /* Multiply 256 for internal 256 div */ |
600 | static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 }; | |
601 | ||
602 | /* Multiply 10 to eliminate decimials */ | |
603 | static const int bclk_divs[] = { | |
604 | 10, 15, 20, 30, 40, 55, 60, 80, 110, | |
605 | 120, 160, 220, 240, 320, 320, 320 | |
606 | }; | |
607 | ||
3176bf2d | 608 | static int wm8960_configure_clocking(struct snd_soc_codec *codec) |
0e50b51a ZW |
609 | { |
610 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
3176bf2d | 611 | int sysclk, bclk, lrclk, freq_out, freq_in; |
0e50b51a | 612 | u16 iface1 = snd_soc_read(codec, WM8960_IFACE1); |
3176bf2d | 613 | int i, j, k; |
0e50b51a ZW |
614 | |
615 | if (!(iface1 & (1<<6))) { | |
616 | dev_dbg(codec->dev, | |
617 | "Codec is slave mode, no need to configure clock\n"); | |
3176bf2d ZW |
618 | return 0; |
619 | } | |
620 | ||
621 | if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) { | |
622 | dev_err(codec->dev, "No MCLK configured\n"); | |
623 | return -EINVAL; | |
0e50b51a ZW |
624 | } |
625 | ||
3176bf2d ZW |
626 | freq_in = wm8960->freq_in; |
627 | bclk = wm8960->bclk; | |
628 | lrclk = wm8960->lrclk; | |
629 | /* | |
630 | * If it's sysclk auto mode, check if the MCLK can provide sysclk or | |
631 | * not. If MCLK can provide sysclk, using MCLK to provide sysclk | |
632 | * directly. Otherwise, auto select a available pll out frequency | |
633 | * and set PLL. | |
634 | */ | |
635 | if (wm8960->clk_id == WM8960_SYSCLK_AUTO) { | |
636 | /* disable the PLL and using MCLK to provide sysclk */ | |
637 | wm8960_set_pll(codec, 0, 0); | |
638 | freq_out = freq_in; | |
639 | } else if (wm8960->sysclk) { | |
640 | freq_out = wm8960->sysclk; | |
641 | } else { | |
642 | dev_err(codec->dev, "No SYSCLK configured\n"); | |
643 | return -EINVAL; | |
0e50b51a ZW |
644 | } |
645 | ||
6bb74514 SH |
646 | if (wm8960->clk_id != WM8960_SYSCLK_PLL) { |
647 | /* check if the sysclk frequency is available. */ | |
648 | for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { | |
649 | if (sysclk_divs[i] == -1) | |
650 | continue; | |
651 | sysclk = freq_out / sysclk_divs[i]; | |
652 | for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) { | |
653 | if (sysclk != dac_divs[j] * lrclk) | |
654 | continue; | |
3176bf2d ZW |
655 | for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) |
656 | if (sysclk == bclk * bclk_divs[k] / 10) | |
657 | break; | |
658 | if (k != ARRAY_SIZE(bclk_divs)) | |
659 | break; | |
660 | } | |
6bb74514 SH |
661 | if (j != ARRAY_SIZE(dac_divs)) |
662 | break; | |
3176bf2d | 663 | } |
0e50b51a | 664 | |
6bb74514 SH |
665 | if (i != ARRAY_SIZE(sysclk_divs)) { |
666 | goto configure_clock; | |
667 | } else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) { | |
668 | dev_err(codec->dev, "failed to configure clock\n"); | |
669 | return -EINVAL; | |
670 | } | |
3176bf2d ZW |
671 | } |
672 | /* get a available pll out frequency and set pll */ | |
673 | for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { | |
674 | if (sysclk_divs[i] == -1) | |
675 | continue; | |
676 | for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) { | |
677 | sysclk = lrclk * dac_divs[j]; | |
678 | freq_out = sysclk * sysclk_divs[i]; | |
679 | ||
680 | for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) { | |
681 | if (sysclk == bclk * bclk_divs[k] / 10 && | |
682 | is_pll_freq_available(freq_in, freq_out)) { | |
683 | wm8960_set_pll(codec, | |
684 | freq_in, freq_out); | |
0e50b51a | 685 | break; |
3176bf2d ZW |
686 | } else { |
687 | continue; | |
688 | } | |
0e50b51a | 689 | } |
3176bf2d | 690 | if (k != ARRAY_SIZE(bclk_divs)) |
0e50b51a ZW |
691 | break; |
692 | } | |
3176bf2d ZW |
693 | if (j != ARRAY_SIZE(dac_divs)) |
694 | break; | |
0e50b51a ZW |
695 | } |
696 | ||
3176bf2d ZW |
697 | if (i == ARRAY_SIZE(sysclk_divs)) { |
698 | dev_err(codec->dev, "failed to configure clock\n"); | |
699 | return -EINVAL; | |
0e50b51a ZW |
700 | } |
701 | ||
3176bf2d ZW |
702 | configure_clock: |
703 | /* configure sysclk clock */ | |
704 | snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1); | |
705 | ||
706 | /* configure frame clock */ | |
707 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3); | |
708 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6); | |
0e50b51a ZW |
709 | |
710 | /* configure bit clock */ | |
3176bf2d ZW |
711 | snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k); |
712 | ||
713 | return 0; | |
0e50b51a ZW |
714 | } |
715 | ||
f2644a2c MB |
716 | static int wm8960_hw_params(struct snd_pcm_substream *substream, |
717 | struct snd_pcm_hw_params *params, | |
718 | struct snd_soc_dai *dai) | |
719 | { | |
e6968a17 | 720 | struct snd_soc_codec *codec = dai->codec; |
afd6d36a | 721 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
17a52fd6 | 722 | u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3; |
0e50b51a | 723 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
db059c0f | 724 | int i; |
f2644a2c | 725 | |
0e50b51a ZW |
726 | wm8960->bclk = snd_soc_params_to_bclk(params); |
727 | if (params_channels(params) == 1) | |
728 | wm8960->bclk *= 2; | |
729 | ||
f2644a2c | 730 | /* bit size */ |
39e9cc46 MB |
731 | switch (params_width(params)) { |
732 | case 16: | |
f2644a2c | 733 | break; |
39e9cc46 | 734 | case 20: |
f2644a2c MB |
735 | iface |= 0x0004; |
736 | break; | |
39e9cc46 | 737 | case 24: |
f2644a2c MB |
738 | iface |= 0x0008; |
739 | break; | |
7a8c7867 ZW |
740 | case 32: |
741 | /* right justify mode does not support 32 word length */ | |
742 | if ((iface & 0x3) != 0) { | |
743 | iface |= 0x000c; | |
744 | break; | |
745 | } | |
4c2474c0 | 746 | default: |
39e9cc46 MB |
747 | dev_err(codec->dev, "unsupported width %d\n", |
748 | params_width(params)); | |
4c2474c0 | 749 | return -EINVAL; |
f2644a2c MB |
750 | } |
751 | ||
3176bf2d | 752 | wm8960->lrclk = params_rate(params); |
afd6d36a | 753 | /* Update filters for the new rate */ |
3176bf2d | 754 | if (tx) { |
afd6d36a | 755 | wm8960_set_deemph(codec); |
db059c0f MB |
756 | } else { |
757 | for (i = 0; i < ARRAY_SIZE(alc_rates); i++) | |
758 | if (alc_rates[i].rate == params_rate(params)) | |
759 | snd_soc_update_bits(codec, | |
760 | WM8960_ADDCTL3, 0x7, | |
761 | alc_rates[i].val); | |
afd6d36a MB |
762 | } |
763 | ||
f2644a2c | 764 | /* set iface */ |
17a52fd6 | 765 | snd_soc_write(codec, WM8960_IFACE1, iface); |
0e50b51a | 766 | |
3176bf2d ZW |
767 | wm8960->is_stream_in_use[tx] = true; |
768 | ||
769 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON && | |
770 | !wm8960->is_stream_in_use[!tx]) | |
771 | return wm8960_configure_clocking(codec); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static int wm8960_hw_free(struct snd_pcm_substream *substream, | |
777 | struct snd_soc_dai *dai) | |
778 | { | |
779 | struct snd_soc_codec *codec = dai->codec; | |
780 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
781 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
782 | ||
783 | wm8960->is_stream_in_use[tx] = false; | |
0e50b51a | 784 | |
f2644a2c MB |
785 | return 0; |
786 | } | |
787 | ||
788 | static int wm8960_mute(struct snd_soc_dai *dai, int mute) | |
789 | { | |
790 | struct snd_soc_codec *codec = dai->codec; | |
f2644a2c MB |
791 | |
792 | if (mute) | |
16b24881 | 793 | snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8); |
f2644a2c | 794 | else |
16b24881 | 795 | snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0); |
f2644a2c MB |
796 | return 0; |
797 | } | |
798 | ||
913d7b4c MB |
799 | static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, |
800 | enum snd_soc_bias_level level) | |
f2644a2c | 801 | { |
0ebe36c6 | 802 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
3176bf2d | 803 | u16 pm2 = snd_soc_read(codec, WM8960_POWER2); |
75aa8868 | 804 | int ret; |
0ebe36c6 | 805 | |
f2644a2c MB |
806 | switch (level) { |
807 | case SND_SOC_BIAS_ON: | |
808 | break; | |
809 | ||
810 | case SND_SOC_BIAS_PREPARE: | |
93f32f53 | 811 | switch (snd_soc_codec_get_bias_level(codec)) { |
75aa8868 ZW |
812 | case SND_SOC_BIAS_STANDBY: |
813 | if (!IS_ERR(wm8960->mclk)) { | |
814 | ret = clk_prepare_enable(wm8960->mclk); | |
815 | if (ret) { | |
816 | dev_err(codec->dev, | |
817 | "Failed to enable MCLK: %d\n", | |
818 | ret); | |
819 | return ret; | |
820 | } | |
821 | } | |
822 | ||
3176bf2d ZW |
823 | ret = wm8960_configure_clocking(codec); |
824 | if (ret) | |
825 | return ret; | |
826 | ||
75aa8868 ZW |
827 | /* Set VMID to 2x50k */ |
828 | snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80); | |
829 | break; | |
830 | ||
831 | case SND_SOC_BIAS_ON: | |
3176bf2d ZW |
832 | /* |
833 | * If it's sysclk auto mode, and the pll is enabled, | |
834 | * disable the pll | |
835 | */ | |
836 | if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1)) | |
837 | wm8960_set_pll(codec, 0, 0); | |
838 | ||
75aa8868 ZW |
839 | if (!IS_ERR(wm8960->mclk)) |
840 | clk_disable_unprepare(wm8960->mclk); | |
841 | break; | |
842 | ||
843 | default: | |
844 | break; | |
845 | } | |
846 | ||
f2644a2c MB |
847 | break; |
848 | ||
849 | case SND_SOC_BIAS_STANDBY: | |
93f32f53 | 850 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { |
0ebe36c6 | 851 | regcache_sync(wm8960->regmap); |
bc45df2d | 852 | |
f2644a2c | 853 | /* Enable anti-pop features */ |
17a52fd6 | 854 | snd_soc_write(codec, WM8960_APOP1, |
913d7b4c MB |
855 | WM8960_POBCTRL | WM8960_SOFT_ST | |
856 | WM8960_BUFDCOPEN | WM8960_BUFIOEN); | |
f2644a2c MB |
857 | |
858 | /* Enable & ramp VMID at 2x50k */ | |
16b24881 | 859 | snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80); |
f2644a2c MB |
860 | msleep(100); |
861 | ||
862 | /* Enable VREF */ | |
16b24881 AL |
863 | snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF, |
864 | WM8960_VREF); | |
f2644a2c MB |
865 | |
866 | /* Disable anti-pop features */ | |
17a52fd6 | 867 | snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN); |
f2644a2c MB |
868 | } |
869 | ||
870 | /* Set VMID to 2x250k */ | |
16b24881 | 871 | snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100); |
f2644a2c MB |
872 | break; |
873 | ||
874 | case SND_SOC_BIAS_OFF: | |
875 | /* Enable anti-pop features */ | |
17a52fd6 | 876 | snd_soc_write(codec, WM8960_APOP1, |
f2644a2c MB |
877 | WM8960_POBCTRL | WM8960_SOFT_ST | |
878 | WM8960_BUFDCOPEN | WM8960_BUFIOEN); | |
879 | ||
880 | /* Disable VMID and VREF, let them discharge */ | |
17a52fd6 | 881 | snd_soc_write(codec, WM8960_POWER1, 0); |
f2644a2c | 882 | msleep(600); |
913d7b4c MB |
883 | break; |
884 | } | |
885 | ||
913d7b4c MB |
886 | return 0; |
887 | } | |
888 | ||
889 | static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec, | |
890 | enum snd_soc_bias_level level) | |
891 | { | |
b2c812e2 | 892 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
3176bf2d | 893 | u16 pm2 = snd_soc_read(codec, WM8960_POWER2); |
75aa8868 | 894 | int reg, ret; |
913d7b4c MB |
895 | |
896 | switch (level) { | |
897 | case SND_SOC_BIAS_ON: | |
898 | break; | |
899 | ||
900 | case SND_SOC_BIAS_PREPARE: | |
93f32f53 | 901 | switch (snd_soc_codec_get_bias_level(codec)) { |
913d7b4c MB |
902 | case SND_SOC_BIAS_STANDBY: |
903 | /* Enable anti pop mode */ | |
904 | snd_soc_update_bits(codec, WM8960_APOP1, | |
905 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
906 | WM8960_BUFDCOPEN, | |
907 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
908 | WM8960_BUFDCOPEN); | |
909 | ||
910 | /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */ | |
911 | reg = 0; | |
912 | if (wm8960->lout1 && wm8960->lout1->power) | |
913 | reg |= WM8960_PWR2_LOUT1; | |
914 | if (wm8960->rout1 && wm8960->rout1->power) | |
915 | reg |= WM8960_PWR2_ROUT1; | |
916 | if (wm8960->out3 && wm8960->out3->power) | |
917 | reg |= WM8960_PWR2_OUT3; | |
918 | snd_soc_update_bits(codec, WM8960_POWER2, | |
919 | WM8960_PWR2_LOUT1 | | |
920 | WM8960_PWR2_ROUT1 | | |
921 | WM8960_PWR2_OUT3, reg); | |
922 | ||
923 | /* Enable VMID at 2*50k */ | |
924 | snd_soc_update_bits(codec, WM8960_POWER1, | |
925 | WM8960_VMID_MASK, 0x80); | |
926 | ||
927 | /* Ramp */ | |
928 | msleep(100); | |
929 | ||
930 | /* Enable VREF */ | |
931 | snd_soc_update_bits(codec, WM8960_POWER1, | |
932 | WM8960_VREF, WM8960_VREF); | |
933 | ||
934 | msleep(100); | |
75aa8868 ZW |
935 | |
936 | if (!IS_ERR(wm8960->mclk)) { | |
937 | ret = clk_prepare_enable(wm8960->mclk); | |
938 | if (ret) { | |
939 | dev_err(codec->dev, | |
940 | "Failed to enable MCLK: %d\n", | |
941 | ret); | |
942 | return ret; | |
943 | } | |
944 | } | |
3176bf2d ZW |
945 | |
946 | ret = wm8960_configure_clocking(codec); | |
947 | if (ret) | |
948 | return ret; | |
949 | ||
913d7b4c MB |
950 | break; |
951 | ||
952 | case SND_SOC_BIAS_ON: | |
3176bf2d ZW |
953 | /* |
954 | * If it's sysclk auto mode, and the pll is enabled, | |
955 | * disable the pll | |
956 | */ | |
957 | if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1)) | |
958 | wm8960_set_pll(codec, 0, 0); | |
959 | ||
75aa8868 ZW |
960 | if (!IS_ERR(wm8960->mclk)) |
961 | clk_disable_unprepare(wm8960->mclk); | |
962 | ||
913d7b4c MB |
963 | /* Enable anti-pop mode */ |
964 | snd_soc_update_bits(codec, WM8960_APOP1, | |
965 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
966 | WM8960_BUFDCOPEN, | |
967 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
968 | WM8960_BUFDCOPEN); | |
969 | ||
970 | /* Disable VMID and VREF */ | |
971 | snd_soc_update_bits(codec, WM8960_POWER1, | |
972 | WM8960_VREF | WM8960_VMID_MASK, 0); | |
973 | break; | |
974 | ||
bc45df2d | 975 | case SND_SOC_BIAS_OFF: |
0ebe36c6 | 976 | regcache_sync(wm8960->regmap); |
bc45df2d | 977 | break; |
913d7b4c MB |
978 | default: |
979 | break; | |
980 | } | |
981 | break; | |
f2644a2c | 982 | |
913d7b4c | 983 | case SND_SOC_BIAS_STANDBY: |
93f32f53 | 984 | switch (snd_soc_codec_get_bias_level(codec)) { |
913d7b4c MB |
985 | case SND_SOC_BIAS_PREPARE: |
986 | /* Disable HP discharge */ | |
987 | snd_soc_update_bits(codec, WM8960_APOP2, | |
988 | WM8960_DISOP | WM8960_DRES_MASK, | |
989 | 0); | |
990 | ||
991 | /* Disable anti-pop features */ | |
992 | snd_soc_update_bits(codec, WM8960_APOP1, | |
993 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
994 | WM8960_BUFDCOPEN, | |
995 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
996 | WM8960_BUFDCOPEN); | |
997 | break; | |
998 | ||
999 | default: | |
1000 | break; | |
1001 | } | |
1002 | break; | |
f2644a2c | 1003 | |
913d7b4c | 1004 | case SND_SOC_BIAS_OFF: |
f2644a2c MB |
1005 | break; |
1006 | } | |
1007 | ||
f2644a2c MB |
1008 | return 0; |
1009 | } | |
1010 | ||
1011 | /* PLL divisors */ | |
1012 | struct _pll_div { | |
1013 | u32 pre_div:1; | |
1014 | u32 n:4; | |
1015 | u32 k:24; | |
1016 | }; | |
1017 | ||
3176bf2d ZW |
1018 | static bool is_pll_freq_available(unsigned int source, unsigned int target) |
1019 | { | |
1020 | unsigned int Ndiv; | |
1021 | ||
1022 | if (source == 0 || target == 0) | |
1023 | return false; | |
1024 | ||
1025 | /* Scale up target to PLL operating frequency */ | |
1026 | target *= 4; | |
1027 | Ndiv = target / source; | |
1028 | ||
1029 | if (Ndiv < 6) { | |
1030 | source >>= 1; | |
1031 | Ndiv = target / source; | |
1032 | } | |
1033 | ||
1034 | if ((Ndiv < 6) || (Ndiv > 12)) | |
1035 | return false; | |
1036 | ||
1037 | return true; | |
1038 | } | |
1039 | ||
f2644a2c MB |
1040 | /* The size in bits of the pll divide multiplied by 10 |
1041 | * to allow rounding later */ | |
1042 | #define FIXED_PLL_SIZE ((1 << 24) * 10) | |
1043 | ||
1044 | static int pll_factors(unsigned int source, unsigned int target, | |
1045 | struct _pll_div *pll_div) | |
1046 | { | |
1047 | unsigned long long Kpart; | |
1048 | unsigned int K, Ndiv, Nmod; | |
1049 | ||
1050 | pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target); | |
1051 | ||
1052 | /* Scale up target to PLL operating frequency */ | |
1053 | target *= 4; | |
1054 | ||
1055 | Ndiv = target / source; | |
1056 | if (Ndiv < 6) { | |
1057 | source >>= 1; | |
1058 | pll_div->pre_div = 1; | |
1059 | Ndiv = target / source; | |
1060 | } else | |
1061 | pll_div->pre_div = 0; | |
1062 | ||
1063 | if ((Ndiv < 6) || (Ndiv > 12)) { | |
1064 | pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv); | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | ||
1068 | pll_div->n = Ndiv; | |
1069 | Nmod = target % source; | |
1070 | Kpart = FIXED_PLL_SIZE * (long long)Nmod; | |
1071 | ||
1072 | do_div(Kpart, source); | |
1073 | ||
1074 | K = Kpart & 0xFFFFFFFF; | |
1075 | ||
1076 | /* Check if we need to round */ | |
1077 | if ((K % 10) >= 5) | |
1078 | K += 5; | |
1079 | ||
1080 | /* Move down to proper range now rounding is done */ | |
1081 | K /= 10; | |
1082 | ||
1083 | pll_div->k = K; | |
1084 | ||
1085 | pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n", | |
1086 | pll_div->n, pll_div->k, pll_div->pre_div); | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
3176bf2d ZW |
1091 | static int wm8960_set_pll(struct snd_soc_codec *codec, |
1092 | unsigned int freq_in, unsigned int freq_out) | |
f2644a2c | 1093 | { |
f2644a2c MB |
1094 | u16 reg; |
1095 | static struct _pll_div pll_div; | |
1096 | int ret; | |
1097 | ||
1098 | if (freq_in && freq_out) { | |
1099 | ret = pll_factors(freq_in, freq_out, &pll_div); | |
1100 | if (ret != 0) | |
1101 | return ret; | |
1102 | } | |
1103 | ||
1104 | /* Disable the PLL: even if we are changing the frequency the | |
1105 | * PLL needs to be disabled while we do so. */ | |
16b24881 AL |
1106 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0); |
1107 | snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0); | |
f2644a2c MB |
1108 | |
1109 | if (!freq_in || !freq_out) | |
1110 | return 0; | |
1111 | ||
17a52fd6 | 1112 | reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f; |
f2644a2c MB |
1113 | reg |= pll_div.pre_div << 4; |
1114 | reg |= pll_div.n; | |
1115 | ||
1116 | if (pll_div.k) { | |
1117 | reg |= 0x20; | |
1118 | ||
85fa532b MD |
1119 | snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); |
1120 | snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); | |
1121 | snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); | |
f2644a2c | 1122 | } |
17a52fd6 | 1123 | snd_soc_write(codec, WM8960_PLL1, reg); |
f2644a2c MB |
1124 | |
1125 | /* Turn it on */ | |
16b24881 | 1126 | snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1); |
f2644a2c | 1127 | msleep(250); |
16b24881 | 1128 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1); |
f2644a2c MB |
1129 | |
1130 | return 0; | |
1131 | } | |
1132 | ||
3176bf2d ZW |
1133 | static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
1134 | int source, unsigned int freq_in, unsigned int freq_out) | |
1135 | { | |
1136 | struct snd_soc_codec *codec = codec_dai->codec; | |
1137 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
1138 | ||
1139 | wm8960->freq_in = freq_in; | |
1140 | ||
1141 | if (pll_id == WM8960_SYSCLK_AUTO) | |
1142 | return 0; | |
1143 | ||
1144 | return wm8960_set_pll(codec, freq_in, freq_out); | |
1145 | } | |
1146 | ||
f2644a2c MB |
1147 | static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
1148 | int div_id, int div) | |
1149 | { | |
1150 | struct snd_soc_codec *codec = codec_dai->codec; | |
1151 | u16 reg; | |
1152 | ||
1153 | switch (div_id) { | |
f2644a2c | 1154 | case WM8960_SYSCLKDIV: |
17a52fd6 MB |
1155 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9; |
1156 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); | |
f2644a2c MB |
1157 | break; |
1158 | case WM8960_DACDIV: | |
17a52fd6 MB |
1159 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7; |
1160 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); | |
f2644a2c MB |
1161 | break; |
1162 | case WM8960_OPCLKDIV: | |
17a52fd6 MB |
1163 | reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f; |
1164 | snd_soc_write(codec, WM8960_PLL1, reg | div); | |
f2644a2c MB |
1165 | break; |
1166 | case WM8960_DCLKDIV: | |
17a52fd6 MB |
1167 | reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f; |
1168 | snd_soc_write(codec, WM8960_CLOCK2, reg | div); | |
f2644a2c MB |
1169 | break; |
1170 | case WM8960_TOCLKSEL: | |
17a52fd6 MB |
1171 | reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd; |
1172 | snd_soc_write(codec, WM8960_ADDCTL1, reg | div); | |
f2644a2c MB |
1173 | break; |
1174 | default: | |
1175 | return -EINVAL; | |
1176 | } | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
f0fba2ad LG |
1181 | static int wm8960_set_bias_level(struct snd_soc_codec *codec, |
1182 | enum snd_soc_bias_level level) | |
1183 | { | |
1184 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
1185 | ||
1186 | return wm8960->set_bias_level(codec, level); | |
1187 | } | |
1188 | ||
0e50b51a ZW |
1189 | static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
1190 | unsigned int freq, int dir) | |
1191 | { | |
1192 | struct snd_soc_codec *codec = dai->codec; | |
1193 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
1194 | ||
1195 | switch (clk_id) { | |
1196 | case WM8960_SYSCLK_MCLK: | |
1197 | snd_soc_update_bits(codec, WM8960_CLOCK1, | |
1198 | 0x1, WM8960_SYSCLK_MCLK); | |
1199 | break; | |
1200 | case WM8960_SYSCLK_PLL: | |
1201 | snd_soc_update_bits(codec, WM8960_CLOCK1, | |
1202 | 0x1, WM8960_SYSCLK_PLL); | |
1203 | break; | |
3176bf2d ZW |
1204 | case WM8960_SYSCLK_AUTO: |
1205 | break; | |
0e50b51a ZW |
1206 | default: |
1207 | return -EINVAL; | |
1208 | } | |
1209 | ||
1210 | wm8960->sysclk = freq; | |
3176bf2d | 1211 | wm8960->clk_id = clk_id; |
0e50b51a ZW |
1212 | |
1213 | return 0; | |
1214 | } | |
1215 | ||
f2644a2c MB |
1216 | #define WM8960_RATES SNDRV_PCM_RATE_8000_48000 |
1217 | ||
1218 | #define WM8960_FORMATS \ | |
1219 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
7a8c7867 | 1220 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
f2644a2c | 1221 | |
85e7652d | 1222 | static const struct snd_soc_dai_ops wm8960_dai_ops = { |
f2644a2c | 1223 | .hw_params = wm8960_hw_params, |
3176bf2d | 1224 | .hw_free = wm8960_hw_free, |
f2644a2c MB |
1225 | .digital_mute = wm8960_mute, |
1226 | .set_fmt = wm8960_set_dai_fmt, | |
1227 | .set_clkdiv = wm8960_set_dai_clkdiv, | |
1228 | .set_pll = wm8960_set_dai_pll, | |
0e50b51a | 1229 | .set_sysclk = wm8960_set_dai_sysclk, |
f2644a2c MB |
1230 | }; |
1231 | ||
f0fba2ad LG |
1232 | static struct snd_soc_dai_driver wm8960_dai = { |
1233 | .name = "wm8960-hifi", | |
f2644a2c MB |
1234 | .playback = { |
1235 | .stream_name = "Playback", | |
1236 | .channels_min = 1, | |
1237 | .channels_max = 2, | |
1238 | .rates = WM8960_RATES, | |
1239 | .formats = WM8960_FORMATS,}, | |
1240 | .capture = { | |
1241 | .stream_name = "Capture", | |
1242 | .channels_min = 1, | |
1243 | .channels_max = 2, | |
1244 | .rates = WM8960_RATES, | |
1245 | .formats = WM8960_FORMATS,}, | |
1246 | .ops = &wm8960_dai_ops, | |
1247 | .symmetric_rates = 1, | |
1248 | }; | |
f2644a2c | 1249 | |
f0fba2ad | 1250 | static int wm8960_probe(struct snd_soc_codec *codec) |
f2644a2c | 1251 | { |
f0fba2ad | 1252 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
e2280c90 | 1253 | struct wm8960_data *pdata = &wm8960->pdata; |
f2644a2c | 1254 | |
e2280c90 ZW |
1255 | if (pdata->capless) |
1256 | wm8960->set_bias_level = wm8960_set_bias_level_capless; | |
1257 | else | |
1258 | wm8960->set_bias_level = wm8960_set_bias_level_out3; | |
f2644a2c | 1259 | |
022658be | 1260 | snd_soc_add_codec_controls(codec, wm8960_snd_controls, |
f0fba2ad LG |
1261 | ARRAY_SIZE(wm8960_snd_controls)); |
1262 | wm8960_add_widgets(codec); | |
f2644a2c MB |
1263 | |
1264 | return 0; | |
1265 | } | |
1266 | ||
f0fba2ad LG |
1267 | static struct snd_soc_codec_driver soc_codec_dev_wm8960 = { |
1268 | .probe = wm8960_probe, | |
f0fba2ad | 1269 | .set_bias_level = wm8960_set_bias_level, |
0a87a6e1 | 1270 | .suspend_bias_off = true, |
0ebe36c6 MB |
1271 | }; |
1272 | ||
1273 | static const struct regmap_config wm8960_regmap = { | |
1274 | .reg_bits = 7, | |
1275 | .val_bits = 9, | |
1276 | .max_register = WM8960_PLL4, | |
1277 | ||
1278 | .reg_defaults = wm8960_reg_defaults, | |
1279 | .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults), | |
1280 | .cache_type = REGCACHE_RBTREE, | |
1281 | ||
1282 | .volatile_reg = wm8960_volatile, | |
f0fba2ad LG |
1283 | }; |
1284 | ||
e2280c90 ZW |
1285 | static void wm8960_set_pdata_from_of(struct i2c_client *i2c, |
1286 | struct wm8960_data *pdata) | |
1287 | { | |
1288 | const struct device_node *np = i2c->dev.of_node; | |
1289 | ||
1290 | if (of_property_read_bool(np, "wlf,capless")) | |
1291 | pdata->capless = true; | |
1292 | ||
1293 | if (of_property_read_bool(np, "wlf,shared-lrclk")) | |
1294 | pdata->shared_lrclk = true; | |
1295 | } | |
1296 | ||
7a79e94e BP |
1297 | static int wm8960_i2c_probe(struct i2c_client *i2c, |
1298 | const struct i2c_device_id *id) | |
f2644a2c | 1299 | { |
37061631 | 1300 | struct wm8960_data *pdata = dev_get_platdata(&i2c->dev); |
f2644a2c | 1301 | struct wm8960_priv *wm8960; |
f0fba2ad | 1302 | int ret; |
f2644a2c | 1303 | |
b9791c01 MB |
1304 | wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv), |
1305 | GFP_KERNEL); | |
f2644a2c MB |
1306 | if (wm8960 == NULL) |
1307 | return -ENOMEM; | |
1308 | ||
75aa8868 ZW |
1309 | wm8960->mclk = devm_clk_get(&i2c->dev, "mclk"); |
1310 | if (IS_ERR(wm8960->mclk)) { | |
1311 | if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER) | |
1312 | return -EPROBE_DEFER; | |
1313 | } | |
1314 | ||
c5e6f5fa | 1315 | wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap); |
0ebe36c6 MB |
1316 | if (IS_ERR(wm8960->regmap)) |
1317 | return PTR_ERR(wm8960->regmap); | |
1318 | ||
e2280c90 ZW |
1319 | if (pdata) |
1320 | memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data)); | |
1321 | else if (i2c->dev.of_node) | |
1322 | wm8960_set_pdata_from_of(i2c, &wm8960->pdata); | |
1323 | ||
3ad5e861 ZW |
1324 | ret = wm8960_reset(wm8960->regmap); |
1325 | if (ret != 0) { | |
1326 | dev_err(&i2c->dev, "Failed to issue reset\n"); | |
1327 | return ret; | |
1328 | } | |
1329 | ||
1330 | if (wm8960->pdata.shared_lrclk) { | |
37061631 MB |
1331 | ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, |
1332 | 0x4, 0x4); | |
1333 | if (ret != 0) { | |
1334 | dev_err(&i2c->dev, "Failed to enable LRCM: %d\n", | |
1335 | ret); | |
1336 | return ret; | |
1337 | } | |
1338 | } | |
1339 | ||
3ad5e861 ZW |
1340 | /* Latch the update bits */ |
1341 | regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100); | |
1342 | regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100); | |
1343 | regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100); | |
1344 | regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100); | |
1345 | regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100); | |
1346 | regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100); | |
1347 | regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100); | |
1348 | regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100); | |
1349 | regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100); | |
1350 | regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100); | |
1351 | ||
f2644a2c | 1352 | i2c_set_clientdata(i2c, wm8960); |
f2644a2c | 1353 | |
f0fba2ad LG |
1354 | ret = snd_soc_register_codec(&i2c->dev, |
1355 | &soc_codec_dev_wm8960, &wm8960_dai, 1); | |
b9791c01 | 1356 | |
f0fba2ad | 1357 | return ret; |
f2644a2c MB |
1358 | } |
1359 | ||
7a79e94e | 1360 | static int wm8960_i2c_remove(struct i2c_client *client) |
f2644a2c | 1361 | { |
f0fba2ad | 1362 | snd_soc_unregister_codec(&client->dev); |
f2644a2c MB |
1363 | return 0; |
1364 | } | |
1365 | ||
1366 | static const struct i2c_device_id wm8960_i2c_id[] = { | |
1367 | { "wm8960", 0 }, | |
1368 | { } | |
1369 | }; | |
1370 | MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id); | |
1371 | ||
e2280c90 ZW |
1372 | static const struct of_device_id wm8960_of_match[] = { |
1373 | { .compatible = "wlf,wm8960", }, | |
1374 | { } | |
1375 | }; | |
1376 | MODULE_DEVICE_TABLE(of, wm8960_of_match); | |
1377 | ||
f2644a2c MB |
1378 | static struct i2c_driver wm8960_i2c_driver = { |
1379 | .driver = { | |
091edccf | 1380 | .name = "wm8960", |
e2280c90 | 1381 | .of_match_table = wm8960_of_match, |
f2644a2c MB |
1382 | }, |
1383 | .probe = wm8960_i2c_probe, | |
7a79e94e | 1384 | .remove = wm8960_i2c_remove, |
f2644a2c MB |
1385 | .id_table = wm8960_i2c_id, |
1386 | }; | |
1387 | ||
3c010e60 | 1388 | module_i2c_driver(wm8960_i2c_driver); |
f2644a2c | 1389 | |
f2644a2c MB |
1390 | MODULE_DESCRIPTION("ASoC WM8960 driver"); |
1391 | MODULE_AUTHOR("Liam Girdwood"); | |
1392 | MODULE_LICENSE("GPL"); |