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Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / codecs / wm8960.c
CommitLineData
f2644a2c
MB		 1/*
2 * wm8960.c -- WM8960 ALSA SoC Audio driver
3 *
656baaeb
MB		 4 * Copyright 2007-11 Wolfson Microelectronics, plc
5 *
f2644a2c
MB		 6 * Author: Liam Girdwood
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
75aa8868 18#include <linux/clk.h>
f2644a2c 19#include <linux/i2c.h>
5a0e3ad6 20#include <linux/slab.h>
f2644a2c
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
f2644a2c
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
b6877a47 27#include <sound/wm8960.h>
f2644a2c
MB		 28
29#include "wm8960.h"
30
f2644a2c 31/* R25 - Power 1 */
913d7b4c 32#define WM8960_VMID_MASK 0x180
f2644a2c
MB		 33#define WM8960_VREF 0x40
34
913d7b4c
MB		 35/* R26 - Power 2 */
36#define WM8960_PWR2_LOUT1 0x40
37#define WM8960_PWR2_ROUT1 0x20
38#define WM8960_PWR2_OUT3 0x02
39
f2644a2c
MB		 40/* R28 - Anti-pop 1 */
41#define WM8960_POBCTRL 0x80
42#define WM8960_BUFDCOPEN 0x10
43#define WM8960_BUFIOEN 0x08
44#define WM8960_SOFT_ST 0x04
45#define WM8960_HPSTBY 0x01
46
47/* R29 - Anti-pop 2 */
48#define WM8960_DISOP 0x40
913d7b4c 49#define WM8960_DRES_MASK 0x30
f2644a2c 50
3176bf2d
ZW		 51static bool is_pll_freq_available(unsigned int source, unsigned int target);
52static int wm8960_set_pll(struct snd_soc_codec *codec,
53 unsigned int freq_in, unsigned int freq_out);
f2644a2c
MB		 54/*
55 * wm8960 register cache
56 * We can't read the WM8960 register space when we are
57 * using 2 wire for device control, so we cache them instead.
58 */
0ebe36c6 59static const struct reg_default wm8960_reg_defaults[] = {
b3df026e
MB		 60 { 0x0, 0x00a7 },
61 { 0x1, 0x00a7 },
0ebe36c6
MB		 62 { 0x2, 0x0000 },
63 { 0x3, 0x0000 },
64 { 0x4, 0x0000 },
65 { 0x5, 0x0008 },
66 { 0x6, 0x0000 },
67 { 0x7, 0x000a },
68 { 0x8, 0x01c0 },
69 { 0x9, 0x0000 },
70 { 0xa, 0x00ff },
71 { 0xb, 0x00ff },
72
73 { 0x10, 0x0000 },
74 { 0x11, 0x007b },
75 { 0x12, 0x0100 },
76 { 0x13, 0x0032 },
77 { 0x14, 0x0000 },
78 { 0x15, 0x00c3 },
79 { 0x16, 0x00c3 },
80 { 0x17, 0x01c0 },
81 { 0x18, 0x0000 },
82 { 0x19, 0x0000 },
83 { 0x1a, 0x0000 },
84 { 0x1b, 0x0000 },
85 { 0x1c, 0x0000 },
86 { 0x1d, 0x0000 },
87
88 { 0x20, 0x0100 },
89 { 0x21, 0x0100 },
90 { 0x22, 0x0050 },
91
92 { 0x25, 0x0050 },
93 { 0x26, 0x0000 },
94 { 0x27, 0x0000 },
95 { 0x28, 0x0000 },
96 { 0x29, 0x0000 },
97 { 0x2a, 0x0040 },
98 { 0x2b, 0x0000 },
99 { 0x2c, 0x0000 },
100 { 0x2d, 0x0050 },
101 { 0x2e, 0x0050 },
102 { 0x2f, 0x0000 },
103 { 0x30, 0x0002 },
104 { 0x31, 0x0037 },
105
106 { 0x33, 0x0080 },
107 { 0x34, 0x0008 },
108 { 0x35, 0x0031 },
109 { 0x36, 0x0026 },
110 { 0x37, 0x00e9 },
f2644a2c
MB		 111};
112
0ebe36c6
MB		 113static bool wm8960_volatile(struct device *dev, unsigned int reg)
114{
115 switch (reg) {
116 case WM8960_RESET:
117 return true;
118 default:
119 return false;
120 }
121}
122
f2644a2c 123struct wm8960_priv {
75aa8868 124 struct clk *mclk;
0ebe36c6 125 struct regmap *regmap;
f0fba2ad
LG		 126 int (*set_bias_level)(struct snd_soc_codec *,
127 enum snd_soc_bias_level level);
913d7b4c
MB		 128 struct snd_soc_dapm_widget *lout1;
129 struct snd_soc_dapm_widget *rout1;
130 struct snd_soc_dapm_widget *out3;
afd6d36a 131 bool deemph;
3176bf2d 132 int lrclk;
0e50b51a
ZW		 133 int bclk;
134 int sysclk;
3176bf2d
ZW		 135 int clk_id;
136 int freq_in;
137 bool is_stream_in_use[2];
e2280c90 138 struct wm8960_data pdata;
f2644a2c
MB		 139};
140
3ad5e861 141#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
f2644a2c
MB		 142
143/* enumerated controls */
f2644a2c
MB		 144static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
145 "Right Inverted", "Stereo Inversion"};
146static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
147static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
148static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
149static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
150
151static const struct soc_enum wm8960_enum[] = {
f2644a2c
MB		 152 SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
153 SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
154 SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
155 SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
156 SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
157 SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
158};
159
afd6d36a
MB		 160static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
161
162static int wm8960_set_deemph(struct snd_soc_codec *codec)
163{
164 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
165 int val, i, best;
166
167 /* If we're using deemphasis select the nearest available sample
168 * rate.
169 */
170 if (wm8960->deemph) {
171 best = 1;
172 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
3176bf2d
ZW		 173 if (abs(deemph_settings[i] - wm8960->lrclk) <
174 abs(deemph_settings[best] - wm8960->lrclk))
afd6d36a
MB		 175 best = i;
176 }
177
178 val = best << 1;
179 } else {
180 val = 0;
181 }
182
183 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
184
185 return snd_soc_update_bits(codec, WM8960_DACCTL1,
186 0x6, val);
187}
188
189static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
190 struct snd_ctl_elem_value *ucontrol)
191{
ea53bf77 192 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a
MB		 193 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
194
b4a18c8b 195 ucontrol->value.integer.value[0] = wm8960->deemph;
3f343f85 196 return 0;
afd6d36a
MB		 197}
198
199static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
200 struct snd_ctl_elem_value *ucontrol)
201{
ea53bf77 202 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a 203 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
b4a18c8b 204 int deemph = ucontrol->value.integer.value[0];
afd6d36a
MB		 205
206 if (deemph > 1)
207 return -EINVAL;
208
209 wm8960->deemph = deemph;
210
211 return wm8960_set_deemph(codec);
212}
213
f2644a2c
MB		 214static const DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 50, 0);
215static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
216static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
217static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
21eb2693 218static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
f2644a2c
MB		 219
220static const struct snd_kcontrol_new wm8960_snd_controls[] = {
221SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
222 0, 63, 0, adc_tlv),
223SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
224 6, 1, 0),
225SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
226 7, 1, 0),
227
21eb2693
MB		 228SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
229 WM8960_INBMIX1, 4, 7, 0, boost_tlv),
230SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
231 WM8960_INBMIX1, 1, 7, 0, boost_tlv),
232SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
233 WM8960_INBMIX2, 4, 7, 0, boost_tlv),
234SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
235 WM8960_INBMIX2, 1, 7, 0, boost_tlv),
236
f2644a2c
MB		 237SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
238 0, 255, 0, dac_tlv),
239
240SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
241 0, 127, 0, out_tlv),
242SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
243 7, 1, 0),
244
245SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
246 0, 127, 0, out_tlv),
247SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
248 7, 1, 0),
249SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
250SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
251
252SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
4faaa8d9 253SOC_ENUM("ADC Polarity", wm8960_enum[0]),
f2644a2c
MB		 254SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
255
a077e81e 256SOC_ENUM("DAC Polarity", wm8960_enum[1]),
afd6d36a
MB		 257SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
258 wm8960_get_deemph, wm8960_put_deemph),
f2644a2c 259
4faaa8d9
MB		 260SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
261SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
f2644a2c
MB		 262SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
263SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
264
4faaa8d9 265SOC_ENUM("ALC Function", wm8960_enum[4]),
f2644a2c
MB		 266SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
267SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
268SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
269SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
4faaa8d9 270SOC_ENUM("ALC Mode", wm8960_enum[5]),
f2644a2c
MB		 271SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
272SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
273
274SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
275SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
276
c324aac0
MH		 277SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
278 0, 255, 0, adc_tlv),
f2644a2c
MB		 279
280SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
281 WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
282SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
283 WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
284SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
285 WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
286SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
287 WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
288};
289
290static const struct snd_kcontrol_new wm8960_lin_boost[] = {
291SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
292SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
293SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
294};
295
296static const struct snd_kcontrol_new wm8960_lin[] = {
297SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
298};
299
300static const struct snd_kcontrol_new wm8960_rin_boost[] = {
301SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
302SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
303SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
304};
305
306static const struct snd_kcontrol_new wm8960_rin[] = {
307SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
308};
309
310static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
311SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
312SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
313SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
314};
315
316static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
317SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
318SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
319SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
320};
321
322static const struct snd_kcontrol_new wm8960_mono_out[] = {
323SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
324SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
325};
326
327static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
328SND_SOC_DAPM_INPUT("LINPUT1"),
329SND_SOC_DAPM_INPUT("RINPUT1"),
330SND_SOC_DAPM_INPUT("LINPUT2"),
331SND_SOC_DAPM_INPUT("RINPUT2"),
332SND_SOC_DAPM_INPUT("LINPUT3"),
333SND_SOC_DAPM_INPUT("RINPUT3"),
334
187774cb 335SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
f2644a2c
MB		 336
337SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
338 wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
339SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
340 wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
341
342SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
343 wm8960_lin, ARRAY_SIZE(wm8960_lin)),
344SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
345 wm8960_rin, ARRAY_SIZE(wm8960_rin)),
346
44426de4
MB		 347SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
348SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
f2644a2c
MB		 349
350SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
351SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
352
353SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
354 &wm8960_loutput_mixer[0],
355 ARRAY_SIZE(wm8960_loutput_mixer)),
356SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
357 &wm8960_routput_mixer[0],
358 ARRAY_SIZE(wm8960_routput_mixer)),
359
f2644a2c
MB		 360SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
361SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
362
363SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
364SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
365
366SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
367SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
368
369SND_SOC_DAPM_OUTPUT("SPK_LP"),
370SND_SOC_DAPM_OUTPUT("SPK_LN"),
371SND_SOC_DAPM_OUTPUT("HP_L"),
372SND_SOC_DAPM_OUTPUT("HP_R"),
373SND_SOC_DAPM_OUTPUT("SPK_RP"),
374SND_SOC_DAPM_OUTPUT("SPK_RN"),
375SND_SOC_DAPM_OUTPUT("OUT3"),
376};
377
913d7b4c
MB		 378static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
379SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
380 &wm8960_mono_out[0],
381 ARRAY_SIZE(wm8960_mono_out)),
382};
383
384/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
385static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
386SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
387};
388
f2644a2c
MB		 389static const struct snd_soc_dapm_route audio_paths[] = {
390 { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
391 { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
392 { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
393
394 { "Left Input Mixer", "Boost Switch", "Left Boost Mixer", },
395 { "Left Input Mixer", NULL, "LINPUT1", }, /* Really Boost Switch */
396 { "Left Input Mixer", NULL, "LINPUT2" },
397 { "Left Input Mixer", NULL, "LINPUT3" },
398
399 { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
400 { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
401 { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
402
403 { "Right Input Mixer", "Boost Switch", "Right Boost Mixer", },
404 { "Right Input Mixer", NULL, "RINPUT1", }, /* Really Boost Switch */
405 { "Right Input Mixer", NULL, "RINPUT2" },
85e36a1f 406 { "Right Input Mixer", NULL, "RINPUT3" },
f2644a2c
MB		 407
408 { "Left ADC", NULL, "Left Input Mixer" },
409 { "Right ADC", NULL, "Right Input Mixer" },
410
411 { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
412 { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer"} ,
413 { "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
414
415 { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
416 { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" } ,
417 { "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
418
f2644a2c
MB		 419 { "LOUT1 PGA", NULL, "Left Output Mixer" },
420 { "ROUT1 PGA", NULL, "Right Output Mixer" },
421
422 { "HP_L", NULL, "LOUT1 PGA" },
423 { "HP_R", NULL, "ROUT1 PGA" },
424
425 { "Left Speaker PGA", NULL, "Left Output Mixer" },
426 { "Right Speaker PGA", NULL, "Right Output Mixer" },
427
428 { "Left Speaker Output", NULL, "Left Speaker PGA" },
429 { "Right Speaker Output", NULL, "Right Speaker PGA" },
430
431 { "SPK_LN", NULL, "Left Speaker Output" },
432 { "SPK_LP", NULL, "Left Speaker Output" },
433 { "SPK_RN", NULL, "Right Speaker Output" },
434 { "SPK_RP", NULL, "Right Speaker Output" },
913d7b4c
MB		 435};
436
437static const struct snd_soc_dapm_route audio_paths_out3[] = {
438 { "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
439 { "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
f2644a2c
MB		 440
441 { "OUT3", NULL, "Mono Output Mixer", }
442};
443
913d7b4c
MB		 444static const struct snd_soc_dapm_route audio_paths_capless[] = {
445 { "HP_L", NULL, "OUT3 VMID" },
446 { "HP_R", NULL, "OUT3 VMID" },
447
448 { "OUT3 VMID", NULL, "Left Output Mixer" },
449 { "OUT3 VMID", NULL, "Right Output Mixer" },
450};
451
f2644a2c
MB		 452static int wm8960_add_widgets(struct snd_soc_codec *codec)
453{
b2c812e2 454 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 455 struct wm8960_data *pdata = &wm8960->pdata;
93f32f53 456 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
913d7b4c
MB		 457 struct snd_soc_dapm_widget *w;
458
ce6120cc 459 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
f2644a2c
MB		 460 ARRAY_SIZE(wm8960_dapm_widgets));
461
ce6120cc 462 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
f2644a2c 463
913d7b4c
MB		 464 /* In capless mode OUT3 is used to provide VMID for the
465 * headphone outputs, otherwise it is used as a mono mixer.
466 */
467 if (pdata && pdata->capless) {
ce6120cc 468 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
913d7b4c
MB		 469 ARRAY_SIZE(wm8960_dapm_widgets_capless));
470
ce6120cc 471 snd_soc_dapm_add_routes(dapm, audio_paths_capless,
913d7b4c
MB		 472 ARRAY_SIZE(audio_paths_capless));
473 } else {
ce6120cc 474 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
913d7b4c
MB		 475 ARRAY_SIZE(wm8960_dapm_widgets_out3));
476
ce6120cc 477 snd_soc_dapm_add_routes(dapm, audio_paths_out3,
913d7b4c
MB		 478 ARRAY_SIZE(audio_paths_out3));
479 }
480
481 /* We need to power up the headphone output stage out of
482 * sequence for capless mode. To save scanning the widget
483 * list each time to find the desired power state do so now
484 * and save the result.
485 */
00200107 486 list_for_each_entry(w, &codec->component.card->widgets, list) {
93f32f53 487 if (w->dapm != dapm)
97c866de 488 continue;
913d7b4c
MB		 489 if (strcmp(w->name, "LOUT1 PGA") == 0)
490 wm8960->lout1 = w;
491 if (strcmp(w->name, "ROUT1 PGA") == 0)
492 wm8960->rout1 = w;
493 if (strcmp(w->name, "OUT3 VMID") == 0)
494 wm8960->out3 = w;
495 }
496
f2644a2c
MB		 497 return 0;
498}
499
500static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
501 unsigned int fmt)
502{
503 struct snd_soc_codec *codec = codec_dai->codec;
504 u16 iface = 0;
505
506 /* set master/slave audio interface */
507 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
508 case SND_SOC_DAIFMT_CBM_CFM:
509 iface |= 0x0040;
510 break;
511 case SND_SOC_DAIFMT_CBS_CFS:
512 break;
513 default:
514 return -EINVAL;
515 }
516
517 /* interface format */
518 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
519 case SND_SOC_DAIFMT_I2S:
520 iface |= 0x0002;
521 break;
522 case SND_SOC_DAIFMT_RIGHT_J:
523 break;
524 case SND_SOC_DAIFMT_LEFT_J:
525 iface |= 0x0001;
526 break;
527 case SND_SOC_DAIFMT_DSP_A:
528 iface |= 0x0003;
529 break;
530 case SND_SOC_DAIFMT_DSP_B:
531 iface |= 0x0013;
532 break;
533 default:
534 return -EINVAL;
535 }
536
537 /* clock inversion */
538 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
539 case SND_SOC_DAIFMT_NB_NF:
540 break;
541 case SND_SOC_DAIFMT_IB_IF:
542 iface |= 0x0090;
543 break;
544 case SND_SOC_DAIFMT_IB_NF:
545 iface |= 0x0080;
546 break;
547 case SND_SOC_DAIFMT_NB_IF:
548 iface |= 0x0010;
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 /* set iface */
17a52fd6 555 snd_soc_write(codec, WM8960_IFACE1, iface);
f2644a2c
MB		 556 return 0;
557}
558
db059c0f
MB		 559static struct {
560 int rate;
561 unsigned int val;
562} alc_rates[] = {
563 { 48000, 0 },
564 { 44100, 0 },
565 { 32000, 1 },
566 { 22050, 2 },
567 { 24000, 2 },
568 { 16000, 3 },
22ee76da 569 { 11025, 4 },
db059c0f
MB		 570 { 12000, 4 },
571 { 8000, 5 },
572};
573
3176bf2d
ZW		 574/* -1 for reserved value */
575static const int sysclk_divs[] = { 1, -1, 2, -1 };
576
0e50b51a
ZW		 577/* Multiply 256 for internal 256 div */
578static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
579
580/* Multiply 10 to eliminate decimials */
581static const int bclk_divs[] = {
582 10, 15, 20, 30, 40, 55, 60, 80, 110,
583 120, 160, 220, 240, 320, 320, 320
584};
585
3176bf2d 586static int wm8960_configure_clocking(struct snd_soc_codec *codec)
0e50b51a
ZW		 587{
588 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 589 int sysclk, bclk, lrclk, freq_out, freq_in;
0e50b51a 590 u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
3176bf2d 591 int i, j, k;
0e50b51a
ZW		 592
593 if (!(iface1 & (1<<6))) {
594 dev_dbg(codec->dev,
595 "Codec is slave mode, no need to configure clock\n");
3176bf2d
ZW		 596 return 0;
597 }
598
599 if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
600 dev_err(codec->dev, "No MCLK configured\n");
601 return -EINVAL;
0e50b51a
ZW		 602 }
603
3176bf2d
ZW		 604 freq_in = wm8960->freq_in;
605 bclk = wm8960->bclk;
606 lrclk = wm8960->lrclk;
607 /*
608 * If it's sysclk auto mode, check if the MCLK can provide sysclk or
609 * not. If MCLK can provide sysclk, using MCLK to provide sysclk
610 * directly. Otherwise, auto select a available pll out frequency
611 * and set PLL.
612 */
613 if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
614 /* disable the PLL and using MCLK to provide sysclk */
615 wm8960_set_pll(codec, 0, 0);
616 freq_out = freq_in;
617 } else if (wm8960->sysclk) {
618 freq_out = wm8960->sysclk;
619 } else {
620 dev_err(codec->dev, "No SYSCLK configured\n");
621 return -EINVAL;
0e50b51a
ZW		 622 }
623
3176bf2d
ZW		 624 /* check if the sysclk frequency is available. */
625 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
626 if (sysclk_divs[i] == -1)
627 continue;
628 sysclk = freq_out / sysclk_divs[i];
629 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
630 if (sysclk == dac_divs[j] * lrclk) {
631 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k)
632 if (sysclk == bclk * bclk_divs[k] / 10)
633 break;
634 if (k != ARRAY_SIZE(bclk_divs))
635 break;
636 }
637 }
638 if (j != ARRAY_SIZE(dac_divs))
639 break;
0e50b51a
ZW		 640 }
641
3176bf2d
ZW		 642 if (i != ARRAY_SIZE(sysclk_divs)) {
643 goto configure_clock;
644 } else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
645 dev_err(codec->dev, "failed to configure clock\n");
646 return -EINVAL;
647 }
648 /* get a available pll out frequency and set pll */
649 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
650 if (sysclk_divs[i] == -1)
651 continue;
652 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
653 sysclk = lrclk * dac_divs[j];
654 freq_out = sysclk * sysclk_divs[i];
655
656 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
657 if (sysclk == bclk * bclk_divs[k] / 10 &&
658 is_pll_freq_available(freq_in, freq_out)) {
659 wm8960_set_pll(codec,
660 freq_in, freq_out);
0e50b51a 661 break;
3176bf2d
ZW		 662 } else {
663 continue;
664 }
0e50b51a 665 }
3176bf2d 666 if (k != ARRAY_SIZE(bclk_divs))
0e50b51a
ZW		 667 break;
668 }
3176bf2d
ZW		 669 if (j != ARRAY_SIZE(dac_divs))
670 break;
0e50b51a
ZW		 671 }
672
3176bf2d
ZW		 673 if (i == ARRAY_SIZE(sysclk_divs)) {
674 dev_err(codec->dev, "failed to configure clock\n");
675 return -EINVAL;
0e50b51a
ZW		 676 }
677
3176bf2d
ZW		 678configure_clock:
679 /* configure sysclk clock */
680 snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1);
681
682 /* configure frame clock */
683 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3);
684 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6);
0e50b51a
ZW		 685
686 /* configure bit clock */
3176bf2d
ZW		 687 snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k);
688
689 return 0;
0e50b51a
ZW		 690}
691
f2644a2c
MB		 692static int wm8960_hw_params(struct snd_pcm_substream *substream,
693 struct snd_pcm_hw_params *params,
694 struct snd_soc_dai *dai)
695{
e6968a17 696 struct snd_soc_codec *codec = dai->codec;
afd6d36a 697 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
17a52fd6 698 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
0e50b51a 699 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
db059c0f 700 int i;
f2644a2c 701
0e50b51a
ZW		 702 wm8960->bclk = snd_soc_params_to_bclk(params);
703 if (params_channels(params) == 1)
704 wm8960->bclk *= 2;
705
f2644a2c 706 /* bit size */
39e9cc46
MB		 707 switch (params_width(params)) {
708 case 16:
f2644a2c 709 break;
39e9cc46 710 case 20:
f2644a2c
MB		 711 iface |= 0x0004;
712 break;
39e9cc46 713 case 24:
f2644a2c
MB		 714 iface |= 0x0008;
715 break;
7a8c7867
ZW		 716 case 32:
717 /* right justify mode does not support 32 word length */
718 if ((iface & 0x3) != 0) {
719 iface |= 0x000c;
720 break;
721 }
4c2474c0 722 default:
39e9cc46
MB		 723 dev_err(codec->dev, "unsupported width %d\n",
724 params_width(params));
4c2474c0 725 return -EINVAL;
f2644a2c
MB		 726 }
727
3176bf2d 728 wm8960->lrclk = params_rate(params);
afd6d36a 729 /* Update filters for the new rate */
3176bf2d 730 if (tx) {
afd6d36a 731 wm8960_set_deemph(codec);
db059c0f
MB		 732 } else {
733 for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
734 if (alc_rates[i].rate == params_rate(params))
735 snd_soc_update_bits(codec,
736 WM8960_ADDCTL3, 0x7,
737 alc_rates[i].val);
afd6d36a
MB		 738 }
739
f2644a2c 740 /* set iface */
17a52fd6 741 snd_soc_write(codec, WM8960_IFACE1, iface);
0e50b51a 742
3176bf2d
ZW		 743 wm8960->is_stream_in_use[tx] = true;
744
745 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON &&
746 !wm8960->is_stream_in_use[!tx])
747 return wm8960_configure_clocking(codec);
748
749 return 0;
750}
751
752static int wm8960_hw_free(struct snd_pcm_substream *substream,
753 struct snd_soc_dai *dai)
754{
755 struct snd_soc_codec *codec = dai->codec;
756 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
757 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
758
759 wm8960->is_stream_in_use[tx] = false;
0e50b51a 760
f2644a2c
MB		 761 return 0;
762}
763
764static int wm8960_mute(struct snd_soc_dai *dai, int mute)
765{
766 struct snd_soc_codec *codec = dai->codec;
f2644a2c
MB		 767
768 if (mute)
16b24881 769 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8);
f2644a2c 770 else
16b24881 771 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0);
f2644a2c
MB		 772 return 0;
773}
774
913d7b4c
MB		 775static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
776 enum snd_soc_bias_level level)
f2644a2c 777{
0ebe36c6 778 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 779 u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
75aa8868 780 int ret;
0ebe36c6 781
f2644a2c
MB		 782 switch (level) {
783 case SND_SOC_BIAS_ON:
784 break;
785
786 case SND_SOC_BIAS_PREPARE:
93f32f53 787 switch (snd_soc_codec_get_bias_level(codec)) {
75aa8868
ZW		 788 case SND_SOC_BIAS_STANDBY:
789 if (!IS_ERR(wm8960->mclk)) {
790 ret = clk_prepare_enable(wm8960->mclk);
791 if (ret) {
792 dev_err(codec->dev,
793 "Failed to enable MCLK: %d\n",
794 ret);
795 return ret;
796 }
797 }
798
3176bf2d
ZW		 799 ret = wm8960_configure_clocking(codec);
800 if (ret)
801 return ret;
802
75aa8868
ZW		 803 /* Set VMID to 2x50k */
804 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
805 break;
806
807 case SND_SOC_BIAS_ON:
3176bf2d
ZW		 808 /*
809 * If it's sysclk auto mode, and the pll is enabled,
810 * disable the pll
811 */
812 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
813 wm8960_set_pll(codec, 0, 0);
814
75aa8868
ZW		 815 if (!IS_ERR(wm8960->mclk))
816 clk_disable_unprepare(wm8960->mclk);
817 break;
818
819 default:
820 break;
821 }
822
f2644a2c
MB		 823 break;
824
825 case SND_SOC_BIAS_STANDBY:
93f32f53 826 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
0ebe36c6 827 regcache_sync(wm8960->regmap);
bc45df2d 828
f2644a2c 829 /* Enable anti-pop features */
17a52fd6 830 snd_soc_write(codec, WM8960_APOP1,
913d7b4c
MB		 831 WM8960_POBCTRL | WM8960_SOFT_ST |
832 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
f2644a2c
MB		 833
834 /* Enable & ramp VMID at 2x50k */
16b24881 835 snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80);
f2644a2c
MB		 836 msleep(100);
837
838 /* Enable VREF */
16b24881
AL		 839 snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF,
840 WM8960_VREF);
f2644a2c
MB		 841
842 /* Disable anti-pop features */
17a52fd6 843 snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
f2644a2c
MB		 844 }
845
846 /* Set VMID to 2x250k */
16b24881 847 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
f2644a2c
MB		 848 break;
849
850 case SND_SOC_BIAS_OFF:
851 /* Enable anti-pop features */
17a52fd6 852 snd_soc_write(codec, WM8960_APOP1,
f2644a2c
MB		 853 WM8960_POBCTRL | WM8960_SOFT_ST |
854 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
855
856 /* Disable VMID and VREF, let them discharge */
17a52fd6 857 snd_soc_write(codec, WM8960_POWER1, 0);
f2644a2c 858 msleep(600);
913d7b4c
MB		 859 break;
860 }
861
913d7b4c
MB		 862 return 0;
863}
864
865static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
866 enum snd_soc_bias_level level)
867{
b2c812e2 868 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 869 u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
75aa8868 870 int reg, ret;
913d7b4c
MB		 871
872 switch (level) {
873 case SND_SOC_BIAS_ON:
874 break;
875
876 case SND_SOC_BIAS_PREPARE:
93f32f53 877 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 878 case SND_SOC_BIAS_STANDBY:
879 /* Enable anti pop mode */
880 snd_soc_update_bits(codec, WM8960_APOP1,
881 WM8960_POBCTRL | WM8960_SOFT_ST |
882 WM8960_BUFDCOPEN,
883 WM8960_POBCTRL | WM8960_SOFT_ST |
884 WM8960_BUFDCOPEN);
885
886 /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
887 reg = 0;
888 if (wm8960->lout1 && wm8960->lout1->power)
889 reg |= WM8960_PWR2_LOUT1;
890 if (wm8960->rout1 && wm8960->rout1->power)
891 reg |= WM8960_PWR2_ROUT1;
892 if (wm8960->out3 && wm8960->out3->power)
893 reg |= WM8960_PWR2_OUT3;
894 snd_soc_update_bits(codec, WM8960_POWER2,
895 WM8960_PWR2_LOUT1 |
896 WM8960_PWR2_ROUT1 |
897 WM8960_PWR2_OUT3, reg);
898
899 /* Enable VMID at 2*50k */
900 snd_soc_update_bits(codec, WM8960_POWER1,
901 WM8960_VMID_MASK, 0x80);
902
903 /* Ramp */
904 msleep(100);
905
906 /* Enable VREF */
907 snd_soc_update_bits(codec, WM8960_POWER1,
908 WM8960_VREF, WM8960_VREF);
909
910 msleep(100);
75aa8868
ZW		 911
912 if (!IS_ERR(wm8960->mclk)) {
913 ret = clk_prepare_enable(wm8960->mclk);
914 if (ret) {
915 dev_err(codec->dev,
916 "Failed to enable MCLK: %d\n",
917 ret);
918 return ret;
919 }
920 }
3176bf2d
ZW		 921
922 ret = wm8960_configure_clocking(codec);
923 if (ret)
924 return ret;
925
913d7b4c
MB		 926 break;
927
928 case SND_SOC_BIAS_ON:
3176bf2d
ZW		 929 /*
930 * If it's sysclk auto mode, and the pll is enabled,
931 * disable the pll
932 */
933 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
934 wm8960_set_pll(codec, 0, 0);
935
75aa8868
ZW		 936 if (!IS_ERR(wm8960->mclk))
937 clk_disable_unprepare(wm8960->mclk);
938
913d7b4c
MB		 939 /* Enable anti-pop mode */
940 snd_soc_update_bits(codec, WM8960_APOP1,
941 WM8960_POBCTRL | WM8960_SOFT_ST |
942 WM8960_BUFDCOPEN,
943 WM8960_POBCTRL | WM8960_SOFT_ST |
944 WM8960_BUFDCOPEN);
945
946 /* Disable VMID and VREF */
947 snd_soc_update_bits(codec, WM8960_POWER1,
948 WM8960_VREF | WM8960_VMID_MASK, 0);
949 break;
950
bc45df2d 951 case SND_SOC_BIAS_OFF:
0ebe36c6 952 regcache_sync(wm8960->regmap);
bc45df2d 953 break;
913d7b4c
MB		 954 default:
955 break;
956 }
957 break;
f2644a2c 958
913d7b4c 959 case SND_SOC_BIAS_STANDBY:
93f32f53 960 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 961 case SND_SOC_BIAS_PREPARE:
962 /* Disable HP discharge */
963 snd_soc_update_bits(codec, WM8960_APOP2,
964 WM8960_DISOP | WM8960_DRES_MASK,
965 0);
966
967 /* Disable anti-pop features */
968 snd_soc_update_bits(codec, WM8960_APOP1,
969 WM8960_POBCTRL | WM8960_SOFT_ST |
970 WM8960_BUFDCOPEN,
971 WM8960_POBCTRL | WM8960_SOFT_ST |
972 WM8960_BUFDCOPEN);
973 break;
974
975 default:
976 break;
977 }
978 break;
f2644a2c 979
913d7b4c 980 case SND_SOC_BIAS_OFF:
f2644a2c
MB		 981 break;
982 }
983
f2644a2c
MB		 984 return 0;
985}
986
987/* PLL divisors */
988struct _pll_div {
989 u32 pre_div:1;
990 u32 n:4;
991 u32 k:24;
992};
993
3176bf2d
ZW		 994static bool is_pll_freq_available(unsigned int source, unsigned int target)
995{
996 unsigned int Ndiv;
997
998 if (source == 0 || target == 0)
999 return false;
1000
1001 /* Scale up target to PLL operating frequency */
1002 target *= 4;
1003 Ndiv = target / source;
1004
1005 if (Ndiv < 6) {
1006 source >>= 1;
1007 Ndiv = target / source;
1008 }
1009
1010 if ((Ndiv < 6) || (Ndiv > 12))
1011 return false;
1012
1013 return true;
1014}
1015
f2644a2c
MB		 1016/* The size in bits of the pll divide multiplied by 10
1017 * to allow rounding later */
1018#define FIXED_PLL_SIZE ((1 << 24) * 10)
1019
1020static int pll_factors(unsigned int source, unsigned int target,
1021 struct _pll_div *pll_div)
1022{
1023 unsigned long long Kpart;
1024 unsigned int K, Ndiv, Nmod;
1025
1026 pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
1027
1028 /* Scale up target to PLL operating frequency */
1029 target *= 4;
1030
1031 Ndiv = target / source;
1032 if (Ndiv < 6) {
1033 source >>= 1;
1034 pll_div->pre_div = 1;
1035 Ndiv = target / source;
1036 } else
1037 pll_div->pre_div = 0;
1038
1039 if ((Ndiv < 6) || (Ndiv > 12)) {
1040 pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
1041 return -EINVAL;
1042 }
1043
1044 pll_div->n = Ndiv;
1045 Nmod = target % source;
1046 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1047
1048 do_div(Kpart, source);
1049
1050 K = Kpart & 0xFFFFFFFF;
1051
1052 /* Check if we need to round */
1053 if ((K % 10) >= 5)
1054 K += 5;
1055
1056 /* Move down to proper range now rounding is done */
1057 K /= 10;
1058
1059 pll_div->k = K;
1060
1061 pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
1062 pll_div->n, pll_div->k, pll_div->pre_div);
1063
1064 return 0;
1065}
1066
3176bf2d
ZW		 1067static int wm8960_set_pll(struct snd_soc_codec *codec,
1068 unsigned int freq_in, unsigned int freq_out)
f2644a2c 1069{
f2644a2c
MB		 1070 u16 reg;
1071 static struct _pll_div pll_div;
1072 int ret;
1073
1074 if (freq_in && freq_out) {
1075 ret = pll_factors(freq_in, freq_out, &pll_div);
1076 if (ret != 0)
1077 return ret;
1078 }
1079
1080 /* Disable the PLL: even if we are changing the frequency the
1081 * PLL needs to be disabled while we do so. */
16b24881
AL		 1082 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0);
1083 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0);
f2644a2c
MB		 1084
1085 if (!freq_in || !freq_out)
1086 return 0;
1087
17a52fd6 1088 reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
f2644a2c
MB		 1089 reg |= pll_div.pre_div << 4;
1090 reg |= pll_div.n;
1091
1092 if (pll_div.k) {
1093 reg |= 0x20;
1094
85fa532b
MD		 1095 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
1096 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
1097 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
f2644a2c 1098 }
17a52fd6 1099 snd_soc_write(codec, WM8960_PLL1, reg);
f2644a2c
MB		 1100
1101 /* Turn it on */
16b24881 1102 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1);
f2644a2c 1103 msleep(250);
16b24881 1104 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1);
f2644a2c
MB		 1105
1106 return 0;
1107}
1108
3176bf2d
ZW		 1109static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1110 int source, unsigned int freq_in, unsigned int freq_out)
1111{
1112 struct snd_soc_codec *codec = codec_dai->codec;
1113 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1114
1115 wm8960->freq_in = freq_in;
1116
1117 if (pll_id == WM8960_SYSCLK_AUTO)
1118 return 0;
1119
1120 return wm8960_set_pll(codec, freq_in, freq_out);
1121}
1122
f2644a2c
MB		 1123static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1124 int div_id, int div)
1125{
1126 struct snd_soc_codec *codec = codec_dai->codec;
1127 u16 reg;
1128
1129 switch (div_id) {
f2644a2c 1130 case WM8960_SYSCLKDIV:
17a52fd6
MB		 1131 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
1132 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1133 break;
1134 case WM8960_DACDIV:
17a52fd6
MB		 1135 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
1136 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1137 break;
1138 case WM8960_OPCLKDIV:
17a52fd6
MB		 1139 reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
1140 snd_soc_write(codec, WM8960_PLL1, reg | div);
f2644a2c
MB		 1141 break;
1142 case WM8960_DCLKDIV:
17a52fd6
MB		 1143 reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
1144 snd_soc_write(codec, WM8960_CLOCK2, reg | div);
f2644a2c
MB		 1145 break;
1146 case WM8960_TOCLKSEL:
17a52fd6
MB		 1147 reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
1148 snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
f2644a2c
MB		 1149 break;
1150 default:
1151 return -EINVAL;
1152 }
1153
1154 return 0;
1155}
1156
f0fba2ad
LG		 1157static int wm8960_set_bias_level(struct snd_soc_codec *codec,
1158 enum snd_soc_bias_level level)
1159{
1160 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1161
1162 return wm8960->set_bias_level(codec, level);
1163}
1164
0e50b51a
ZW		 1165static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1166 unsigned int freq, int dir)
1167{
1168 struct snd_soc_codec *codec = dai->codec;
1169 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1170
1171 switch (clk_id) {
1172 case WM8960_SYSCLK_MCLK:
1173 snd_soc_update_bits(codec, WM8960_CLOCK1,
1174 0x1, WM8960_SYSCLK_MCLK);
1175 break;
1176 case WM8960_SYSCLK_PLL:
1177 snd_soc_update_bits(codec, WM8960_CLOCK1,
1178 0x1, WM8960_SYSCLK_PLL);
1179 break;
3176bf2d
ZW		 1180 case WM8960_SYSCLK_AUTO:
1181 break;
0e50b51a
ZW		 1182 default:
1183 return -EINVAL;
1184 }
1185
1186 wm8960->sysclk = freq;
3176bf2d 1187 wm8960->clk_id = clk_id;
0e50b51a
ZW		 1188
1189 return 0;
1190}
1191
f2644a2c
MB		 1192#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
1193
1194#define WM8960_FORMATS \
1195 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
7a8c7867 1196 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
f2644a2c 1197
85e7652d 1198static const struct snd_soc_dai_ops wm8960_dai_ops = {
f2644a2c 1199 .hw_params = wm8960_hw_params,
3176bf2d 1200 .hw_free = wm8960_hw_free,
f2644a2c
MB		 1201 .digital_mute = wm8960_mute,
1202 .set_fmt = wm8960_set_dai_fmt,
1203 .set_clkdiv = wm8960_set_dai_clkdiv,
1204 .set_pll = wm8960_set_dai_pll,
0e50b51a 1205 .set_sysclk = wm8960_set_dai_sysclk,
f2644a2c
MB		 1206};
1207
f0fba2ad
LG		 1208static struct snd_soc_dai_driver wm8960_dai = {
1209 .name = "wm8960-hifi",
f2644a2c
MB		 1210 .playback = {
1211 .stream_name = "Playback",
1212 .channels_min = 1,
1213 .channels_max = 2,
1214 .rates = WM8960_RATES,
1215 .formats = WM8960_FORMATS,},
1216 .capture = {
1217 .stream_name = "Capture",
1218 .channels_min = 1,
1219 .channels_max = 2,
1220 .rates = WM8960_RATES,
1221 .formats = WM8960_FORMATS,},
1222 .ops = &wm8960_dai_ops,
1223 .symmetric_rates = 1,
1224};
f2644a2c 1225
f0fba2ad 1226static int wm8960_probe(struct snd_soc_codec *codec)
f2644a2c 1227{
f0fba2ad 1228 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 1229 struct wm8960_data *pdata = &wm8960->pdata;
f2644a2c 1230
e2280c90
ZW		 1231 if (pdata->capless)
1232 wm8960->set_bias_level = wm8960_set_bias_level_capless;
1233 else
1234 wm8960->set_bias_level = wm8960_set_bias_level_out3;
f2644a2c 1235
022658be 1236 snd_soc_add_codec_controls(codec, wm8960_snd_controls,
f0fba2ad
LG		 1237 ARRAY_SIZE(wm8960_snd_controls));
1238 wm8960_add_widgets(codec);
f2644a2c
MB		 1239
1240 return 0;
1241}
1242
f0fba2ad
LG		 1243static struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
1244 .probe = wm8960_probe,
f0fba2ad 1245 .set_bias_level = wm8960_set_bias_level,
0a87a6e1 1246 .suspend_bias_off = true,
0ebe36c6
MB		 1247};
1248
1249static const struct regmap_config wm8960_regmap = {
1250 .reg_bits = 7,
1251 .val_bits = 9,
1252 .max_register = WM8960_PLL4,
1253
1254 .reg_defaults = wm8960_reg_defaults,
1255 .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
1256 .cache_type = REGCACHE_RBTREE,
1257
1258 .volatile_reg = wm8960_volatile,
f0fba2ad
LG		 1259};
1260
e2280c90
ZW		 1261static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
1262 struct wm8960_data *pdata)
1263{
1264 const struct device_node *np = i2c->dev.of_node;
1265
1266 if (of_property_read_bool(np, "wlf,capless"))
1267 pdata->capless = true;
1268
1269 if (of_property_read_bool(np, "wlf,shared-lrclk"))
1270 pdata->shared_lrclk = true;
1271}
1272
7a79e94e
BP		 1273static int wm8960_i2c_probe(struct i2c_client *i2c,
1274 const struct i2c_device_id *id)
f2644a2c 1275{
37061631 1276 struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
f2644a2c 1277 struct wm8960_priv *wm8960;
f0fba2ad 1278 int ret;
f2644a2c 1279
b9791c01
MB		 1280 wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
1281 GFP_KERNEL);
f2644a2c
MB		 1282 if (wm8960 == NULL)
1283 return -ENOMEM;
1284
75aa8868
ZW		 1285 wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
1286 if (IS_ERR(wm8960->mclk)) {
1287 if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
1288 return -EPROBE_DEFER;
1289 }
1290
c5e6f5fa 1291 wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
0ebe36c6
MB		 1292 if (IS_ERR(wm8960->regmap))
1293 return PTR_ERR(wm8960->regmap);
1294
e2280c90
ZW		 1295 if (pdata)
1296 memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
1297 else if (i2c->dev.of_node)
1298 wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
1299
3ad5e861
ZW		 1300 ret = wm8960_reset(wm8960->regmap);
1301 if (ret != 0) {
1302 dev_err(&i2c->dev, "Failed to issue reset\n");
1303 return ret;
1304 }
1305
1306 if (wm8960->pdata.shared_lrclk) {
37061631
MB		 1307 ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
1308 0x4, 0x4);
1309 if (ret != 0) {
1310 dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
1311 ret);
1312 return ret;
1313 }
1314 }
1315
3ad5e861
ZW		 1316 /* Latch the update bits */
1317 regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
1318 regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
1319 regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
1320 regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
1321 regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
1322 regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
1323 regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
1324 regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
1325 regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
1326 regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
1327
f2644a2c 1328 i2c_set_clientdata(i2c, wm8960);
f2644a2c 1329
f0fba2ad
LG		 1330 ret = snd_soc_register_codec(&i2c->dev,
1331 &soc_codec_dev_wm8960, &wm8960_dai, 1);
b9791c01 1332
f0fba2ad 1333 return ret;
f2644a2c
MB		 1334}
1335
7a79e94e 1336static int wm8960_i2c_remove(struct i2c_client *client)
f2644a2c 1337{
f0fba2ad 1338 snd_soc_unregister_codec(&client->dev);
f2644a2c
MB		 1339 return 0;
1340}
1341
1342static const struct i2c_device_id wm8960_i2c_id[] = {
1343 { "wm8960", 0 },
1344 { }
1345};
1346MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
1347
e2280c90
ZW		 1348static const struct of_device_id wm8960_of_match[] = {
1349 { .compatible = "wlf,wm8960", },
1350 { }
1351};
1352MODULE_DEVICE_TABLE(of, wm8960_of_match);
1353
f2644a2c
MB		 1354static struct i2c_driver wm8960_i2c_driver = {
1355 .driver = {
091edccf 1356 .name = "wm8960",
e2280c90 1357 .of_match_table = wm8960_of_match,
f2644a2c
MB		 1358 },
1359 .probe = wm8960_i2c_probe,
7a79e94e 1360 .remove = wm8960_i2c_remove,
f2644a2c
MB		 1361 .id_table = wm8960_i2c_id,
1362};
1363
3c010e60 1364module_i2c_driver(wm8960_i2c_driver);
f2644a2c 1365
f2644a2c
MB		 1366MODULE_DESCRIPTION("ASoC WM8960 driver");
1367MODULE_AUTHOR("Liam Girdwood");
1368MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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